STK672-732A-E_11 [SANYO]
2-phase Stepping Motor Driver; 两相步进电机驱动器
| 型号： | STK672-732A-E_11 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | 2-phase Stepping Motor Driver |
| 文件： | 总19页 (文件大小：154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA1590A
Thick-Film Hybrid IC
STK672-732A-E
2-phase Stepping Motor Driver
Overview
The STK672-732A-E is a hybrid IC for use as a unipolar, 2-phase stepping motor driver with PWM current control.
Applications
• Office photocopiers, printers, etc.
Features
• Built-in overcurrent detection function (output current OFF).
• Built-in overheat detection function (output current OFF).
• If either overcurrent or overheat detection function is activated, the FAULT signal (active low) is output.
• Built-in power on reset function.
• Phase signal input driver activated with an active Low and incorporates a simultaneous ON prevention function.
• Supports schmitt input for 2.5V high level input.
• Incorporating a current detection resistor (0.141Ω: resistor tolerance 2%), motor current can be set using two
external resistors.
• Provides the output current cutoff ENABLE pin.
• Miniature package (provides pin compatibility with STK672-730A-E)
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
62911HKPC 018-08-0086/N1809HKIM No. A1590-1/19
STK672-732A-E
Specifications
Absolute Maximum Ratings at Tc = 25°C
Parameter
Maximum supply voltage 1
Maximum supply voltage 2
Input voltage
Symbol
Conditions
Ratings
unit
V
V
max
No signal
52
CC
DD
V
max
max
max
max
max
No signal
-0.3 to +6.0
V
V
Logic input pins
-0.3 to +6.0
V
IN
OP
OH
Output current 1
I
10μs, 1 pulse (resistance load)
10
2.65
A
Output current 2
I
V
=5V, CLOCK≥200Hz
A
DD
Output current 3
I
Pin16 output current
10
mA
W
W
°C
°C
°C
OF
Allowable power dissipation 1
Allowable power dissipation 2
Operating substrate temperature
Junction temperature
Storage temperature
PdMF max
PdPK max
Tc max
Tj max
With an arbitrarily large heat sink. Per MOSFET
No heat sink
7.3
2.8
105
150
Tstg
-40 to +125
Allowable Operating Ranges at Ta=25°C
Parameter
Operating supply voltage 1
Operating supply voltage 2
Input high voltage
Symbol
Conditions
Ratings
unit
V
V
With signals applied
With signals applied
10 to 42
5 5%
CC
V
V
DD
V
Pins 13, 17, 12, 10, 14, 15
Pins 13, 17, 12, 10, 14, 15
2.5 to V
V
IH
DD
Input low voltage
V
0 to 0.8
V
IL
Output current 1
I
I
1
Tc=105°C, CLOCK≥200Hz,
OH
2.0
A
Continuous operation, duty=100%
Tc=80°C, CLOCK≥200Hz,
Output current 2
2
OH
Continuous operation, duty=100%,
2.2
A
See the motor current (I
=1mA (Tc=25°C)
) derating curve
OH
Phase driver withstand voltage
V
I
D
100min
0 to 105
V
°C
V
DSS
Tc
Recommended operating
substrate temperature
No condensation
Recommended Vref range
Vref
Tc=105°C
0.14 to 1.38
Refer to the graph for each conduction-period tolerance range for the output current and brake current.
Electrical Characteristics at Tc=25°C, V =24V, V =5.0V
CC
DD
Parameter
Symbol
Conditions
min
typ
max
unit
mA
A
V
supply current
I
Pin 9 current CLOCK=GND
4.4
8
DD
CCO
Output average current
FET diode forward voltage
Output saturation voltage
Input high voltage
Ioave
Vdf
R/L=1Ω/0.62mH in each phase
0.273
0.329
0.92
0.33
0.385
1.6
If=1A (R =23Ω)
V
L
Vsat
R =23Ω
0.48
V
L
V
Pins 13, 17, 12, 10, 14, 15
Pins 13, 17, 12, 10, 14, 15
2.5
V
IH
Input low voltage
V
0.8
0.5
10
75
10
15
61
V
IL
FAULT low output voltage
5V level FAULT leakage current
5V level input current
V
Pin 16 (I =5mA)
O
0.25
50
V
OLF
I
Pin 16=5V
μA
μA
μA
μA
kHz
°C
ILF
I
Pins 13, 17, 12, 10, 14, 15=5V
Pins 13, 17, 12, 10, 14, 15=GND
Pin 19=1.0V
ILH
GND level input current
Vref input bias current
PWM frequency
I
ILL
I
10
45
IB
fc
29
Overheat detection temperature
TSD
Design guarantee
144
*Ioave values are for when the lead frame of the product is soldered to the mounting substrate.
Notes: A fixed-voltage power supply must be used.
No. A1590-2/19
STK672-732A-E
Package Dimensions
unit:mm (typ)
24.2
(18.4)
4.5
(R1.47)
1
19
0.4
1.0
0.5
2.0
18 1.0=18.0
4.0
4.45
Derating curve of motor current, I
vs. Operating substrate temperature, Tc
OH,
I
- Tc
OH
3.0
200Hz 2 phase excitation
2.5
2.0
1.5
1.0
Hold mode
0.5
0
0
10
20
30
40
50
60
70
80
90 100 110
Operating Substrate Temperature, Tc- °C
ITF02548
Notes
• The current range given above represents conditions when output voltage is not in the avalanche state.
• If the output voltage is in the avalanche state, see the allowable avalanche energy for STK672-7** series hybrid ICs given
in a separate document.
• The operating substrate temperature, Tc, given above is measured while the motor is operating.
Because Tc varies depending on the ambient temperature, Ta, the value of I , and the continuous or intermittent
OH
operation of I , always verify this value using an actual set.
OH
• The Tc temperature should be checked in the center of the metal surface of the product package.
No. A1590-3/19
STK672-732A-E
Block Diagram
NC
4
A
5
AB
7
B
3
NC
8
BB
1
V
V
=5V
9
DD
DD
F1
F2
F3
F4
φBB 10
FAO
BBIN
BIN
NC
FAB
FBO
FBB
11
17
φAB
12
13
φB
φA
ABIN
AIN
Latch
circuit
Overcurrent
detection
Power-on
reset
RESETB
ENABLE
FAULT
14
15
16
R2
R1
AI
BI
Current control
chopper circuit
FAULT signal
(open drain)
Vref/4.9
2
6
P.G1
P.G2
-
Vref
Overheating
detection
Latch
circuit
+
Amplifier
100kΩ
V
V
SS
SS
V
SS
S.G
Vref
18
19
Sample Application Circuit
STK672-732A-E
V
(5V)
φA
φAB
9
DD
13
17
2 phase stepping motor driver
φB
12
A
5
φBB
10
AB
7
ENABLE
FAULT
15
V
=24V
CC
B
RESETB
3
1
14
BB
R01
R02
+
C01
at least 100μF
16
19
Vref
P.G1
P.G2
2
6
P.GND
18
S.G
No. A1590-4/19
STK672-732A-E
Precautions
[GND wiring]
• To reduce noise on the 5V system, be sure to place the GND of C01 in the circuit given above as close as possible to
Pin 2 and Pin 6 of the hybrid IC. Also, to achieve accurate current settings, be sure to connect Vref GND to Pin 18
(S.G) used to set the current and to the point where P.G1 and P.G2 share a connection.
[Input pins]
• If V
is being applied, use care that each input pin does not apply a negative voltage less than -0.3V to S.G, Pin 18,
DD
and do not apply a voltage greater than or equal to V
voltage.
DD
• Do not wire by connecting the circuit pattern on the P.C.B side to Pins 4, 8, or 11 on the N.C. shown in the internal
block diagram.
• Apply 2.5V High level input to pins 13, 17, 12, 10, 14, and 15.
• Since the input pins do not have built-in pull-up resistors, when the open-collector type pins 13, 17, 12, 10, 14, and 15
are used as inputs, a 1 to 20kΩ pull-up resistor (to V ) must be used.
DD
At this time, use a device for the open collector driver that has output current specifications that pull the voltage down
to less than 0.8V at Low level (less than 0.8V at Low level when I =5mA).
OL
[Current setting Vref]
• Considering the specifications of the Vref input bias current, I , a value of 1kΩ or less is recommended for R02.
IB
• If the motor current is temporarily reduced, the circuit given below (STK672-730A-E, 732A-E: I >0.2A) is
OH
recommended.
5V
5V
R01
R01
Vref
Vref
R02
R3
R3
R02
• Motor current peak value I
setting
OH
I
OH
0
I
=(Vref ÷ 4.9) ÷ Rs
OH
The value of 4.9 in Equation above represents the Vref voltage as divided by a circuit inside the control IC.
Vref=(R02 ÷ (R01+R02))×5V(or 3.3V)
Rs is an internal current detection resistor value of the hybrid IC.
STK672-732A-E: Rs=0.141Ω
No. A1590-5/19
STK672-732A-E
[Smoke Emission Precuations]
If Pin 18 (S.G terminal) is attached to the PCB without using solder, overcurrent may flow into the MOSFET at
ON (24V ON), causing to emit smoke because 5V circuits cannot be controlled.
V
CC
In addition, as long as one of the output Pins, 1, 3, 5, or 7, is open, inductance energy stored in the motor results in
electrical stress on the driver, possibly resulting in the emission of smoke.
Input Pin Functions
Pin Name
Pin No.
13
Function
Input Conditions When Operating
Low active (with a function to prevent simultaneous
φA
Pin 5, phase A output
Pin 7, phase AB output
Pin 3, phase B output
Pin 1, phase BB output
System reset
ON of φA and φAB, or φB and φBB)
17
φAB
12
φB
10
φBB
14
A reset is applied by a low level
RESETB
ENABLE
15
A, AB, B, and BB outputs are cut off by a low level
A, AB, B, and, BB outputs cut off
Output Pin Functions
Pin Name
FAULT
Pin No.
16
Function
Input Conditions When Operating
Low level is output when detected.
Monitor pin used when over-current detection or overheat
detection function is activated.
Note: See the timing chart for the concrete details on circuit operation.
No. A1590-6/19
STK672-732A-E
Timing Charts
2-phase excitation
V
DD
Power on reset
(or RESETB)
φA
φAB
φB
φBB
ENBALE
FAO
FAB
FBO
FBB
1-2 phase excitation
V
DD
Power on reset
(or RESETB)
φA
φAB
φB
φBB
ENBALE
FAO
FAB
FBO
FBB
No. A1590-7/19
STK672-732A-E
1-2 phase excitation (ENABLE)
V
DD
Power on reset
(or RESETB)
φA
φAB
φB
φBB
ENBALE
Output off
FAO
FAB
FBO
FBB
1-2 phase excitation (Hold operation results during fixed CLOCK)
V
DD
Power on reset
(or RESETB)
φA
φAB
φB
φBB
ENBALE
Hold mode
FAO
FAB
FBO
FBB
No. A1590-8/19
STK672-732A-E
Usage Notes
1. Input signal functions and timing
[ENABLE, power on reset, and RESETB (Input signal timing when power is first applied)]
The control IC of the driver is equipped with a power on reset function capable of initializing internal IC operations
when power is supplied. A 4V typ setting is used for power on reset. Because the specification for the MOSFET gate
voltage is 5V 5%, conduction of current to output at the time of power on reset adds electromotive stress to the
MOSFET due to lack of gate voltage. To prevent electromotive stress, be sure to set ENABLE=Low while V
which is outside the operating supply voltage, is less than 4.75V.
,
DD
3.8V typ
4V typ
Control IC power (V ) rising edge
DD
Control IC power on reset
RESETB signal input
ENABLE signal input
No time specification
φA to φBB signal
No time specification
No time specification
ENABLE, φA to φBB Signals Input Timing
[ENABLE (Forcible on/off control of the A, AB, B, and BB outputs, and hybrid IC internal operation)]
ENABLE=1: Normal operation
ENABLE=0: Outputs A, AB, B, and BB forced to the off state.
If the φA to φBB signal used for motor rotation suddenly stops, the motor shaft may advance beyond the control
position due to inertia. A SLOW DOWN setting where the φA to φBB cycle gradually decreases is required in order to
stop at the control position.
No. A1590-9/19
STK672-732A-E
[Configuration of I/O pins]
<Configuration of the φA, φAB, φB, φBB, ENABLE, and RESETB input pins>
Input pins13, 17, 12, 10, 15, and 14
5V
10kΩ
100kΩ
V
SS
The input pins of this driver all use Schmitt input. Typical specifications at Tc=25°C are given below. Hysteresis
voltage is 0.3V (VIHa-VILa).
When rising
When falling
1.8V typ
1.5V typ
Input voltage
VILa
VIHa
Input voltage specifications are as follows.
V
V
=2.5V min
IH
=0.8V max
IL
<Configuration of the FAULT output pin>
<Configuration of the Vref input pin>
5V
Vref/4.9
-
Output pin
Pin 16
Input pin
Pin 19
+
Amplifier
100kΩ
V
SS
V
V
SS
SS
The internal impedance, 100kΩ, is designed so that the increase in current is prevented while Pin 19 is open.
The recommended Vref voltage is 0.14V or higher because the output offset voltage of Vref/4.9 amplifier cannot be
controlled down to 0V
No. A1590-10/19
STK672-732A-E
2. Overcurrent Detection and Overheat Detection Functions
Each detection function operates using a latch system and turns output off. Because a RESET signal is required to
restore output operations, once the power supply, V , is turned off, you must either again apply power on reset with
DD
ON or apply a RESETB=High→Low→High signal.
V
DD
[Overcurrent detection]
This hybrid IC is equipped with a function for detecting overcurrent that arises when the motor burns out or when there
is a short between the motor terminals.
Overcurrent detection occurs at 3.5A typ with the STK672-732A-E
Current when motor terminals are shorted
PWM period
Over-current detection
max
Set motor
current,
I
OH
I
OH
MOSFET all OFF
5.5μs typ
No detection interval
(5.5μs typ)
Normal operation
Operation when motor pins are shorted
Overcurrent detection begins after an interval of no detection (a dead time of 5.5μs typ) during the initial ringing part
during PWM operations. The no detection interval is a period of time where overcurrent is not detected even if the
current exceeds I
.
OH
[Overheat detection]
Rather than directly detecting the temperature of the semiconductor device, overheat detection detects the temperature
of the aluminum substrate (144°C typ).
Within the allowed operating range recommended in the specification manual, if a heat sink attached for the purpose of
reducing the operating substrate temperature, Tc, comes loose, the semiconductor can operate without breaking.
However, we cannot guarantee operations without breaking in the case of operations other than those recommended,
such as operations at a current exceeding I
max that occurs before overcurrent detection is activated.
OH
No. A1590-11/19
STK672-732A-E
3. Calculating HIC Internal Power Loss
The average internal power loss in each excitation mode of the STK672-732A-E can be calculated from the following
formulas.
Each excitation mode
2-phase excitation mode
2PdAVex=(Vsat+Vdf) × (1/(t1+t2+t3)) ×I ×t2+(1/(t1+t2+t3)) ×I × (Vsat×t1+Vdf×t3)
OH OH
1-2 Phase excitation mode
1-2PdAVex=(Vsat+Vdf) × (1/(t1+t2+t3)) ×I ×t2+(1/(t1+t2+t3)) ×I × (Vsat×t1+Vdf×t3)
OH OH
Motor hold mode
HoldPdAVex= (Vsat+Vdf) ×I
OH
Vsat: Combined voltage represented by the Ron voltage drop+shunt resistor
Vdf: Combined voltage represented by the MOSFET body diode+shunt resistor
t1, t2, and t3 represent the waveforms shown in the figure below.
t1: Time required for the winding current to reach the set current (I
t2: Time in the constant current control (PWM) region
)
OH
t3: Time from end of phase input signal until inverse current regeneration is complete
I
OH
0A
t1
t2
t3
Motor COM Current Waveform Model
t1= (-L/(R+0.33)) In (1-((R+0.33)/V )×I
CC OH
)
t3= (-L/R) In ((V +0.33)/(I ×R+V +0.33))
CC OH CC
: Motor supply voltage (V)
CC
L: Motor inductance (H)
V
R: Motor winding resistance (Ω)
I
: Motor set output current crest value (A)
OH
For Vsat and Vdf, be sure to substitute values from the graphs of Vsat vs. I
and Vdf vs. I
while the set current
OH
OH
value is I
.
OH
Then, determine whether a heat sink is required by comparing with the graph of ΔTc vs. Pd based on the average HIC
power loss calculated.
When designing a heat sink, refer to the section “Thermal design” found on the next page. The average HIC power
loss, PdAV, described above does not have the avalanche’s loss. To include the avalanche’s loss, be sure to add
Equation (2), “STK672-7** Allowable Avalanche Energy Value” to PdAV above. When using this IC without a fin
always check for temperature increases in the set, because the HIC substrate temperature, Tc, varies due to effects of
convection around the HIC.
No. A1590-12/19
STK672-732A-E
Output saturation voltage, Vsat - Output current, I
OH
Vsat - I
OH
1.0
0.8
0.6
0.4
0.2
0
0
0.5
1.0
1.5
2.0
2.5
3.0
Output current, I
OH
- A
ITF02571
Forward voltage, Vdf -Output current, I
OH
Vdf- I
OH
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
0.5
1.0
1.5
2.0
2.5
3.0
Output current, I
OH
- A
ITF02572
Substrate temperature rise, ΔTc (no heat sink) - Internal average power dissipation, PdAV
ΔTc - PdAV
80
70
60
50
40
30
20
10
0
0
0.5
1.0
1.5
2.0
2.5
3.0
Hybrid IC internal average power dissipation, PdAV - W
ITF02717
No. A1590-13/19
STK672-732A-E
4. Allowable Avalanche Energy Value
(1) Allowable Range in Avalanche Mode
When driving a 2-phase stepping motor with constant current chopping using an STK672-7** Series hybrid IC,
the waveforms shown in Figure 1 below result for the output current, I , and voltage, V
.
DS
D
V
: Voltage during avalanche operations
DSS
V
DS
I : Motor current peak value
OH
IAVL: Current during avalanche operations
I
D
tAVL: Time of avalanche operations
ITF02557
Figure 1 Output Current, I , and Voltage, V , Waveforms 1 of the STK672-7** Series when
DS
D
Driving a 2-Phase Stepping Motor with Constant Current Chopping
When operations of the MOSFET built into STK672-7** Series ICs is turned off for constant current chopping,
the I signal falls like the waveform shown in the figure above. At this time, the output voltage, V , suddenly
D
DS
rises due to electromagnetic induction generated by the motor coil.
In the case of voltage that rises suddenly, voltage is restricted by the MOSFET V
. Voltage restriction by
DSS
V
results in a MOSFET avalanche. During avalanche operations, I flows and the instantaneous energy at
D
DSS
this time, EAVL1, is represented by Equation (1).
EAVL1=V
V
×IAVL×0.5×tAVL ------------------------------------------- (1)
DSS
: V units, IAVL: A units, tAVL: sec units
DSS
The coefficient 0.5 in Equation (1) is a constant required to convert the IAVL triangle wave to a
square wave.
During STK672-7** Series operations, the waveforms in the figure above repeat due to the constant current
chopping operation. The allowable avalanche energy, EAVL, is therefore represented by Equation (2) used to find
the average power loss, PAVL, during avalanche mode multiplied by the chopping frequency in Equation (1).
PAVL=V
×IAVL×0.5×tAVL×fc ------------------------------------------- (2)
fc: Hz units (fc is set to the PWM frequency of 50kHz.)
DSS
For V
DSS
, IAVL, and tAVL, be sure to actually operate the STK672-7** Series and substitute values when
operations are observed using an oscilloscope.
Ex. If V =110V, IAVL=1A, tAVL=0.2μs when using a STK672-732A-E driver, the result is:
DSS
PAVL=110×1×0.5×0.2×10-6×50×103=0.55W
=110V is a value actually measured using an oscilloscope.
V
DSS
The allowable loss range for the allowable avalanche energy value, PAVL, is shown in the graph in Figure 3.
When examining the avalanche energy, be sure to actually drive a motor and observe the I , V , and tAVL
D
DSS
waveforms during operation, and then check that the result of calculating Equation (2) falls within the allowable
range for avalanche operations.
No. A1590-14/19
STK672-732A-E
(2) I
V
Operating Waveforms in Non-avalanche Mode
D and DSS
Although the waveforms during avalanche mode are given in Figure 1, sometimes an avalanche does not result during
actual operations.
Factors causing avalanche are listed below.
• Poor coupling of the motor’s phase coils (electromagnetic coupling of A phase and AB phase, B phase and
BB phase).
• Increase in the lead inductance of the harness caused by the circuit pattern of the P.C. board and motor.
• Increases in V
, tAVL, and IAVL in Figure 1 due to an increase in the supply voltage from 24V to 36V.
DSS
If the factors above are negligible, the waveforms shown in Figure 1 become waveforms without avalanche as
shown in Figure 2.
Under operations shown in Figure 2, avalanche does not occur and there is no need to consider the allowable loss
range of PAVL shown in Figure 3.
V
DS
I : Motor current peak value
OH
I
D
ITF02558
Figure 2 Output Current, I , and Voltage, V , Waveforms 2 of the STK672-7** Series when Driving a
DS
D
2-Phase Stepping Motor with Constant Current Chopping
Figure 3 Allowable Loss Range, PAVL-I
OH
During Avalanche Operations
PAVL - I
OH
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
0.5
1.0
1.5
2.0
2.5
Motor phase current, I
OH
- A
ITF02573
Note:
The operating conditions given above represent a loss when driving a 2-phase stepping motor with constant current
chopping.
Because it is possible to apply 2.6W or more at I =0A, be sure to avoid using the MOSFET body diode that is used
OH
to drive the motor as a zener diode.
No. A1590-15/19
STK672-732A-E
5. Thermal design
[Operating range in which a heat sink is not used]
Use of a heat sink to lower the operating substrate temperature of the HIC (Hybrid IC) is effective in increasing the
quality of the HIC.
The size of heat sink for the HIC varies depending on the magnitude of the average power loss, PdAV, within the
HIC. The value of PdAV increases as the output current increases. To calculate PdAV, refer to “Calculating Internal
HIC Loss for the STK672-732A-E”.
Calculate the internal HIC loss, PdAV, assuming repeat operation such as shown in Figure 1 below, since conduction
during motor rotation and off time both exist during actual motor operations.
I 1
O
Motor phase current
(sink side)
I 2
O
0A
-I 1
O
T1
T3
T2
T0
Figure 1 Motor Current Timing
T1: Motor rotation operation time
T2: Motor hold operation time
T3: Motor current off time
T2 may be reduced, depending on the application.
T0: Single repeated motor operating cycle
I 1 and I 2: Motor current peak values
O
O
Due to the structure of motor windings, the phase current is a positive and negative current with a pulse form.
Note that figure 1 presents the concepts here, and that the on/off duty of the actual signals will differ.
The hybrid IC internal average power dissipation PdAV can be calculated from the following formula.
PdAV= (T1×P1+T2×P2+T3×0) ÷TO ---------------------------- (I)
(Here, P1 is the PdAV for I 1 and P2 is the PdAV for I 2)
O
O
If the value calculated using Equation (I) is 1.5W or less, and the ambient temperature, Ta, is 60°C or less, there is no
need to attach a heat sink. Refer to Figure 2 for operating substrate temperature data when no heat sink is used.
[Operating range in which a heat sink is used]
Although a heat sink is attached to lower Tc if PdAV increases, the resulting size can be found using the value of
θc-a in Equation (II) below and the graph depicted in Figure 3.
θc-a= (Tc max-Ta) ÷PdAV ---------------------------- (II)
Tc max: Maximum operating substrate temperature =105°C
Ta: HIC ambient temperature
Although a heat sink can be designed based on equations (I) and (II) above, be sure to mount the HIC in a set and
confirm that the substrate temperature, Tc, is 105°C or less.
The average HIC power loss, PdAV, described above represents the power loss when there is no avalanche operation.
To add the loss during avalanche operations, be sure to add Equation (2), “Allowable STK672-7** Avalanche
Energy Value”, to PdAV.
No. A1590-16/19
STK672-732A-E
Figure 2 Substrate temperature rise, ΔTc (no heat sink) - Internal average power dissipation, PdAV
ΔTc - PdAV
80
70
60
50
40
30
20
10
0
0
0.5
1.0
1.5
2.0
2.5
3.0
Hybrid IC internal average power dissipation, PdAV - W
ITF02717
Figure 3 Heat sink area (Board thickness: 2mm) - θc-a
θc-a - S
100
7
5
3
2
10
7
5
3
2
1.0
10
2
3
5
7
2
3
5
7
1000
100
Heat sink area, S - cm2
ITF02554
6. Mitigated Curve of Package Power Loss, PdPK, vs. Ambient Temperature, Ta
Package power loss, PdPK, refers to the average internal power loss, PdAV, allowable without a heat sink.
The figure below represents the allowable power loss, PdPK, vs. fluctuations in the ambient temperature, Ta.
Power loss of up to 2.8W is allowable at Ta=25°C, and of up to 1.5W at Ta=60°C.
Allowable power dissipation, PdPK (no heat sink) - Ambient temperature, Ta
PdPK - Ta
3.0
2.5
2.0
1.0
1.5
0.5
0
0
20
40
60
80
100
120
Ambient Temperature, Ta - °C
ITF02718
No. A1590-17/19
STK672-732A-E
7. Example of Stepping Motor Driver Output Current Path (1-2 phase excitation)
2-phase stepping motor driver
I AB
O
I A
O
N.C
N.C
A
AB
F2
B
BB
F4
V
DD
F3
F1
FAO
BBIN
V
CC
24V
FAB
FBO
BIN
ABIN
FBB
AIN
R1
R2
Latch
OCD
Power on
reset
C02
at least 100μF
P.G2
P.G1
AI
BI
Chopper
circuit
FAULT
signal
P.GND
Vref/4.9
Overheating
detection
Vref
SS
Latch
Amp
100kΩ
SS
V
V
V
SS
φA(Pin 13)
φAB(Pin 17)
Phase A output current
I A
O
PWM operations
When PWM operations of I A
O
are OFF, for I AB, negative
current flows through the
parasitic diode, F2.
O
Phase AB output current
I AB
O
When PWM operations of I AB are
O
OFF, for I A, negative current flows
O
through the parasitic diode, F1.
No. A1590-18/19
STK672-732A-E
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PS
No. A1590-19/19
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