SSD40N03 [SECOS]
N-Channel Enhancement Mode Power Mos.FET; N沟道增强模式电源Mos.FET
| 型号： | SSD40N03 |
| 厂家： | 
SECOS HALBLEITERTECHNOLOGIE GMBH |
| 描述： | N-Channel Enhancement Mode Power Mos.FET |
| 文件： | 总5页 (文件大小：646K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SSD40N03
36A, 30V,RDS(ON)21mΩ
Elektronische Bauelemente
N-Channel Enhancement Mode PowerMos.FET
RoHS Compliant Product
Description
TO-252
The SSD40N03 provide the designer with the best combination
of fast switching, ruggedized device design, low on-resistance
and cost-effectiveness.
The TO-252 is universally preferred for all commercial-industrial
surface mount applications and suited for low voltage applications
such as DC/DC converters.
Features
* Repetitive Avalanche Rated
* Dynamic dv/dt Rating
* Simple Drive Requirement
* Fast Switching
D
Millimeter
Millimeter
Min.
0.50
2.20
0.45
0
0.90
5.40
0.80
REF.
REF.
Min.
Max.
6.80
5.50
7.20
2.80
Max.
0.70
2.40
0.55
0.15
1.50
5.80
1.20
A
B
C
D
E
F
6.40
5.20
6.80
2.20
G
H
J
K
L
G
2.30 REF.
0.70
0.60
0.90
0.90
M
R
S
S
Absolute Maximum Ratings
Parameter
Drain-Source Voltage
Symbol
VDS
Ratings
Unit
V
30
± 20
36
Gate-Source Voltage
VGS
V
A
ID@TC=25oC
Continuous Drain Current,VGS@10V
o
Continuous Drain Current,VGS@10V
C
25
ID@TC=100
A
A
Pulsed Drain Current1
Total Power Dissipation
150
50
IDM
oC
PD@TC=25
W
W/oC
oC
Linear Derating Factor
0.4
Operating Junction and Storage Temperature Range
-55~+150
Tj, Tstg
Thermal Data
Parameter
Symbol
Rthj-c
Ratings
2.5
Unit
o
C /W
Max.
Max.
Thermal Resistance Junction-case
oC /W
110
Rthj-a
Thermal Resistance Junction-ambient
http://www.SeCoSGmbH.com/
Any changing of specification will not be informed individual
01-Jun-2002 Rev. A
Page 1 of 5
SSD40N03
36A, 30V,RDS(ON)21mΩ
Elektronische Bauelemente
N-Channel Enhancement Mode PowerMos.FET
Electrical Characteristics( Tj=25oC Unless otherwise specified)
Parameter
Symbol
Max.
Min.
Typ.
Unit
Test Condition
_
_
V
VGS=0V, ID=250uA
30
_
BVDSS
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Gate Threshold Voltage
Reference to 25oC, ID=1mA
V/oC
V
BVDS/ Tj
0.037
_
VGS(th)
1.0
_
VDS=VGS, ID=250uA
VGS= 20V
3.0
100
25
_
nA
uA
uA
IGSS
Gate-Source Leakage Current
o
_
_
VDS=30V,VGS=0
C
Drain-Source Leakage Current (Tj=25 )
IDSS
o
_
_
_
C
Drain-Source Leakage Current(Tj=150 )
VDS=24V,VGS=0
250
VGS=10V, ID=18A
VGS=4.5V, ID=14A
18
24
17
21
30
Static Drain-Source On-Resistance
mΩ
RDS(ON)
_
_
Total Gate Charge2
_
_
Qg
ID=18A
_
_
VDS=24V
VGS= 5V
nC
Gate-Source Charge
Gate-Drain ("Miller") Charge
Qgs
3
_
_
Qgd
Td(ON)
Tr
10
7.2
Turn-on Delay Time2
Rise Time
_
_
VDD=15V
ID=18A
_
_
_
60
VGS=10V
nS
_
Ω
RG=3.3
Td(Off)
Turn-off Delay Time
Fall Time
22.5
Ω
RD=0.83
_
_
_
_
T
f
10
_
_
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
800
Ciss
Coss
Crss
VGS=0V
VDS=25V
f=1.0MHz
pF
S
380
133
26
_
_
_
VDS=10V, ID=18A
Gfs
Forward Transconductance
Source-Drain Diode
Parameter
Symbol
Max.
1.3
Min.
Typ.
Unit
Test Condition
o
_
_
Forward On Voltage2
VSD
V
IS=36 A, VGS=0V.Tj=25C
_
_
_
IS
36
Continuous Source Current(Body Diode)
Pulsed Source Current(Body Diode)1
A
A
VD=VG=0V,VS=1.3 V
_
150
ISM
Notes:
1.
2.
Pulse width limited by safe operating area.
≦
≦
Pulse width 300us, dutycycle 2%.
http://www.SeCoSGmbH.com/
Any changing of specification will not be informed individual
01-Jun-2002 Rev. A
Page 2 of 5
SSD40N03
36A, 30V,RDS(ON)21mΩ
Elektronische Bauelemente
N-Channel Enhancement Mode PowerMos.FET
Characteristics Curve
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
Fig 3. On-Resistance v.s. Gate Voltage
Fig 4. Normalized On-Resistance
v.s. Junction Temperature
Fig 5. Maximum Drain Current
v.s. Case Temperature
Fig 6. Type Power Dissipation
http://www.SeCoSGmbH.com/
Any changing of specification will not be informed individual
01-Jun-2002 Rev. A
Page 3 of 5
SSD40N03
36A, 30V,RDS(ON)21mΩ
Elektronische Bauelemente
N-Channel Enhancement Mode PowerMos.FET
Fig 7. Maximum Safe Operating Area Fig 8. Effective Transient Thermal Impedance
Fig 10. Typical Capacitance Characteristics
Fig 9. Gate Charge Characteristics
Fig 11. Forward Characteristics of
Reverse Diode
Fig 12. Gate Threshold Voltage v.s.
Junction Temperature
http://www.SeCoSGmbH.com/
Any changing of specification will not be informed individual
01-Jun-2002 Rev. A
Page 4 of 5
SSD40N03
36A, 30V,RDS(ON)21mΩ
Elektronische Bauelemente
N-Channel Enhancement Mode PowerMos.FET
Fig 13. Switching Time Circuit
Fig 14. Switching Time Waveform
Fig 15. Gate Charge Circuit
Fig 16. Gate Charge Waveform
http://www.SeCoSGmbH.com/
01-Jun-2002 Rev. A
Any changing of specification will not be informed individual
Page 5 of 5
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