E0C62L33D [SEIKO]
4-BIT, MROM, 0.032768MHz, MICROCONTROLLER, UUC, DIE;
| 型号： | E0C62L33D |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | 4-BIT, MROM, 0.032768MHz, MICROCONTROLLER, UUC, DIE 时钟 外围集成电路 |
| 文件： | 总10页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PF592-05
E0C6233
4-bit Single Chip Microcomputer
● Core CPU Architecture
● SVD Circuit/Comparator
● Event Counter
■ DESCRIPTION
The E0C6233 is an advanced single-chip CMOS 4-bit microcomputer consisting of the E0C6200 4-bit core
CPU. It also contains the ROM, RAM, LCD driver, event counter, SVD circuit, stopwatch counter and time base
counter. With wide voltage range and low power consumption, the E0C6233 provides an excellent solution for
the low-power consumption systems with manganese dry cell.
■ FEATURES
● CMOS LSI 4-bit parallel processing
● Clock .....................................................32.768kHz (Typ.)/500kHz (Typ.) (selectable by software)
● Instruction set........................................108 instructions
● Instruction cycle time ............................153µsec, 214µsec or 366µsec at 32kHz
(depending on instruction)
10µsec, 14µsec or 24µsec at 500kHz
(depending on instruction)
● ROM capacity .......................................3,072 × 12 bits
● RAM capacity ........................................256 × 4 bits
● Input port ...............................................5 bits (pull-down resistors are available by mask option)
● Output port ............................................4 bits (general purpose)
2 bits (buzzer output): BZ, BZ
1 bit (lamp output)
1 bit (clock output)
● I/O port ..................................................8 bits
● LCD driver .............................................40 segments × 3 commons/40 segments × 4 commons
(1/3 or 1/4 duty is selectable by mask option)
● Built-in time base counter
● Built-in serial interface ..........................Clock synchronous
● Built-in stopwatch counter
● Built-in watchdog timer
● Event counter ........................................8 lines
● Built-in AMP ..........................................Operational AMP for MOS input analog comparator
● Built-in SVD...........................................1.2 ± 0.1V/2.4 ± 0.1V (supply voltage detector)
● Interrupts ...............................................External : Input interrupt
2 lines
2 lines
Internal : Timer interrupt
Serial interface interrupt 1 line
HALT mode (32kHz)
● Current consumption ............................E0C62L33
: 1.0µA (Typ.)
: 1.5µA (Typ.)
: 2.0µA (Typ.)
E0C6233
HALT mode (32kHz)
E0C62A33
HALT mode (32kHz)
OPERATING mode (500kHz) : 135µA (Typ.)
● Package ................................................QFP5-100pin (plastic)
Die form
■ LINE UP
Model
Supply voltage
1.5V (0.9V to 1.7V)
3.0V (1.8V to 3.5V)
3.0V (2.2V to 3.5V)
Clock
32kHz (Crystal oscillation)
E0C62L33
E0C6233
E0C62A33
32kHz (Crystal oscillation)
32kHz (Crystal oscillation) & 500kHz (Ceramic or CR oscillation)
SEIKO EPSON CORPORATION
1
E0C6233
■ BLOCK DIAGRAM
ROM
3,072 words x 12 bits
System Reset
Control
OSC
Core CPU E0C6200
RAM
256 words x 4 bits
Interrupt
Generator
COM0~3
SEG0~39
K00~03, K10
TEST
LCD Driver
Input Port
I/O Port
P00~03, P10~13
R00~03, R10~13
V
DD
V
L1~3
Power
Controller
Output Port
Comparator
CA~CC
VS1
AMPP
AMPM
VSS
Timer
SVD
Stop Watch
SIN
Event
Counter
SOUT
SCLK
SIOF
Serial Interface
2
E0C6233
■ PIN CONFIGURATION
No. Pin name No. Pin name No. Pin name No. Pin name
1
2
3
4
5
6
7
8
9
N.C.
N.C.
TEST
N.C.
N.C.
SEG18
SEG19
SEG20
SEG21
26 SEG38
27 SEG39
28 N.C.
29 AMPP
30 N.C.
31 AMPM
32 K10
33 K03
34 K02
35 K01
36 K00
37 P03
38 P02
39 P01
40 P00
41 P13
42 P12
43 P11
44 P10
45 R03
46 R02
47 N.C.
48 R01
49 R00
50 R12
51 N.C.
52 N.C.
53 N.C.
54 N.C.
55 R11
56 R10
57 R13
58 VSS
59 RESET
60 OSC4
61 OSC3
62 VS1
63 OSC2
64 OSC1
65 VDD
66 VL3
67 VL2
68 VL1
69 CC
70 CB
71 CA
72 COM3
73 COM2
74 COM1
75 COM0
76 SIOF
77 SCLK
78 N.C.
79 N.C.
80 N.C.
QFP5-100pin
80
51
81 SOUT
82 SIN
83 SEG0
84 SEG1
85 SEG2
86 SEG3
87 SEG4
88 SEG5
89 SEG6
90 SEG7
91 SEG8
92 SEG9
93 SEG10
94 SEG11
95 SEG12
96 SEG13
97 SEG14
98 SEG15
99 SEG16
100 SEG17
81
50
10 SEG22
11 SEG23
12 SEG24
13 SEG25
14 SEG26
15 SEG27
16 SEG28
17 SEG29
18 SEG30
19 SEG31
20 SEG32
21 SEG33
22 SEG34
23 SEG35
24 SEG36
25 SEG37
E0C6233
INDEX
31
100
1
30
N.C. = No Connection
■ PIN DESCRIPTION
Pin name
Pin No.
In/Out
Function
V
V
V
V
V
V
DD
SS
S1
L1
L2
L3
65
58
62
68
67
66
69–71
64
I
I
Power source (+) terminal
Power source (-) terminal
O
O
O
O
–
Oscillation and internal logic system regulated voltage output terminal
LCD system regulated voltage output terminal (approx. -1.05 V)
LCD system booster output terminal (VL1 x 2)
LCD system booster output terminal (VL1 x 3)
Booster capacitor connecting terminal
CA–CC
OSC1
I
Crystal oscillation input terminal
OSC2
OSC3
OSC4
K00–K03, K10
P00–P03, P10–P13
R00–R03
R10
R13
R11
R12
AMPP
AMPM
SEG0–39
COM0–3
SIN
63
61
60
32–36
O
I
O
I
I/O
O
O
O
O
O
I
Crystal oscillation output terminal
Ceramic or CR oscillation input terminal (Switchable by mask option, 62A33 only)
Ceramic or CR oscillation output terminal (Switchable by mask option, 62A33 only)
Input terminal
I/O terminal
Output terminal
Output terminal (DC or BZ output may be selected by mask option)
Output terminal (DC or BZ output may be selected by mask option)
Output terminal
Output terminal (DC or FOUT output may be selected by mask option)
Analog comparator non-inverted input terminal
Analog comparator inverted input terminal
LCD segment output terminal (Convertible to DC output by mask option)
LCD common output terminal
37–44
45, 46, 48, 49
56
57
55
50
29
31
I
6–27, 83–100
O
O
I
72–75
82
Serial interface input terminal
SOUT
SCLK
SIOF
RESET
TEST
81
77
76
59
O
I/O
O
I
Serial interface output terminal
Serial interface clock input/output terminal
Serial interface status output terminal
Initial reset input terminal
Test input terminal
3
I
3
E0C6233
■ ELECTRICAL CHARACTERISTICS
● Absolute Maximum Ratings
E0C6233/62A33
(VDD=0V)
Rating
Supply voltage
Symbol
VSS
Value
-5.0 to 0.5
Unit
V
Input voltage (1)
Input voltage (2)
Permissible total output current *1 ΣIVSS
Operating temperature
Storage temperature
Soldering temperature / Time
Permissible dissipation *2
VI
VIOSC
VSS - 0.3 to 0.5
VS1 - 0.3 to 0.5
10
-20 to 70
-65 to 150
V
V
mA
°C
°C
–
Topr
Tstg
Tsol
PD
260°C, 10sec (lead section)
250
mW
1: The permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pins (or is draw in).
2: In case of plastic package (QFP5-100pin).
E0C62L33
(VDD=0V)
Rating
Supply voltage
Symbol
VSS
Value
-2.0 to 0.5
Unit
V
Input voltage (1)
Input voltage (2)
Permissible total output current *1 ΣIVSS
Operating temperature
Storage temperature
Soldering temperature / Time
Permissible dissipation *2
VI
VIOSC
VSS - 0.3 to 0.5
VS1 - 0.3 to 0.5
10
-20 to 70
-65 to 150
V
V
mA
°C
°C
–
Topr
Tstg
Tsol
PD
260°C, 10sec (lead section)
250
mW
1: The permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pins (or is draw in).
2: In case of plastic package (QFP5-100pin).
● Recommended Operating Conditions
E0C6233
(Ta=-20 to 70°C)
Condition
Supply voltage
Oscillation frequency
Symbol
Remark
Min.
-3.5
–
Typ.
-3.0
32.768
Max.
-1.8
–
Unit
V
kHz
V
SS
VDD=0V
f
OSC1
E0C62L33
(Ta=-20 to 70°C)
Condition
Supply voltage
Symbol
VSS
Remark
Min.
-1.7
-1.7
-1.7
–
Typ.
-1.5
-1.5
-1.5
32.768
Max.
-1.1
-0.9 *2
-1.2
–
Unit
V
V
V
kHz
VDD=0V
VDD=0V, With software control *1
VDD=0V, When the analog comparator is used
Oscillation frequency
fOSC1
1: When switching to heavy load protection mode. Note, however, that the ON time for SVD in the heavy load protection must be limited
to 10 msec per second of operation time.
2: The possibility of LCD panel display differs depending on the characteristics of the LCD panel.
E0C62A33
(Ta=-20 to 70°C)
Condition
Supply voltage
Oscillation frequency (1)
Oscillation frequency (2)
Symbol
VSS
fOSC1
Remark
Min.
-3.5
–
Typ.
-3.0
32.768
500
Max.
-2.2
–
Unit
V
kHz
kHz
VDD=0V
fOSC3 duty 50±5%
50
600
4
E0C6233
● DC Characteristics
E0C6233/62A33
(Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25°C, VS1/VL1–VL3 are internal voltage, C1–C6=0.1µF)
Characteristic
High level input voltage (1)
Symbol
VIH1
Condition
Min.
Typ.
Max.
0
Unit
V
K00–03, K10, P00–03, P10–13 0.2•VSS
SIN, SCLK
High level input voltage (2)
Low level input voltage (1)
VIH2
VIL1
RESET, TEST
K00–03, K10, P00–03, P10–13
SIN, SCLK
0.1•VSS
VSS
0
V
V
0.8•VSS
Low level input voltage (2)
High level input current (1)
VIL2
IIH1
RESET, TEST
K00–03, K10, P00–03, P10–13
VSS
0
0.9•VSS
0.5
V
µA
VIH1=0V
No pull down resistor SIN, SCLK, AMPP, AMPM
High level input current (2)
High level input current (3)
Low level input current
IIH2
IIH3
IIL
VIH2=0V
With pull down resistor
VIH3=0V
With pull down resistor RESET, TEST
VIL=VSS
K00–03, K10
4
16
100
0
µA
µA
µA
P00–03, P10–13
25
K00–03, K10, P00–03, P10–13
-0.5
SIN, SCLK, AMPP, AMPM
RESET, TEST
High level output current (1)
High level output current (2)
IOH1
IOH2
VOH1=0.1•VSS
VOH2=0.1•VSS
R10, R11, R13
-1.8
-0.9
mA
mA
R00–03, R12, P00–03, P10–13
SOUT, SIOF, SCLK
R10, R11, R13
R00–03, R12, P00–03, P10–13
SOUT, SIOF, SCLK
COM0–COM3
Low level output current (1)
Low level output current (2)
IOL1
IOL2
VOL1=0.9•VSS
VOL2=0.9•VSS
6.0
3.0
mA
mA
Common output current
IOH3
IOL3
IOH4
IOL4
IOH5
IOL5
VOH3=-0.05V
VOL3=VL3+0.05V
VOH4=-0.05V
VOL4=VL3+0.05V
VOH5=0.1•VSS
VOL5=0.9•VSS
-3
-3
µA
µA
µA
µA
µA
µA
3
3
Segment output current
(during LCD output)
Segment output current
(during DC output)
SEG0–SEG39
SEG0–SEG39
-200
200
E0C62L33
(Unless otherwise specified: VDD=0V, VSS=-1.5V, fOSC1=32.768kHz, Ta=25°C, VS1/VL1–VL3 are internal voltage, C1–C6=0.1µF)
Characteristic
High level input voltage (1)
Symbol
VIH1
Condition
Min.
Typ.
Max.
0
Unit
V
K00–03, K10, P00–03, P10–13 0.2•VSS
SIN, SCLK
High level input voltage (2)
Low level input voltage (1)
VIH2
VIL1
RESET, TEST
K00–03, K10, P00–03, P10–13
SIN, SCLK
0.1•VSS
VSS
0
V
V
0.8•VSS
Low level input voltage (2)
High level input current (1)
VIL2
IIH1
RESET, TEST
K00–03, K10, P00–03, P10–13
VSS
0
0.9•VSS
0.5
V
µA
VIH1=0V
No pull down resistor SIN, SCLK, AMPP, AMPM
High level input current (2)
High level input current (3)
Low level input current
IIH2
IIH3
IIL
VIH2=0V
With pull down resistor
VIH3=0V
With pull down resistor RESET, TEST
VIL=VSS
K00–03, K10
2
10
60
0
µA
µA
µA
P00–03, P10–13
12
K00–03, K10, P00–03, P10–13
-0.5
SIN, SCLK, AMPP, AMPM
RESET, TEST
High level output current (1)
High level output current (2)
IOH1
IOH2
VOH1=0.1•VSS
VOH2=0.1•VSS
R10, R11, R13
-300
-150
µA
µA
R00–03, R12, P00–03, P10–13
SOUT, SIOF, SCLK
R10, R11, R13
R00–03, R12, P00–03, P10–13
SOUT, SIOF, SCLK
COM0–COM3
Low level output current (1)
Low level output current (2)
IOL1
IOL2
VOL1=0.9•VSS
VOL2=0.9•VSS
1,400
700
µA
µA
Common output current
IOH3
IOL3
IOH4
IOL4
IOH5
IOL5
VOH3=-0.05V
VOL3=VL3+0.05V
VOH4=-0.05V
VOL4=VL3+0.05V
VOH5=0.1•VSS
VOL5=0.9•VSS
-3
-3
µA
µA
µA
µA
µA
µA
3
3
Segment output current
(during LCD output)
Segment output current
(during DC output)
SEG0–SEG39
SEG0–SEG39
-100
100
5
E0C6233
● Analog Circuit Characteristics and Current Consumption
E0C6233 (Normal Mode)
(Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25°C, CG=25pF, VS1/VL1–VL3 are internal voltage, C1–C6=0.1µF)
Characteristic
Internal voltage
Symbol
Condition
Min.
-1.15
Typ.
-1.05
Max.
-0.95
Unit
V
V
V
V
V
L1
Connect 1MΩ load resistor between VDD and VL1
(without panel load)
Connect 1MΩ load resistor between VDD and VL2
(without panel load)
Connect 1MΩ load resistor between VDD and VL3
(without panel load)
L2
2•VL1
-0.1
3•VL1
-0.1
2•VL1
×0.9
3•VL1
×0.9
-2.25
100
V
V
L3
SVD voltage
SVD
-2.55
-2.40
V
µS
V
SVD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
t
SVD
V
V
V
IP
Noninverted input (AMPP)
Inverted input (AMPM)
V
SS+0.3
VDD-0.9
IM
OF
10
mV
mS
Analog comparator
response time
t
AMP
V
IP=-1.5V, VIM=VIP±15mV
3
Current consumption
I
OP
During HALT
During operation *1
1.5
6.0
4.0
10.0
µA
µA
Without panel load
1: The SVD circuit and analog comparator are in the OFF status.
E0C6233 (Heavy Load Protection Mode)
(Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25°C, CG=25pF, VS1/VL1–VL3 are internal voltage, C1–C6=0.1µF)
Characteristic
Internal voltage
Symbol
Condition
Min.
-1.15
Typ.
-1.05
Max.
-0.95
Unit
V
V
V
V
V
L1
Connect 1MΩ load resistor between VDD and VL1
(without panel load)
Connect 1MΩ load resistor between VDD and VL2
(without panel load)
Connect 1MΩ load resistor between VDD and VL3
(without panel load)
L2
2•VL1
-0.1
3•VL1
-0.1
2•VL1
×0.9
3•VL1
×0.9
-2.25
100
V
V
L3
SVD voltage
SVD
-2.55
-2.40
V
µS
V
SVD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
t
SVD
V
V
V
IP
Noninverted input (AMPP)
Inverted input (AMPM)
V
SS+0.3
VDD-0.9
IM
OF
10
mV
mS
Analog comparator
response time
t
AMP
V
IP=-1.5V, VIM=VIP±15mV
3
Current consumption
I
OP
During HALT
During operation *1
11.2
14.5
34.0
40.0
µA
µA
Without panel load
1: The SVD circuit is in the ON status (HVLD="1", SVDON="0"). The analog comparator is in the OFF status.
E0C62L33 (Normal Mode)
(Unless otherwise specified: VDD=0V, VSS=-1.5V, fOSC1=32.768kHz, Ta=25°C, C
Characteristic Symbol Condition
Internal voltage
G=25pF, VS1/VL1–VL3 are internal voltage, C1–C6=0.1µF)
Min.
-1.15
Typ.
-1.05
Max.
-0.95
Unit
V
V
V
V
V
L1
Connect 1MΩ load resistor between VDD and VL1
(without panel load)
L2
Connect 1MΩ load resistor between VDD and VL2
(without panel load)
2•VL1
-0.1
3•VL1
-0.1
2•VL1
×0.9
3•VL1
×0.9
-1.10
100
V
V
L3
Connect 1MΩ load resistor between VDD and VL3
(without panel load)
SVD voltage
SVD
-1.30
-1.20
V
µS
V
SVD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
t
SVD
V
V
V
IP
Noninverted input (AMPP)
Inverted input (AMPM)
V
SS+0.3
VDD-0.9
IM
OF
20
mV
mS
Analog comparator
response time
t
AMP
V
IP=-1.1V, VIM=VIP±30mV
3
Current consumption
I
OP
During HALT
During operation *1
1.0
3.0
3.0
8.0
µA
µA
Without panel load
1: The SVD circuit and analog comparator are in the OFF status.
6
E0C6233
E0C62L33 (Heavy Load Protection Mode)
(Unless otherwise specified: VDD=0V, VSS=-1.5V, fOSC1=32.768kHz, Ta=25°C, C
G
=25pF, VS1/VL1–VL3 are internal voltage, C1–C6=0.1µF)
Characteristic
Internal voltage
Symbol
Condition
Min.
-1.15
Typ.
-1.05
Max.
-0.95
Unit
V
V
V
V
V
L1
Connect 1MΩ load resistor between VDD and VL1
(without panel load)
Connect 1MΩ load resistor between VDD and VL2
(without panel load)
Connect 1MΩ load resistor between VDD and VL3
(without panel load)
L2
2•VL1
-0.1
3•VL1
-0.1
2•VL1
×0.85
3•VL1
×0.85
-1.10
100
V
V
L3
SVD voltage
SVD
-1.30
-1.20
V
µS
V
SVD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
t
SVD
V
V
V
IP
Noninverted input (AMPP)
Inverted input (AMPM)
V
SS+0.3
V
DD-0.9
IM
OF
20
mV
mS
Analog comparator
response time
t
AMP
V
IP=-1.1V, VIM=VIP±30mV
3
Current consumption
I
OP
During HALT *1
During operation *1
2.0
8.0
7.0
18.0
µA
µA
Without panel load
1: The SVD circuit is in the ON status (HVLD="1", SVDON="0"). The analog comparator is in the OFF status.
E0C62A33 (Normal Mode)
(Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25°C, C
Characteristic Symbol Condition
Internal voltage
G=25pF, VS1/VL1–VL3 are internal voltage, C1–C6=0.1µF)
Min.
-1.15
Typ.
-1.05
Max.
-0.95
Unit
V
V
V
V
V
L1
Connect 1MΩ load resistor between VDD and VL1
(without panel load)
L2
Connect 1MΩ load resistor between VDD and VL2
(without panel load)
2•VL1
-0.1
3•VL1
-0.1
2•VL1
×0.9
3•VL1
×0.9
-2.25
100
V
V
L3
Connect 1MΩ load resistor between VDD and VL3
(without panel load)
SVD voltage
SVD
-2.55
-2.40
V
µS
V
SVD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
t
SVD
V
V
V
IP
Noninverted input (AMPP)
Inverted input (AMPM)
V
SS+0.3
V
DD-0.9
IM
OF
10
mV
mS
Analog comparator
response time
t
AMP
V
IP=-1.5V, VIM=VIP±15mV
3
Current consumption
I
OP
During HALT
During operation at 32kHz *1
During operation at 500kHz *1 Without panel load
Without panel load
OSCC="0"
2.0
8.0
135
5.0
15.0
300
µA
µA
µA
1: The SVD circuit and analog comparator are in the OFF status.
E0C62A33 (Heavy Load Protection Mode)
(Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25°C, CG=25pF, VS1/VL1–VL3 are internal voltage, C1–C6=0.1µF)
Characteristic
Internal voltage
Symbol
Condition
Min.
-1.15
Typ.
-1.05
Max.
-0.95
Unit
V
V
V
V
V
L1
Connect 1MΩ load resistor between VDD and VL1
(without panel load)
Connect 1MΩ load resistor between VDD and VL2
(without panel load)
Connect 1MΩ load resistor between VDD and VL3
(without panel load)
L2
2•VL1
-0.1
3•VL1
-0.1
2•VL1
×0.9
3•VL1
×0.9
-2.25
100
V
V
L3
SVD voltage
SVD
-2.55
-2.40
V
µS
V
SVD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
t
SVD
V
V
V
IP
Noninverted input (AMPP)
Inverted input (AMPM)
V
SS+0.3
V
DD-0.9
IM
OF
10
mV
mS
Analog comparator
response time
t
AMP
V
IP=-1.5V, VIM=VIP±15mV
3
Current consumption
I
OP
During HALT
During operation at 32kHz *1
During operation at 500kHz *1 Without panel load
Without panel load
OSCC="0"
11.5
16.0
130
35.0
45.0
330
µA
µA
µA
1: The SVD circuit is in the ON status (HVLD="1", SVDON="0"). The analog comparator is in the OFF status.
7
E0C6233
● Oscillation Characteristics
The oscillation characteristics change depending on the conditions (components used, board pattern, etc.). Use the follow-
ing characteristics as reference values.
E0C6233 (Crystal oscillation circuit)
(Unless otherwise specified: VDD=0V, VSS=-3.0V, Crystal: C-002R (C
I
=35kΩ), C
G
=25pF, CD=built-in, Ta=25°C)
Characteristic
Oscillation start voltage
Oscillation stop voltage
Built-in capacitance (drain)
Frequency/voltage deviation
Frequency/IC deviation
Frequency adjustment range
Harmonic oscillation start voltage
Permitted leak resistance
Symbol
Vsta
Vstp
Condition
Min.
-1.8
-1.8
Typ.
Max.
Unit
V
V
t
t
sta≤5sec
stp≤10sec
(VSS
(VSS
)
)
C
D
Including the parasitic capacity inside the IC
18
45
pF
∂f/∂V
∂f/∂IC
V
SS=-1.8 to -3.5V
=5 to 25pF
Between OSC1 and VDD, VSS
5
10
ppm
ppm
ppm
V
-10
35
∂f/∂CG
CG
V
hho
(VSS
)
-3.5
Rleak
200
MΩ
E0C62L33 (Crystal oscillation circuit)
(Unless otherwise specified: VDD=0V, VSS=-1.5V, Crystal: C-002R (CI=35kΩ), CG=25pF, CD=built-in, Ta=25°C)
Characteristic
Oscillation start voltage
Oscillation stop voltage
Built-in capacitance (drain)
Frequency/voltage deviation
Frequency/IC deviation
Frequency adjustment range
Symbol
Vsta
Vstp
CD
∂f/∂V
∂f/∂IC
Condition
Min.
-1.1
Typ.
Max.
Unit
V
V
tsta≤5sec
(VSS)
tstp≤10sec
(VSS) -1.1(-0.9)*1
Including the parasitic capacity inside the IC
VSS=-1.1 to -1.7V (-0.9) *1
18
pF
5
10
ppm
ppm
ppm
V
-10
∂f/∂CG CG=5 to 25pF
35
(VSS)
45
Harmonic oscillation start voltage Vhho
Permitted leak resistance
-1.7
Rleak
Between OSC1 and VDD, VSS
200
MΩ
1: Items enclosed in parentheses ( ) are those used when operating at heavy load protection mode.
Note, however, that the ON time for SVD must be limited to 10 msec per second of operation time.
E0C62A33 (Crystal oscillation circuit)
(Unless otherwise specified: VDD=0V, VSS=-3.0V, Crystal: C-002R (C
I
=35kΩ), C
G
=25pF, CD=built-in, Ta=25°C)
Characteristic
Oscillation start voltage
Oscillation stop voltage
Built-in capacitance (drain)
Frequency/voltage deviation
Frequency/IC deviation
Frequency adjustment range
Harmonic oscillation start voltage
Permitted leak resistance
Symbol
Vsta
Vstp
Condition
Min.
-2.2
-2.2
Typ.
Max.
Unit
V
V
t
t
sta≤5sec
stp≤10sec
(VSS
(VSS
)
)
C
D
Including the parasitic capacity inside the IC
18
45
pF
∂f/∂V
∂f/∂IC
V
SS=-2.2 to -3.5V
=5 to 25pF
Between OSC1 and VDD, VSS
5
10
ppm
ppm
ppm
V
-10
35
∂f/∂CG
CG
V
hho
(VSS
)
-3.5
Rleak
200
MΩ
E0C62A33 (CR oscillation circuit)
(Unless otherwise specified: VDD=0V, VSS=-3.0V, RCR=82kΩ, Ta=25°C)
Characteristic
Oscillation frequency dispersion
Oscillation start voltage
Oscillation start time
Symbol
Condition
Min.
-30
-2.2
Typ.
430kHz
Max.
30
Unit
%
V
mS
V
f
OSC3
Vsta
sta
Vstp
(VSS
(VSS
)
)
t
V
SS=-2.2 to -3.5V
3
Oscillation stop voltage
-2.2
E0C62A33 (Ceramic oscillation circuit)
(Unless otherwise specified: VDD=0V, VSS=-3.0V, ceramic oscillation: 500kHz, CGC=CDC=100pF, Ta=25°C)
Characteristic
Oscillation start voltage
Oscillation start time
Symbol
Vsta
tsta
Vstp
Condition
Min.
-2.2
Typ.
Max.
Unit
V
mS
V
(VSS)
(VSS)
VSS=-2.2 to -3.5V
5
Oscillation stop voltage
-2.2
8
E0C6233
■ BASIC EXTERNAL CONNECTION DIAGRAM
LCD PANEL
C1
CC
~
~
C2
CB
CA
K00~K03
K10
I
C3
C4
C5
VL1
VL2
VL3
VDD
P00~P03
P10~P13
I/O
CGX
X'tal
OSC1
1.5V
(E0C62L33)
or
3.0V
(E0C6233)
O
I
SIOF
SIN
E0C
LCD PANEL
OSC2
VS1
C6
SCLK 6233/62L33
I/O
O
C1
C2
CC
CB
CA
SOUT
OSC3
OSC4
N.C.
N.C.
~
~
K00~K03
K10
AMPM
AMPP
I
C3
C4
C5
VL1
VL2
VL3
VDD
RESET
+CP
P00~P03
P10~P13
R00~R03
O
TEST
Vss
I/O
CGX
X'tal
OSC1
O
I
SIOF
SIN
Piezo
OSC2
VS1
E0C62A33
C6
SCLK
SOUT
LAMP
I/O
O
CGC
RCR
OSC3
1
3.0V
2
CR
CDC
AMPM
AMPP
OSC4
X'tal
Crystal oscillator 32.768kHz, CI(Max.)=35kΩ
Trimmer capacitor 5~25pF
RESET
CGX
R00~R03
O
+ CP
TEST
Vss
CR
Ceramic oscillator 500kHz
C
C
R
GC
Gate capacitance 100pF
1 Ceramic oscillation
2 CR oscillation
Piezo
DC
CR
Drain capacitance 100pF
LAMP
Resistance for
CR oscillation
82kΩ
C1~C6
CP
0.1µF
3.3µF
Note: The above table is simply an example, and is not guaranteed
to work.
■ PACKAGE DIMENSIONS
Plastic QFP5-100pin
25.6±0.4
20±0.1
80
51
81
50
INDEX
31
100
1
30
0.65
0.3±0.1
0.15±0.05
0°
12°
1.5
2.8
Unit: mm
9
E0C6233
NOTICE:
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© Seiko Epson Corporation 1999 All right reserved.
SEIKO EPSON CORPORATION
ELECTRONIC DEVICES MARKETING DIVISION
IC Marketing & Engineering Group
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421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone : 042-587-5812 FAX : 042-587-5564
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Phone : 042-587-5814 FAX : 042-587-5110
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