MG-5100SA [SEIKO]
100MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO14, ROHS COMPLIANT, SO-14;
| 型号： | MG-5100SA |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | 100MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO14, ROHS COMPLIANT, SO-14 时钟 光电二极管 输出元件 外围集成电路 |
| 文件： | 总1页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Crystal oscillator
MULTI-OUTPUT CRYSTAL OSCILLATOR
MG-5100SA series
Product number (Please contact us)
Q33M21SA1xxxxx00
•Frequency range
•Operating voltage
•Built-in crystal
•Thickness
:
:
:
:
:
76.9 kHz to 100 MHz
3.3 V or 5.0 V
AT crystal unit
3.2 mm Typ.
Complies with EU RoHS directive
•Lead(Pb)-free
•Available output in 8 frequencies by selecting pin
for CPU CLK.
Actual size
■
Specifications (characteristics)
Specifications
Item
Symbol
Remarks
V
DD=5.0V
76.9 kHz to 100 MHz
-0.3 V to +7.0 V
5.0 V ±0.5 V
-55 °C to +100 °C
VDD=3.3V
Output frequency range
f
0
76.9 kHz to 80 MHz Please contact us for inquiries about the available frequency.
Power source Max. supply voltage
V
DD-GND
voltage
Temperature
range
Operating voltage
VDD
STG
OPR
3.3 V ±0.3 V
Storage temperature
Operating temperature
T
Stored as bare product after unpacking
T
-20 °C to +70 °C
Frequency stability
Current consumption
Duty
∆f/f
0
±100 × 10-6
I
OP
100 mA Max.
65 mA Max.
No load, Max. frequency
50 % VDD, CL=15 pF
tw/t
40 % to 60 %
High output voltage
Low output voltage
Output condition
Output enable /
disenable input voltage
Output rise time
Output fall time
V
OH
V
DD-0.4 V Min.
0.4 V Max.
15 pF Max.
IOH=-4 mA
V
OL
IOL=4 mA
C
L
Max. frequency and Max. operating voltage
V
IH
80 % VDD Min.
V
20 % VDD Max.
5 ns Max.
tIL
20 %→80 % VDD
tR
F
4 ns Max.
80 %→20 % VDD
450 ps Max.
Cycle to Cycle jitter
Jitter
t
j
500 ps Max.
Peak to Peak jitter
Skew
t
500 ps Max
Please contact us for inquiries about details.
Time at minimum operating voltage to be 0s.
Oscillation start up time
Aging
tOskSwC
70 ms Max.
fa
±5 × 10-6 / year Max.
Ta=+25 °C,VDD=5.0 V/ 3.3 V, First year
■
Block diagram
XBUF
Pin terminal
TIN
XBUF
CPUCLK
CLKA
CLKB
CLKC
CLKD
S0
••••• Output pin of internal X’tal
••••• Output pin
PLL 1
PLL 2
PLL 3
CPUCLK
CLKA
CLKB
CLKC
CLKD
OUTPUT
MULTIPLEXER
AND
••••• Output pin
OSC.
••••• Output pin
••••• Output pin
DIVIDERS
••••• Output pin
••••• CPUCLK Output frequency select pin 0
••••• CPUCLK Output frequency select pin 1
••••• CPUCLK Output frequency select pin 2
••••• Test pin.Do not connect them to any terminals.
••••• Output control ("H"? Output ,"L"? weak pull - down)
S2
S1
S1
S2
TIN
S0
OE
OE
ROM AND LOGIC
■
External dimensions
(Unit:mm)
■
Recommended soldering pattern
(Unit:mm)
10.1 0.2
±
#14
#8
No. Pin terminal
No. Pin terminal
S1
1
2
3
4
5
6
7
14
13
12
11
10
9
VDD1
VDD2
S2
S0
CLKA
CLKB
CPUCLK
CLKD
XBUF
M5100 AB
E 935 6A
OE
CLKC
GND
TIN
#14
# 1
# 8
# 7
8
#1
#7
0.05
Min.
0.15
0.7
1.27
7.62
0.35
0.6
1.27
1.2
0
- 10
°
°
Metal may be exposed on the top or bottom of this product.
This won't affect any quality, reliability or electrical spec.
52
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