S1C62N81F_技术文档

CONTENTS

CHAPTER 1

INTRODUCTION ............................................................... I-1

1.1 Configuration ................................................................... I-1

1.2 Features .......................................................................... I-2

1.3 Block Diagram ................................................................. I-3

1.4 Pin Layout Diagram ......................................................... I-4

1.5 Pin Description ................................................................ I-5

CHAPTER 2

POWER SUPPLY AND INITIAL RESET ................................ I-6

2.1 Power Supply .................................................................. I-6

2.2 Initial Reset...................................................................... I-7

Oscillation detection circu it ...................................... I-8

Reset pin (RESET) .................................................... I-8

Sim u ltan eou s h igh in pu t to in pu t ports (K00–K03) ... I-8

In tern al register followin g in itialization ..................... I-9

2.3 Test Pin (TEST, MTEST) ................................................ I-9

CHAPTER 3

CPU, ROM, RAM ............................................................ I-10

3.1 CPU................................................................................ I-10

3.2 ROM ............................................................................... I-11

3.3 RAM ............................................................................... I-11

S1C62N81 TECHNICAL HARDWARE

EPSON

I-i

CONTENTS

CHAPTER 4

PERIPHERAL CIRCUITS AND OPERATION ...................... I-12

4.1 Memory Map .................................................................. I-12

4.2 Oscillation Circuit............................................................ I-20

Crystal oscillation circu it ......................................... I-20

CR oscillation circu it ............................................... I-21

4.3 Input Ports (K00–K03, K10) ........................................... I-22

Con figu ration of in pu t ports .................................... I-22

In pu t com parison registers an d in terru pt fu n ction .. I-23

Mask option ............................................................ I-25

Con trol of in pu t ports .............................................. I-26

4.4 Output Ports (R00–R03, R10–R12) ............................... I-29

Con figu ration of ou tpu t ports .................................. I-29

Mask option ............................................................ I-30

Con trol of ou tpu t ports ............................................ I-32

4.5 I/O Ports (P00–P03) ....................................................... I-34

Con figu ration of I/ O port ........................................ I-34

I/ O con trol register an d I/ O m ode ........................... I-35

Mask option ............................................................ I-35

Con trol of I/ O port .................................................. I-36

4.6 LCD Driver (COM0–COM3, SEG0–SEG25) .................. I-38

Con figu ration of LCD driver ..................................... I-38

Switch in g between dyn am ic an d static drive ............ I-41

Mask option (segm en t allocation )............................. I-42

Con trol of LCD driver .............................................. I-44

4.7 Clock Timer .................................................................... I-45

Con figu ration of clock tim er .................................... I-45

In terru pt fu n ction ................................................... I-46

Con trol of clock tim er .............................................. I-47

I-ii

EPSON

S1C62N81 TECHNICAL HARDWARE

CONTENTS

4.8 Stopwatch Timer ............................................................ I-50

Con figu ration of stopwatch tim er ............................ I-50

Cou n t-u p pattern .................................................... I-51

In terru pt fu n ction ................................................... I-52

Con trol of stopwatch tim er ...................................... I-53

4.9 Battery Voltage Low Detection (BLD) Circuit

and Heavy Load Protection Function ............................. I-56

Con figu ration of BLD circu it

an d h eavy load protection fu n ction .......................... I-56

Operation of BLD detection tim in g........................... I-58

Operation of h eavy load protection fu n ction ............ I-59

Con trol of BLD circu it

an d h eavy load protection fu n ction .......................... I-60

4.10 Analog Voltage Comparator ........................................... I-62

Con figu ration of an alog voltage com parator ............. I-62

Operation of an alog voltage com parator ................... I-63

Con trol of an alog voltage com parator ...................... I-64

4.11 Melody Generator........................................................... I-65

Ou tlin e of m elody gen erator .................................... I-65

Melody data ............................................................ I-84

Playin g of silen t n ote ............................................... I-87

En velope fu n ction ................................................... I-88

Playin g tem po ......................................................... I-90

Playin g m ode ........................................................... I-92

Con trol of th e m elody gen erator .............................. I-96

4.12 Interrupt and HALT ........................................................ I-100

In terru pt factors ..................................................... I-102

Specific m asks an d factor flags for in terru pt ........... I-103

In terru pt vectors an d priorities ............................... I-104

Con trol of in terru pt ................................................ I-105

S1C62N81 TECHNICAL HARDWARE

EPSON

I-iii

CONTENTS

CHAPTER 5

BASIC EXTERNAL WIRING DIAGRAM........................... I-109

CHAPTER 6

ELECTRICAL CHARACTERISTICS ................................... I-112

6.1 Absolute Maximum Rating ............................................ I-112

6.2 Recommended Operating Conditions ........................... I-113

6.3 DC Characteristics ........................................................ I-114

6.4 Analog Circuit Characteristics

and Power Current Consumption .................................. I-116

6.5 Oscillation Characteristics ............................................. I-124

CHAPTER 7

PACKAGE ..................................................................... I-126

7.1 Plastic Package (1) ....................................................... I-126

7.2 Plastic Package (2) ....................................................... I-127

7.3 Ceramic Package for Test Sample................................ I-128

CHAPTER 8

PAD LAYOUT ................................................................. I-129

8.1 Diagram of Pad Layout.................................................. I-129

8.2 S1C62N81 List of Pad Names ...................................... I-130

8.3 Pad Coordinates............................................................ I-131

I-iv

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 1: INTRODUCTION

CHAPTER 1

INTRODUCTION

Each m em ber of th e S1C62N81 Series of sin gle ch ip m icro-

com pu ters featu re a 4-bit S1C6200 core CPU, 1,024 words

of ROM (12 bits per word), 96 words of RAM (4 bits per

word), an LCD driver, 5 bits for in pu t ports (K00–K03 an d

K10), 7 bits for ou tpu t ports (R00–R03 an d R10–R12), on e 4-

bit I/ O port (P00–P03), two tim er (clock tim er an d stopwatch

tim er), an d a m elody gen erator.

Becau se of th eir low voltage operation an d low power con -

su m ption , th e S1C62N81 Series are ideal for a wide ran ge

of application s, an d are especially su itable for battery-driven

system s with a m elody.

1.1 Config ura tion

Th e S1C62N81 Series are con figu red as follows, depen din g

on th e su pply voltage an d oscillation circu its.

Table 1.1.1

Model

Supply Voltage

3.0 V

Oscillation Circuits

Configuration of the

S1C62N81 Series

S1C62N81

S1C62L81

S1C62A81

S1C62B81

Crystal

CR

1.5 V

3.0 V

1.5 V

CR

S1C62N81 TECHNICAL HARDWARE

EPSON

I-1

CHAPTER 1: INTRODUCTION

1.2 Fe a ture s

Built-in oscillation circuit

Instruction set

Crystal or CR oscillation circu it, 32.768 kHz (typ.)

100 in stru ction s

ROM capacity

1,024 words ×12 bits

RAM capacity (data RAM)

Input port

96 words × 4 bits

5 bits (Su pplem en tary pu ll-down resistors m ay be u sed *1)

Output port

7 bits (*2), 1 bit m elody ou tpu t (Piezo bu zzer can be driven

directry by m ask option )

Input/output port

LCD driver

4 bits

26 segm en ts × 4 com m on du ty (or 3 com m on du ty)

2 system s: clock tim er/ stopwatch tim er

1 ch an n el

Timer

Analog comparator

Melody generation circuit

Sin gle-ton e sou rce gen eration , 15 ton e in tervals am on g 3

octaves, 8 n otes, 2 tem pos am on g 16 types

Option al n u m ber of m elodies, with in ROM capacity (80

words)

Su pplem en tary en velope ou tpu t m ay be u sed (*1)

Piezo bu zzer can be driven directry (*1)

Battery voltage low detec-

tion circuit (BLD)

1.2 V / 2.4 V (*1)

Interrupts:

External interrupt

Internal interrupt

In pu t port in terru pt

Tim er in terru pt

2 system s

1 system

Melody in terru pt

Supply voltage

1.5 V (0.9–3.5 V) S1C62L81, S1C62B81

3.0 V (1.8–3.5 V) S1C62N81, S1C62A81

Current consumption (typ.)

1.0 µA (CLK = 32.768 kHz, wh en h alted)

3.0 µA (CLK = 32.768 kHz, wh en execu tin g)

Supply form

Note

64-pin QFP (plastic) or ch ip

*1. May be selected with mask option

*2. FOUT output is possible through mask option selections

I-2

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 1: INTRODUCTION

1.3 Bloc k Dia g ra m

System

Reset

Control

ROM

1,024x12

OSC

Core CPU S1C6200

RAM

96x4

Interrupt

Generator

COM0

|

COM3

SEG0

|

K00–K03

K10

LCD

Driver

I Port

Test Port

TEST

SEG25

MTEST

V

DD

L1

|

L3

P00–P03

I/O Port

O Port

V

CA

Power

Controller

|

CC

R00–R03

R10, R11

V

S1

SS

CMPP

CMPM

Comparator

& BLD

Timer

MO

Stop

Watch

Melody

R12

Fig. 1.3.1

Block diagram

S1C62N81 TECHNICAL HARDWARE

EPSON

I-3

CHAPTER 1: INTRODUCTION

1.4 Pin La yout Dia g ra m

48

33

49

32

Index

64

17

1

16

Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name

1

2

COM1

COM2

COM3

SEG25

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

TEST

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

N.C.

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

P01

P02

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

R00

R01

R02

R03

3

P03

4

CMPM

CMPP

MTEST

RESET

K00

5

V

S1

DD

SS

6

V

7

V

8

OSC2

OSC1

9

K01

10

11

12

13

14

15

16

K02

V

L3

L2

L1

K03

V

K10

V

R10

CC

CB

R11

R12

CA

Fig. 1.4.1

P00

MO

COM0

Pin assignment

(N.C. = No Connection)

I-4

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 1: INTRODUCTION

1.5 Pin De sc rip tion

Table 1.5.1 Pin description

Terminal Name

Pin No.

54

Input/Output

Function

V

DD

SS

S1

L1

L2

L3

(I)

O

–

Power source (+) terminal

Power source (-) terminal

V

55

V

53

Oscillation and internal logic system regulated voltage output terminal

LCD system regulated voltage output terminal (approx. -1.05V)

LCD system booster output terminal (VL1 × 2)

LCD system booster output terminal (VL1 × 3)

Booster capacitor connecting terminal

Crystal or CR oscillation input terminal

Crystal or CR oscillation output terminal

Input terminal

V

60

V

59

V

58

CA–CC

OSC1

61, 62, 63

57

I

OSC2

56

O

I

K00–K10

P00–P03

R00–R03

R10

40–44

32–35

49–52

45

I/O

O

I/O terminal

Output terminal

Output terminal (FOUT output available through mask option selection)

Ouput terminal

R11

46

R12

47

Output terminal (melody inverted output and

envelope function available through mask option selection)

Melody signal output terminal

MO

48

37

O

I

CMPP

CMPM

SEG0–25

Analog comparator non-inverted input terminal

Analog comparator inverted input terminal

LCD segment output terminal

36

I

4–17

19–30

64, 1–3

39

O

(convertible to DC output terminal by mask option)

LCD common output terminal

COM0–3

RESET

TEST

O

I

Initial setting input terminal

18

I

Test input terminal

MTEST

38

I

Melody test input terminal

S1C62N81 TECHNICAL HARDWARE

EPSON

I-5

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

CHAPTER 2

POWER SUPPLY AND INITIAL

RESET

2.1

Powe r Sup p ly

With a sin gle extern al power su pply (*1) su pplied to VDD

th rou gh VSS, th e S1C62N81 Series gen erate th e n ecessary

in tern al voltages with th e regu lated voltage circu it (<VS1> for

oscillators an d in tern al circu it, <VL1> for LCDs) an d th e

voltage booster circu it (<VL2, VL3> for LCDs).

Figu re 2.1.1 sh ows th e power su pply con figu ration .

*1 Su pply voltage: S1C62N81/ 62A81...3.0 V

S1C62L81/ 62B81...1.5 V

Note

-

External loads cannot be driven by the output voltage of the

regulated voltage circuit and voltage booster circuit.

See Chapter 6, "ELECTRICAL CHARACTERISTICS", for

voltage values.

V

DD

Internal

circuit

V

S1

Internal system

regulated voltage

circuit

VS1

Oscillation

circuit

OSC1, 2

LCD system regulated

voltage circuit

V

L1

V

L1

V

L1

V

CA

CB

CC

L2

L3

LCD system

voltage

booster circuit

COM0–3

SEG0–25

LCD driver

circuit

V

L2

L3

External

power

supply

Vss

Fig. 2.1.1

Configuration of

power supply

I-6

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

2.2 Initia l Re se t

To in itialize th e S1C62N81 Series circu its, an in itial reset

m u st be execu ted. Th ere are th ree ways of doin g th is.

(1) In itial reset by th e oscillation detection circu it

(2) Extern al in itial reset via th e RESET pin

(3) Extern al in itial reset by sim u ltan eou s h igh in pu t to pin s

K00–K03 (depen din g on m ask option )

Figu re 2.2.1 sh ows th e con figu ration of th e in itial reset

circu it.

OSC1

Oscillation

circuit

OSC2

Oscillation

detection

circuit

K00

Noise

rejection

circuit

Vss

Initial

reset

K01

K02

K03

Noise

rejection

circuit

Fig. 2.2.1

Configuration of

initial reset circuit

RESET

Vss

S1C62N81 TECHNICAL HARDWARE

EPSON

I-7

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

Th e oscillation detection circu it ou tpu ts th e in itial reset

Osc illa tion d e te c tion

c irc uit

sign al at power-on u n til th e crystal oscillation circu it starts

oscillatin g, or wh en th e crystal oscillation circu it stops

oscillatin g for som e reason .

An in itial reset can be in voked extern ally by m akin g th e

reset pin h igh . Th is h igh level m u st be m ain tain ed for at

least 5 m s (wh en oscillatin g frequ en cy, fosc = 32 kHz),

becau se th e in itial reset circu it con tain s a n oise rejection

circu it. Wh en th e reset pin goes low th e CPU begin s to

operate.

Re se t p in (RESET)

An oth er way of in vokin g an in itial reset extern ally is to in pu t

a h igh sign al sim u ltan eou sly to th e in pu t ports (K00–K03)

selected with th e m ask option . Th e specified in pu t port pin s

m u st be kept h igh for 2–4 sec (wh en oscillatin g frequ en cy

fosc = 32 kHz), becau se of th e n oise rejection circu it. Table

2.2.1 sh ows th e com bin ation s of in pu t ports (K00–K03) th at

can be selected with th e m ask option .

Sim ulta ne ous hig h

inp ut to inp ut p orts

(K00–K03)

Table 2.2.1

A

B

C

D

Not used

Input port combinations

K00*K01

K00*K01*K02

K00*K01*K02*K03

Wh en , for in stan ce, m ask option D (K00*K01*K02*K03) is

selected, an in itial reset is execu ted wh en th e sign als in pu t

to th e fou r ports K00–K03 are all h igh at th e sam e tim e.

If you u se th is fu n ction , m ake su re th at th e specified ports

do n ot go h igh at th e sam e tim e du rin g n orm al operation .

I-8

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

An in itial reset in itializes th e CPU as sh own in th e table

below.

Inte rna l re g iste r fol-

lowing initia liza tion

Table 2.2.2

Initial values

CPU Core

Name

Program counter step

Program counter page

New page pointer

Stack pointer

Signal

PCS

PCP

NPP

SP

X

Number of Bits

Setting Value

00H

8

4

8

4

1

1H

Undefined

0

Index register X

Index register Y

Register pointer

General register A

General register B

Interrupt flag

Y

RP

A

B

I

Decimal flag

D

Undefined

Zero flag

Z

Carry flag

C

Peripheral Circuits

Name

RAM

Number of Bits

Setting Value

Undefined

*1

96 × 4

26 × 4

–

Display memory

Other peripheral circuit

*1: See section 4.1, "Mem ory Map"

2.3 Te st Pin (TEST, MTEST)

Th is pin is u sed wh en IC is in spected for sh ipm en t.

Du rin g n orm al operation con n ect it to VSS.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-9

CHAPTER 3: CPU, ROM, RAM

CHAPTER 3

CPU, ROM, RAM

3.1 CPU

Th e S1C62N81 Series em ploys th e S1C6200 core CPU, so

th at register con figu ration , in stru ction s, an d so forth are

virtu ally iden tical to th ose in oth er processors in th e fam ily

u sin g th e S1C6200. Refer to th e "S1C6200/ 6200A Core

CPU Man u al" for details of th e S1C6200.

Note th e followin g poin ts with regard to th e S1C62N81

Series:

(1) Th e SLEEP operation is n ot provided, so th e SLP in stru c-

tion can n ot be u sed.

(2) Becau se th e ROM capacity is 1,024 words, 12 bits per

word, ban k bits are u n n ecessary, an d PCB an d NBP are

n ot u sed.

(3) Th e RAM page is set to 0 on ly, so th e page part (XP, YP) of

th e in dex register th at specifies addresses is in valid.

PUSH XP

PUSH YP

POP

LD

XP

POP

LD

YP

XP,r

r,XP

YP,r

r,YP

LD

I-10

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 3: CPU, ROM, RAM

3.2 ROM

Th e bu ilt-in ROM, a m ask ROM for th e program , h as a

capacity of 1,024 × 12-bit steps. Th e program area is 4

pages (0–3), each con sistin g of 256 steps (00H–FFH). After

an in itial reset, th e program start address is page 1, step

00H. Th e in terru pt vector is allocated to page l, steps 02H–

0BH.

Bank 0

00H step

01H step

02H step

Program start address

0 page

1 page

2 page

3 page

Interrupt vector area

0BH step

0CH step

Program area

FFH step

12 bits

Fig. 3.2.1

ROM configuration

3.3 RAM

Th e RAM, a data m em ory for storin g a variety of data, h as a

capacity of 96 words, 4-bit words. Wh en program m in g,

keep th e followin g poin ts in m in d:

(1) Part of th e data m em ory is u sed as stack area wh en

savin g su brou tin e retu rn addresses an d registers, so be

carefu l n ot to overlap th e data area an d stack area.

(2) Su brou tin e calls an d in terru pts take u p th ree words on

th e stack.

(3) Data m em ory 000H–00FH is th e m em ory area poin ted by

th e register poin ter (RP).

S1C62N81 TECHNICAL HARDWARE

EPSON

I-11

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

CHAPTER 4

PERIPHERAL CIRCUITS AND OPERA-

TION

Periph eral circu its (tim er, I/ O, an d so on ) of th e S1C62N81

Series are m em ory m apped. Th u s, all th e periph eral circu its

can be con trolled by u sin g m em ory operation s to access th e

I/ O m em ory. Th e followin g section s describe h ow th e pe-

riph eral circu its operate.

4.1 Me m ory Ma p

Th e data m em ory of th e S1C62N81 Series h as an address

space of 154 words, of wh ich 32 words are allocated to

display m em ory an d 26 words, to I/ O m em ory. Figu re 4.1.1

sh ow th e overall m em ory m as for th e S1C62N81 Series, an d

Tables 4.1.1 (a)–(g), th e m em ory m aps for th e periph eral

circu its (I/ O space).

Address

Low

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

Page

High

0

M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF

1

2

RAM area (000H–05FH)

96 words x 4 bits (R/W)

3

4

5

6

7

0

8

9

Display memory area (090H–0AFH)

32 words x 4 bits (Write only)

A

B

C

D

E

F

Fig. 4.1.1

I/O memory area Table 4.1.1 (a)–(g)

Memory map

Unused area

Note

Memory is not mounted in unused area within the memory map

and in memory area not indicated in this chapter. For this reason,

normal operation cannot be assured for programs that have been

prepared with access to these areas.

I-12

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1 (a) I/O memory map (0E0H–0E3H)

Register

Address

Comment

*1

*2

D3

D2

D1

D0

Name

K03

SR

1

0

High

Low

K03

K02

K01

K00

–

*2

High

Low

R

K02

K01

K00

–

0E0H

Input port (K00–K03)

*5

0

K10

0

*5

0

R

0E1H

0E2H

0E3H

*5

0

*2

K10

–

0

High

Low

Input port (K10)

MSB

SWL3

SWL2

SWL1

SWL0

SWL3

SWL2

SWL1

SWL0

SWH3

SWH2

SWH1

SWH0

Stopwatch timer

1/100 sec (BCD)

LSB

SWH3

SWH2

SWH1

SWH0

MSB

Stopwatch timer

1/10 sec (BCD)

LSB

* 1

* 2

* 3

* 4

* 5

* 6

In itial valu e followin g in itial reset

Not set in th e circu it

Un defin ed

Reset (0) im m ediately after bein g read

Con stan tly 0 wh en bein g read

Refer to m ain m an u al

S1C62N81 TECHNICAL HARDWARE

EPSON

I-13

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1 (b) I/O memory map (0E4H–0E7H)

Register

Address

Comment

*1

D3

D2

D1

D0

Name

TM3

SR

1

0

High

Low

TM3

TM2

TM1

TM0

–

Timer data (clock timer 2 Hz)

Timer data (clock timer 4 Hz)

Timer data (clock timer 8 Hz)

Timer data (clock timer 16 Hz)

Input comparison register (K03)

Input comparison register (K02)

Input comparison register (K01)

Input comparison register (K00)

High

Low

R

TM2

TM1

–

0

0E4H

0E5H

0E6H

0E7H

High

Low

TM0

KCP03

KCP02

KCP01

KCP00

KCP03

KCP02

KCP01

KCP00

Falling

Rising

R/W

*5

0

KCP10

R/W

0

*5

0

R

*5

0

KCP10

0

Falling

Rising

Input comparison register (K10)

*5

0

EIMEL

R/W

0

*5

R

0

*5

0

EIMEL

0

Enable

Mask

Interrupt mask register (melody)

* 1

In itial valu e followin g in itial reset

Not set in th e circu it

Un defin ed

* 2

* 3

* 4

* 5

* 6

Reset (0) im m ediately after bein g read

Con stan tly 0 wh en bein g read

Refer to m ain m an u al

I-14

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1 (c) I/O memory map (0E8H–0EBH)

Register

Address

Comment

*1

D3

D2

D1

D0

Name

EIK03

SR

0

1

0

Enable

Mask

EIK03

EIK02

EIK01

EIK00

Interrupt mask register (K03)

Interrupt mask register (K02)

Interrupt mask register (K01)

Interrupt mask register (K00)

Enable

Mask

R/W

EIK02

EIK01

EIK00

0

0E8H

*5

0

EIK10

R/W

0

*5

0

R

0E9H

0EAH

0EBH

*5

0

EIK10

0

Enable

Mask

Interrupt mask register (K10)

*5

0

EISW1

EISW0

0

*5

0

R

R/W

EISW1

EISW0

0

Enable

Mask

Interrupt mask register (stopwatch 1 Hz)

Interrupt mask register (stopwatch 10 Hz)

*5

0

EIT2

EIT8

R/W

EIT32

0

R

EIT2

EIT8

0

Enable

Mask

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

EIT32

* 1

In itial valu e followin g in itial reset

Not set in th e circu it

Un defin ed

* 2

* 3

* 4

* 5

* 6

Reset (0) im m ediately after bein g read

Con stan tly 0 wh en bein g read

Refer to m ain m an u al

S1C62N81 TECHNICAL HARDWARE

EPSON

I-15

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1 (d) I/O memory map (0ECH–0EFH)

Register

Address

Comment

*1

D3

D2

D1

D0

Name

SR

1

0

*5

0

IMEL

0

*5

*4

*5

*4

*5

*4

R

0ECH

0EDH

0EEH

0EFH

0

Yes

No

IMEL

0

Interrupt factor flag (melody)

0

IK1

ISW1

IT8

IK0

ISW0

IT32

0

R

IK1

IK0

0

Yes

No

Interrupt factor flag (K10)

Interrupt factor flag (K00–K03)

0

ISW1

0

Yes

No

Interrupt factor flag (stopwatch 1 Hz)

Interrupt factor flag (stopwatch 10 Hz)

*4

ISW0

0

*5

*4

IT2

IT8

IT32

0

Yes

No

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

* 1

In itial valu e followin g in itial reset

Not set in th e circu it

Un defin ed

* 2

* 3

* 4

* 5

* 6

Reset (0) im m ediately after bein g read

Con stan tly 0 wh en bein g read

Refer to m ain m an u al

I-16

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1 (e) I/O memory map (0F0H–0F3H)

Register

Address

Comment

*1

D3

D2

D1

D0

Name

MAD3

SR

0

1

0

High

Low

MAD3

MAD2

MAD1

MAD0

Melody ROM address (AD3)

Melody ROM address (AD2)

Melody ROM address (AD1)

Melody ROM address (AD0, LSB)

High

Low

R/W

MAD2

MAD1

MAD0

0

0F0H

*5

0

MAD6

MAD5

R/W

MAD4

MELC

R00

0

MAD6

MAD5

MAD4

CLKC1

CLKC0

TEMPC

MELC

R03

0

High

ON

Low

OFF

Low

Melody ROM address (AD6, MSB)

Melody ROM address (AD5)

Melody ROM address (AD4)

R

0F1H

0F2H

0F3H

CLKC1

CLKC0

TEMPC

CLKC1(0)&CLKC0(0) : melody speed × 1

CLKC1(0)&CLKC0(1) : melody speed × 8

CLKC1(1)&CLKC0(0) : melody speed × 16

CLKC1(1)&CLKC0(1) : melody speed × 32

Tempo change control

R/W

Melody control ON/OFF

R03

R02

R01

High

R/W

R02

Output port data (R00–R03)

R01

R00

* 1

In itial valu e followin g in itial reset

Not set in th e circu it

Un defin ed

* 2

* 3

* 4

* 5

* 6

Reset (0) im m ediately after bein g read

Con stan tly 0 wh en bein g read

Refer to m ain m an u al

S1C62N81 TECHNICAL HARDWARE

EPSON

I-17

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1 (f) I/O memory map (0F4H, 0F6H, 0F9H–0FAH)

Register

Address

Comment

*1

D3

D2

D1

D0

R10

FOUT

Name

SR

1

0

R12

MO

*3

R11

ENV

0

1

High

–

Low

–

R12

MO

Output port data (R12)

R/W

Inverting melody output

Melody envelope control

Output port data (R11)

Output port data (R10)

Frequency output

0F4H

Hz

0

–

ENV

R11

High

ON

Low

OFF

0

R10

FOUT

*2

P03

P02

P01

P00

P03

P02

P01

P00

–

High

Low

R/W

0F6H

0F9H

0FAH

I/O port (P00–P03)

*5

0

TMRST SWRUN SWRST

0

*5

TMRST

Reset

0

Reset

Run

–

Stop

–

Clock timer reset

R

W

R/W

W

SWRUN

Stopwatch timer RUN/STOP

Stopwatch timer reset

*5

SWRST

Reset

0

Reset

HLMOD

R/W

0

BLDDT

BLDON

R/W

HLMOD

Heavy

load

Normal

load

Heavy load protection mode register

*5

R

0

Battery

voltage

low

Battery

voltage

normal

BLDDT

BLDON

0

Battery voltage detector data

ON

OFF

Battery voltage detector ON/OFF

* 1

In itial valu e followin g in itial reset

Not set in th e circu it

Un defin ed

* 2

* 3

* 4

* 5

* 6

Reset (0) im m ediately after bein g read

Con stan tly 0 wh en bein g read

Refer to m ain m an u al

I-18

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1 (g) I/O memory map (0FBH–0FCH)

Register

D2 D1

Address

Comment

LCD drive switch

*1

D3

D0

Name

CSDC

SR

0

1

0

Static

Dynamic

CSDC

0

CMPDT CMPON

R/W

*5

R/W

R

0

0FBH

Comparator's voltage condition:

1 = CMPP(+)input > CMPM(-)input,

0 = CMPM(-)input > CMPP(+)input

Analog voltage comparator ON/OFF

+ > -

On

- > +

Off

CMPDT

CMPON

1

0

*5

0

IOC

R/W

0

*5

R

0FCH

0

IOC

0

Output

Input

I/O port P00–P03 Input/Output

* 1

In itial valu e followin g in itial reset

Not set in th e circu it

Un defin ed

* 2

* 3

* 4

* 5

* 6

Reset (0) im m ediately after bein g read

Con stan tly 0 wh en bein g read

Refer to m ain m an u al

S1C62N81 TECHNICAL HARDWARE

EPSON

I-19

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

4.2 Osc illa tion Circ uit

Th e S1C62N81 Series h ave a bu ilt-in crystal oscillation

Crysta l osc illa tion

c irc uit

circu it. Th is circu it gen erates th e operatin g clock for th e

CPU an d periph eral circu it on con n ection to an extern al

crystal oscillator (typ. 32.768 kHz) an d trim m er capacitor

(5–25 pF).

Figu re 4.2.1 is th e block diagram of th e crystal oscillation

circu it.

V

DD

C

G

OSC1

OSC2

To CPU and

peripheral circuits

V

DD

C

D

Fig. 4.2.1

Crystal oscillation circuit

The S1C62N81 Series

As Figu re 4.2.1 in dicates, th e crystal oscillation circu it can

be con figu red sim ply by con n ectin g th e crystal oscillator

(X'tal) between th e OSC1 an d OSC2 pin s an d th e trim m er

capacitor (CG) between th e OSC1 an d VDD pin s.

I-20

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

For th e S1C62N81 Series, CR oscillation circu it (typ. 32.768

kHz) m ay also be selected by a m ask option . Figu re 4.2.2 is

th e block diagram of th e CR oscillation circu it.

CR osc illa tion c irc uit

OSC1

To CPU and

peripheral circuits

R

C

OSC2

Fig. 4.2.2

The S1C62N81 Series

CR oscillation circuit

As Figu re 4.2.2 in dicates, th e CR oscillation circu it can be

con figu red sim ply by con n ectin g th e register (R) between

pin s OSC1 an d OSC2 sin ce capacity (C) is bu ilt-in .

See Ch apter 6, "ELECTRICAL CHARACTERISTICS" for R

valu e.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-21

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

4.3 Inp ut Ports (K00–K03, K10)

Th e S1C62N81 Series h ave a gen eral-pu rpose in pu t (4 bits +

Config ura tion of

inp ut p orts

1 bit). Each of th e in pu t port pin s (K00–K03, K10) h as an

in tern al pu ll-down resistan ce. Th e pu ll-down resistan ce can

be selected for each bit with th e m ask option .

Figu re 4.3.1 sh ows th e con figu ration of in pu t port.

V

DD

Interrupt

request

Kxx

Address

Fig. 4.3.1

Configuration of input port

Vss

Mask option

Selectin g "pu ll-down resistan ce en abled" with th e m ask

option allows in pu t from a pu sh bu tton , key m atrix, an d so

forth . Wh en "pu ll-down resistan ce disabled" is selected, th e

port can be u sed for slide switch in pu t an d in terfacin g with

oth er LSIs.

I-22

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

All five in pu t port bits (K00–K03, K10) provide th e in terru pt

fu n ction . Th e con dition s for issu in g an in terru pt can be set

by th e software for th e five bits. Also, wh eth er to m ask th e

in terru pt fu n ction can be selected in dividu ally for all five

bits by th e software. Figu re 4.3.2 sh ows th e con figu ration of

K00–K03 an d K10.

Inp ut c om p a rison

re g iste rs a nd inte r-

rup t func tion

Kxx

One for each pin series

Address

Input comparison

register (KCP)

Noise

rejector

Interrupt factor

flag (IK)

Interrupt

request

Address

Fig. 4.3.2

Input interrupt

Mask option

(K00–K03, K10)

Interrupt mask

register (EIK)

circuit configuration

(K00–K03, K10)

Address

Th e in pu t in terru pt tim in g for K00–K03 an d K10 depen ds on

th e valu e set in th e in pu t com parison registers (KCP00–

KCP03 an d KCP10). An in terru pt can be set to occu r on th e

risin g or fallin g edge of th e in pu t.

Th e in terru pt m ask registers (EIK00–EIK03, EIK10) en able

th e in terru pt m ask to be selected in dividu ally for K00–K03

an d K10. An in terru pt occu rs wh en th e in pu t valu e wh ich

are n ot m asked ch an ge so th ey n o lon ger m atch th ose of th e

in pu t com parison register. An in terru pt for K10 can be

gen erated by settin g th e sam e con dition s in dividu ally.

Wh en an in terru pt is gen erated, th e in terru pt factor flag (IK0

an d IK1) is set to 1.

Figu re 4.3.3 sh ows an exam ple of an in terru pt for K00–K03.

Note Writing to the interrupt mask registers (EIK00–EIK03, EIK10)

should be done only in the DI status (interrupt flag = 0).

Otherwise, it causes malfunction.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-23

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

Interrupt mask registers

Input comparison registers

EIK03 EIK02 EIK01 EIK00

KCP03 KCP02 KCP01 KCP00

1

0

1

0

1

0

With the above setting, an interrupt for K00–K03 occurs under the

following conditions.

Input ports

(1)

K03 K02 K01 K00

1

0

1

0

(In itial valu e)

↓

(2)

K03 K02 K01 K00

1

0

1

↓

→ In terru pt gen erated

K03 K02 K01 K00

(3)

(4)

K00 is masked, so the three bits of

K01–K03 cease to match those of the

input comparison register KCP01–

KCP03, and an interrupt occurs.

0

1

↓

K03 K02 K01 K00

0

1

↓

Fig. 4.3.3 (5)

K03 K02 K01 K00

Example of interrupt

of K00–K03

1

0

1

K00 is m asked by th e in terru pt m ask register (EIK00), so an

in terru pt does n ot occu r at (2). At (3), K03 ch an ges to 0; th e

data of th e pin th at is in terru pt-en abled n o lon ger m atch es

th e data of th e in pu t com parison register, so an in terru pt

occu rs. As already explain ed, th e con dition for th e in terru pt

to occu r is th e ch an ge in th e port data an d con ten ts of th e

in pu t com parison register so th ey n o lon ger m atch . Hen ce,

in (4) or (5), wh en th e n on m atch in g pattern ch an ges to

an oth er n on m atch in g pattern or m atch in g pattern , an

in terru pt does n ot occu r. Also, pin s th at h ave been m asked

for in terru pt do n ot affect th e con dition s for in terru pt gen -

eration .

I-24

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

Th e con ten ts th at can be selected with th e in pu t port m ask

option are as follows:

Ma sk op tion

(1) An in tern al pu ll-down resistan ce can be selected for each

of th e five bits of th e in pu t ports (K00–K03, K10). Havin g

selected "pu ll-down resistan ce disabled", take care th at

th e in pu t does n ot float. Select "pu ll-down resistan ce

en abled" for in pu t ports th at are n ot bein g u sed.

(2) Th e in pu t in terru pt circu it con tain s a n oise rejection

circu it to preven t in terru pts form occu rrin g th rou gh

n oise. Th e m ask option en ables selection of th e n oise

rejection circu it for each separate pin series. Wh en "u se"

is selected, a m axim u m delay of 0.5 m s (fosc = 32 kHz)

occu rs from th e tim e an in terru pt con dition is establish ed

u n til th e in terru pt factor flag (IK) is set to 1.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-25

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

Tables 4.3.1 (a) an d 4.3.1 (b) list th e in pu t port con trol bits

Control of inp ut p orts

an d th eir addresses.

Table 4.3.1 (a) Input port control bits (1)

Register

Address

Comment

D3

D2

D1

D0

Name

K03

SR

1

0

High

Low

K03

K02

K01

K00

–

High

Low

R

K02

K01

–

0E0H

0E1H

0E5H

0E6H

Input port (K00–K03)

K00

0

KCP03

0

K10

0

R

0

K10

–

0

High

Low

Input port (K10)

KCP02

KCP01

KCP00

KCP03

KCP02

KCP01

KCP00

Falling

Rising

Input comparison register (K03)

Input comparison register (K02)

Input comparison register (K01)

Input comparison register (K00)

R/W

0

KCP10

R/W

0

R

KCP10

0

Falling

Rising

Input comparison register (K10)

I-26

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

Table 4.3.1 (b) Input port control bits (2)

Register

Address

Comment

D3

D2

D1

D0

Name

EIK03

SR

0

1

0

Enable

Mask

EIK03

EIK02

EIK01

EIK00

Interrupt mask register (K03)

Interrupt mask register (K02)

Interrupt mask register (K01)

Interrupt mask register (K00)

Enable

Mask

R/W

EIK02

EIK01

EIK00

0

0E8H

0

EIK10

R/W

0

R

0E9H

0

EIK10

0

Enable

Mask

Interrupt mask register (K10)

0

IK1

IK0

0

R

0EDH

IK1

IK0

0

Yes

No

Interrupt factor flag (K10)

Interrupt factor flag (K00–K03)

K00–K03, K10 Input port data (0E0H, 0E1H D0)

Th e in pu t data of th e in pu t port pin s can be read with th ese

registers.

Wh en 1 is read: High level

Wh en 0 is read: Low level

Writin g:

In valid

Th e valu e read is 1 wh en th e pin voltage of th e five bits of

th e in pu t ports (K00–K03, K10) goes h igh (VDD), an d 0 wh en

th e voltage goes low (VSS). Th ese bits are readin g, so writin g

can n ot be don e.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-27

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

KCP00–KCP03, KCP10 Input comparison registers (0E5H, 0E6H D0)

Th e in terru pt con dition s for pin s K00–K03 an d K10 can be

set with th ese registers.

Wh en 1 is read: Fallin g edge

Wh en 0 is read: Risin g edge

Readin g:

Valid

Of th e five bits of th e in pu t ports, th e in terru pt con dition s

can be set for th e risin g or fallin g edge of th e in pu t for each

of th e five bits (K00–K03 an d K10) th rou gh th e in pu t com -

parison registers (KCP00–KCP03 an d KCP10).

After an in itial reset, th ese registers are set to 0.

EIK00–EIK03, EIK10 Interrupt mask registers (0E8H, 0E9H D0)

Maskin g th e in terru pt of th e in pu t port pin s can be don e

with th ese registers.

Wh en 1 is written :

Wh en 0 is written :

Readin g:

En able

Mask

Valid

With th ese registers, m askin g of th e in pu t port bits can be

don e for each of th e five bits. After an in itial reset, th ese

registers are all set to 0.

Writin g to th ese registers sh ou ld be don e on ly in th e DI

statu s (in terru pt flag = 0). Oth erwise, it cau ses m alfu n ction .

K0, IK1 Interrupt factor flags (0EDH D0 and D1)

Th ese flags in dicate th e occu rren ce of an in pu t in terru pt.

Wh en 1 is read: In terru pt h as occu rred

Wh en 0 is read: In terru pt h as n ot occu rred

Writin g:

In valid

Th e in terru pt factor flags IK0 an d IK1 are associated with

K00–K03 an d K10, respectively. From th e statu s of th ese

flags, th e software can decide wh eth er an in pu t in terru pt

h as occu rred.

Th ese flags are reset wh en th e software h as read th em .

Readin g sh ou ld be don e on ly in th e DI statu s (in terru pt flag

= 0). Oth erwise, it cau ses m alfu n ction .

After an in itial reset, th ese flags are set to 0.

I-28

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

4.4

Outp ut Ports (R00–R03, R10–R12)

Th e S1C62N81 Series h ave 7 bits for gen eral ou tpu t ports

(R00–R03 an d R10–R12).

Config ura tion of

outp ut p orts

Ou tpu t specification s of th e ou tpu t ports can be selected

in dividu ally with th e m ask option . Two kin ds of ou tpu t

specification s are available: com plem en tary ou tpu t, an d Pch

open drain ou tpu t. Also, th e m ask option en ables th e

ou tpu t ports R10 an d R12 to be u sed as special ou tpu t

ports. Figu re 4.4.1 sh ows th e con figu ration of th e ou tpu t

ports.

VDD

Register

Rxx

Complementary

Pch open drain

Address

VSS

Fig. 4.4.1

Configuration of output ports

Mask option

S1C62N81 TECHNICAL HARDWARE

EPSON

I-29

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

Th e m ask option en ables th e followin g ou tpu t port selection .

Ma sk op tion

(1) Output specifications of output ports

Th e ou tpu t specification s for th e ou tpu t ports (R00–R03,

R10–R12) m ay be eith er com plem en tary ou tpu t or Pch

open drain ou tpu t for each of th e seven bits. However,

even wh en Pch open drain ou tpu t is selected, a voltage

exceedin g th e sou rce voltage m u st n ot be applied to th e

ou tpu t port.

(2) Special output

In addition to th e regu lar DC ou tpu t, special ou tpu t can

be selected for ou tpu t ports R10 an d R12, as sh own in

Table 4.4.1. Figu re 4.4.2 sh ows th e stru ctu re of ou tpu t

ports R10–R12.

Table 4.4.1

Pin Name

R12

When Special Output is Selected

Special output

MO or ENV

FOUT

R10

MO or

ENV

Register

(R12)

R12

Register

(R11)

R11

R10

FOUT

Register

(R10)

Fig. 4.4.2

Structure of output port

R10–R12

Address

(0F4H)

Mask option

I-30

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

FOUT (R10) Wh en ou tpu t port R10 is set for FOUT ou tpu t, it ou tpu ts th e

clock of fosc or th e divided fosc. Th e clock frequ en cy is

selectable by m ask option from th e frequ en cies listed in

Table 4.4.2.

Table 4.4.2

Setting Value

fosc/1

Clock Frequency (Hz)

FOUT clock frequency

32,768

16,384

8,192

4,096

2,048

1,024

512

fosc/2

fosc/4

fosc/8

fosc/16

fosc/32

fosc/64

fosc/128

256

(fosc = 32,768 Hz)

Note A hazard may occur when the FOUT signal is turned on or off.

MO, ENV (R12) R12 can select th e followin g two fu n ction s u sin g th e m ask

option as special ou tpu t.

(1) Inverse output (MO) of melody output (MO)

Usin g th e MO an d MO term in als togeth er, piezoelectric

bu zzer m ay be driven directly. Th is m ean s th e m in im u m

n u m ber of extern al parts is n ecessary to play m elodies.

(2) Envelope function

An en velope can be added wh en playin g a m elody by

con n ectin g th e play sou n d pressu re dam pin g capacitor to

term in al R12.

For details, see Ch apter 5, "BASIC EXTERNAL WIRING

DIAGRAM", an d Section 4.11, "Melody Gen erator".

S1C62N81 TECHNICAL HARDWARE

EPSON

I-31

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

Table 4.4.3 lists th e ou tpu t port con trol bits an d th eir ad-

dresses.

Control of outp ut

p orts

Table 4.4.3 Control bits of output ports

Register

Address

Comment

D3

D2

D1

D0

Name

R03

SR

0

1

0

R03

R02

R01

R00

High

Low

R/W

R02

R01

R00

0

High

Low

0F3H

Output port data (R00–R03)

R10

FOUT

R12

MO

R11

ENV

0

1

High

–

Low

–

R12

MO

Output port data (R12)

Inverting melody output

Melody envelope control

Output port data (R11)

Output port data (R10)

Frequency output

R/W

0F4H

Hz

0

–

ENV

R11

High

ON

Low

OFF

0

R10

FOUT

R00–R03, R10–R12 Output port data (0F3H, 0F4H D0–D2)

(DC output) Sets th e ou tpu t data for th e ou tpu t ports.

Wh en 1 is written :

Wh en 0 is written :

Readin g:

High ou tpu t

Low ou tpu t

Valid

Th e ou tpu t port pin s ou tpu t th e data written to th e corre-

spon din g registers (R00–R03, R10–R12) with ou t ch an gin g it.

Wh en 1 is written to th e register, th e ou tpu t port pin goes

h igh (VDD), an d wh en 0 is written , th e ou tpu t port pin goes

low (VSS). After an in itial reset, all registers are set to 0.

I-32

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

R12 (when MO or ENV is Special output port data (0F4H D2)

selected) Th is bit will n ot affect th e m elody (MO) or en velope (ENV)

sign al at Rl2. R12 register is a gen eral pu rpose register

wh ich can be read an d written .

Wh en 1 is written :

Wh en 0 is written :

Readin g:

No effect at R12

Valid

R10 (when FOUT is

selected)

Special output port data (0F4H D0)

Con trols th e FOUT (clock) ou tpu t.

Wh en 1 is written :

Wh en 0 is written :

Readin g:

Clock ou tpu t

Low level (DC) ou tpu t

Valid

FOUT ou tpu t can be con trolled by writin g data to R10. After

an in itial reset, th is register is set to 0.

Figu re 4.4.3 sh ows th e ou tpu t waveform for FOUT ou tpu t.

R10 Register

0

1

Fig. 4.4.3

FOUT output

waveform

FOUT output waveform

S1C62N81 TECHNICAL HARDWARE

EPSON

I-33

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

4.5 I/ O Ports (P00–P03)

Th e S1C62N81 Series h ave a 4-bit gen eral-pu rpose I/ O port.

Config ura tion of I/ O

p ort

Figu re 4.5.1 sh ows th e con figu ration of th e I/ O port. Th e

fou r bits of th e I/ O port P00–P03 can be set to eith er in pu t

m ode or ou tpu t m ode. Th e m ode can be set by writin g data

to th e I/ O con trol register (IOC).

Input

control

Register

Pxx

Address

I/O control

register

(IOC)

Fig. 4.5.1

Address

V

SS

Configuration of I/O port

I-34

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

In pu t or ou tpu t m ode can be set for th e fou r bits of I/ O port

P00–P03 by writin g data in to I/ O con trol register IOC.

To set th e in pu t m ode, 0 is written to th e I/ O con trol regis-

ter. Wh en an I/ O port is set to in pu t m ode, its im pedan ce

becom es h igh an d it works as an in pu t port. However, th e

in pu t lin e is pu lled down wh en in pu t data is read.

I/ O c ontrol re g iste r

a nd I/ O m od e

Th e ou tpu t m ode is set wh en 1 is written to th e I/ O con trol

register (IOC). Wh en an I/ O port set to ou tpu t m ode works

as an ou tpu t port, it ou tpu ts a h igh sign al (VDD) wh en th e

port ou tpu t data is 1, an d a low sign al (VSS) wh en th e port

ou tpu t data is 0.

After an in itial reset, th e I/ O con trol register is set to 0, an d

th e I/ O port en ters th e in pu t m ode.

Th e ou tpu t specification du rin g ou tpu t m ode (IOC = 1) of th e

I/ O port can be set with th e m ask option for eith er com ple-

m en tary ou tpu t or Pch open drain ou tpu t. Th is settin g can

be perform ed for each bit of th e I/ O port. However, wh en

Pch open drain ou tpu t h as been selected, voltage in excess

of th e su pply voltage m u st n ot be applied to th e port.

Ma sk op tion

S1C62N81 TECHNICAL HARDWARE

EPSON

I-35

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

Table 4.5.1 lists th e I/ O port con trol bits an d th eir ad-

dresses.

Control of I/ O p ort

Table 4.5.1 I/O port control bits

Register

Address

0F6H

Comment

D3

D2

D1

D0

Name

P03

SR

–

1

0

P03

P02

P01

P00

High

Low

P02

P01

P00

0

–

High

Low

R/W

I/O port (P00–P03)

0

IOC

R/W

0

R

0FCH

0

IOC

0

Output

Input

I/O port P00–P03 Input/Output

P00–P03 I/O port data (0F6H)

I/ O port data can be read an d ou tpu t data can be written

th rou gh th e port.

• Wh en writin g data

Wh en 1 is written :

Wh en 0 is written :

High level

Low level

Wh en an I/ O port is set to th e ou tpu t m ode, th e written

data is ou tpu t from th e I/ O port pin u n ch an ged. Wh en 1

is written as th e port data, th e port pin goes h igh (VDD),

an d wh en 0 is written , th e level goes low (VSS). Port data

can also be written in th e in pu t m ode.

• Wh en readin g data

Wh en 1 is read:

Wh en 0 is read:

High level

Low level

I-36

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

The pin voltage level of the I/ O port is read. When the I/ O

port is in the inpu t mode the voltage level being inpu t to

the port pin can be read; in the ou tpu t mode the ou tpu t

voltage level can be read. When the pin voltage is high

(VDD) the port data read is 1, and when the pin voltage is

low (VSS) the data is 0. Also, the bu ilt-in pu ll-down resis-

tance fu nctions du ring reading, so the I/ O port pin is

pu lled down.

Note

-

When the I/O port is set to the output mode and a low-imped-

ance load is connected to the port pin, the data written to the

register may differ from the data read.

When the I/O port is set to the input mode and a low-level

voltage (Vss) is input by the built-in pull-down resistance, an

erroneous input results if the time constant of the capacitive

load of the input line and the built- in pull-down resistance load

is greater than the read-out time. When the input data is being

read, the time that the input line is pulled down is equivalent to

0.5 cycles of the CPU system clock. Hence, the electric poten-

tial of the pins must settle within 0.5 cycles. If this condition

cannot be met, some measure must be devised, such as

arranging a pull-down resistance externally, or performing

multiple read-outs.

IOC I/O control register (0FCH D0)

Th e in pu t or ou tpu t I/ O port m ode can be set with th is

register.

Wh en 1 is written :

Wh en 0 is written :

Readin g:

Ou tpu t m ode

In pu t m ode

Valid

Th e in pu t or ou tpu t m ode of th e I/ O port is set in u n its of

fou r bits. For in stan ce, IOC sets th e m ode for P00–P03.

Writin g 1 to th e I/ O con trol register m akes th e I/ O port

en ter th e ou tpu t m ode, an d writin g 0, th e in pu t m ode.

After an in itial reset, th e IOC register is set to 0, so th e I/ O

port is in th e in pu t m ode.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-37

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

4.6 LCD Drive r (COM0–COM3, SEG0–SEG25)

Th e S1C62N81 Series h ave fou r com m on pin s an d 26

(SEG0–SEG25) segm en t pin s, so th at an LCD with a m axi-

m u m of 104 (26 × 4) segm en ts can be driven . Th e power for

drivin g th e LCD is gen erated by th e CPU in tern al circu it, so

th ere is n o n eed to su pply power extern ally.

Config ura tion of LCD

d rive r

Th e drivin g m eth od is 1/ 4 du ty (or 1/ 3 du ty by m ask op-

tion ) dyn am ic drive, adoptin g th e fou r types of poten tial,

VDD, VL1, VL2 an d VL3. Th e fram e frequ en cy is 32 Hz for 1/ 4

du ty, an d 42.7 Hz for 1/ 3 du ty (in th e case of fosc = 32.768

kHz). Figu re 4.6.1 sh ows th e drive waveform for 1/ 4 du ty,

an d Figu re 4.6.2 sh ows th e drive waveform for 1/ 3 du ty.

Note

fosc indicates the oscillation frequency of the oscillation circuit.

I-38

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

LCD lighting status

COM0

-VDD

-VL1

COM0

-VL2

-VL3

COM1

COM2

COM3

COM1

COM2

COM3

SEG0–25

Not lit

Lit

-VDD

-VL1

-VL2

-VL3

SEG

0–25

Fig. 4.6.1

Drive waveform

for 1/4 duty

Frame frequency

S1C62N81 TECHNICAL HARDWARE

EPSON

I-39

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

COM0

-VDD

-VL1

-VL2

-VL3

LCD lighting status

COM0

COM1

COM2

COM1

COM2

COM3

SEG0–25

Not lit

Lit

-VDD

-VL1

-VL2

-VL3

SEG

0–25

Fig. 4.6.2

Frame frequency

Drive waveform

for 1/3 duty

I-40

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

Th e S1C62N81 Series m em bers allow software settin g of th e

LCD static drive. Th is fu n ction en ables easy adju stm en t

(caden ce adju stm en t) of th e oscillation frequ en cy of th e OSC

circu it.

Switc hing b e twe e n

d yna m ic a nd sta tic

d rive

Th e procedu re for execu tin g of th e LCD static drive is as

follows:

➀ Write 1 to th e CSDC register at address 0FBH D3.

➀ Write th e sam e valu e to all registers correspon din g to

COM0–COM3 of th e display m em ory.

Note

-

Even when l/3 duty is selected, the display data corresponding

to COM3 is valid for static drive. Hence, for static drive, set the

same value to all display memory corresponding COM0–COM3.

For cadence adjustment, set the display data including display

data corresponding to COM3, so that all the LCD segments go

on.

Figu re 4.6.3 sh ows th e drive waveform for static drive.

LCD lighting status

-VDD

-VL1

-VL2

-VL3

COM0

COM1

COM2

COM3

COM

0–3

Frame frequency

SEG0–25

Not lit

-VDD

-VL1

-VL2

-VL3

Lit

SEG

0–25

-VDD

-VL1

-VL2

-VL3

Fig. 4.6.3

LCD static drive waveform

S1C62N81 TECHNICAL HARDWARE

EPSON

I-41

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

(1) Segment allocation

Ma sk op tion

(se g m e nt a lloc a tion)

As sh own in Figu re 4.l.1, th e S1C62N81 Series display

data is decided by th e display data written to th e display

m em ory (write-on ly) at address 090H–0AFH.

Th e address an d bits of th e display m em ory can be m ade

to correspon d to th e segm en t pin s (SEG0–SEG25) in an y

com bin ation th rou gh m ask option . Th is sim plifies design

by in creasin g th e degree of freedom with wh ich th e liqu id

crystal pan el can be design ed.

Figu re 4.6.4 sh ows an exam ple of th e relation sh ip be-

tween th e LCD segm en ts (on th e pan el) an d th e display

m em ory in th e case of 1/ 3 du ty.

Common 0

9A, D0

(a)

Common 1

9B, D1

(f)

Common 2

9B, D0

(e)

Data

Address

D3

d

D2

c

D1

b

D0

a

SEG10

SEG11

SEG12

09AH

09BH

09CH

09DH

p

g

f

e

9A, D1

(b)

9B, D2

(g)

9A, D3

(d)

d'

p'

c'

g'

b'

f'

a'

e'

9D, D1

(f')

9A, D2

(c)

9B, D3

(p)

Display data memory allocation

Pin address allocation

a

a'

g'

b'

b

f'

f

g

c'

e

c

e'

p'

p

d'

d

SEG10 SEG11 SEG12

Common 0

Common 1

Common 2

Fig. 4.6.4

Segment allocation

I-42

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

(2) Drive duty

Accordin g to th e m ask option , eith er 1/ 4 or 1/ 3 du ty can

be selected as th e LCD drive du ty.

Table 4.6.1 sh ows th e differen ces in th e n u m ber of seg-

m en ts accordin g to th e selected du ty.

Table 4.6.1

Differences according to

selected duty

Pins Used

in Common

Maximum Number

of Segments

Frame Frequency

(when fosc = 32 kHz)

Duty

1/ 4

1/ 3

COM0–3

COM0–2

104 (26 × 4)

78 (26 × 3)

32 Hz

42.7 Hz

(3) Output specification

➀ Th e segm en t pin s (SEG0–SEG25) are selected by m ask

option in pairs for eith er segm en t sign al ou tpu t or DC

ou tpu t (VDD an d VSS bin ary ou tpu t). Wh en DC ou tpu t

is selected, th e data correspon din g to COM0 of each

segm en t pin is ou tpu t.

➀ Wh en DC ou tpu t is selected, eith er com plem en tary

ou tpu t or Pch open drain ou tpu t can be selected for

each pin by m ask option .

Note

The pin pairs are the combination of SEG (2*n) and SEG (2*n +

1) (where n is an integer from 0 to 12).

S1C62N81 TECHNICAL HARDWARE

EPSON

I-43

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

Table 4.6.2 sh ows th e con trol bits of th e LCD driver an d

Control of LCD

d rive r

th eir addresses. Figu re 4.6.5 sh ows th e display m em ory

m ap.

Table 4.6.2 Control bits of LCD driver

Register

D2 D1

Address

Comment

LCD drive switch

D3

D0

Name

CSDC

SR

0

1

0

Static

Dynamic

CSDC

0

CMPDT CMPON

R/W

R

0

0FBH

Comparator's voltage condition:

1 = CMPP(+)input > CMPM(-)input,

0 = CMPM(-)input > CMPP(+)input

Voltage comparator ON/OFF

+ > -

On

- > +

Off

CMPDT

CMPON

1

0

Address

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

Fig. 4.6.5

Display

090

0A0

Display memory (Write only)

32 words x 4 bits

memory map

CSDC LCD drive switch (0FBH D3)

Th e LCD drive form at can be selected with th is switch .

Wh en 1 is written :

Wh en 0 is written :

Readin g:

Static drive

Dyn am ic drive

Valid

After an in itial reset, dyn am ic drive (CSDC = 0) is selected.

Display memory (090H–0AFH)

Th e LCD segm en ts are tu rn ed on or off accordin g to th is

data.

Wh en 1 is written :

Wh en 0 is written :

Readin g:

On

Off

In valid

By writin g data in to th e display m em ory allocated to th e

LCD segm en t (on th e pan el), th e segm en t can be tu rn ed on

or off. After an in itial reset, th e con ten ts of th e display

m em ory are u n defin ed.

I-44

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

4.7 Cloc k Tim e r

Th e S1C62N81 Series h ave a bu ilt-in clock tim er driven by

th e sou rce oscillator. Th e clock tim er is con figu red as a

seven -bit bin ary cou n ter th at serves as a frequ en cy divider

takin g a 256 Hz sou rce clock from a prescaler. Th e fou r

h igh -order bits (16 Hz–2 Hz) can be read by th e software.

Figu re 4.7.1 is th e block diagram of th e clock tim er.

Config ura tion of

c loc k tim e r

Data bus

256 Hz

OSC

128 Hz–32 Hz

16 Hz–2 Hz

(oscillation

circuit)

32 Hz, 8 Hz, 2 Hz

Fig. 4.7.1

Clock timer reset signal

Block diagram of

clock timer

Interrupt

request

Interrupt

control

Norm ally, th is clock tim er is u sed for all kin ds of tim in g

pu rpose, su ch as clocks.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-45

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

Th e clock tim er can in terru pt on th e fallin g edge of th e 32

Inte rrup t func tion

Hz, 8 Hz, an d 2 Hz sign als. Th e software can m ask an y of

th ese in terru pt sign als.

Figu re 4.7.2 is th e tim in g ch art of th e clock tim er.

Register

Address

Frequency

16 Hz

8 Hz

Clock timer timing chart

bits

D0

D1

D2

D3

0E4H

4 Hz

2 Hz

Occurrence of

32 Hz interrupt request

Occurrence of

8 Hz interrupt request

Occurrence of

2 Hz interrupt request

Fig. 4.7.2 Timing chart of the clock timer

As sh own in Figu re 4.7.2, an in terru pt is gen erated on th e

fallin g edge of th e 32 Hz, 8 Hz, an d 2 Hz frequ en cies. Wh en

th is h appen s, th e correspon din g in terru pt even t flag (IT32,

IT8, IT2) is set to 1. Maskin g th e separate in terru pts can be

don e with th e in terru pt m ask register (EIT32, EIT8, EIT2).

However, regardless of th e in terru pt m ask register settin g,

th e in terru pt even t flags will be set to 1 on th e fallin g edge of

th eir correspon din g sign al (e.g. th e fallin g edge of th e 2 Hz

sign al sets th e 2 Hz in terru pt factor flag to 1).

Note Write to the interrupt mask register (EIT32, EIT8, EIT2) and read

the interrupt factor flags (IT32, IT8, IT2) only in the DI status

(interrupt flag = 0). Otherwise, it causes malfunction.

I-46

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

Table 4.7.1 sh ows th e clock tim er con trol bits an d th eir

addresses.

Control of c loc k

tim e r

Table 4.7.1 Control bits of clock timer

Register

Address

Comment

D3

D2

D1

D0

Name

TM3

SR

1

0

High

Low

TM3

TM2

EIT2

IT2

TM1

TM0

–

Timer data (clock timer 2 Hz)

Timer data (clock timer 4 Hz)

Timer data (clock timer 8 Hz)

Timer data (clock timer 16 Hz)

High

Low

R

TM2

TM1

TM0

0

–

0E4H

0

EIT8

R/W

EIT32

R

EIT2

EIT8

EIT32

0

Enable

Mask

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

0EBH

0EFH

0F9H

0

IT8

IT32

R

IT2

0

Yes

No

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

IT8

IT32

0

TMRST SWRUN SWRST

TMRST

SWRUN

SWRST

Reset

0

Reset

Run

–

Stop

–

Clock timer reset

R

W

R/W

W

Stopwatch timer RUN/STOP

Stopwatch timer reset

Reset

S1C62N81 TECHNICAL HARDWARE

EPSON

I-47

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

TM0–TM3 Timer data (0E4H)

Th e 16 Hz to 2 Hz tim er data of th e clock tim er can be read

from th is register. Th ese fou r bits are read-on ly, an d write

operation s are in valid.

After an in itial reset, th e tim er data is in itialized to 0H.

EIT32, EIT8, EIT2 Interrupt mask registers (0EBH D0–D2)

Th ese registers are u sed to m ask th e clock tim er in terru pt.

Wh en 1 is written : En abled

Wh en 0 is written : Masked

Readin g:

Valid

Th e in terru pt m ask register bits (EIT32, EIT8, EIT2) m ask

th e correspon din g in terru pt frequ en cies (32 Hz, 8 Hz, 2 Hz).

Writin g to th e in terru pt m ask registers sh ou ld be don e on ly

in th e DI statu s. Oth erwise, it cau ses m alfu n ction .

After an in itial reset, th ese registers are all set to 0.

IT32, IT8, IT2 Interrupt factor flags (0EFH D0–D2)

Th ese flags in dicate th e statu s of th e clock tim er in terru pt.

Wh en 1 is read:

Wh en 0 is read:

Writin g:

In terru pt h as occu rred

In terru pt h as n ot occu rred

In valid

Th e in terru pt factor flags (IT32, IT8, IT2) correspon d to th e

clock tim er in terru pts (32 Hz, 8 Hz, 2 Hz). Th e software can

determ in e from th ese flags wh eth er th ere is a clock tim er

in terru pt. However, even if th e in terru pt is m asked, th e

flags are set to 1 on th e fallin g edge of th e sign al. Th ese

flags can be reset wh en th e register is read by th e software.

Also, th e flags sh ou ld be read on ly in th e DI statu s (in ter-

ru pt flag = 0). Oth erwise, it cau ses m alfu n ction .

After an in itial reset, th ese flags are set to 0.

I-48

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

TMRST Clock timer reset (0F9H D2)

Th is bit resets th e clock tim er.

Wh en 1 is written : Clock tim er reset

Wh en 0 is written : No operation

Readin g:

Always 0

Th e clock tim er is reset by writin g 1 to TMRST. Th e clock

tim er starts im m ediately after th is. No operation resu lts

wh en 0 is written to TMRST.

Th is bit is write-on ly, an d so is always 0 wh en read.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-49

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

4.8 Stop wa tc h Tim e r

Th e S1C62N81 Series in corporate a 1/ 100 sec an d 1/ 10 sec

Config ura tion of

stop wa tc h tim e r

stopwatch tim er. Th e stopwatch tim er is con figu red as a

two-stage, fou r-bit BCD tim er servin g as th e clock sou rce for

an approxim ately 100 Hz sign al (obtain ed by approxim ately

dividin g th e 256 Hz sign al ou tpu t from th e prescaler). Data

can be read ou t fou r bits at a tim e by th e software.

Figu re 4.8.1 is th e block diagram of th e stopwatch tim er.

Data bus

256 Hz

OSC

(oscillation

circuit)

10 Hz

SWL timer

SWH timer

10 Hz, 1 Hz

Stopwatch timer reset signal

Fig. 4.8.1

Interrupt

control

Interrupt

request

Block diagram of

stopwatch timer

Stopwatch timer RUN/STOP signal

Th e stopwatch tim er can be u sed separately from th e clock

tim er. In particu lar, digital stopwatch fu n ction s can be

easily realized by software.

I-50

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

Th e stopwatch tim er is con figu red as two fou r-bit BCD

tim ers, SWL an d SWH. Th e SWL tim er, at th e stage preced-

in g th e stopwatch tim er, h as an approxim ate l00 Hz sign al

as its in pu t clock. It cou n ts u p every 1/ 100 sec an d gen er-

ates an approxim ate 10 Hz sign al. Th e SWH tim er h as an

approxim ate 10 Hz sign al gen erated by th e SWL tim er for its

in pu t clock. It cou n ts u p every 1/ 10 sec an d gen erates a 1

Hz sign al.

Count-up p a tte rn

Figu re 4.8.2 sh ows th e cou n t-u p pattern of th e stopwatch

tim er.

SWH count-up pattern

SWH count value

0

1

2

3

4

5

6

7

8

9

0

1 Hz

signal

26

26 25 25 26

26 25 25 26 26

Counting time (S)

256 256 256 256 256 256 256 256 256 256

generation

26

256

25

256

x 4 = 1 (S)

x 6 +

SWL count-up pattern 1

SWL count value

0

1

2

3

4

2

5

6

7

8

9

0

Approximate

10 Hz

signal

3

2

3

2

3

2

3

2

Counting time (S)

256 256 256 256 256 256 256 256 256 256

generation

25

256

(S)

SWL count-up pattern 2

SWL count value

0

1

2

3

4

5

6

7

8

9

0

Approximate

10 Hz

signal

3

2

3

2

3

2

3

2

Counting time (S)

256 256 256 256 256 256 256 256 256 256

Fig. 4.8.2

Count-up pattern of

stopwatch timer

generation

26

(S)

256

SWL gen erates an approxim ate 10 Hz sign al from th e 256

Hz based sign al. Th e cou n t-u p in tervals are 2/ 256 sec an d

3/ 256 sec, so th at two fin al pattern s are gen erated: a 25/

256 sec in terval an d a 26/ 256 sec in terval. Con sequ en tly,

th e cou n t-u p in tervals are 2/ 256 sec an d 3/ 256 sec, wh ich

do n ot am ou n t to an accu rate 1/ 100 sec. SWH cou n ts th e

approxim ate 10 Hz sign als gen erated by th e 25/ 256 sec,

an d 26/ 256 sec in tervals in th e ratio of 4:6 to gen erate a l

Hz sign al. Th e cou n t-u p in tervals are 25/ 256 sec an d 26/

256 sec, wh ich do n ot am ou n t to an accu rate 1/ 10 sec.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-51

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

Th e 10 Hz (approxim ate 10 Hz) an d 1 Hz in terru pts can be

Inte rrup t func tion

gen erated by th e overflow of th e SWL an d SWH stopwatch

tim ers, respectively. Also, software can separately m ask th e

frequ en cies as described earlier.

Figu re 4.8.3 is th e tim in g ch art for th e stopwatch tim er.

Stopwatch timer (SWL) timing chart

Register bit

D0

Address

D1

0E2H

(1/100 sec BCD)

D2

D3

Occurrence of

10 Hz interrupt request

Address

Register bit

Stopwatch timer (SWH) timing chart

D0

D1

D2

D3

0E3H

(1/10 sec BCD)

Fig. 4.8.3

Timing chart for

stopwatch timer

Occurrence of

1 Hz interrupt request

As sh own in Figu re 4.8.3, th e in terru pts are gen erated by

th e overflow of th e respective tim ers (9 ch an gin g to 0). Also

wh en th is h appen s, th e correspon din g in terru pt factor flags

(ISW0, ISW1) are set to 1. Th e respective in terru pts can be

m asked separately with th e in terru pt m ask registers

(EISW0, EISW1). However, regardless of th e settin g of th e

in terru pt m ask registers, th e in terru pt factor flags are set to

1 by th e overflow of th e correspon din g tim ers.

Write to the interrupt mask registers (EISW0, EISW1) and read the

interrupt factor flags (ISW0, ISW1) only in the DI status (interrupt

flag = 0). Otherwise, it causes malfunction.

Note

I-52

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

Table 4.8.1 sh ows th e stopwatch tim er con trol bits an d th eir

addresses.

Control of stop wa tc h

tim e r

Table 4.8.1 Stopwatch timer control bits

Register

Address

Comment

D3

D2

D1

D0

Name

SWL3

SR

0

1

0

SWL3

SWL2

SWL1

SWL0

MSB

SWL2

SWL1

SWL0

SWH3

SWH2

SWH1

SWH0

0

Stopwatch timer

1/100 sec (BCD)

R

0E2H

0E3H

0EAH

0EEH

0F9H

LSB

SWH3

SWH2

SWH1

SWH0

EISW0

ISW0

MSB

R

Stopwatch timer

1/10 sec (BCD)

LSB

0

EISW1

0

R

R/W

EISW1

EISW0

0

Enable

Mask

Interrupt mask register (stopwatch 1 Hz)

Interrupt mask register (stopwatch 10 Hz)

0

ISW1

0

R

ISW1

ISW0

0

Yes

No

Interrupt factor flag (stopwatch 1 Hz)

Interrupt factor flag (stopwatch 10 Hz)

0

TMRST SWRUN SWRST

TMRST

SWRUN

SWRST

Reset

0

Reset

Run

–

Stop

–

Clock timer reset

R

W

R/W

W

Stopwatch timer RUN/STOP

Stopwatch timer reset

Reset

S1C62N81 TECHNICAL HARDWARE

EPSON

I-53

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

SWL0–SWL3 1/100 sec stopwatch timer (0E2H)

Data (BCD) of th e 1/ 100 sec colu m n of th e stopwatch tim er

can be read. Th ese fou r bits are read-on ly, an d can n ot be

written to.

After an in itial reset, th e tim er data is set to 0H.

SWH0–SWH3

1/10 sec stopwatch timer (0E3H)

Data (BCD) of th e 1/ 10 sec colu m n of th e stopwatch tim er

can be read. Th ese fou r bits are read-on ly, an d can n ot be

written to.

After an in itial reset, th e tim er data is set to 0H.

EISW0, EISW1 Interrupt mask register (0EAH D0 and D1)

Th ese registers m ask th e stopwatch tim er in terru pt.

Wh en 1 is written : En abled

Wh en 0 is written : Masked

Readin g:

Valid

Th e in terru pt m ask register bits (EISW0, EISW1) are u sed to

m ask th e 10 Hz an d 1Hz in terru pts, respectively. Writin g to

th e in terru pt m ask registers sh ou ld be don e on ly in th e DI

statu s (in terru pt flag = 0). Oth erwise, it cau ses m alfu n ction .

After an in itial reset, th ese registers are both set to 0.

ISW0, ISW1 Interrupt factor flags (0EEH D0 and D1)

Th ese flags in dicate th e statu s of th e stopwatch tim er in ter-

ru pt.

Wh en 1 is read:

Wh en 0 is read:

Writin g:

In terru pt h as occu rred

In terru pt h as n ot occu rred

In valid

Th e in terru pt factor flags (ISW0, ISW1) correspon d to th e 10

Hz an d 1 Hz in terru pts, respectively. With th ese flags, th e

software can determ in e wh eth er a stopwatch tim er in terru pt

h as occu rred. However, regardless of th e in terru pt m ask

register settin g, th ese flags are set to 1 by th e tim er over-

flow. Th ey are reset wh en th e register is read by th e soft-

ware. Also, readin g sh ou ld be don e on ly in th e DI statu s

(in terru pt flag = 0). Oth erwise, it cau ses m alfu n ction .

After an in itial reset, th ese flags are set to 0.

I-54

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

SWRST Stopwatch timer reset (0F9H D0)

Th is bit resets th e stopwatch tim er.

Wh en 1 is written : Stopwatch tim er reset

Wh en 0 is written : No operation

Readin g:

Always 0

Th e stopwatch tim er is reset wh en 1 is written to SWRST.

Wh en th e stopwatch tim er is reset wh ile ru n n in g, operation

restarts im m ediately. Also,wh ile stopped, th e reset data is

m ain tain ed.

Th is bit is write-on ly, an d is always 0 wh en read.

SWRUN Stopwatch timer run/stop (0F9H D1)

Th is bit con trols ru n / stop of th e stopwatch tim er.

Wh en 1 is written : Ru n

Wh en 0 is written : Stop

Readin g:

Valid

Th e stopwatch tim er ru n s wh en 1 is written to SWRUN, an d

stops wh en 0 is written .

Wh en stopped, th e tim er data is m ain tain ed u n til th e tim er

n ext Ru n or is reset. Also, wh en th e tim er ru n s after bein g

stopped, th e data th at was m ain tain ed can be u sed to res-

u m e th e cou n t.

If th e tim er data is read wh ile ru n n in g, a correct read m ay

be im possible becau se of th e carry from th e low-order bit

(SWL) to th e h igh -order bit (SWH). Th is occu rs if readin g

h as exten ded over th e SWL an d SWH bits wh en th e carry

occu rs. To preven t th is, read after stoppin g, an d th en

con tin u e ru n n in g. Also, th e stopped du ration m u st be

with in 976 µs (256 Hz, 1/ 4 cycle).

After an in itial reset, th is register is set to 0.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-55

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (BLD Circuit and Heavy Load Protection Function)

4.9 Ba tte ry Volta g e Low De te c tion (BLD) Circ uit

a nd He a vy Loa d Prote c tion Func tion

The S1C62N81 Series have a built-in battery voltage low

detection (BLD) circuit and a heavy load protection function.

Figure 4.9.1 shows the configuration of the circuit.

Config ura tion of BLD

c irc uit a nd he a vy

loa d p rote c tion

func tion

BLD circuit

The BLD circuit monitors the conditions of the battery

voltage (supply voltage), and software can check whether the

battery voltage has dropped below the detecting voltage level

of the BLD circuit: 2.4 V when supply voltage is 3.0 V

(S1C62N81), or 1.2 V when supply voltage is 1.5 V

(S1C62L81). Registers BLDON (BLD control on/off) and

BLDDT (BLD data) are used for the BLD circuit. The soft-

ware can turn BLD operation on and off. When BLD is on,

the IC draws a large current, so keep BLD off unless it is.

Since battery voltage detection is automatically performed

by the hardware every 2 Hz (0.5 second) when the heavy

load protection function operates, do not permit the opera-

tion of the BLD circuit by the software in order to minimize

power current consumption.

Heavy load protection function circuit

When using the S1C62N81, the melody, lamp, and other

features impose a heavy load on the battery. Therefore, a

heavy load protection function is incorporated in case of a

voltage drop. Software-initiated switching can be effected in

heavy load protection mode. The HLMOD register controls

the heavy load protection function. Conversely, when the

BLD circuit detects a voltage drop below 1.2 V (S1C62L81),

or 2.4 V (S1C62N81), switching to heavy load protection

mode is carried out automatically.

This function enables 0.9 V operation (S1C62L81/62B81).

I-56

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (BLD Circuit and Heavy Load Protection Function)

In th e h eavy load protection m ode, th e BLD circu it is acti-

vated in term itten tly by h ardware. Th e cycle is 2 Hz an d th e

operatin g tim e is 122 µs (wh en th e oscillation frequ en cy,

fosc, of th e oscillation circu it is 32.768 kHz). If th e sou rce

voltage is redu ced by a h eavy load wh ile in th e h eavy load

protection m ode, th e rate of decrease can be detected by

h ardware. Th e resu lt is th at th e h eavy load is lost. Even

wh en th e h eavy load protection m ode is released by soft-

ware, th e m ode con tin u es u n til th e sou rce voltage exceeds

th e voltage detected by th e BLD circu it. Th erefore, m alfu n c-

tion in g du e to a redu ced sou rce voltage can be preven ted

com pletely.

Regulated

voltage

circuit

BLD

circuit

VS1

VL1

Vss

Address 0FAH

BLD

sampling

control

D3

D1

HLMOD

BLDDT

BLDON

Vss

Fig. 4.9.1

Configuration of BLD and

heavy load protection circuits

D0

S1C62N81 TECHNICAL HARDWARE

EPSON

I-57

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (BLD Circuit and Heavy Load Protection Function)

Th e followin g explain s th e tim in g wh en th e BLD circu it

Op e ra tion of BLD

writes th e resu lt of battery voltage detection to th e BLDDT

d e te c tion tim ing

register.

Th e resu lt of battery voltage detection is written to th e

BLDDT register by th e BLD circu it, an d th is data can be

read by th e software to determ in e th e battery voltage.

Th ere are two m eth ods, explain ed below, for execu tin g th e

detection by th e BLD circu it.

(1) Sampling with HLMOD set to 1

Wh en HLMOD is set to 1 an d BLD sam plin g is execu ted,

th e detection resu lts can be written to th e BLDDT register

with th e followin g tim in g:

Im m ediately after sam plin g with th e 2 Hz cycle ou tpu t by

th e oscillation circu it wh ile HLMOD = 1 (sam plin g tim e is

122 µs in th e case of fosc = 32.768 kHz).

Con sequ en tly, after HLMOD h as been set to 1, th e n ew

detection resu lt is written in a 2 Hz.

(2) Sampling with BLDON set to 1

Wh en BLDON is set to 1, BLD detection is execu ted. As

soon as BLDON is reset to 0, th e resu lt is loaded to in th e

BLDDT register. To obtain a stable BLD detection resu lt,

th e BLD circu it m u st be on for at least 100 µs. So, to

obtain th e BLD detection resu lt, follow th e program m in g

sequ en ce below.

➀ Set BLDON to 1

➀ Main tain for 100 µs m in im u m

➀ Set BLDON to 0

➀ Read BLDDT

However, at 32 kHz for th e S1C62N81 an d S1C62L81,

th e in stru ction cycles are lon g en ou gh , so th ere is n o

n eed to worry abou t m ain tain in g 100 µs for BLDON = 1

in th e software.

I-58

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (BLD Circuit and Heavy Load Protection Function)

Notice that even if the BLD circuit detects a drop in the

supply voltage (1.2 V/2.4 V or less) and invokes the heavy

load protection mode, this will be the same as when the

software invokes the heavy load protection mode, in that the

BLD circuit will be sampled with a timing synchronized to

the 2 Hz output from the prescaler. If the BLD circuit

detects a voltage drop and enters the heavy load protection

mode, it will return to the normal mode once the supply

voltage recovers and the BLD circuit determines that the

supply voltage is 1.2 V/2.4 V or more.

The S1C62N81 has a heavy load protection function for

when the battery load becomes heavy and the supply voltage

drops, such as when a melody is played or an external lamp

lights. This functions works in the heavy load protection

Op e ra tion of he a vy

loa d p rote c tion

func tion

mode. The normal mode changes to the heavy load protec-

tion mode in the following two cases:

➀ When the software changes the mode to the heavy load

protection mode

➀ When the BLD circuit detects a supply voltage less than

2.4 V (S1C62N81) or 1.2 V (S1C62L81), in which case the

mode is automatically changed to the heavy load protec-

tion mode

Based on the operation of the BLD circuit and the heavy

load protection function, the S1C62L81 obtains an opera-

tion supply voltage as low as 0.9 V. See the electrical char-

acteristics for the precision of voltage detection by the BLD

circuit.

In the heavy load protection mode, the internally regulated

voltage is generated by the liquid crystal driver supply

output, VL2, in order to operate the internal circuit. Conse-

quently, more current is consumed in the heavy load protec-

tion mode than in the normal mode. Unless necessary, do

not select the heavy load protection mode with the software.

Note Activation of the BLD circuit by software in the heavy load protec-

tion mode causes a malfunction. Avoid such activation if possible.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-59

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (BLD Circuit and Heavy Load Protection Function)

Table 4.9.1 sh ows th e con trol bits an d th eir addresses for

Control of BLD c irc uit

th e BLD circu it an d th e h eavy load protection fu n ction .

a nd he a vy loa d

p rote c tion func tion

Table 4.9.1 Control bits for BLD circuit and heavy load protection function

Register

Address

Comment

D3

D2

D1

D0

Name

SR

0

1

0

HLMOD

0

BLDDT

BLDON

HLMOD

Heavy

load

Normal

load

Heavy load protection mode register

R/W

R

R/W

0

0FAH

Battery

voltage

low

Battery

voltage

normal

BLDDT

BLDON

0

BLD data

ON

OFF

BLD ON/OFF

HLMOD Heavy load protection mode on/off (0FAH D3)

Wh en 1 is written : Heavy load protection m ode on

Wh en 0 is written : Heavy load protection m ode off

Readin g: Valid

Wh en HLMOD is set to 1, th e IC en ters th e h eavy load

protection m ode, an d sam plin g con trol is execu ted for th e

tim e th e BLD circu it is on . Th e sam plin g tim in g is as fol-

lows:

Sam plin g in cycles of 2 Hz ou tpu t by th e oscillation circu it

wh ile HLMOD = 1 (sam plin g tim e is 122 µs in th e case of

fosc = 32.768 kHz).

Wh en BLD sam plin g is don e with HLMOD set to 1, th e

resu lts are written to th e BLDDT register with th e as follow-

in g tim in g:

Im m ediately on com pletion of sam plin g in cycles of 2 Hz

ou tpu t by th e oscillation circu it wh ile HLMOD = 1.

Con sequ en tly, after HLMOD is set to 1, th e n ew detected

resu lt is written in 2 Hz.

In th e h eavy load protection m ode, th e con su m ed cu rren t

becom es larger. Un less n ecessary, do n ot select th e h eavy

load protection m ode with th e software.

I-60

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (BLD Circuit and Heavy Load Protection Function)

BLDON BLD control on/off (0FAH D0)

Wh en 0 is written : BLD detection off

Wh en 1 is written : BLD detection on

Readin g:

Valid

Wh en th is bit is written , th e BLD detection on / off operation

is con trolled. Large cu rren t is drawn du rin g BLD detection ,

so keep BLD detection off except wh en n ecessary. Wh en

BLDON is set to 1, BLD detection is execu ted. As soon as

BLDON is reset to 0, th e detected resu lt is loaded in to th e

BLDDT register.

BLDDT BLD data (0FAH D1)

Wh en 0 is read:

Wh en 1 is read:

Su pply voltage ≥ Criteria voltage

Su pply voltage < Criteria voltage

Wh en BLDDT is 1, th e S1C62N81 en ters th e h eavy load

protection m ode. In th is m ode, th e detection operation of

th e BLD circu it is sam pled in 2 Hz cycles an d th e respective

detection resu lts are written to th e BLDDT register.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-61

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Analog Voltage Comparator)

4.10 Ana log Volta g e Com p a ra tor

Th e S1C62N81 Series h ave a bu ilt-in an alog voltage com -

Config ura tion of

a na log volta g e

c om p a ra tor

parator th at com pares two an alog in pu t voltages to produ ce

resu lt data 0 or 1 in register CMPDT, accordin g to th e com -

pared voltages, CMPP an d CMPM. Th e con figu ration of th e

an alog voltage com parator circu it is sh own in Figu re 4.10.1.

Th e voltage com parator h as two an alog voltage in pu ts,

CMPP (n on -in vertin g in pu t, +) an d CMPM (in vertin g in pu t,

-). Wh en th e voltage com parator is tu rn ed on by con trol

register CMPON, th e resu lt of com parin g CMPP an d CMPM

will be stored in register CMPDT. Th erefore, th e resu lt in

th e register will in dicate wh eth er CMPP is greater th an

CMPM (wh en CMPDT = 1) or sm aller th an CMPM (wh en

CMPDT = 0).

VDD

CMPP

CMPM

CMPDT

Data bus (D1)

Output

control

Address (0FBH)

Fig. 4.10.1

Data bus (D0)

CMPON

Power

control

Configuration of analog

VSS

Address (0FBH)

voltage comparator circuit

I-62

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Analog Voltage Comparator)

Two registers, CMPON an d CMPDT, are u sed in th e an alog

Op e ra tion of a na log

volta g e c om p a ra tor

voltage com parator. Th e CMPON register switch es th e

an alog voltage com parator on or off to redu ce power con -

su m ption . Th e CMPDT register in dicates th e resu lt of

com parison of th e CMPP an d CMPM pin s.

Writin g 1 to th e CMPON register tu rn s on th e com parator

circu it. After an in itial reset, th is bit is set to 0. Data in th e

CMPON register is read-accessible or write-accessible. A

wait tim e of at least 3 m s is requ ired for an alog voltage

com parator to becom e stable after its power is tu rn ed on .

Th e com parator respon se tim e depen ds on th e poten tial

differen ce between th e CMPP an d CMPM in pu ts.

Wh en an alog voltage com parator is tu rn ed on , th e circu it

com pares th e two an alog voltages from th e CMPP an d

CMPM in pu ts, th en ou tpu ts th e resu lt as bin ary 0

(CMPM>CMPP) or 1 (CMPP>CMPM). Th e resu lt of th e com -

parison is read from th e CMPDT register. Writin g to th e

CMPDT register is proh ibited.

Note Data in the CMPDT register becomes 1 when CMPON is 0 (analog

voltage comparator circuit is off), and undefined when the CMPP

and / or CMPM input is disconnected. Avoid reading operation

under those conditions.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-63

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Analog Voltage Comparator)

Table 4.10.1 lists th e con trol bits of th e an alog voltage

com parator an d th eir addresses.

Control of a na log

volta g e c om p a ra tor

Table 4.10.1 Control bits of analog voltage comparator

Register

Address

Comment

D3

D2

D1

D0

Name

CSDC

SR

0

1

0

Static

Dynamic

CSDC

0

CMPDT CMPON

R/W

LCD drive switch

R/W

R

0

0FBH

Comparator's voltage condition:

1 = CMPP(+)input > CMPM(-)input,

0 = CMPM(-)input > CMPP(+)input

Voltage comparator ON/OFF

+ > -

On

- > +

Off

CMPDT

CMPON

1

0

CMPON Comparator on/off control (0FBH D0)

Switch es th e an alog voltage com parator circu it to on or off.

Wh en 1 is written : Com parator tu rn s on

Wh en 0 is written : Com parator tu rn s off

Readin g:

Valid

After an in itial reset, th is bit is set to 0.

Note While analog voltage comparator is ON, the consumed current

becomes large. Unless necessary, do not turn on the analog

comparator.

Comparator data (0FBH D1)

CMPDT

Sh ows th e resu lt of com parin g CMPP an d CMPM.

Wh en 1 is read:

Wh en 0 is read:

Writin g:

CMPP voltage is greater th an

CMPM voltage

CMPP voltage is sm aller th an

CMPM voltage

In valid

Th is bit is u n defin ed wh en th e CMPP an d/ or CMPM in pu t

pin is discon n ected, an d is 1 wh en CMPON is 0.

After an in itial reset, th is bit is set to 1.

I-64

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

4.11 Me lod y Ge ne ra tor

Th e S1C62N81 Series h as bu ilt-in m elody gen erator. Ou t-

pu ts related to th e m elody fu n ction are gen erated from MO

term in al or R12 term in al. Th e followin g 3 types of m elody

playin g m ay be selected th rou gh th e m ask option :

Outline of m e lod y

g e ne ra tor

(1 )Piezo bu zzer sin gle t erm in al drivin g t h rou gh t h e MO

t erm in al

Th e R12 ou tpu t is set to DC ou tpu t th rou gh th e m ask

option . Melody is ou tpu t from th e MO term in al alon e.

Th is settin g in creases th e n u m ber of extern ally fitted

parts to play th e m elody bu t sin ce th e R12 ou tpu t m ay be

u sed as a com m on h igh -power cu rren t ou tpu t, it is u sefu l

wh en h igh -power cu rren t drivin g com m on ou tpu t is

requ ired.

(2 )Piezo bu zzer direct drivin g t h rou gh t h e MO an d R1 2

ou t pu t s

Th e R12 ou tpu t is set to piezo direct drivin g th rou gh th e

m ask option . Reversed sign al of th e MO term in al ou tpu t

sign al is ou tpu t from th e R12 term in al. Th is allows th e

piezo bu zzer direct drivin g to m aterialize. Th is settin g

m akes it possible to keep th e n u m ber of extern ally fitted

parts to th e m in im u m .

(3 )En velope drivin g

Th e R12 ou tpu t is set to th e en velope fu n ction th rou gh

th e m ask option . Sou n d pressu re of th e playin g is at-

ten u ated with tim e, m akin g it possible to im plem en t a

fu lly expressive playin g.

Refer to Ch apter 5, "BASIC EXTERNAL WIRING DIAGRAM"

for th e respective extern al wirin gs.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-65

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

Th e ch aracteristics of th e m elody gen erator are as follows:

(1 )Size of t h e Melody ROM: 80 words

Basically, on e n ote is equ ivalen t to on e word. An y n u m -

ber of m elodies m ay be written as lon g as it is with in 80

words. Data su ch as n ote len gth , in tervals an d en d of

m elody m ay be written .

(2 )Size of Scale ROM: 15 scales

C3–C6^#(with ou t frequ en cy booster) or C4–C7^#(with

frequ en cy booster) m ay be selected from am on g 15 scales.

Th e u se of frequ en cy booster m ay also be selected by th e

m ask option .

(3 )Playin g m ode:

Th ere are 3 playin g m odes.

➀ On e sh ot m ode (on ly 1 m elody is played)

➀ Level h old m ode (th e sam e or a differen t m elody is

con tin u ou sly played)

➀ Retrigger m ode (forced ch an ge or term in ation of

m elody)

(4 )Tem po:

2 types m ay be selected from am on g 16 types th rou gh th e

m ask option .

(5 )Playin g speed:

Aside from th e n orm al speed m ode, 8 tim es, 16 tim es,

an d 32 tim es speed m ode m ay be con trolled th rou gh

software. Th is fu n ction allows th e gen eration of sou n d

effects.

I-66

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

Th e block diagram of th e m elody gen erator is sh own in

Figu re 4.11.1. Th e n ote an d in terval data of th e m elody to

be played is pre-written on th e m elody ROM. Th e in terval

data of th e m elody ROM is u sed to specify th e scale ROM

address an d accordin g to th e scale ROM data read from it,

th e in terval gen eratin g circu it gen erates th e in terval. Th e

ou tpu t is con trolled at th e m elody ou tpu t con trol circu it an d

is ou tpu t at th e MO an d R12 term in als. Th e n ote gen erator

is gen erated accordin g to th e m elody ROM data. Th e ou tpu t

is en tered in th e m elody ROM address cou n ter; every tim e

th e playin g of a n ote is com pleted, on e address is

in crem en ted. Th is resu lts in con tin u ou s m elody bein g

au tom atically played. Th e playin g tem po is created by th e

tem po gen erator based on th e sign al wh ich divided th e

oscillation frequ en cy in th e oscillation circu it. Th rou gh th e

m ask option , 2 types of tem po m ay be selected from am on g

16 types. Moreover, th e division ratio of th e divider m ay be

m odified by software an d 4 types of playin g speed can be

im plem en ted. En velope fu n ction m ay also be added to th e

ou tpu t m elody an d R12 ou tpu t m ay be im plem en ted by

settin g it to correspon d with th e en velope.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-67

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

Interval

generating

circuit

Melody

output

control circuit

MO

Frequency

booster

R12

To CPU

Melody

interrupt

generator

Scale

ROM

32.768 kHz

End-of-melody

signal

Address

register

Address

counter

Melody

ROM

generator

Tempo

generator

Note

generator

Controller

Divider

Fig. 4.11.1

Melody generator

block diagram

I-68

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

A detailed description of th e circu its wh ich form th e m elody

gen erator is provided below.

(a) Frequ en cy boost er

Th e con figu ration of th e frequ en cy booster is sh own in

Figu re 4.11.2. It is a circu it wh ich raises th e in pu t

frequ en cy (32.768 kHz) for th e m elody gen erator to 2

tim es th e frequ en cy. Th e ou tpu t of th is frequ en cy

booster is provided with a switch th rou gh th e m ask

option ; by selectin g th is switch , scale wh ich can be

ou tpu t m ay be ch an ged. In oth er words, if frequ en cy

booster ou tpu t were selected for in pu t to in terval

gen eratin g circu it, in terval can be created between C4 to

C7^#an d if 32.768 kHz were selected as is, in terval can be

created between C3 to C6^#.

32.768 kHz

To interval

generating circuit

Booster

Fig. 4.11.2

Frequency booster

S1C62N81 TECHNICAL HARDWARE

EPSON

I-69

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

(b) Con t roller

Th e con figu ration of th e con troller is sh own in Figu re

4.11.3. Th e con troller con sists of a 4-bit register located

in th e I/ O RAM space an d an ON/ OFF con trol circu it an d

con trols th e m elody's ON/ OFF, tem po selection , playin g

speed selection . Th e ON/ OFF con trol circu it con trols th e

tu rn in g ON/ OFF of th e m elody playin g by en terin g th e

MELC register ou tpu t an d th e sign al from th e en d-of-

m elody sign al gen erator. Th e address of th e 4-bit register

is "0F2H" an d th e m ean in g of each bit is as follows:

D0 (MELC):

Th is is th e bit th at con trols th e tu rn in g ON/ OFF of th e

m elody playin g. Th e con trollin g fu n ction of th is bit

m akes it possible to con trol th e above-described 3

types of playin g. Refer to "Playin g m ode" regardin g th e

m eth od of con trol.

D1 (TEMPC):

Th is is th e bit th at selects th e tem po. 2 types of tem po

selected by m ask option m ay be ch an ged. Th e tim in g

of tem po ch an ge is n ot don e wh en data is written on

th is bit bu t rath er, wh en th e n ext m elody begin s.

D2 and D3 (CLKC0 and CLKC1):

Th is is th e bit th at ch an ges playin g speed. By th e

com bin ation of CLKC0 an d CLKC1, 4 types of playin g

speed m ay be selected. Th e playin g speed for th e

selectable tem po listed in Table 4.11.7 is th e n orm al

speed; playin g speeds wh ich are 8, 16 an d 32 tim es

th e n orm al speed m ay also be selected. Th is is u sefu l

in gen eratin g sou n d effects. For details, see "Playin g

tem po".

Note Since playing speed is modified simultaneously with data writing

on these bits, caution must be observed when operating these

bits in the middle of a playing.

I-70

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

End-of-melody signal

ON/OFF

control

circuit

ON/OFF

control signal

MELC

(D0)

Tempo control

signal

TEMPC

(D1)

CLKC0

(D2)

Playing speed

control signal

CLKC1

(D3)

Fig. 4.11.3

Controller

Address "0F2H"

(c) Address regist er

Th e con figu ration of th e m elody ROM address registers is

sh own in Figu re 4.11.4. It con sists of th e 7-bit register in

th e I/ O RAM space. Th e addresses are "0F0H" an d

"0F1H". Th e data of th ese registers in dicate th e ad-

dresses of th e m elody ROM wh ich becom e th e addresses

of th e m elody ROM wh en th e m elody is started. Th ese

m elody ROM addresses are written to th e m elody ROM

address cou n ter wh en th e m elody playin g begin s, i.e.,

before th e th e m elody playin g begin s, th e desired m elody

m ay be played from am on g th e m elodies written in th e

m elody ROM by settin g data on th ese registers.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-71

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

MAD0

(D0)

MAD1

(D1)

MAD2

(D2)

MAD3

(D3)

To Address counter

Address "0F0H"

MAD4

(D0)

MAD5

(D1)

MAD6

(D2)

Fig. 4.11.4

Address register

Address "0F1H"

Note Caution must be observed because when an address from

"50H" to "7FH" is set on the address register, since the address

does not exist in the melody ROM hardware-wise, all melody

ROM output will become "1" and silent notes equivalent to 32

notes will be played.

(d)Address cou n t er

Th e con figu ration of th e m elody ROM address cou n ters is

sh own in Figu re 4.11.5. It con sists of a cou n ter in wh ich

n ote playin g en d sign al gen erated from th e n ote gen erator

is en tered an d wh ich in creases th e m elody ROM ad-

dresses by 1 address every tim e a n ote playin g is com -

pleted. Moreover, wh en a m elody playin g begin s, address

register data (MAD0 to MAD6) are set on th ese cou n ters.

Th is cau ses th e address set in th e address register to

specify th e m elody ROM address.

Melody ROM Address

Note playing

end signal

Fig. 4.11.5

Address counters

I-72

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

(e) Melody ROM

Th e m elody ROM is a m ask ROM with 80 words × 9 bits

capacity in wh ich data of th e m elody to be played (n ote,

in terval, en d-of-m elody, etc.) is stored beforeh an d. An y

n u m ber of m elodies m ay be stored as lon g as th e total

n u m ber of n otes is with in 80 words (basically, 1 n ote/

word). Details regardin g th e m elody ROM con figu ration ,

etc., can be fou n d in n ext ection , "Melody data".

Note When the melody ROM is set with a non-existent address

("50H" and above), all of its output will become "1" (i.e., 32

silent notes) by the hardware.

(f) Divider

Th e con figu ration of th e divider is sh own in Figu re

4.11.6. It is a circu it th at divides th e clock (32.768 kHz)

wh ich is in pu t in th e m elody gen erator an d in pu ts th e

divided clock in to th e tem po gen erator. Th e dividin g ratio

m ay be con trolled by software. Th e data of th e "CLKC0"

an d "CLKC1" registers in th e above-m en tion ed con troller

is in pu t an d th e dividin g ratio will differ accordin g to th e

valu e of th e in pu t data. Th e dividin g ratio an d playin g

speed for th e com bin ation s of CLKC0 an d CLKC1 valu es

are sh own in Table 4.11.1. Th e "n orm al" speed in th e

playin g speed colu m n refers to th e playin g speed by

wh ich th e tem po listed in Table 4.11.7 m ay be im ple-

m en ted. playin g speeds 8 tim es (th e n orm al speed) or

m ore are u sefu l for gen eratin g sou n d effects.

Table 4.11.1

Playing

Speed

Dividing

Ratio

CLKC1

CLKC0

Dividing ratio

0

1

0

1

0

1

1/512

1/64

1/32

1/16

Normal

8 times

16 times

32 times

S1C62N81 TECHNICAL HARDWARE

EPSON

I-73

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

To tempo

generator

1/2

divider

1/2

divider

1/2

divider

1/8

divider

1/8

divider

32.768 kHz

Fig. 4.11.6

Divider

(g) Tem po gen erat or

Th e con figu ration of th e tem po gen erator is sh own in

Figu re 4.11.7. Th e tem po gen erator is a circu it wh ich

gen erates th e 2 types of tem po selected by m ask option

an d con sists of th e 4-bit cou n ter in wh ich th e ou tpu t

sign al from th e divider is in pu t an d th e 4 switch es wh ich

set th eir respective bit. Th e 4-bit cou n ter ou tpu t serves

as th e n ote gen erator in pu t. Th e 4 switch es are au to-

m atically set to gen erate th e 2 types of tem po selected by

m ask option . Bit settin gs an d th e correspon din g tem po

gen erated are sh own in Table 4.11.2. On th e oth er h an d,

th e relation sh ip between th e 2 types of tem po selected by

m ask option an d switch settin gs are sh own in Table

4.11.3. For exam ple, if th e respective bit valu es of th e 2

types of tem po selected by m ask option are "1" for

TEMPC = 0 an d "0" for TEMPC = 1, th e switch settin g for

th is bit com bin ation will be TEMPC (reverse sign al of th e

TEMPC register ou tpu t).

I-74

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

Table 4.11.2

TS3

0

TS2

0

TS1

0

TS0

0

30

32

Counter setting and tempo

0

1

0

1

0

1

0

34.3

36.9

40

0

1

0

1

0

43.6

48

0

1

0

1

0

1

0

53.3

60

1

0

1

0

68.6

80

1

0

1

96

1

0

1

0

1

0

1

120

160

240

480

Table 4.11.3

TEMPC=0 TEMPC=1

Switch Setting

Pull down

TEMPC

Pull up

Tempo and switch setting

0

1

0

1

0

1

Divider

output

signal

To note generator

Mask option

1/2

divider

1/2

divider

1/2

divider

1/2

divider

TS0

TS1

TS2

TS3

VDD

V

SS

Fig. 4.11.7

TEMPC

Tempo generator

TEMPC

S1C62N81 TECHNICAL HARDWARE

EPSON

I-75

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

(h )Not e gen erat or

Th is is a gen erator wh ich cou n ts th e tem po gen erator

ou tpu t an d creates variou s n otes. Its con figu ration is

sh own in Figu re 4.11.8. It con sists of cou n ters in wh ich

3 bits can be set. Each cou n ter is set by th e 3 bits (D5–

D7) from th e m elody ROM cau sin g th e cou n ter dividin g

ratio to ch an ge an d h en ce variou s n otes are gen erated.

Th e bit settin gs an d th e correspon din g n otes gen erated

are sh own in Table 4.11.4. Th e cou n ter ou tpu t becom es

th e n ote playin g en d sign al an d th e address of th e m elody

ROM is in crem en ted 1 step at a tim e.

Table 4.11.4

D7

0

D6

0

D5

0

Note

Note data and notes

0

1

0

1

0

1

+

1

0

1

0

1

0

1

Note playing

signal

Tempo generator

output signal

1/2

divider

1/2

divider

1/2

divider

Fig. 4.11.8

Melody ROM output

(D5–D7)

Note generator

I-76

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

(i) Scale ROM

Th is is a m ask ROM in wh ich 15 scale types wh ich h ave

been option ally selected an d created from eith er C3–C6^#

(available ou tpu t frequ en cy ran ge: 4,096 Hz–125.5 Hz;

with ou t frequ en cy booster) or C4–C7^#(available ou tpu t

frequ en cy ran ge: 8,192 Hz–251.1 Hz; with frequ en cy

booster) are stored beforeh an d. Th e 15 available ad-

dresses are "00H"–"0EH". Word len gth is 8 bits; th e data

written on th em an d th e correspon din g scale (frequ en cy)

gen erated are sh own in Tables 4.11.5 (a) an d (b). Th e

m axim u m valu e wh ich m ay be written as a data is "FDH".

Th e address is specified by th e m elody ROM ou tpu t an d

th e ou tpu t is en tered in th e in terval gen eratin g circu it.

Note Bear in mind that the range of the data which can be written on

the scale ROM is from "00H" to "FDH". If any data beyond this

range is written, the interval generating circuit will not function

normally.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-77

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

Table 4.11.5 (a) Scale ROM data and interval (without frequency booster)

Scale ROM Code

S7 S6 S5 S4 S3 S2 S1 S0 Hex.

Dividing

Ratio

Absolute

Error (%) Frequency (Hz)

Standard

Scale Frequency

Data

(Hz)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

04 1/128 x 1/2

12 1/121 x 1/2

20 1/114 x 1/2

2F 1/107 + 103

0

-0.152

0.031

0.024

0.092

-0.113

0.010

-0.030

0.167

0.143

-0.226

-0.287

0

-0.153

0.031

-0.339

-0.400

-0.113

-0.542

0.503

-0.453

0.144

-0.226

-0.287

0

0.675

0.031

-0.339

-0.400

-0.113

0.563

-0.668

0.787

0.144

-0.226

-0.287

0

128

C3

C3#

D3

D3#

E3

F3

F3#

G3

G3#

A3

A3#

B3

C4

C4#

D4

D4#

E4

F4

F4#

G4

G4#

A4

A4#

B4

C5

C5#

D5

128

135.611

143.675

152.218

161.270

170.860

181.019

191.783

203.187

215.270

228.070

241.632

256

271.222

287.350

304.436

322.540

341.720

362.038

383.566

406.374

430.540

456.140

483.264

512

542.444

574.700

608.872

645.080

683.440

724.076

767.132

812.748

861.080

912.280

966.528

1024

135.405

143.719

152.409

161.419

170.667

181.039

191.626

203.528

215.579

227.556

240.941

256

270.810

287.439

303.407

321.255

341.333

360.088

385.506

404.543

431.158

455.111

481.882

512

546.133

574.877

606.815

642.510

682.667

728.178

762.047

819.200

862.316

910.222

963.765

1024

1 3B 1/101 + 102

0

1

44 1/96 x 1/2

51 1/90 + 91

1 5B 1/85 + 86

65 1/80 + 81

0 6C 1/76 x 1/2

74 1/72 x 1/2

0 7C 1/68 x 1/2

84 1/64 x 1/2

1 8D 1/60 + 61

1

0

92 1/57 x 1/2

98 1/54 x 1/2

0 9E 1/51 x 1/2

0 A4 1/48 x 1/2

1 AB 1/45 + 46

1 B1 1/42 + 43

1 B5 1/40 + 41

0 B8 1/38 x 1/2

0 BC 1/36 x 1/2

0 C0 1/34 x 1/2

0 C4 1/32 x 1/2

0 C8 1/30 x 1/2

1 CD 1/28 + 29

0 CE 1/27 x 1/2

1 D3 1/25 + 26

0 D4 1/24 x 1/2

1 D9 1/22 + 23

1 DB 1/21 + 22

0 DC 1/20 x 1/2

0 DE 1/19 x 1/2

0 E0 1/18 x 1/2

0 E2 1/17 x 1/2

0 E4 1/16 x 1/2

0 E6 1/15 x 1/2

D5#

E5

F5

F5#

G5

G5#

A5

A5#

B5

C6

0.675

1084.888

C6#

1092.267

I-78

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

Table 4.11.5 (b) Scale ROM data and interval (with frequency booster)

Scale ROM Code

S7 S6 S5 S4 S3 S2 S1 S0 Hex.

Dividing

Ratio

Absolute

Error (%) Frequency (Hz)

Standard

Scale Frequency

Data

(Hz)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

04 1/128 x 1/2

12 1/121 x 1/2

20 1/114 x 1/2

2F 1/107 + 103

0

-0.152

0.031

2.448

0.092

-0.113

0.011

-0.082

0.168

0.143

-0.226

-0.287

0

-0.152

0.031

-0.339

-0.400

-0.113

-0.541

0.503

-0.453

0.143

-0.226

-0.287

0

0.676

0.031

-0.339

-0.399

-0.113

0.563

-0.667

0.788

0.143

-0.226

-0.287

0

256

C4

C4#

D4

D4#

E4

F4

F4#

G4

G4#

A4

A4#

B4

C5

C5#

D5

D5#

E5

F5

F5#

G5

G5#

A5

A5#

B5

C6

C6#

D6

256

271.222

287.350

304.436

322.540

341.720

362.038

383.566

406.374

430.540

456.140

483.264

512

542.444

574.700

608.872

645.080

683.440

724.076

767.132

812.748

861.080

912.280

966.528

1024

1084.888

1149.400

1217.748

1290.160

1366.880

1448.152

1534.264

1625.496

1722.160

1824.560

1933.056

2048

270.810

287.439

304.819

322.837

341.333

362.077

383.251

407.056

431.158

455.111

481.882

512

541.620

574.877

606.815

642.510

682.667

720.176

771.012

809.086

862.316

910.222

963.765

1024

1092.267

1149.754

1213.630

1285.020

1365.333

1456.356

1524.093

1638.400

1724.632

1820.444

1927.529

2048

1 3B 1/101 + 102

0

1

44 1/96 x 1/2

51 1/90 + 91

1 5B 1/85 + 86

65 1/80 + 81

0 6C 1/76 x 1/2

74 1/72 x 1/2

0 7C 1/68 x 1/2

84 1/64 x 1/2

1 8D 1/60 + 61

1

0

92 1/57 x 1/2

98 1/54 x 1/2

0 9E 1/51 x 1/2

0 A4 1/48 x 1/2

1 AB 1/45 + 46

1 B1 1/42 + 43

1 B5 1/40 + 41

0 B8 1/38 x 1/2

0 BC 1/36 x 1/2

0 C0 1/34 x 1/2

0 C4 1/32 x 1/2

0 C8 1/30 x 1/2

1 CD 1/28 + 29

0 CE 1/27 x 1/2

1 D3 1/25 + 26

0 D4 1/24 x 1/2

1 D9 1/22 + 23

1 DB 1/21 + 22

0 DC 1/20 x 1/2

0 DE 1/19 x 1/2

0 E0 1/18 x 1/2

0 E2 1/17 x 1/2

0 E4 1/16 x 1/2

0 E6 1/15 x 1/2

D6#

E6

F6

F6#

G6

G6#

A6

A6#

B6

C7

0.676

2169.776

C7#

2194.533

S1C62N81 TECHNICAL HARDWARE

EPSON

I-79

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

(j) In t erval gen erat in g circu it

Th e in terval gen eratin g circu it gen erates th e in terval

(frequ en cy) correspon din g to th e scale ROM ou tpu t. Its

con figu ration is sh own in Figu re 4.11.9. Usin g th e in pu t

clock (32.768 kHz) to th e m elody gen erator or th e 8-bit

divider with th e booster ou tpu t (65.536 kHz) as in pu t

clock, dividin g ratios (1/ 8–1/ 261) set by th e scale ROM

ou tpu t (S0–S7) can be attain ed. Th e divider ou tpu t

passes th rou gh th e ou tpu t con troller an d becom es sou n d

ou tpu t. Scales wh ich can be ou tpu t are C3–C6^#(avail-

able ou tpu t frequ en cy ran ge: 4,096 Hz–125.5 Hz; with ou t

frequ en cy booster) or C4–C7^#(available ou tpu t frequ en cy

ran ge: 8,192 Hz–251.1 Hz; with frequ en cy booster). Th e

dividin g ratio m ay be derived from S0–S7 valu es wh ich

are th e scale ROM ou tpu t u sin g th e followin g equ ation :

N (dividing ratio) = (/S7 × 2⁶+ /S6 × 2⁵+ /S5 × 2⁴+ /S4 × 2³+ /S3

× 2²+ /S2 × 2¹+ /S1 × 2⁰+3) × 2 + S0

(Note: / SX = reversed valu e of SX)

Example:

If

(S7, S6, S5, S4, S3, S2, S1, S0) = (1, 1, 1, 0, 0, 1, 0, 0),

th en ,

N = (0 × 2⁶+ 0 × 2⁵+ 0 × 2⁴+ 1 × 2³+ 1 × 2²+ 0 × 2¹+ 1 × 2⁰

+3) × 2 + 0 = 32

In oth er words, if th e in pu t clock were 32.768 kHz,

th e ou tpu t will be 32,768/ 32 = 1,024 Hz (C6).

Th e selection of in pu t clock m ay be don e by ch an gin g th e

switch (by m ask option ) explain ed in th e section on

booster.

Booster

output

To melody output

control circuit

Divider (dividing ratio: 1/8–1/261)

S0–S7

Scale ROM output (8 bits)

Fig. 4.11.9

Interval generating circuit

I-80

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

(k )En d-of-m elody sign al gen erat or

Th is is a circu it th at receives th e en d-of-m elody data

written on th e m elody ROM an d gen erates th e en d-of-

m elody sign al wh ich syn ch ron ized with th e en d of a n ote

playin g. Th e ou tpu t is en tered in to th e con troller an d th e

m elody in terru pt gen erator an d becom es th e sou rce

sign al wh ich in form s th e en d of a m elody.

(l) Melody in t erru pt gen erat or

Th e con figu ration of th e m elody in terru pt gen erator is

sh own in Figu re 4.11.10. It is a circu it th at receives th e

en d-of-m elody sign al from th e en d-of-m elody sign al

gen erator an d gen erates th e m elody in terru pt sign al

wh ich in form s th e CPU th at a certain m elody h as been

com pleted. At th e sam e tim e, it sets an in terru pt factor

flag th e tim in g of wh ich is sh own in Figu re 4.11.11. Th e

in terru pt factor flag becom es valid approxim ately 7.8 m s

(in case of n orm al speed) after th e en d-of-m elody sign al is

gen erated. Th e in terru pt factor flag m ay be read ou t by

software an d is reset sim u ltan eou sly with th e read ou t.

Th e register address is "ECH D0". It can also be m asked

for th e in terru pt sign al an d m askin g can be con trolled by

software. Th e m ask register address is "E7H D0".

End-of-melody signal

IMEL

Interrupt signal

Address "0ECH"

EIMEL

Address "0E7H"

Fig. 4.11.10

Melody interrupt generator

S1C62N81 TECHNICAL HARDWARE

EPSON

I-81

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

Playing

End-of-melody

signal

Approx. 7.8 ms

Valid

Melody interrupt

signal

Fig. 4.11.11

Interrupt factor

flag

Valid

Interrupt generation timing

Note Reading out the interrupt request flag or writing on the mask

register should always be performed in the "DI (interrupt prohib-

ited)" state. Otherwise, misoperation may result.

(m )Melody ou t pu t con t rol circu it

Th is is a circu it th at determ in es th e form of m elody

playin g (piezo bu zzer direct drivin g an d addition of en ve-

lope fu n ction ) accordin g to th e m ask option selection .

(n ) Melody ou t pu t t erm in al (M0 an d R1 2 )

Th is is a term in al wh ich produ ces m elody du rin g playin g.

Its ou tpu t con figu ration an d ou tpu t waveform are sh own

in Figu re 4.11.12. Th e con figu ration differs if th e m ask

option selection were R12.

I-82

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

VDD

R12

register

output

R12

Attack signal

Melody signal

R12

register

output

R12

Vss

VDD

Vss

VDD

MO

Melody signal

MO

Melody signal

Analog switch

Vss

R12

(with external

capacitor)

R12

MO

R12

MO

(2) R12: Melody reverse output

(1) R12: DC output

(3) R12: With envelope function

Fig. 4.11.12 Melody terminal output configuration and output waveform

(1 )R1 2 : DC ou t pu t

Melody is ou tpu t from th e MO term in al an d from th e

R12 term in al, data written on th e "R12" register is

ou tpu t. Th e MO term in al is a com plem en tary ou tpu t

term in al an d goes h igh wh en m elody is n ot played.

Com plem en tary ou tpu t or Pch open -drain ou tpu t m ay

be selected for th e R12 term in al by m ask option .

(2 )R1 2 : Melody reverse ou t pu t

Usin g MO an d R12 term in als, th e piezo bu zzer m ay be

directly driven . Du rin g playin g, reverse sign al of th e

MO term in al is ou tpu t from th e R12 term in al. Both

term in als go h igh wh en m elody is n ot bein g played.

Th e ou tpu t con figu ration of both term in als becom es

com plem en tary.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-83

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

(3 )R1 2 : Wit h en velope fu n ct ion

En velope fu n ction can be im plem en ted by con n ectin g

an extern al capacitor to th e R12 term in al. Melody is

ou tpu t from th e MO term in al an d th e sign al wh ich will

rech arge th e extern al capacitor will be ou tpu t from th e

R12 term in al. Th e R12 electric poten tial will tu rn ou t

su pplyin g th e n egative electric poten tial of th e MO

term in al ou tpu t an d wh en th e m elody sign al goes

h igh , it will pass th e an alog switch an d will be su p-

plied to th e MO term in al. For details regardin g th e

en velope fu n ction , refer to "En velope fu n ction ".

•

Melody ROM

Me lod y d a ta

Th e m elody ROM h as an 80-word capacity, th e len gth of a

word bein g 9 bits. Basically, data of 1 n ote is stored in 1

word. Th ese data are con tin u ou sly read ou t by th e h ard-

ware an d m elody is played. Th e 4 types of data wh ich

m ay be written as 1-n ote data are as follows:

(1) In terval data

(2) Note data

(3) En d data

(4) Attack data

Wh en m elody playin g starts, th e start address is specified

with th e address written on th e address register. Th e

m elody ROM address is th en au tom atically in creased by

th e address cou n ter on e step at a tim e an d m elody is

played. Th e m elody au tom atically stops at th e poin t

wh ere th e en d-of-m elody data written on th e m elody ROM

is read ou t by th e h ardware. At th e sam e tim e, in terru pt

flag is set an d in terru pt for th e CPU is gen erated.

D8 D7 D6 D5 D4 D3 D2 D1 D0

Fig. 4.11.13

Attack

data

End

data

Data format of

Note data

Scale data

the melody ROM

I-84

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

Sin ce on ly m elody start address settin g an d m elody start

con trol m ay be con trolled by software, option al m elodies

wh ich h ave been written on th e m elody ROM can easily

be played by lessen in g th e load of th e software.

Th e form at of th e data con tain ed in a m elody ROM word

is sh own in Figu re 4.11.13. Th ese m elody data are

explain ed in details below.

•

Not e dat a (D5 –D7 )

Note data are data wh ich in dicate th e n otes to be u sed.

As sh own in Figu re 4.11.13, n ote data are written on 3

bits: D5–D7. Th ere are 8 types of n otes wh ich can be

u sed in th e S1C62N81 Series an d th e correspon din g 3

n ote data bits are sh own in Table 4.11.6. Alth ou gh n otes

sh orter th an 32 n otes m ay n ot be played, n otes lon ger

th an 2 n otes m ay be played by operatin g th e above-

m en tion ed attack n ote. Th is procedu re is explain ed in

th e section on attack data.

Table 4.11.6

D7

0

D6

0

D5

0

Note

Note data and notes

0

1

0

1

0

1

+

1

0

1

0

1

0

1

S1C62N81 TECHNICAL HARDWARE

EPSON

I-85

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

•

Scale dat a (D1 –D4 )

In tervals to be u sed are pre-written on th e scale ROM.

Th ere are 15 scale ROM addresses wh ich can be u sed:

"00H" to "0EH". Th e addresses are written on th e 4 bits

(D1–D4; see Figu re 4.11.13) wh ich serve as in terval data

area. In tervals written on th e in terval ROM address wh ich

h as been specified with th e in terval data (refer to Table

4.11.5) are gen erated at th e in terval gen eratin g circu it.

Alth ou gh th e scale ROM addresses are on ly from "00H" to

"0EH", "0FH" also exists in th e h ardware an d is set for

silen t n otes. Becau se of th is, writin g "0FH" on th e

m elody ROM in terval data area will resu lt in th e playin g

of silen t n otes. Th e len gth of a silen t n ote depen ds on th e

n ote data written on th e sam e word.

•

At t ack dat a (D8 )

Th e attack data is a 1-bit data wh ich determ in es wh eth er

or n ot to m ake th e break between n otes clear. In each

m elody first word, set th is data to "1". Oth erwise, th ere

will be n o m elody play even if th e u ser starts play.

If en velope fu n ction is n ot available, writin g "1" for th is

bit will produ ce an approxim ately 12 m s rest every tim e

th e m elody ROM address in creases by 1 step (i.e., at th e

break of th e playin g of differen t n otes). Th is is particu -

larly u sefu l wh en th e sam e n otes follow on e an oth er. As

a ru le, "1" is written on th e attack bit of all words. How-

ever, wh en lon g n otes oth er th an th ose listed in Table

4.11.6 are desired, th ey can be im plem en ted by lin kin g

several words of th e sam e in terval to a con tin u ou s ad-

dress an d at th e sam e tim e settin g th e attack bit to "0".

On th e oth er h an d, wh en en velope fu n ction is available,

settin g th is bit to "1" will cau se th e capacitor for th e

en velope fu n ction wh ich is extern ally in stalled to be

rech arged wh en th e playin g starts an d in crease th e

sou n d pressu re of th e playin g. Moreover, wh en th is bit is

set to "0", sin ce th e capacitor will be con tin u ou sly dis-

ch arged with ou t bein g rech arged, th e sou n d pressu re of

th e playin g will con tin u e to dim in ish . Th e prin ciple of th e

en velope fu n ction is explain ed in details in th e n ext

section .

I-86

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

•

En d dat a (D0 )

Th is is 1-bit data wh ich in dicate th e en d of a set of played

m elody. If th is bit were written with "1", wh en th e word

is played, en d-of-m elody sign al will be gen erated at th e

en d-of-m elody sign al gen erator an d will th en be in pu t to

th e m elody in terru pt gen erator an d th e con troller. Th is

sign al is received at th e m elody in terru pt gen erator wh ich

issu es in terru pt requ est to th e CPU an d gen erates in ter-

ru pt flag. Moreover, th e con troller stops th e playin g

wh en th e m elody ON/ OFF con trol register is set to "0"

wh en th e sign al is received an d eith er repeats th e sam e

m elody or con tin u ou sly plays n ew m elodies wh en it is set

to "1". By dividin g th e 80-word m elody ROM with en d-of-

m elody data, an y n u m ber of m elodies m ay be written as

lon g as it is with in th e capacity. Also, a m elody wh ich

will be repeatedly u sed n eed be written on ly on ce, i.e.,

th ere is n o n eed to write th e m elody for as m an y n u m ber

of tim es you wish to repeat it. Repeated playin g can be

easily accom plish ed by m erely specifyin g th e playin g start

address repeatedly th rou gh th e software. Con trol of

playin g is explain ed in details in "Con trol of playin g".

Silen t n ote m ay be played by writin g "0FH" on th e m elody

ROM in terval data. Th e len gth of th e silen t n ote is th e sam e

as th e len gth of th e n ote written on th e sam e word. For

details, refer to "Melody data".

Pla ying of sile nt note

S1C62N81 TECHNICAL HARDWARE

EPSON

I-87

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

Th e S1C62N81 Series m ay be added with en velope fu n ction

Enve lop e func tion

for m elody playin g by m ask option . Th e IC in tern al circu it

wh en th e en velope fu n ction is valid an d th e extern al circu it

requ ired is sh own in Figu re 4.11.14. Th e IC in tern al settin g

is don e by m ask option an d th e followin g n eed to be exter-

n ally in stalled:

-

piezo bu zzer sou n din g body;

booster coil for raisin g th e sou n d pressu re of th e playin g;

PNP bipolar tran sistor to drive th e sou n din g body (piezo

bu zzer);

-

capacitor for im plem en tin g sm ooth sou n d pressu re

atten u ation ; an d

resistor for con trollin g th e power cu rren t disch arge of th e

capacitor.

Th e ou tpu t waveform wh en en velope fu n ction is sh own in

Figu re 4.11.15. Th e attack sign al in dicated in th e diagram

will go h igh ("H" level) wh en th e playin g of th e word starts if

th e attack data written on th e m elody ROM were "1". Th e

pu lse width is approxim ately 12 m s. Th e ATK (attack) sign al

rech arges th e extern ally in stalled capacitor an d th e R12

term in al ou tpu t level will be rech arged u p to th e power

voltage as sh own in Figu re 4.11.15. Th is will resu lt in th e

MO term in al ou tpu t am plitu de becom in g th e power voltage

sin ce th ey (R12 an d MO term in als) are wired togeth er in side

th e IC as sh own in Figu re 4.11.14. Th e sou n d pressu re of

th e m elody played th en will be m axim u m . Hen ceforth ,

becau se th e capacitor con n ected to th e R12 term in al is

disch arged as th e base cu rren t of th e extern ally in stalled

tran sistor as tim e passes, th e base cu rren t will drop an d th e

playin g sou n d pressu re will atten u ate with th e passin g of

tim e. Th e MO term in al ou tpu t waveform is sh own in Figu re

4.11.15. Th e MO term in al ou tpu t am plitu de will decrease

with capacitor disch arge. Th is is th e prin ciple of th e en ve-

lope fu n ction .

I-88

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

VDD

Capacitor

R12

Attack signal

S1C62N81

Melody signal

PNP

Transistor

Piezo

buzzer

Booster

coil

MO

Fig. 4.11.14

Configuration of the

envelope function

Analog switch

Vss

Attack signal

R12 pin output

Melody signal

MO pin output

Fig. 4.11.15

Envelope output waveform

S1C62N81 TECHNICAL HARDWARE

EPSON

I-89

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

In th e S1C62N81 Series, 2 types of m elody playin g tem po

Pla ying te m p o

m ay be selected from am on g 16 types by m ask option .

Tem pos wh ich m ay be selected are sh own in Table 4.11.7

(see also "Tem po gen erator"). Th e proper u se of th e 2 types

of tem po selected is specified th rou gh th e software. Th e 2

types of tem po wh ich m ay selected are: th e tem po to be

played wh en "0" is written on th e TEMPC register of th e

con troller an d th e tem po to be played wh en "1" is written on

th e said register.

TS3

0

TS2

0

TS1

0

1

TS0

0

1

0

1

Table 4.11.7

30

32

34.3

36.9

40

Tempos available

for selection

0

1

0

1

0

1

0

43.6

48

0

1

0

1

0

1

0

53.3

60

1

0

1

0

68.6

80

1

0

1

96

1

0

1

0

1

0

1

120

160

240

480

Note Changing the 2 types of tempo selected by mask option is not done

on the spot when data is written on the TEMPC register but rather,

the tempo is changed when a new melody is played after the data

has been written, i.e., the tempo cannot be changed in the middle

of a melody playing.

I-90

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

Fu rth erm ore, 4 types of playin g speed m ay be selected in

th e S1C62N81 Series. Th e selection can be don e th rou gh

th e software an d con trol is perform ed by writin g data on

CLKC0 an d CLKC1 registers of th e con troller. Th e data

written on th e registers an d th e correspon din g playin g speed

are sh own in Table 4.11.8. By writin g "0" on CLKC0 an d

CLKC1, n orm al speed tem po (i.e., tem po selected by m ask

option ) m ay be played. playin g at 8 tim es, 16 tim es an d 32

tim es of th e n orm al speed is u sefu l for produ cin g sou n d

effects for gam es an d an im al sou n ds.

Table 4.11.8

CLKC1

CLKC0 Playing Speed

Playing speed

0

1

0

1

0

1

Normal

8 times

16 times

32 times

Note Changing the playing speed is instantly accomplished by writing

data on CLKC0 and CLKC1 registers. When speed need not be

changed in the middle of a melody, write the playing speed data

upon completion of a melody playing, i.e., during rest.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-91

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

Th e S1C62N81 Series h ave 3 m odes for m elody playin g: on e

Pla ying m od e

sh ot m ode, level h old m ode an d retrigger m ode. Th e con trol

of th ese m odes is don e th rou gh operation of th e MELC

register of th e con troller.

(a) On e sh ot m ode

In th is m ode, on ly on e specified m elody is played; playin g

au tom atically stops wh en th e m elody en ds. Con trol

procedu res are as follows:

(1) Set th e m elody ROM address (start address) of th e

desired m elody in th e address register (MAD0–MAD6).

(2) Im m ediately after writin g "1" (before th e m elody play-

in g en ds), write "0" on th e MELC register.

Th e above operation will allow on ly on e m elody to be

played. Melody playin g is started from th e address writ-

ten on th e address register, by writin g "1" on th e MELC

register. Wh en playin g of th e last word of a m elody (en d-

of-m elody data is "1") en ds, en d-of-m elody sign al is gen er-

ated an d in terru pt requ est to th e CPU an d in terru pt flag

are gen erated in th e m elody in terru pt gen erator. At th is

poin t, sin ce "0" h as previou sly been written on th e MELC

register with th e above operation (2), sign al to h alt play-

in g is gen erated in th e con troller an d h en ce, playin g will

stop.

Th e relation sh ip between MELC register valu e an d play-

in g ou tpu t is sh own in Figu re 4.11.16.

"MELC"

register

0

1

0

Approx. 125 ms

Playing

Fig. 4.11.16

One shot mode

Generation of

melody interrupt

I-92

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

Note Bear in mind that playing will start approximately 125 ms (in

case of normal speed) after writing "1" on the MELC register.

(b) Level h old m ode

Repetition of th e sam e m elody or con tin u ou s playin g of

differen t m elodies is possible in th is m ode. Th e operatin g

procedu re are as follows:

(1) Set th e m elody ROM address (start address) of th e

desired m elody in th e address register (MAD0–MAD6).

(2) Write "1" on th e MELC register.

(3) Im m ediately after procedu re (2) above (before th e

m elody bein g played en ds), write th e start address of

th e secon d m elody on th e address register (MAD0–

MAD6). Wh en repeatin g th e sam e m elody, th ere is n o

n eed to write an ew on th e address register.

(4) Sin ce m elody in terru pt will be gen erated wh en th e first

m elody en ds, write th e address for th e th ird m elody on

th e address register (MAD0–MAD6) with th e in terru pt

rou tin e. Th is operation m u st be com pleted before th e

secon d m elody en ds. Wh en th e sam e m elody is to be

repeatedly played, th ere is n o n eed for th is operation .

Th e option al m elody in th e m elody ROM m ay con tin u -

ou sly be played by repeatin g th e above steps.

(5) To stop playin g, write "0" on th e MELC register wh ile

th e last m elody is bein g played. Th is will cau se th e

playin g to be au tom atically stopped wh en playin g of

th e last m elody is com pleted.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-93

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

Th e relation sh ip between MELC register valu e an d play-

in g ou tpu t is sh own in Figu re 4.11.17.

"MELC"

register

0

1

Approx. 125 ms

Melody Melody .... Melody Melody

Playing

1

2

n-1

n

Fig. 4.11.17

Generation of

Level hold mode

melody interrupt

(c) Ret rigger m ode

Th is playin g m ode is for m odifyin g or stoppin g th e m elody

forcedly in th e m iddle of playin g. Its operatin g procedu re

is as follows:

(1) In th e m iddle of a m elody playin g, write th e m elody

ROM address of th e n ext m elody to be played on th e

address register (MAD0–MAD6).

(2) Ch an ge th e MELC register settin g from "0" to "1". At

th is poin t, th e played m elody will be forcedly ch an ged.

(3) After th is operation , th e 3 types of playin g m ode m ay

be selected freely again .

To stop a m elody in th e m iddle of its playin g is also

im plem en ted by em ployin g th is m ode. Th e operation is

as follows:

(1) In th e m iddle of a m elody playin g, set th e m elody ROM

address written with silen t n otes on th e address regis-

ter (MAD0–MAD6).

(2) Ch an ge th e MELC register settin g from "0" to "1" an d

th en to "0" again .

I-94

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

With th e above operation , th e m elody bein g played will be

forced to ch an ge in to silen t n ote playin g; as soon as th e

playin g of th e silen t n otes is com pleted, th e playin g will

au tom atically stop. In th e above operation (2), writin g

operation for th e last "0" m u st be don e before th e playin g

of silen t n otes en ds.

Th e relation sh ip between MELC register valu e an d play-

in g ou tpu t is sh own in Figu re 4.11.18.

"MELC"

register

0

1

0

1

Approx.

125 ms

Approx.

125 ms

Playing

Melody 1

Melody 2

Generation of

melody interrupt

Fig. 4.11.18

Retrigger mode

Note Bear in mind that when melody playing is forcedly modified with

the above operations, playing of the modified melody will start

approximately 125 ms (in case of normal speed) after "1" has

been written on the MELC register.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-95

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

Operation of registers for m elody con trol is explain ed in th is

section .

Control of the

m e lod y g e ne ra tor

Table 4.11.9 Control bits of melody generator

Register

Address

Comment

D3

D2

D1

D0

Name

0

SR

1

0

EIMEL

R

0

R/W

0

0E7H

0ECH

0F0H

0F1H

0F2H

EIMEL

0

Enable

Mask

Interrupt mask register (melody)

0

IMEL

R

0

Yes

High

No

IMEL

MAD3

MAD2

MAD1

MAD0

0

Interrupt factor flag (melody)

Melody ROM address (AD3)

Melody ROM address (AD2)

Melody ROM address (AD1)

Melody ROM address (AD0, LSB)

Low

MAD3

MAD2

MAD1

MAD0

R/W

0

MAD6

MAD5

R/W

MAD4

MAD6

MAD5

MAD4

0

High

ON

Low

OFF

Melody ROM address (AD6, MSB)

Melody ROM address (AD5)

Melody ROM address (AD4)

R

CLKC1

CLKC0

TEMPC

MELC

CLKC1

CLKC0

TEMPC

MELC

CLKC1(0)&CLKC0(0) : melody speed × 1

CLKC1(0)&CLKC0(1) : melody speed × 8

CLKC1(1)&CLKC0(0) : melody speed × 16

CLKC1(1)&CLKC0(1) : melody speed × 32

Tempo change control

R/W

Melody control ON/OFF

I-96

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

– MELC: Melody ON/OFF Control Register (F2H D0)

By operatin g th is register, con trol of th e m elody playin g

ON/ OFF an d th e 3 types playin g m odes—on e sh ot m ode,

level h old m ode an d retrigger m ode—can be perform ed.

Wh en 1 is written :

Wh en 0 is written :

Readin g:

Playin g starts

Playin g stops

Valid

– TEMPC: Tempo Control Register (F2H D1)

By operatin g th is register, 1 type of tem po m ay be se-

lected from th e 2 types previou sly selected by m ask

option .

Wh en 1 is written :

Wh en 0 is written :

Readin g:

Selects th e tem po of TEMPC1

selected by m ask option

Selects th e tem po of TEMPC0

selected by m ask option

Valid

Note Changing the tempo through this register is not possible in the

middle of a melody playing even if this register is operated while

a melody is being played. Change of melody will synchronize

with the playing of a new melody.

– CLKC0: Playing Speed Control Register (F2H D2)

CLKC1: Playing Speed Control Register (F2H D3)

By operatin g th ese registers, playin g speed of a m elody

m ay be ch an ged. Th e com bin ation of CLKC0 an d CLKC1

register valu es an d playin g speed are sh own in Table

4.11.10.

Wh en 1 is written :

Wh en 0 is written :

Readin g:

1

0

Valid

S1C62N81 TECHNICAL HARDWARE

EPSON

I-97

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

Table 4.11.10

CLKC1

CLKC0 Playing Speed

Playing speed

0

1

0

1

0

1

Normal

8 times

16 times

32 times

Note Playing speeds are changed the moment these registers are

operated. Take caution when operating these registers in the

middle of a melody playing.

– MAD0–MAD6: Address Registers

(F0H D0–D3 and F1H D0–D2)

Th ese registers are u sed to set th e m elody playin g start.

By operatin g th e "MELC" register, wh en playin g of a n ew

m elody starts, th e addresses set in th ese registers are

read by th e m elody ROM address cou n ter an d becom e th e

m elody start addresses.

Wh en 1 is written :

Wh en 0 is written :

Readin g:

1

0

Valid

Note When these registers are written with "50H" –"7FH", since these

addresses do not exist in the melody ROM, the hardware will

cause silent notes equivalent to 32 notes to be played and so,

caution must be observed.

– EIMEL: Melody Interrupt Mask Register (E7H D0)

By operatin g th is register, m elody in terru pt can be

m asked.

Wh en 1 is written :

Wh en 0 is written :

Readin g:

In terru pt is valid

In terru pt is in valid

Valid

I-98

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)

Note Be sure to operate this register in the "DI (interrupt not allowed)"

state. Otherwise, it may result in misoperation.

– IMEL: Melody Interrupt Factor Flag (ECH D0)

Th e m om en t th e m elody playin g (i.e., playin g of th e

address th e en d-of-m elody data in th e m elody ROM of

wh ich is "1") en ds, a flag is set on th is register. Du e to

th is, th e en d of a m elody playin g can be kn own by read-

in g ou t th is register. Th is register is also reset by th e

h ardware after th e readou t.

Wh en 1 is read: In terru pt gen eration ; 0 after readou t

Wh en 0 is read: In terru pt is n ot gen erated

Writin g:

In valid

S1C62N81 TECHNICAL HARDWARE

EPSON

I-99

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

4.12 Inte rrup t a nd HALT

Th e S1C62N81 Series provide th e followin g in terru pt set-

tin gs, each of wh ich is m askable.

Extern al in terru pt:

In tern al in terru pt:

In pu t in terru pt (two)

Tim er in terru pt (on e)

Stopwatch in terru pt (on e)

Melody in terru pt (on e)

To en able in terru pts, th e in terru pt flag m u st be set to 1 (EI)

an d th e n ecessary related in terru pt m ask registers m u st be

set to 1 (en able). Wh en an in terru pt occu rs, th e in terru pt

flag is au tom atically reset to 0 (DI) an d in terru pts after th at

are in h ibited.

Wh en a HALT in stru ction is in pu t, th e CPU operatin g clock

stops an d th e CPU en ters th e h alt state. Th e CPU is reacti-

vated from th e h alt state wh en an in terru pt requ est occu rs.

Figu re 4.12.1 sh ows th e con figu ration of th e in terru pt

circu it.

I-100

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

IMEL

Interrupt vector

EIMEL

Address

Priority

10A

Highest

K10

KCP10

EIK10

108

106

104

102

:

IK1

Program counter of CPU

(four low-order bits)

:

K00

KCP00

EIK00

K01

Lowest

KCP01

EIK01

K02

INT

(Interrupt request)

IK0

KCP02

EIK02

K03

KCP03

EIK03

ISW0

EISW0

Interrupt factor flag

ISW1

Interrupt mask register

Input comparison register

EISW1

IT2

EIT2

IT8

EIT8

IT32

EIT32

Fig. 4.12.1 Configuration of interrupt circuit

S1C62N81 TECHNICAL HARDWARE

EPSON

I-101

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Table 4.12.1 sh ows th e factors th at gen erate in terru pt

Inte rrup t fa c tors

requ ests.

Th e in terru pt factor flags are set to 1 depen din g on th e

correspon din g in terru pt factors.

Th e CPU is in terru pted wh en th e followin g two con dition s

occu r an d an in terru pt factor flag is set to 1.

• Th e correspon din g m ask register is 1 (en abled)

• Th e in terru pt flag is 1 (EI)

Th e in terru pt factor flag is a read-on ly register, bu t can be

reset to 0 wh en th e register data is read.

After an in itial reset, th e in terru pt factor flags are reset to 0.

Note Read the interrupt factor flags only in the DI status (interrupt flag =

0). A malfunction could result from a read during the EI status

(interrupt flag = 1).

Table 4.12.1

Interrupt factors

Interrupt Factor

Clock timer 2 Hz falling edge

Clock timer 8 Hz falling edge

Clock timer 32 Hz falling edge

Stopwatch timer

Interrupt Factor Flag

(0EFH D2)

IT2

IT8

(0EFH D1)

IT32

(0EFH D0)

ISW1

(0EEH D1)

1 Hz falling edge

Stopwatch timer

ISW0

IK0

(0EEH D0)

(0EDH D0)

(0EDH D1)

(0ECH D0)

10 Hz falling edge

Input data (K00–K03)

Rising or falling edge

Input data (K10)

IK1

Rising or falling edge

Melody generator

IMEL

End of melody

I-102

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Th e in terru pt factor flags can be m asked by th e correspon d-

in g in terru pt m ask registers. Th e in terru pt m ask registers

are read/ write registers. Th ey are en abled (in terru pt en -

abled) wh en 1 is written to th em , an d m asked (in terru pt

disabled) wh en 0 is written to th em . After an in itial reset,

th e in terru pt m ask register is set to 0.

Sp e c ific m a sks a nd

fa c tor fla g s for inte r-

rup t

Table 4.12.2 sh ows th e correspon den ce between in terru pt

m ask registers an d in terru pt factor flags.

Table 4.12.2

Interrupt mask registers and

interrupt factor flags

Interrupt Mask Register

Interrupt Factor Flag

EIT2

(0EBH D2)

(0EBH D1)

(0EBH D0)

(0EAH D1)

(0EAH D0)

IT2

IT8

(0EFH D2)

(0EFH D1)

EIT8

EIT32

EISW1

EISW0

IT32 (0EFH D0)

ISW1 (0EEH D1)

ISW0 (0EEH D0)

EIK03 * (0E8H D3)

EIK02 * (0E8H D2)

EIK01 * (0E8H D1)

EIK00 * (0E8H D0)

EIK10 * (0E9H D0)

IK0

IK1

(0EDH D0)

(0EDH D1)

EIMEL

(0E7H D0)

IMEL (0ECH D0)

* Th ere is an in terru pt m ask register for each in pu t port pin .

Note

Writing to the interrupt mask registers should be done only in the

DI status (interrupt flag = 0). Otherwise it causes malfunction.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-103

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Wh en an in terru pt requ est is in pu t to th e CPU, th e CPU

Inte rrup t ve c tors a nd

p rioritie s

begin s in terru pt processin g. After th e program bein g exe-

cu ted is su spen ded, in terru pt processin g is execu ted in th e

followin g order:

➀ Th e address data (valu e of th e program cou n ter) of th e

program step to be execu ted n ext is saved on th e stack

(RAM).

➀ Th e in terru pt requ est cau ses th e valu e of th e in terru pt

vector (page 1, 02H–0BH) to be loaded in to th e program

cou n ter.

➀ Th e program at th e specified address is execu ted (execu -

tion of in terru pt processin g rou tin e).

Table 4.12.3 sh ows th e correspon den ce of in terru pt vectors

an d priorities.

Note

The processing in steps 1 and 2, above, takes 12 cycles of the

CPU system clock.

Table 4.12.3

Interrupt vectors

and priorities

Vector

10AH

108H

106H

104H

102H

Priority

Interrupt Request

1

2

3

4

5

Melody interrupt

Input (K10) interrupt

Input (K00–K03) interrupt

Stopwatch timer interrupt

Clock timer interrupt

Note

When multiple interrupts occur simultaneously, the interrupt vec-

tors with higher priority will be executed.

I-104

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Tables 4.12.4 (a)–(c) sh ows th e in terru pt con trol bits an d

th eir addresses.

Control of inte rrup t

Table 4.12.4 (a) Interrupt control bits (1)

Register

Address

0E5H

Comment

D3

D2

D1

D0

Name

KCP03

SR

0

1

0

KCP03

KCP02

KCP01

KCP00

Falling

Rising

Input comparison register (K03)

Input comparison register (K02)

Input comparison register (K01)

Input comparison register (K00)

KCP02

KCP01

KCP00

0

Falling

Rising

R/W

0

KCP10

R/W

0

R

0E6H

0E7H

0E8H

0

KCP10

0

Falling

Rising

Input comparison register (K10)

0

EIMEL

R/W

R

0

EIMEL

EIK03

EIK02

EIK01

EIK00

0

Enable

Mask

Interrupt mask register (melody)

Interrupt mask register (K03)

Interrupt mask register (K02)

Interrupt mask register (K01)

Interrupt mask register (K00)

EIK03

EIK02

EIK01

EIK00

R/W

S1C62N81 TECHNICAL HARDWARE

EPSON

I-105

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Table 4.12.4 (b) Interrupt control bits (2)

Register

Address

Comment

D3

0

D2

0

D1

0

D0

Name

0

SR

1

0

EIK10

0

R

R/W

0E9H

0EAH

0EBH

0ECH

EIK10

0

Enable

Mask

Interrupt mask register (K10)

0

EISW1

EISW0

0

R

R/W

EISW1

EISW0

0

Enable

Mask

Interrupt mask register (stopwatch 1 Hz)

Interrupt mask register (stopwatch 10 Hz)

0

EIT2

EIT8

R/W

EIT32

R

EIT2

EIT8

EIT32

0

Enable

Mask

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

0

IMEL

R

0

Yes

No

IMEL

0

Interrupt factor flag (melody)

I-106

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Table 4.12.4 (c) Interrupt control bits (3)

Register

Address

Comment

D3

0

D2

D1

D0

IK0

Name

0

SR

1

0

IK1

0

IK1

IK0

0

R

0EDH

Yes

No

0

Interrupt factor flag (K10)

Interrupt factor flag (K00–K03)

0

ISW1

ISW0

0

0EEH

ISW1

ISW0

0

Yes

No

Interrupt factor flag (stopwatch 1 Hz)

Interrupt factor flag (stopwatch 10 Hz)

0

IT2

IT8

IT32

IT2

IT8

IT32

0

Yes

No

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

0EFH

S1C62N81 TECHNICAL HARDWARE

EPSON

I-107

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

EIT32, EIT8, EIT2 Interrupt mask registers (0EBH D0–D2)

IT32, IT8, IT2 Interrupt factor flags (0EFH D0–D2)

See 4.7, "Clock Tim er".

EISW0, EISW1 Interrupt mask registers (0EAH D0–D1)

ISW0, ISW1 Interrupt factor flags (0EEH D0–D1)

See 4.8, "Stopwatch Tim er".

KCP00–KCP03 Input comparison registers (0E5H)

EIK00–EIK03 Interrupt mask registers (0E8H)

IK0 Interrupt factor flag (0EDH D0)

See 4.3, "In pu t Ports".

KCP10 Input comparison register (0E6H D0)

EIK10 Interrupt mask register (0E9H D0)

IK1 Interrupt factor flag (0EDH D1)

See 4.3, "In pu t Ports".

EIMEL Interrupt mask register (0E7H D0)

IMEL Interrupt factor flag (0ECH D0)

See 4.11, "Melody Gen erator".

I-108

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM

CHAPTER 5

BASIC EXTERNAL WIRING DIA-

GRAM

(1) Pie zo Buzze r Sing le Te rm ina l Driving

LCD

PANEL

K00

CA

CB

CC

C1

C2

C3

C4

C5

I

K03

K10

P00

V

L1

L2

L3

DD

V

I/O

P03

C

G

OSC1

X'tal

CMPP

CMPM

S1C62N81/62L81

OSC2

C6

1.5V

or

3.0V

V

S1

R00

RESET

R03

R10

R11

TEST

MTEST

Vss

O

Cp

Piezo

O

Buzzer

Coil

X'tal

Crystal oscillator

Trimmer capacitor

Capacitor

32.768kHz CI(MAX)=35kΩ

C

G

5–25pF

0.1 µF

3.3 µF

C1–C6

Cp

Capacitor

S1C62N81 TECHNICAL HARDWARE

EPSON

I-109

CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM

(2) Pie zo Buzze r Dire c t Driving

LCD

PANEL

K00

CA

CB

C1

C2

C3

C4

C5

I

K03

K10

P00

CC

V^L1

V^L2

V^L3

I/O

P03

V^DD

OSC1

C

G

X'tal

CMPP

CMPM

S1C62N81/62L81

OSC2

V^S1

C6

1.5V

or

3.0V

R00

RESET

R03

R10

R11

TEST

MTEST

Vss

O

Cp

R1

R2

Piezo

Buzzer

X'tal

Crystal oscillator

32.768kHz CI(MAX)=35kΩ

C

G

Trimmer capacitor

Capacitor

5–25pF

0.1µF

3.3µF

100Ω

C1–C6

Cp

Capacitor

R1, R2

Protection resistance

I-110

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM

(3) Enve lop e Driving

LCD

PANEL

K00

CA

CB

CC

C1

C2

C3

C4

C5

I

K03

K10

P00

V

L1

L2

L3

DD

V

I/O

P03

C

G

OSC1

X'tal

CMPP

CMPM

S1C62N81/62L81

OSC2

C6

1.5V

or

3.0V

V

S1

R00

RESET

R03

R10

R11

TEST

MTEST

Vss

O

Cp

C7

R3

Piezo

Buzzer

Coil

X'tal

Crystal oscillator

Trimmer capacitor

Capacitor

32.768kHz CI(MAX)=35kΩ

5–25pF

CG

C1–C6

C7

0.1 µF

Capacitor

1µF–10 µF

3.3 µF

Cp

Capacitor

R3

Resistor

1kΩ or more

S1C62N81 TECHNICAL HARDWARE

EPSON

I-111

CHAPTER 6: ELECTRICAL CHARACTERISTICS

CHAPTER 6

ELECTRICAL CHARACTERISTICS

6.1 Ab solute Ma xim um Ra ting

S1 C6 2 N8 1 / 6 2 A8 1

(VDD =0V)

Item

Symbol

Rated Value

-5.0 to 0.5

Unit

V

Power voltage

Vss

Input voltage (1)

V

I

Vss-0.3 to 0.5

10

V

Input voltage (2)

IOSC

V

Permissible total output current *1

Operating temperature

Storage temperature

ΣIvss

Topr

Tstg

mA

°C

–

-20 to 70

-65 to 150

Soldering temperature / Time

Allowable dissipation *2

Tsol

260°C, 10sec (lead section)

250

P

D

mW

*1 Th e perm issible total ou tpu t cu rren t is th e su m total of

th e cu rren t (average cu rren t) th at sim u ltan eou sly flows

from th e ou tpu t pin s (or is drawn in ).

*2 In case of 64-pin plastic package.

S1 C6 2 L8 1 / 6 2 B8 1

(VDD =0V)

Item

Symbol

Rated Value

-5.0 to 0.5

Unit

V

Power voltage

Vss

Input voltage (1)

V

I

Vss-0.3 to 0.5

10

V

Input voltage (2)

IOSC

V

Permissible total output current *1

Operating temperature

Storage temperature

ΣIvss

Topr

Tstg

mA

°C

–

-20 to 70

-65 to 150

Soldering temperature / Time

Allowable dissipation *2

Tsol

260°C, 10sec (lead section)

250

P

D

mW

*1 Th e perm issible total ou tpu t cu rren t is th e su m total of

th e cu rren t (average cu rren t) th at sim u ltan eou sly flows

from th e ou tpu t pin s (or is drawn in ).

*2 In case of 64-pin plastic package.

I-112

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 6: ELECTRICAL CHARACTERISTICS

6.2 Re c om m e nd e d Op e ra ting Cond itions

S1 C6 2 N8 1 / 6 2 A8 1

(Ta=-20 to 70°C)

Item

Power voltage

Symbol

Vss

Condition

Min

-3.5

Typ

-3.0

Max Unit

V^DD=0V

-1.8

V

Oscillation frequency

fosc

32.768

kHz

S1 C6 2 L8 1 / 6 2 B8 1

(Ta=-20 to 70°C)

Item

Symbol

Condition

Min

Typ

Max Unit

Power voltage

Vss

V

DD=0V

-3.5

-1.5

-1.1

-0.9

-1.3

V

^DD=0V,

With software correspondence ^*1-3.5

^DD=0V, When analog

comparator is used

*2

-1.5

V

-3.5

-1.5

V

Oscillation frequency

fosc

32.768

kHz

*1 Wh en switch in g to th e h eavy load protection m ode.

Th e BLD circu it an d an alog voltage com parator are

tu rn ed OFF.

(For details, refer to Section 4.9).

*2 Th e voltage wh ich can be displayed on th e LCD pan el will

differ accordin g to th e ch aracteristics of th e LCD pan el.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-113

CHAPTER 6: ELECTRICAL CHARACTERISTICS

6.3 DC Cha ra c te ristic s

S1 C6 2 N8 1 / 6 2 A8 1

Un less oth erwise specified

VDD=0 V, VSS=-3.0 V, fosc=32.768 kHz, Ta=25°C, VS1,

VL1, VL2 an d VL3 are in tern al voltages, an d

C1=C2=C3=C4=C5=C6=0.1 µF

Item

Symbol

IH1

IH2

IL1

IL2

Condition

Min

Typ

Max

0

Unit

V

High level input voltage (1)

High level input voltage (2)

Low level input voltage (1)

Low level input voltage (2)

High level input current (1)

V

K00–K03, K10, P00–P03, MTEST 0.2•Vss

V

RESET, TEST

0.10•Vss

Vss

0

V

K00–K03, K10, P00–P03, MTEST

RESET, TEST

0.8•Vss

0.90•Vss

0.5

V

Vss

V

I

IH1

IH2

IH3

IL

V

IH =0V

K00–K03, K10, P00–P03

0

µA

Without pull down resistor CMPP, CMPM

High level input current (2)

High level input current (3)

Low level input current

V

IH =0V

With pull down resistor

IH =0V

With pull down resistor

IL =Vss

K00–K03, K10

5

16

100

0

µA

V

P00–P03

30

RESET, TEST, MTEST

K00–K03, K10

P00–P03

V

-0.5

CMPP, CMPM

RESET, TEST, MTEST

R11

High level output current (1)

High level output current (2)

I

OH1

OH2

V

OH1=0.1•Vss

-1.0

mA

VOH2=0.1•Vss

R00–R03, R10

P00–P03

High level output current (3)

Low level output current (1)

Low level output current (2)

I

OH3

OL1

OL2

V

OH3=0.1•Vss

OL1 =0.9•Vss

OL2 =0.9•Vss

MO, R12

-2.0

mA

V

R11

3.0

V

R00–R03, R10

P00–P03

Low level output current (3)

Common output current

I

OL3

OH4

OL4

OH5

OL5

OH6

OL6

V

OL3 =0.9•Vss

OH4=-0.05V

OL4 =V^L3+0.05V

OH5=-0.05V

OL5 =V^L3+0.05V

OH6=0.1•Vss

OL6 =0.9•Vss

MO, R12

4.5

3

mA

µA

V

-3

COM0–COM3

SEG0–SEG25

V

Segment output current

(during LCD output)

Segment output current

(during DC output)

V

3

V

-300

V

300

I-114

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1 C6 2 L8 1 / 6 2 B8 1

Un less oth erwise specified

VDD=0 V, VSS=-1.5 V, fosc=32.768 kHz, Ta=25°C, VS1,

VL1, VL2 an d VL3 are in tern al voltages, an d

C1=C2=C3=C4=C5=C6=0.1 µF

Item

Symbol

IH1

IH2

IL1

IL2

Condition

Min

Typ

Max

0

Unit

V

High level input voltage (1)

High level input voltage (2)

Low level input voltage (1)

Low level input voltage (2)

High level input current (1)

V

K00–K03, K10, P00–P03, MTEST 0.2•Vss

V

RESET, TEST

0.10•Vss

Vss

0

V

K00–K03, K10, P00–P03, MTEST

RESET, TEST

0.8•Vss

0.90•Vss

0.5

V

Vss

V

I

IH1

IH2

IH3

IL

V

IH =0V

K00–K03, K10, P00–P03

0

µA

Without pull down resistor CMPP, CMPM

High level input current (2)

High level input current (3)

Low level input current

V

IH =0V

With pull down resistor

IH =0V

With pull down resistor

IL =Vss

K00–K03, K10

2.0

9.0

10

60

0

µA

V

P00–P03

RESET, TEST, MTEST

K00–K03, K10

P00–P03

V

-0.5

CMPP, CMPM

RESET, TEST, MTEST

R11

High level output current (1)

High level output current (2)

I

OH1

OH2

V

OH1=0.1•Vss

-450

-200

µA

VOH2=0.1•Vss

R00–R03, R10

P00–P03

High level output current (3)

High level output current (4)

I

OH3

OH4

V

OH3=0.1•Vss

OH4=0.1•Vss

When envelope is used

OL1 =0.9•Vss

OL2 =0.9•Vss

MO, R12

-0.8

-0.4

mA

V

MO

Low level output current (1)

Low level output current (2)

I

OL1

OL2

V

R11

1300

700

µA

V

R00–R03, R10

P00–P03

MO, R12

Low level output current (3)

Common output current

I

OL3

OH5

OL5

OH6

OL6

OH7

OL7

V

OL3 =0.9•Vss

OH5=-0.05V

OL5 =V^L3+0.05V

OH6=-0.05V

OL6 =V^L3+0.05V

OH7=0.1•Vss

OL7 =0.9•Vss

1.5

3

mA

µA

V

-3

COM0–COM3

SEG0–SEG25

V

Segment output current

(during LCD output)

Segment output current

(during DC output)

V

3

V

-100

V

130

S1C62N81 TECHNICAL HARDWARE

EPSON

I-115

CHAPTER 6: ELECTRICAL CHARACTERISTICS

6.4 Ana log Circ uit Cha ra c te ristic s a nd Powe r

Curre nt Consum p tion

S1 C6 2 N8 1 (Norm al Operat in g Mode)

Un less oth erwise specified

VDD=0 V, VSS=-3.0 V, fosc=32.768 kHz, Ta=25°C,

CG=25 pF, VS1, VL1, VL2 an d VL3 are in tern al voltages,

an d C1=C2=C3=C4=C5=C6=0.1 µF

Item

Symbol

Condition

Min

Typ

Max

Unit

Internal voltage

VL1

Connect 1MΩ load resistor between V^DDand V^L1

(without panel load)

-1.15

-1.05

-0.95

V

L2

Connect 1MΩ load resistor between V^DDand V^L2

(without panel load)

2•V^L1

-0.1

2•V^L1

× 0.9

3•V^L1

× 0.9

-2.25

100

V

VL3

Connect 1MΩ load resistor between V^DDand V^L3

(without panel load)

3•V^L1

-0.1

BLD voltage

V

t

V

BLD

IP

IM

OF

-2.55

-2.40

V

µs

V

BLD circuit response time

Analog comparator

input voltage

Non-inverted input (CMPP)

Inverted input (CMPM)

Vss+0.3

V^DD-0.9

V

Analog comparator

offset voltage

V

10

3

mV

ms

Analog comparator

response time

t

CMP

OP

V

^IP=-1.5V

V

^IM=V^IP±15mV

Power current

I

During HALT

During execution

1.0

2.5

5.0

µA

Without panel load

*1

consumption

*1 Th e BLD circu it an d an alog voltage com parator are

tu rn ed OFF.

I-116

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1 C6 2 N8 1 (Heavy Load Prot ect ion Mode)

Un less oth erwise specified

VDD=0 V, VSS=-3.0 V, fosc=32.768 kHz, Ta=25°C,

CG=25 pF VS1, VL1, VL2 an d VL3 are in tern al voltages, an d

C1=C2=C3=C4=C5=C6=0.1 µF

Item

Internal voltage

Symbol

Condition

Connect 1MΩ load resistor between V^DDand V^L1

(without panel load)

Min

-1.15

Typ

-1.05

Max

-0.95

Unit

V

VL1

V

L2

Connect 1MΩ load resistor between V^DDand V^L2

(without panel load)

2•V^L1

-0.1

2•V^L1

×0.85

3•V^L1

×0.85

-2.25

100

V

VL3

Connect 1MΩ load resistor between V^DDand V^L3

(without panel load)

3•V^L1

-0.1

BLD voltage

V

t

V

BLD

IP

IM

OF

-2.55

-2.40

V

µs

V

BLD circuit response time

Analog comparator

input voltage

Non-inverted input (CMPP)

Inverted input (CMPM)

Vss+0.3

V^DD-0.9

V

Analog comparator

offset voltage

V

10

3

mV

ms

Analog comparator

response time

t

CMP

OP

V

^IP=-1.5V

^IM=V^IP±15mV

During HALT

During execution

V

Power current

I

2.0

5.5

µA

Without panel load

*1

consumption

10.0

*1 Th e BLD circu it an d an alog voltage com parator are

tu rn ed OFF.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-117

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1 C6 2 L8 1 (Norm al Operat in g Mode)

Un less oth erwise specified

VDD=0 V, VSS=-1.5 V, fosc=32.768 kHz, Ta=25°C, CG=25

pF VS1, VL1, VL2 an d VL3 are in tern al voltages, an d

C1=C2=C3=C4=C5=C6=0.1 µF

Item

Symbol

Condition

Min

Typ

Max

Unit

Internal voltage

VL1

Connect 1MΩ load resistor between V^DDand VL1

(without panel load)

-1.15

-1.05

-0.95

V

L2

Connect 1MΩ load resistor between V^DDand V^L2

(without panel load)

2•V^L1

-0.1

2•V^L1

× 0.9

3•V^L1

× 0.9

-1.10

100

V

VL3

Connect 1MΩ load resistor between V^DDand V^L3

(without panel load)

3•V^L1

-0.1

BLD voltage

V

t

V

BLD

IP

IM

OF

-1.30

-1.20

V

µs

V

BLD circuit response time

Analog comparator

input voltage

Non-inverted input (CMPP)

Inverted input (CMPM)

Vss+0.3

V^DD-0.9

V

Analog comparator

offset voltage

V

20

3

mV

ms

Analog comparator

response time

t

CMP

OP

V

^IP=-1.1V

^IM=V^IP±30mV

Power current

I

During HALT

During execution ^*1

1.0

2.5

5.0

µA

Without panel load

consumption

*1 Th e BLD circu it an d an alog voltage com parator are

tu rn ed OFF.

I-118

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1 C6 2 L8 1 (Heavy Load Prot ect ion Mode)

Un less oth erwise specified

VDD=0 V, VSS=-1.5 V, fosc=32.768 kHz, Ta=25°C, CG=25

pF VS1, VL1, VL2 an d VL3 are in tern al voltages, an d

C1=C2=C3=C4=C5=C6=0.1 µF

Item

Internal voltage

Symbol

Condition

Connect 1MΩ load resistor between V^DDand VL1

(without panel load)

Min

-1.15

Typ

-1.05

Max

-0.95

Unit

V

L1

L2

L3

Connect 1MΩ load resistor between V^DDand V^L2

(without panel load)

2•V^L1

-0.1

2•V^L1

× 0.85

3•V^L1

× 0.85

-1.10

100

V

Connect 1MΩ load resistor between V^DDand V^L3

(without panel load)

3•V^L1

-0.1

BLD voltage

V

t

V

BLD

IP

-1.30

-1.20

V

µs

V

BLD circuit response time

Analog comparator

input voltage

Non-inverted input (CMPP)

Inverted input (CMPM)

Vss+0.3

V^DD-0.9

IM

Analog comparator

offset voltage

OF

20

3

mV

ms

Analog comparator

response time

t

CMP

OP

V

^IP=-1.1V

^IM=V^IP±30mV

Power current

I

During HALT

During execution

2.0

5.5

µA

Without panel load

*1

consumption

10.0

*1 Th e BLD circu it an d an alog voltage com parator are

tu rn ed OFF.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-119

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1 C6 2 A8 1 (Norm al Operat in g Mode)

Un less oth erwise specified

VDD=0 V, VSS=-3.0 V, fosc=32.768 kHz, Ta=25°C,

CG=25pF VS1, VL1, VL2 an d VL3 are in tern al voltages, an d

C1=C2=C3=C4=C5=C6=0.1 µF

Item

Symbol

Condition

Min

Typ

Max

Unit

Internal voltage

VL1

Connect 1MΩ load resistor between V^DDand V^L1

(without panel load)

-1.15

-1.05

-0.95

V

L2

Connect 1MΩ load resistor between V^DDand V^L2

(without panel load)

2•V^L1

-0.1

2•V^L1

× 0.9

3•V^L1

× 0.9

-2.25

100

V

VL3

Connect 1MΩ load resistor between V^DDand V^L3

(without panel load)

3•V^L1

-0.1

BLD voltage

V

t

V

BLD

IP

IM

OF

-2.55

-2.40

V

µs

V

BLD circuit response time

Analog comparator

input voltage

Non-inverted input (CMPP)

Inverted input (CMPM)

Vss+0.3

V^DD-0.9

V

Analog comparator

offset voltage

V

10

3

mV

ms

Analog comparator

response time

t

CMP

OP

V

^IP=-1.5V

^IM=V^IP±15mV

During HALT

During execution ^*1

V

Power current

I

5.5

7.2

10.0

12.0

µA

Without panel load

consumption

*1 Th e BLD circu it an d an alog voltage com parator are

tu rn ed OFF.

I-120

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1 C6 2 A8 1 (Heavy Load Prot ect ion Mode)

Un less oth erwise specified

VDD=0 V, VSS=-3.0 V, fosc=32.768 kHz, Ta=25°C,

CG=25pF VS1, VL1, VL2 an d VL3 are in tern al voltages, an d

C1=C2=C3=C4=C5=C6=0.1 µF

Item

Internal voltage

Symbol

Condition

Connect 1MΩ load resistor between V^DDand V^L1

(without panel load)

Min

-1.15

Typ

-1.05

Max

-0.95

Unit

V

VL1

V

L2

Connect 1MΩ load resistor between V^DDand V^L2

(without panel load)

2•VL1

-0.1

2•VL1

× 0.85

3•V^L1

× 0.85

-2.25

100

V

VL3

Connect 1MΩ load resistor between V^DDand V^L3

(without panel load)

3•V^L1

-0.1

BLD voltage

V

t

V

BLD

IP

IM

OF

-2.55

-2.40

V

µs

V

BLD circuit response time

Analog comparator

input voltage

Non-inverted input (CMPP)

Inverted input (CMPM)

Vss+0.3

V^DD-0.9

V

Analog comparator

offset voltage

V

10

3

mV

ms

Analog comparator

response time

t

CMP

OP

V

IP =-1.5V

^IM=V^IP±15mV

During HALT

Power current

I

11.0

15.0

20.0

25.0

µA

Without panel load

consumption

During execution ^*1

*1 Th e BLD circu it an d an alog voltage com parator are

tu rn ed OFF.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-121

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1 C6 2 B8 1 (Norm al Operat in g Mode)

Un less oth erwise specified

VDD=0 V, VSS=-1.5 V, fosc=32.768 kHz, Ta=25°C,

CG=25pF VS1, VL1, VL2 an d VL3 are in tern al voltages, an d

C1=C2=C3=C4=C5=C6=0.1 µF

Item

Internal voltage

Symbol

Condition

Connect 1MΩ load resistor between V^DDand V^L1

(without panel load)

Min

-1.15

Typ

-1.05

Max

-0.95

Unit

V

L1

L2

L3

Connect 1MΩ load resistor between V^DDand V^L2

(without panel load)

2•V^L1

-0.1

2•V^L1

× 0.9

3•V^L1

× 0.9

-1.10

100

V

Connect 1MΩ load resistor between V^DDand V^L3

(without panel load)

3•V^L1

-0.1

BLD voltage

V

t

V

BLD

IP

-1.30

-1.20

V

µs

V

BLD circuit response time

Analog comparator

input voltage

Non-inverted input (CMPP)

Inverted input (CMPM)

Vss+0.3

V^DD-0.9

IM

Analog comparator

offset voltage

OF

20

3

mV

ms

Analog comparator

response time

t

CMP

OP

V

^IP=-1.1V

^IM=V^IP±30mV

Power current

I

During HALT

During execution^*1

5.5

7.2

10.0

12.0

µA

Without panel load

consumption

*1 Th e BLD circu it an d an alog voltage com parator are

tu rn ed OFF.

I-122

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1 C6 2 B8 1 (Heavy Load Prot ect ion Mode)

Un less oth erwise specified

VDD=0 V, VSS=-1.5 V, fosc=32.768 kHz, Ta=25°C, VS1,

VL1, VL2 an d VL3 are in tern al voltages, an d

C1=C2=C3=C4=C5=C6=0.1 µF

Item

Symbol

Condition

Min

Typ

Max

Unit

Internal voltage

V

L1

L2

L3

Connect 1MΩ load resistor between V^DDand V^L1

(without panel load)

-1.15

-1.05

-0.95

V

Connect 1MΩ load resistor between V^DDand V^L2

(without panel load)

2•V^L1

-0.1

2•V^L1

× 0.85

3•V^L1

× 0.85

-1.10

100

V

Connect 1MΩ load resistor between V^DDand V^L3

(without panel load)

3•V^L1

-0.1

BLD voltage

V

t

V

BLD

IP

-1.30

-1.20

V

µs

V

BLD circuit response time

Analog comparator

input voltage

Non-inverted input (CMPP)

Inverted input (CMPM)

Vss+0.3

V^DD-0.9

IM

Analog comparator

offset voltage

OF

20

3

mV

ms

Analog comparator

response time

t

CMP

OP

V

^IP=-1.1V

^IM=V^IP±30mV

Power current

I

During HALT

During execution

11.0

15.0

20.0

25.0

µA

Without panel load

*1

consumption

*1 Th e BLD circu it an d an alog voltage com parator are

tu rn ed OFF.

S1C62N81 TECHNICAL HARDWARE

EPSON

I-123

CHAPTER 6: ELECTRICAL CHARACTERISTICS

6.5 Osc illa tion Cha ra c te ristic s

Oscillation ch aracteristics will vary accordin g to differen t

con dition s. Use th e followin g ch aracteristics are as refer-

en ce valu es.

S1 C6 2 N8 1

Un less oth erwise specified,

VDD=0 V, VSS=-3.0 V, Crystal: Q13MC146, CG=25 pF,

C^D=bu ilt-in , Ta=25°C

Item

Oscillation start

voltage

Oscillation stop

voltage

Symbol

Vsta

(Vss)

Vstp

Condition

Min

-1.8

Typ

Max Unit

t

sta

stp

≤

3 sec

V

10 sec

-1.8

V

(Vss)

Built-in capacity (drain)

Frequency voltage deviation

Frequency IC deviation

Frequency adjustment range

Higher harmonic oscillation

start voltage

C

D

Including the parasitic capacity inside the IC

f/V Vss=-1.8 to -3.5 V

f/I

f/C

20

pF

5

10

ppm

V

C

-10

40

G

CG =5–25pF

Vhho

-3.5

(Vss)

Allowable leak resistor

R

leak Between OSC1 and V^DDand Vss

200

MΩ

S1 C6 2 L8 1

Un less oth erwise specified,

VDD=0 V, VSS=-1.5 V, Crystal: Q13MC146, CG=25 pF,

CD=bu ilt-in , Ta=25°C

Item

Oscillation start

Symbol

Vsta

(Vss)

Vstp

Condition

Min

-1.1

Typ

Max Unit

t

sta

stp

≤

3 sec

V

voltage

Oscillation stop

10 sec

-1.1

(-0.9) ^*1

V

voltage

(Vss)

Built-in capacity (drain)

Frequency voltage deviation

Frequency IC deviation

Frequency adjustment range

Higher harmonic oscillation

start voltage

C

D

Including the parasitic capacity inside the IC

f/V Vss=-1.1 to -3.5 V (-0.9) ^*1

f/I

f/C

20

pF

5

10

ppm

V

C

-10

40

G

CG =5–25pF

Vhho

-3.5

(Vss)

leak Between OSC1 and V^DDand Vss

Allowable leak resistor

R

200

MΩ

*1 Item s en closed in paren th eses ( ) are th ose u sed wh en

operatin g at h eavy load protection m ode.

I-124

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1 C6 2 A8 1

Un less oth erwise specified,

VDD=0 V, VSS=-3.0 V, RCR=850 kΩ, Ta=25°C

Item

Symbol

Condition

Min

Typ

Max

20

Unit

%

Oscillation frequency dispersion fosc

-20 32.768 kHz

Oscillation start voltage

Oscillation start time

Oscillation stop voltage

Vsta

sta Vss=-1.8 to -3.5V

Vstp

-1.8

V

ms

V

t

3

-1.8

S1 C6 2 B8 1

Un less oth erwise specified,

VDD=0 V, VSS=-1.5 V, RCR=850 kΩ, Ta=25°C

Symbol Condition Min Typ

Oscillation frequency dispersion fosc

Item

Max

20

Unit

%

-20 32.768 kHz

Oscillation start voltage

Oscillation start time

Oscillation stop voltage

Vsta

sta Vss=-0.9 to -3.5V

Vstp

-0.9

V

ms

V

t

3

-0.9

S1C62N81 TECHNICAL HARDWARE

EPSON

I-125

CHAPTER 7: PACKAGE

CHAPTER 7

PACKAGE

7.1 Pla stic Pa c ka g e (1)

QFP6-64pin

±0.4

16.8

14.0

±0.2

48

33

49

32

Index

64

17

1

16

±0.15

0.8

0.35

0~12°

0.6 ^±0.3

1.4

I-126

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 7: PACKAGE

7.2 Pla stic Pa c ka g e (2)

QFP13-64pin

±0.4

12.0

±0.1

10.0

48

33

49

32

Index

64

17

1

16

±0.1

0.5

0.18

0~12°

0.5 ^±0.2

1.0

S1C62N81 TECHNICAL HARDWARE

EPSON

I-127

CHAPTER 7: PACKAGE

7.3

Ce ra m ic Pa c ka g e for Te st Sa m p le

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

TEST

SEG12 10

SEG13 11

SEG14 12

SEG15 13

SEG16 14

SEG17 15

SEG18 16

SEG19 17

SEG20 18

SEG21 19

SEG22 20

SEG23 21

SEG24 22

23

1

2

3

4

5

6

7

8

9

64 SEG3

63 SEG2

62 SEG1

61 SEG0

60 SEG25

59 COM3

58 COM2

57 COM1

56 COM0

55 CA

81.28

64 63

34 33

54 CB

53 CC

52 V^L1

51 VL2

50 VL3

49 OSC1

48 OSC2

47 V^SS

46 VDD

45 VS1

44 R03

43 R02

42 R01

41 R00

40 MO

39 R12

38 R11

37 R10

36 K10

35 K03

34 K02

33 K01

Pin No. 1 2

31 32

Index Mark

P00 24

P01 25

P02 26

P03 27

CMPM 28

CMPP 29

MTEST 30

RESET 31

K00 32

2.54

78.78

I-128

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 8: PAD LAYOUT

CHAPTER 8

PAD LAYOUT

8.1 Dia g ra m of Pa d La yout

17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

Die No.

18

19

20

21

22

23

24

25

26

27

28

29

30

31

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

32 33 34 35 36

37 38 39

40 41 42 43 44 45 46 47

48

Ch ip size:

Ch ip th ickn ess: 400 µm

Pad open in g: 95 µm

3.84 m m × 3.84 m m

S1C62N81 TECHNICAL HARDWARE

EPSON

I-129

CHAPTER 8: PAD LAYOUT

8.2 S1C62N81 List of Pa d Na m e s

No PAD Name No PAD Name No PAD Name

1

2

COM0

COM1

COM2

COM3

SEG25

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

TEST

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

P00

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

K03

K10

R10

R11

R12

MO

3

4

5

6

7

R00

R01

R02

R03

8

9

10

11

12

13

14

15

16

17

18

19

20

21

V

S1

DD

SS

P01

V

P02

V

P03

OSC2

OSC1

CMPM

CMPP

MTEST

RESET

K00

V

L3

L2

L1

V

SEG12

SEG13

SEG14

CC

CB

CA

K01

K02

I-130

EPSON

S1C62N81 TECHNICAL HARDWARE

CHAPTER 8: PAD LAYOUT

8.3 Pa d Coord ina te s

PAD No

X

Y

PAD No

22

X

Y

PAD No

43

X

Y

1

2

1722.0

1560.4

1400.4

1238.8

616.0

1753.2

1538.8

1317.2

1157.2

997.2

-1753.2

-1714.0

-1554.0

-1393.2

-1233.2

-1025.6

-685.2

-524.8

-349.6

92.4

837.2

571.6

-1752.4

-856.0

-696.0

-536.0

-376.0

-210.8

-50.8

23

677.2

44

732.4

3

24

517.2

45

914.0

4

25

357.2

46

1090.0

1249.6

1679.2

1753.2

5

26

197.2

47

6

456.0

27

37.2

48

7

296.0

28

-122.8

-282.8

-442.8

-602.8

-1752.4

49

8

136.0

29

50

9

-24.0

30

51

10

11

12

13

14

15

16

17

18

19

20

21

-184.0

-344.0

-504.0

-664.0

-824.0

-984.0

-1144.0

-1304.0

-1753.2

31

52

32

53

33

54

34

55

109.2

35

56

269.2

36

57

430.8

37

58

613.2

38

59

773.2

39

60

937.2

40

61

1097.2

1261.2

1421.2

41

251.6

62

42

412.4

63

S1C62N81 TECHNICAL HARDWARE

EPSON

I-131

S1C62N81

II. Technical Software

CONTENTS

CHAPTER 1

CONFIGURATION ........................................................... II-1

1.1 S1C62N81 Block Diagram ............................................. II-1

1.2 ROM Map ....................................................................... II-2

1.3 Interrupt Vectors ............................................................. II-3

1.4 Data Memory Map .......................................................... II-4

CHAPTER 2

CHAPTER 3

INITIAL RESET .................................................................. II-12

2.1 Internal Register Status on Initial Reset ........................ II-12

2.2 Initialize Program Example............................................ II-14

PERIPHERAL CIRCUITS .................................................... II-16

3.1 Input Ports ..................................................................... II-16

In pu t port m em ory m ap .......................................... II-16

Con trol of th e in pu t port ......................................... II-18

Exam ples of in pu t port con trol program .................. II-18

3.2 Output Ports .................................................................. II-20

Ou tpu t port m em ory m ap ........................................ II-20

Con trol of th e ou tpu t port ....................................... II-21

Exam ples of ou tpu t port con trol program ................ II-21

3.3 Special Use Output Ports .............................................. II-23

Special u se ou tpu t port m em ory m ap ...................... II-23

Con trol of th e special u se ou tpu t port ..................... II-24

Example of special u se ou tpu t port control program .. II-25

3.4 I/O Ports ........................................................................ II-26

I/ O port m em ory m ap ............................................. II-26

Con trol of th e I/ O port ............................................ II-27

Exam ples of I/ O port con trol program ..................... II-28

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-i

CONTENTS

3.5 LCD Driver..................................................................... II-31

LCD driver m em ory m ap ......................................... II-31

Con trol of th e LCD driver ........................................ II-32

Exam ples of LCD driver con trol program ................. II-34

3.6 Timer ............................................................................. II-36

Tim er m em ory m ap ................................................. II-36

Con trol of th e tim er ................................................. II-37

Exam ples of tim er con trol program .......................... II-38

3.7 Stopwatch Timer ........................................................... II-40

Stopwatch tim er m em ory m ap ................................. II-40

Con trol of th e stopwatch tim er ................................ II-41

Exam ples of stopwatch tim er con trol program ......... II-42

3.8 Battery Voltage Low Detection (BLD) Circuit

and Heavy Load Protection Function ............................ II-44

BLD circu it an d h eavy load protection

fu n ction m em ory m ap ............................................. II-44

Con trol of th e BLD circu it ....................................... II-45

Exam ple of BLD circu it con trol program .................. II-45

Heavy load protection fu n ction ................................ II-46

Exam ples of h eavy load protection

fu n ction con trol program ......................................... II-48

3.9 Analog Comparator ....................................................... II-51

An alog com parator m em ory m ap ............................. II-51

Exam ple of CMP con trol program ............................ II-52

3.10 Melody Generator.......................................................... II-53

Melody gen erator m em ory m ap ................................ II-53

Address settin g (Addresses 0F0H an d 0F1H) ........... II-54

Play m ode con trol.................................................... II-54

Melody in terru pt ..................................................... II-61

Melody ROM ........................................................... II-61

Scale ROM .............................................................. II-63

Exam ples of m elody con trol program ....................... II-64

II-ii

EPSON

S1C62N81 TECHNICAL SOFTWARE

CONTENTS

3.11 Interrupt and Halt........................................................... II-67

In terru pt m em ory m ap ............................................ II-67

Con trol of in terru pts an d h alt ................................. II-70

Exam ples of in terru pt an d h alt con trol program ...... II-81

CHAPTER 4

APPENDIX

SUMMARY OF PROGRAMMING POINTS....................... II-85

A

B

C

D

E

Table of Instructions ...................................................... II-89

The S1C62N81 I/O Memory Map .................................. II-94

Table of the ICE Commands ......................................... II-96

Cross-assembler Pseudo Instruction List ...................... II-98

The Format of Melody Source File ................................ II-99

Sou rce File Nam e .................................................... II-99

Statem en t (lin e) ....................................................... II-99

Attack field ........................................................ II-100

Note field ........................................................... II-100

Scale field .......................................................... II-100

En d bit field ....................................................... II-100

Com m en t field ................................................... II-100

F

Dividing Table............................................................... II-101

RAM Map ..................................................................... II-103

G

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-iii

CHAPTER 1: CONFIGURATION

CHAPTER 1

CONFIGURATION

1.1 S1C62N81 Bloc k Dia g ra m

System

Reset

Control

ROM

OSC

1,024x12

Core CPU S1C6200

RAM

96x4

Interrupt

Generator

COM0

|

COM3

SEG0

|

K00–K03

K10

LCD

Driver

I Port

Test Port

TEST

SEG25

MTEST

V

DD

L1

|

L3

P00–P03

I/O Port

O Port

V

CA

Power

Controller

|

CC

R00–R03

R10, R11

V

S1

SS

CMPP

CMPM

Comparator

& BLD

Timer

MO

Stop

Watch

Melody

R12

Fig. 1.1.1

S1C62N81 block diagram

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-1

CHAPTER 1: CONFIGURATION

1.2 ROM Ma p

Th e S1C62N81 h as a bu ilt-in m ask ROM with a capacity of

1,024 steps × 12 bits for program storage. Th e con figu ra-

tion of th e ROM is sh own in Figu re 1.2.1.

Bank 0

00H step

Program start address

Interrupt vector area

0 page

1 page

01H step

02H step

2 page

3 page

0BH step

0CH step

Program area

FFH step

12 bits

Fig. 1.2.1

Configuration of built-in ROM

II-2

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 1: CONFIGURATION

1.3 Inte rrup t Ve c tors

Wh en an in terru pt requ est is received by th e CPU, th e CPU

in itiates th e followin g in terru pt processin g after com pletin g

th e in stru ction bein g execu ted.

(1) Th e address of th e n ext in stru ction to be execu ted (th e

valu e of th e program cou n ter) is saved on th e stack

(RAM).

(2) Th e in terru pt vector address correspon din g to th e in ter-

ru pt requ est is loaded in to th e program cou n ter.

(3) Th e bran ch in stru ction written in th e vector is execu ted

to bran ch to th e software in terru pt processin g rou tin e.

Note Steps 1 and 2 require 12 cycles of the CPU system clock.

Th e correspon den ce between in terru pt requ ests an d vectors

are sh own in Table 1.3.1.

Table 1.3.1

Vector

10AH

108H

106H

104H

102H

Priority

Interrupt Request

Interrupt requests and vectors

1

2

3

4

5

Melody interrupt

Input (K10) interrupt

Input (K00–K03) interrupt

Stopwatch timer interrupt

Clock timer interrupt

Wh en m u ltiple in terru pts occu r sim u ltan eou sly, th ey are

execu ted in order of priority.

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-3

CHAPTER 1: CONFIGURATION

1.4 Da ta Me m ory Ma p

Th e S1C62N81 bu ilt-in RAM h as 96 words of data m em ory,

32 words of display m em ory for th e LCD, an d I/ O m em ory

for con trollin g th e periph eral circu it. Wh en writin g pro-

gram s, n ote th e followin g:

(1) Sin ce th e stack area is in th e data m em ory area, take

care n ot to overwrite th e stack with data. Su brou tin e

calls or in terru pts u se 3 words on th e stack.

(2) Data m em ory addresses 000H–00FH are m em ory register

areas th at are addressed with register poin ter RP.

Address

Page

Low

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

High

0

M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF

1

2

RAM (96 words x 4 bits)

R/W

3

4

5

6

Unused area

Display memory

Unused area

I/O memory

7

0

8

9

A

B

C

D

E

F

Fig. 1.4.1

Data memory map

Note Memory is not mounted in unused area within the memory map

and in memory area not indicated in this chapter. For this reason,

normal operation cannot be assured for programs that have been

prepared with access to these areas.

II-4

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 1: CONFIGURATION

Table 1.4.1 (a) I/O memory map (0E0H–0E3H)

Register

Address

Comment

*1

*2

D3

D2

D1

D0

Name

K03

SR

1

0

High

Low

K03

K02

K01

K00

–

*2

High

Low

R

K02

K01

K00

–

0E0H

0E1H

0E2H

0E3H

Input port (K00–K03)

*5

0

K10

0

*5

0

R

*5

0

*2

K10

–

0

High

Low

Input port (K10)

MSB

SWL3

SWL2

SWL1

SWL0

SWL3

SWL2

SWL1

SWL0

SWH3

SWH2

SWH1

SWH0

Stopwatch timer

1/100 sec (BCD)

LSB

SWH3

SWH2

SWH1

SWH0

MSB

Stopwatch timer

1/10 sec (BCD)

LSB

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-5

CHAPTER 1: CONFIGURATION

Table 1.4.1 (b) I/O memory map (0E4H–0E7H)

Register

Address

Comment

*1

D3

D2

D1

D0

Name

TM3

SR

1

0

High

Low

TM3

TM2

TM1

TM0

–

Timer data (clock timer 2 Hz)

Timer data (clock timer 4 Hz)

Timer data (clock timer 8 Hz)

Timer data (clock timer 16 Hz)

Input comparison register (K03)

Input comparison register (K02)

Input comparison register (K01)

Input comparison register (K00)

High

Low

R

TM2

TM1

–

0

0E4H

0E5H

0E6H

0E7H

High

Low

TM0

KCP03

KCP02

KCP01

KCP00

KCP03

KCP02

KCP01

KCP00

Falling

Rising

R/W

*5

0

KCP10

R/W

0

*5

0

R

*5

0

KCP10

0

Falling

Rising

Input comparison register (K10)

*5

0

EIMEL

R/W

0

*5

R

0

*5

0

EIMEL

0

Enable

Mask

Interrupt mask register (melody)

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

II-6

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 1: CONFIGURATION

Table 1.4.1 (c) I/O memory map (0E8H–0EBH)

Register

Address

Comment

*1

D3

D2

D1

D0

Name

EIK03

SR

0

1

0

Enable

Mask

EIK03

EIK02

EIK01

EIK00

Interrupt mask register (K03)

Enable

Mask

R/W

EIK02

EIK01

EIK00

0

Interrupt mask register (K02)

Interrupt mask register (K01)

Interrupt mask register (K00)

0E8H

0E9H

0EAH

0EBH

*5

0

EIK10

R/W

0

*5

0

R

*5

0

EIK10

0

Enable

Mask

Interrupt mask register (K10)

*5

0

EISW1

EISW0

0

*5

0

R

R/W

EISW1

EISW0

0

Enable

Mask

Interrupt mask register (stopwatch 1 Hz)

Interrupt mask register (stopwatch 10 Hz)

*5

0

EIT2

EIT8

R/W

EIT32

0

R

EIT2

EIT8

0

Enable

Mask

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

EIT32

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-7

CHAPTER 1: CONFIGURATION

Table 1.4.1 (d) I/O memory map (0ECH–0EFH)

Register

Address

Comment

*1

D3

D2

D1

D0

Name

SR

1

0

*5

0

IMEL

0

*5

*4

*5

*4

*5

*4

R

0ECH

0EDH

0EEH

0EFH

0

Yes

No

IMEL

0

Interrupt factor flag (melody)

0

IK1

ISW1

IT8

IK0

ISW0

IT32

0

R

IK1

IK0

0

Yes

No

Interrupt factor flag (K10)

Interrupt factor flag (K00–K03)

0

ISW1

0

Yes

No

Interrupt factor flag (stopwatch 1 Hz)

Interrupt factor flag (stopwatch 10 Hz)

*4

ISW0

0

*5

*4

IT2

IT8

IT32

0

Yes

No

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

II-8

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 1: CONFIGURATION

Table 1.4.1 (e) I/O memory map (0F0H–0F3H)

Register

Address

Comment

*1

D3

D2

D1

D0

Name

MAD3

SR

0

1

0

High

Low

MAD3

MAD2

MAD1

MAD0

Melody ROM address (AD3)

High

Low

R/W

MAD2

MAD1

MAD0

0

Melody ROM address (AD2)

Melody ROM address (AD1)

Melody ROM address (AD0, LSB)

0F0H

0F1H

0F2H

0F3H

*5

0

MAD6

CLKC0

R02

MAD5

R/W

MAD4

MELC

R00

0

MAD6

MAD5

MAD4

CLKC1

CLKC0

TEMPC

MELC

R03

0

High

ON

Low

OFF

Low

Melody ROM address (AD6, MSB)

Melody ROM address (AD5)

Melody ROM address (AD4)

R

CLKC1

TEMPC

CLKC1(0)&CLKC0(0) : melody speed × 1

CLKC1(0)&CLKC0(1) : melody speed × 8

CLKC1(1)&CLKC0(0) : melody speed × 16

CLKC1(1)&CLKC0(1) : melody speed × 32

Tempo change control

R/W

Melody control ON/OFF

R03

R01

High

R/W

R02

Output port data (R00–R03)

R01

R00

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-9

CHAPTER 1: CONFIGURATION

Table 1.4.1 (f) I/O memory map (0F4H, 0F6H, 0F9H–0FAH)

Register

Address

Comment

*1

D3

D2

D1

D0

R10

FOUT

Name

SR

1

0

R12

MO

R11

*3

ENV

0

High

Low

R12

MO

Output port data (R12)

R/W

Inverting melody output

Melody envelope control

Output port data (R11)

Output port data (R10)

Frequency output

0F4H

ENV

R11

0

High

ON

Low

OFF

R10

FOUT

*2

P03

P02

P01

P00

P03

P02

P01

P00

–

High

Low

R/W

0F6H

0F9H

0FAH

I/O port (P00–P03)

*5

0

TMRST SWRUN SWRST

0

*5

TMRST

SWRUN

Reset

0

Reset

Run

–

Stop

–

Clock timer reset

R

W

R/W

W

Stopwatch timer RUN/STOP

Stopwatch timer reset

*5

SWRST

Reset

0

Reset

HLMOD

R/W

0

BLDDT

BLDON

R/W

HLMOD

Heavy

load

Normal

load

Heavy load protection mode register

*5

R

0

Battery

voltage

low

Battery

voltage

normal

BLDDT

BLDON

0

Battery voltage low detector data

ON

OFF

Battery voltage low detector ON/OFF

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

II-10

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 1: CONFIGURATION

Table 1.4.1 (g) I/O memory map (0FBH–0FCH)

Register

Address

Comment

*1

D3

D2

D1

D0

Name

CSDC

SR

0

1

0

Static

Dynamic

CSDC

0

CMPDT CMPON

R/W

LCD drive switch

*5

R/W

R

0

0FBH

0FCH

Comparator's voltage condition:

1 = CMPP(+)input > CMPM(-)input,

0 = CMPM(-)input > CMPP(+)input

Analog comparator ON/OFF

+ > -

On

- > +

Off

CMPDT

CMPON

1

0

*5

0

IOC

R/W

0

*5

R

0

IOC

0

Output

Input

I/O port P00–P03 Input/Output

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-11

CHAPTER 2: INITIAL RESET

CHAPTER 2

INITIAL RESET

2.1 Inte rna l Re g iste r Sta tus on Initia l Re se t

Followin g an in itial reset, th e in tern al registers an d in tern al

data m em ory area are in itialized to th e valu es sh own in

Tables 2.1.1 an d 2.1.2.

Table 2.1.1

Internal Register

Bit Length Initial Value Following Reset

Initial values of internal

registers

Program counter step PCS

Program counter page PCP

8

4

8

4

1

00H

1H

New page pointer

Stack pointer

Index register

Register pointer

General register

Interrupt flag

Decimal flag

Zero flag

NPP

SP

X

1H

Undefined

0

Y

RP

A

B

I

D

Undefined

Z

Carry flag

C

Table 2.1.2

Initial values of internal data

memory area

Internal Data

Memory Area

RAM data

Initial Value

Bit Length

Address

Following Reset

Undefined

4 × 96

4 × 26

000H–05FH

090H–0AFH

0E0H–0FCH

Display memory

Undefined

Internal I/O register See Tables 1.4.1 (a)–1.4.1 (g)

II-12

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 2: INITIAL RESET

After an in itial reset, th e program cou n ter page (PCP) is

in itialized to 1H, an d th e program cou n ter step (PCS), to

00H. Th is is wh y th e program is execu ted from step 00H of

th e first page.

Th e in itial valu es of som e in tern al registers an d in tern al

data m em ory area location s are u n defin ed after a reset. Set

th em as n ecessary to th e proper in itial valu es in th e pro-

gram .

Th e periph eral I/ O fu n ction s (m em ory-m apped I/ O) are

assign ed to in tern al data m em ory area addresses 0E0H to

0FCH. Each address represen ts a 4-bit in tern al I/ O register,

allowin g access to th e periph eral fu n ction s in 1-word (4-bit)

read/ write u n its.

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-13

CHAPTER 2: INITIAL RESET

2.2 Initia lize Prog ra m Exa m p le

Th e followin g is a program th at clears th e RAM an d LCD,

resets th e flags, registers, tim er, an d stopwatch tim er, an d

sets th e stack poin ter im m ediately after resettin g th e sys-

tem .

Label

Mnemonic/operand

Comment

ORG

JP

100H

INIT

;Jump to "INIT"

;

ORG

RST

110H

F,0011B

INIT

;

;Interrupt mask, decimal

;adjustment off

LD

X,0

MX,0

;

RAMCLR LDPX

CP

JP

LD

XH,6H

NZ,RAMCLR

X,90H

MX,0

X,0BH

NZ,LCDCLR

;

Clear RAM (00H–5FH)

Clear LCD (90H–AFH)

LCPCLR LDPX

CP

JP

;

LD

;

A,0

B,5

SPL,A

SPH,B

;

Set stack pointer to 50H

LD

OR

;

X,0F9H

MX,0101B

;

Reset timer and stopwatch

timer

LD

OR

;

X,0EBH

MX,0111B

;

Enable timer interrupt

LD

OR

;

X,0E8H

MX,1111B

;

Enable input interrupt

(K03–K00)

LD

RST

EI

X,0

Y,0

A,0

B,0

F,0

;

Reset register flags

;Enable interrupt

II-14

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 2: INITIAL RESET

Th e above program is a basic in itialization program for th e

S1C62N81. Th e settin g data are all in itialized as sh own in

Table 2.1.1 by execu tin g th is program . Wh en u sin g th is

program , add settin g item s n ecessary for each specific

application . (Figu re 2.2.1 is th e flow ch art for th is program .)

Initialization

Reset

I: Interrupt flag

I (Interrupt flag)

D: Decimal adjustment flag

D (Decimal adjustment flag)

Clear data RAM (00H to 05FH)

Clear segment RAM (90H to 0AFH)

Clear RAM

Set SP

Set stack pointer to 50H

Reset timer,

stopwatch timer

Enable timer interrupt

Enable input interrupt

Enable timer interrupt 2 Hz, 8 Hz, 32 Hz

Enable K03–K00 input port interrupt

Reset registers (X, Y, A, B)

flags (I, Z, D, C)

EI (enable interrupt)

Fig. 2.2.1

Flow chart of the initialization

program

To next process

Table 2.2.2

Execution result of the

initialization program

Internal circuit

General register A

General register B

Index register X

Index register Y

Stack pointer SP

Interrupt flag I

Setting value

0H

00H

50H

1

Decimal flag D

0

Zero flag Z

0

Carry flag C

0

RAM data (00H 5FH)

Segment data (90H 0AFH)

0H

Clock timer: reset, Clock timer interrupt: valid

Stopwatch timer: reset

K00–K03 interrupt: valid

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-15

CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports)

CHAPTER 3

PERIPHERAL CIRCUITS

Details on h ow to con trol th e S1C62N81 periph eral circu it is

given in th is ch apter.

3.1

Inp ut Ports

Inp ut p ort m e m ory

m a p

Table 3.1.1 (a) I/O memory map

Register

Address

Comment

*1

*2

D3

D2

D1

D0

Name

K03

SR

–

1

0

High

Low

K03

K02

K01

K00

*2

High

Low

R

K02

K01

K00

–

0E0H

Input port (K00–K03)

*5

0

KCP03

0

K10

0

*5

0

R

0E1H

0E5H

0E6H

*5

0

*2

K10

–

0

High

Low

Input port (K10)

KCP02

KCP01

KCP00

KCP03

KCP02

KCP01

KCP00

Falling

Rising

Input comparison register (K03)

Input comparison register (K02)

Input comparison register (K01)

Input comparison register (K00)

R/W

*5

0

KCP10

R/W

0

*5

0

R

*5

0

KCP10

0

Falling

Rising

Input comparison register (K10)

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

II-16

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports)

Table 3.1.1 (b) I/O memory map

Register

Address

Comment

*1

D3

D2

D1

D0

Name

EIK03

SR

0

1

0

Enable

Mask

EIK03

EIK02

EIK01

EIK00

Interrupt mask register (K03)

Interrupt mask register (K02)

Interrupt mask register (K01)

Interrupt mask register (K00)

Enable

Mask

R/W

EIK02

EIK01

EIK00

0

0E8H

0E9H

0EDH

*5

0

EIK10

R/W

0

*5

0

R

*5

0

EIK10

0

Enable

Mask

Interrupt mask register (K10)

*5

0

IK1

IK0

0

*5

*4

0

R

IK1

IK0

0

Yes

No

Interrupt factor flag (K10)

Interrupt factor flag (K00–K03)

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-17

CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports)

Th e S1C62N81 Series h ave a 4-bit in pu t port (K00–K03) an d

Control of the inp ut

p ort

a 1-bit in pu t port (K10).

Th e data registers for th e in pu t ports K00–K03 an d K10 are

assign ed to th e addresses 0E0H (D0–D3) an d 0E1H (D0),

respectively. Th e statu s of th e in pu t port term in als can be

read from th e addresses in 4-bit u n its (K00–K03 an d K10).

Th e in pu t ports h ave an in terru pt fu n ction th at can be

con trolled u sin g th e in terru pt factor flags an d in terru pt

m ask registers wh ich h ave been set in each bit. See Section

3.11, "In terru pt an d Halt", for details.

• Loadin g K0 0 –K0 3 in t o t h e A regist er

Exa m p le s of inp ut

p ort c ontrol p rog ra m

Label

Mnemonic/operand

Comment

LD

Y,0E0H

A,MY

;Set address of port

;A register ← K00–K03

As sh own in Figu re 3.1.1, th e two in stru ction steps above

load th e data of th e in pu t port in to th e A register.

D3

D2

D1

D0

A register

K03 K02 K01 K00

Fig. 3.1.1

Loading the A register

Th e data of th e in pu t port can be loaded in to th e B register

or MX in stead of th e A register.

II-18

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports)

• Bit -u n it ch eck in g of in pu t port s

Label

Mnemonic/operand

Comment

DI

;Disable interrupt

LD

Y,0E0H

;Set address of port

INPUT1: FAN

MY,0010B

NZ,INPUT1

MY,0010B

Z,INPUT2

;

JP

INPUT2: FAN

JP

;Loop until K01 becomes "0"

;

;Loop until K01 becomes "1"

Th is program loopes u n til a risin g edge is in pu t to in pu t port

K01.

Th e in pu t port can be addressed u sin g th e Y register in stead

of th e X register.

Note When the input port is changed from high level to low level with a

pull-down resistor, the signal falls following a certain delay caused

by the time constants of the pull-down resistance and the input

gate capacitance. It is therefore necessary to observe a proper

wait time before the input port data is read.

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-19

CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports)

3.2 Outp ut Ports

Outp ut p ort m e m ory

m a p

Table 3.2.1 I/O memory map

Register

Address

Comment

*1

D3

D2

D1

D0

Name

R03

SR

0

1

0

R03

R02

R01

R00

High

Low

R/W

R02

R01

R00

0

High

Low

0F3H

Output port data (R00–R03)

R10

FOUT

R12

MO

R11

*3

ENV

0

High

Low

R12

MO

Output port data (R12)

Inverting melody output

Melody envelope control

Output port data (R11)

Output port data (R10)

Frequency output

R/W

0F4H

ENV

R11

0

High

ON

Low

OFF

R10

FOUT

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

II-20

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports)

Th e S1C62N81 Series h ave 7 bits of gen eral ou tpu t ports

(R00–R03, R10–R12).

Control of the outp ut

p ort

The ou tpu t ports are assigned to the address 0F3H (D0–D3)

for R00–R03 and the address 0F4H (D0–D2) for R10–R12 as

the registers that can read and write. The ou tpu t port termi-

nals ou tpu t the contents written to the registers. In addition,

since the ou tpu t statu s of the ou tpu t port can be read via the

registers, the ou tpu t ports can be controlled in each bit u sing

a logical operation instru ction su ch as AND and OR.

At in itial reset, th e ou tpu t ports go to a low level (th e regis-

ters are 0).

• Loadin g B regist er dat a in t o R0 0 –R0 3

Exa m p le s of outp ut

p ort c ontrol p rog ra m

Label

Mnemonic/operand

Comment

LD

Y,0F3H

MY,B

;Set address of port

;R00–R03 ← B register

As sh own in Figu re 3.2.1, th e two in stru ction steps above

load th e data of th e B register in to th e ou tpu t ports.

D3

D2

D1

D0

B register

R00

R01

R02

R03

Data register

Fig. 3.2.1

Control of the output port

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-21

CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports)

Th e ou tpu t data can be taken from th e A register, MX, or

im m ediate data in stead of th e B register.

• Bit -u n it operat ion of ou t pu t port s

Label

Mnemonic/operand

Comment

LD

OR

AND

Y,0F3H

MY,0010B

MY,1011B

;Set address of port

;Set R01 to 1

;Set R02 to 0

Th e th ree in stru ction steps above cau se th e ou tpu t port to

be set, as sh own in Figu re 3.2.2.

D3

D2

D1

D0

Address 0F3H

R03 R02 R01 R00

No change

Sets "1"

Sets "0"

No change

Fig. 3.2.2

Setting of the output port

II-22

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports)

3.3 Sp e c ia l Use Outp ut Ports

Sp e c ia l use outp ut

p ort m e m ory m a p

Table 3.3.1 I/O memory map

Register

Address

Comment

*1

D3

D2

D1

D0

R10

FOUT

Name

SR

0

1

0

R12

MO

R11

*3

ENV

High

Low

R12

MO

Output port data (R12)

R/W

Inverting melody output

Melody envelope control

Output port data (R11)

Output port data (R10)

Frequency output

0F4H

ENV

R11

0

High

ON

Low

OFF

R10

FOUT

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-23

CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports)

In addition to th e regu lar DC, special ou tpu t can be selected

Control of the sp e -

c ia l use outp ut p ort

for ou tpu t ports R10–R12, as sh own in Table 3.3.2. Figu re

3.3.1 sh ows th e stru ctu re of ou tpu t ports R10–R12.

Table 3.3.2

Pin Name

R12

When Special Output is Selected

Special output

MO or ENV

FOUT

R10

MO

or ENV

Register

(R12)

R12

Register

(R11)

R11

R10

FOUT

Register

(R10)

Address

(0F4H)

Mask option

Fig. 3.3.1

Structure of output ports

R10–R12

II-24

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports)

• Melody ou t pu t MO, MO or en velope ou t pu t (R1 2 )

Exa m p le of sp e c ia l

use outp ut p ort

MO an d MO (or ENV) are th e m elody sign al ou tpu t pin s for

drivin g a piezo or speaker th rou gh an am plifyin g tran sistor.

Refer to 3.10, "Melody Gen erator".

c ontrol p rog ra m

• FOUT (R1 0 )

Wh en ou tpu t port R10 is set for FOUT, it ou tpu ts th e fosc

clock or th e divided fosc. Th e clock frequ en cies listed in

Table 3.3.3 selectable by m ask option .

Table 3.3.3

Clock Frequency (Hz)

Setting Value

Selectable by mask option

fosc = 32,768

fosc / 1

32,768

16,384

8,192

4,096

2,048

1,024

512

fosc / 2

fosc / 4

fosc / 8

fosc / 16

fosc / 32

fosc / 64

fosc / 128

256

Label

Mnemonic/operand

Comment

LD

OR

AND

Y,0F4H

MY,0001B

MY,1110B

;Set address of port

;Turn on FOUT

;Turn off FOUT

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-25

CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)

3.4 I/ O Ports

I/ O p ort m e m ory

m a p

Table 3.4.1 I/O memory map

Register

Address

Comment

*1

*2

D3

D2

D1

D0

Name

P03

SR

–

1

0

P03

P02

P01

P00

High

Low

*2

P02

P01

P00

–

High

Low

R/W

0F6H

I/O port (P00–P03)

*5

0

IOC

R/W

0

*5

R

0FCH

0

IOC

0

Output

Input

I/O port P00–P03 Input/Output

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

II-26

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)

Th e S1C62N81 con tain s a 4-bit gen eral I/ O port (4 bits × 1).

Th is port can be u sed as an in pu t port or an ou tpu t port,

accordin g to I/ O port con trol register IOC. Wh en IOC is "0",

th e port is set for in pu t, wh en it is "1", th e port is set for

ou tpu t.

Control of the I/ O

p ort

• How t o set an in pu t port

Set "0" in th e I/ O port con trol register (D0 of address 0FCH),

an d th e I/ O port is set as an in pu t port. Th e state of th e I/ O

port (P00–P03) is decided by th e data of address 0F6H. (In

th e in pu t m ode, th e port level is read directly.)

• How t o set an ou t pu t port

Set "1" in th e I/ O port con trol register, an d th e I/ O port is

set as an ou tpu t port. Th e state of th e I/ O port is decided by

th e data of address 0F6H. Th is data is h eld by th e register,

an d can be set regardless of th e con ten ts of th e I/ O con trol

register. (Th e data can be set wh eth er P00 to P03 ports are

in pu t ports or ou tpu t ports.)

Th e I/ O con trol registers are cleared to "0" (in pu t/ ou tpu t

ports are set as in pu t ports), an d th e data registers are also

cleared to "0" after an in itial reset.

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-27

CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)

• Loadin g P0 0 –P0 3 in pu t dat a in t o A regist er

Exa m p le s of I/ O p ort

c ontrol p rog ra m

Label

Mnemonic/operand

Comment

LD

AND

LD

Y,0FCH

MY,1110B

Y,0F6H

A,MY

;Set address of I/O control port

;Set port as input port

;Set address of port

;A register ← P00–P03

LD

As sh own in Figu re 3.4.1, th e fou r in stru ction steps above

load th e data of th e I/ O ports in to th e A register.

D3

D2

D1

D0

A register

Fig. 3.4.1

P03 P02 P01 P00

Loading into the A register

II-28

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)

• Loadin g P0 0 –P0 3 ou t pu t dat a in t o A regist er

Label

Mnemonic/operand

Comment

LD

Y,0FCH

;Set the address of input/output

;port control register

;Set as output port

;Set the address of port

;A register ← P00–P03

OR

LD

MY,0001B

Y,0F6H

A,MY

As sh own in Figu re 3.4.2, th e fou r in stru ction steps above

load th e data of th e I/ O ports in to th e A register.

D3

D2

D1

D0

P03 P02 P01 P00

A register

P00

P01

P02

P03

Data register

Fig. 3.4.2

Control of I/O port (input)

Data can be loaded from th e I/ O port in to th e B register or

MX in stead of th e A register.

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-29

CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)

• Loadin g con t en t s of B regist er in t o P0 0 –P0 3

Label

Mnemonic/operand

Comment

LD

Y,0FCH

;Set the address of input/output

;port control register

;Set port as output port

;Set the address of port

;P00–P03 ← B register

OR

LD

MY,0001B

Y,0F6H

MY,B

As sh own in Figu re 3.4.3, th e fou r in stru ction steps above

load th e data of th e B register in to th e I/ O ports.

D3

D2

D1

D0

B register

P00

P01

P02

P03

Data register

Fig. 3.4.3

Control of the I/O port (output)

Th e ou tpu t data can be taken from th e A register, MX, or

im m ediate data in stead of th e B register.

Bit-u n it operation for th e I/ O port is iden tical to th at for th e

in pu t ports (K00–K03, K10) or ou tpu t ports (R00–R03).

II-30

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)

3.5 LCD Drive r

LCD d rive r m e m ory

m a p

Table 3.5.1 I/O memory map

Register

Address

Comment

*1

D3

D2

D1

D0

Name

CSDC

SR

0

1

0

Static

Dynamic

CSDC

0

CMPDT CMPON

R/W

LCD drive switch

*5

R/W

R

0

0FBH

Comparator's voltage condition:

1 = CMPP(+)input > CMPM(-)input,

0 = CMPM(-)input > CMPP(+)input

Analog comparator ON/OFF

+ > -

On

- > +

Off

CMPDT

CMPON

1

0

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

Address

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

090

0A0

Display memory (write only)

32 words x 4 bits

Fig. 3.5.1

Display memory map

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-31

CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)

Th e S1C62N81 con tain s 128 bits of display m em ory in

Control of the LCD

d rive r

addresses 090H to 0AFH of th e data m em ory. Each display

m em ory can be assign ed to an y 104 bits of th e 128 bits for

th e LCD driver (26 SEG × 4 COM) or 78 bits of th e 128 bits

(26 SEG × 3 COM) by u sin g a m ask option . Th e rem ain in g

24 bits or 50 bits of display m em ory are n ot con n ected to

th e LCD driver, an d are n ot ou tpu t even wh en data is writ-

ten . An LCD segm en t is on with "1" set in th e display

m em ory, an d off with "0" set in th e display m em ory. Note

th at th e display m em ory is a write-on ly.

• LCD drive con t rol regist er (CSDC)

Th e LCD drive con trol register (CSDC: address 0FBH, D3)

can be set eith er for dyn am ic drive or for static drive. Set "0"

in CSDC for 1/ 3 du ty or 1/ 4 du ty (tim e-sh ared) dyn am ic

drive. Set "1" in CSDC an d th e sam e valu e in th e registers

correspon din g to COM0 to COM2 (1/ 3) or COM0 to COM3

(1/ 4) for static drive. Figu re 3.5.2 is th e static drive con trol

of th e LCD, an d Figu re 3.5.3 is an exam ple of th e 7-segm en t

LCD assign m en t.

II-32

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)

LCD lighting status

-VDD

-VL1

-VL2

-VL3

COM0

COM1

COM2

COM3

COM

0–3

Frame frequency

SEG0–25

Not lit

-VDD

-VL1

-VL2

-VL3

Lit

SEG

0–25

-VDD

-VL1

-VL2

-VL3

Fig. 3.5.2

LCD static drive control

a

f

b

Register

Address

D3

D2

c

D1

b

D0

a

g

d

090H

091H

g

f

e

c

Fig. 3.5.3

7-segment LCD assignment

d

In th e assign m en t sh own in Figu re 3.5.3, th e 7-segm en t

display pattern is con trolled by writin g data to display

m em ory addresses 090H an d 091H.

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-33

CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)

• Displayin g 7 -segm en t

Exa m p le s of

LCD d rive r c ontrol

p rog ra m

Th e LCD display rou tin e u sin g th e assign m en t of Figu re

3.5.3 can be program m ed as follows.

Label

Mnemonic/operand

Comment

ORG

000H

3FH

06H

5BH

4FH

66H

6DH

7DH

27H

7FH

6FH

RETD

;0 is displayed

;1 is displayed

;2 is displayed

;3 is displayed

;4 is displayed

;5 is displayed

;6 is displayed

;7 is displayed

;8 is displayed

;9 is displayed

SEVENS: LD

LD

B,0

X,090H

;Set the address of jump

;Set address of display memory

JPBA

Wh en th e above rou tin e is called (by th e CALL or CALZ

in stru ction ) with an y n u m ber from "0" to "9" set in th e A

register for th e assign m en t of Figu re 3.5.4, seven segm en ts

are displayed accordin g to th e con ten ts of th e A register.

A resister Display A resister Display A resister Display A resister Display A resister Display

Fig. 3.5.4

0

1

2

3

4

5

6

7

8

9

Data set in A register and

displayed patterns

Th e RETD in stru ction can be u sed to write data to th e

display m em ory on ly if it is addressed u sin g th e X register.

(Addressin g u sin g th e Y register is in valid.)

Note th at th e stack poin ter m u st be set to a proper valu e

before th e CALL (CALZ) in stru ction is execu ted.

II-34

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)

• Bit -u n it operat ion of t h e display m em ory

Data

D2 D1

Address

090H

Fig. 3.5.5

Example of segment

assignment

D3

D0

●

● : SEG - A

● : SEG - B

Label

Mnemonic/operand

Comment

LD

X,SEGBUF

;Set address display

;memory buffer

LD

Y,090H

MX,3

;Set address display memory

;Set buffer data

LD

AND

LD

AND

LD

MY,MX

MX,1110B

MY,MX

MX,1101B

MY,MX

;SEG-A, B ON (●, ●)

;Change buffer data

;SEG-A OFF (●, ●)

;Change buffer data

;SEG-B OFF (●, ●)

For m an ipu lation of th e display m em ory in bit-u n its for th e

assign m en t of Figu re 3.5.5, a bu ffer m u st be provided in

RAM to h old data. Note th at, sin ce th e display m em ory is

write-on ly, data can n ot be ch an ged directly u sin g an ALU

in stru ction (for exam ple, AND or OR).

After m an ipu latin g th e data in th e bu ffer, write it in to th e

correspon din g display m em ory u sin g th e tran sfer com m an d.

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-35

CHAPTER 3: PERIPHERAL CIRCUITS (Timer)

3.6 Tim e r

Tim e r m e m ory m a p

Table 3.6.1 I/O memory map

Register

Address

Comment

*1

D3

D2

D1

D0

Name

TM3

SR

–

1

0

High

Low

TM3

TM2

TM1

TM0

Timer data (clock timer 2 Hz)

Timer data (clock timer 4 Hz)

Timer data (clock timer 8 Hz)

Timer data (clock timer 16 Hz)

High

Low

R

TM2

TM1

TM0

–

0E4H

*5

0

EIT2

EIT8

R/W

EIT32

0

R

EIT2

EIT8

0

Enable

Mask

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

0EBH

EIT32

*5

0

IT2

IT8

IT32

0

*4

R

IT2

IT8

IT32

0

Yes

No

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

0EFH

*5

0

TMRST SWRUN SWRST

0

*5

TMRST

Reset

0

Reset

Run

–

Stop

–

Clock timer reset

R

W

R/W

W

0F9H

SWRUN

Stopwatch timer RUN/STOP

Stopwatch timer reset

*5

SWRST

Reset

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

II-36

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Timer)

Th e S1C62N81 con tain s a tim er with a basic oscillation of

32.768 kHz (typical). Th is tim er is a 4-bit bin ary cou n ter,

an d th e cou n ter data can be read as n ecessary. Th e cou n ter

data of th e 16 Hz clock can be read by readin g TM3 to TM0

(address 0E4H, D3 to D0). ("1" to "0" are set in TM3 to TM0,

correspon din g to th e h igh -low levels of th e 2 Hz, 4 Hz, 8 Hz,

an d 16 Hz 50 % du ty waveform . See Figu re 3.6.1.) Th e tim er

can also in terru pt th e CPU on th e fallin g edges of th e 32 Hz,

8 Hz, an d 2 Hz sign als. For details, see Section 3.11, "In ter-

ru pt an d Halt".

Control of the tim e r

Register

Address

Frequency

16 Hz

8 Hz

Clock timer timing chart

bit

D0

D1

D2

D3

0E4H

4 Hz

2 Hz

Occurrence of

32 Hz interrupt request

Occurrence of

8 Hz interrupt request

Occurrence of

2 Hz interrupt request

Fig. 3.6.1

Output waveform of

timer and interrupt timing

Th e tim er is reset by settin g "1" in TMRST (address 0F9H,

D2).

Note The 128 Hz to 2 Hz of the internal divider is initialized by resetting

the timer, and 128 Hz to 1 Hz of the internal divider is reset by

resetting the stopwatch timer.

Th e dividers of th e tim er an d stopwatch tim ers are in divid-

u al circu its, so resettin g on e circu it does n ot affect th e

oth er.

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-37

CHAPTER 3: PERIPHERAL CIRCUITS (Timer)

• In it ializin g t h e t im er

Exa m p le s of tim e r

c ontrol p rog ra m

Label

Mnemonic/operand

Comment

LD

Y,0F9H

;Set address of the timer

;reset register

OR

MY,0100B

;Reset the timer

Th e two in stru ction steps above are u sed to reset (clear

TM0–TM3 to 0) an d restart th e tim er. Th e TMRST register is

cleared to "0" by h ardware 1 clock after it is set to "1".

• Loadin g t h e t im er

Label

Mnemonic/operand

Comment

LD

Y,0E4H

;Set address of

;the timer data (TM0 to TM3)

;Load the data of

LD

A,MY

;TM0 to TM3 into A register

As sh own in Table 3.6.2, th e two in stru ction steps load th e

data of TM0 to TM3 in to th e A register.

Table 3.6.2

Loading the timer data

D3

D2

D1

D0

A register

TM3 (2 Hz) TM2 (4 Hz) TM1 (8 Hz) TM0 (16 Hz)

II-38

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Timer)

• Ch eck in g t im er edge

Label

Mnemonic/operand

Comment

LD

CP

X,TMSTAT

MX,0

;Set address of the timer edge counter

;Check whether the timer edge

;counter is "0"

JP

LD

Z,RETURN

Y,0E4H

A,MY

;Jump if "0" (Z-flag is "1")

;Set address of the timer

;Read the data of TM0 to TM3

;into A register

LD

XOR

Y,TMDTBF

MY,A

;Set address of the timer data buffer

;Did the count on the timer

;change?

FAN

LD

MY,0100B

MY,A

;Check bit D2 of the timer data buffer

;Set the data of A register into

;the timer data buffer

JP

ADD

Z,RETURN

MX,0FH

;Jump, if the Z-flag is "1"

;Decrement the timer edge counter

;

RETURN: RET

;Return

Th is program takes a su brou tin e form . It is called at sh ort

in tervals, an d decrem en ts th e data at address TMSTAT every

125 m s u n til th e data reach es "0". Th e tim in g ch art is

sh own in Figu re 3.6.2. Th e tim er can be addressed u sin g

th e X register in stead of th e Y register.

TMSTAT and TMDTBF may be any address in RAM and not

involve a hardware function.

Note

TM2

125 ms

Fig. 3.6.2

Timing of the timer

edge counter

Timer edge counter (TMSTAT) decrementing timing

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-39

CHAPTER 3: PERIPHERAL CIRCUITS (Stopwatch Timer)

3.7 Stop wa tc h Tim e r

Stop wa tc h tim e r

m e m ory m a p

Table 3.7.1 I/O memory map

Register

Address

Comment

*1

D3

D2

D1

D0

Name

SWL3

SR

0

1

0

SWL3

SWL2

SWL1

SWL0

MSB

SWL2

SWL1

SWL0

SWH3

SWH2

SWH1

SWH0

0

Stopwatch timer

1/100 sec (BCD)

R

0E2H

0E3H

LSB

SWH3

SWH2

SWH1

SWH0

EISW0

ISW0

MSB

R

Stopwatch timer

1/10 sec (BCD)

LSB

*5

0

EISW1

0

*5

0

R

R/W

0EAH

EISW1

EISW0

0

Enable

Mask

Interrupt mask register (stopwatch 1 Hz)

Interrupt mask register (stopwatch 10 Hz)

*5

0

ISW1

0

*5

R

0EEH

*4

ISW1

0

Yes

No

Interrupt factor flag (stopwatch 1 Hz)

Interrupt factor flag (stopwatch 10 Hz)

*4

ISW0

*5

0

TMRST SWRUN SWRST

0

*5

TMRST

Reset

0

Reset

Run

–

Stop

–

Clock timer reset

R

W

R/W

W

0F9H

SWRUN

Stopwatch timer RUN/STOP

Stopwatch timer reset

*5

SWRST

Reset

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

II-40

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Stopwatch Timer)

Th e S1C62N81 con tain s 1/ 100 sec an d 1/ 10 sec stopwatch

tim ers.

Control of the stop -

wa tc h tim e r

Th is tim er can be loaded in 4-bit u n its. Startin g, stoppin g,

an d resettin g th e tim er can be con trolled by register.

Figu re 3.7.1 sh ows th e operation of th e stopwatch tim er.

Stopwatch timer (SWL) timing chart

Register bit

D0

Address

D1

0E2H

(1/100 sec BCD)

D2

D3

Occurrence of

10 Hz interrupt request

Address

Register bit

Stopwatch timer (SWH) timing chart

D0

D1

D2

D3

0E3H

(1/10 sec BCD)

Fig. 3.7.1

Stopwatch timer

operating timing

Occurrence of

1 Hz interrupt request

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-41

CHAPTER 3: PERIPHERAL CIRCUITS (Stopwatch Timer)

• In it ializin g t h e st opwat ch t im er

Exa m p le s of stop -

wa tc h tim e r c ontrol

p rog ra m

Label

Mnemonic/operand

Comment

LD

OR

Y,0F9H

MY,0001B

;Set address of the SWRST register

;Reset the stopwatch timer

Th e two in stru ction steps above reset th e stopwatch tim er.

(SWL3 to SWL0, SWH3 to SWH0 are all cleared to "0".)

Note The stopwatch timer is reset by setting "1" in the SWRST register.

However, the SWRST register is cleared to "0" by hardware 1

clock after it is set to "1".

• St art in g t h e st opwat ch t im er

Label

Mnemonic/operand

Comment

LD

OR

Y,0F9H

;Set address of SWRUN register

;Start the stopwatch timer

MY,0010B

Th e two in stru ction steps above ru n th e stopwatch tim er of

SWL0 to SWL3, an d SWH0 to SWH3 (addresses 0E2H an d

0E3H, respectively).

• St oppin g t h e st opwat ch t im er

Label

Mnemonic/operand

Comment

LD

AND

Y,0F9H

MY,1101B

;Set address of SWRUN register

;Stop the stopwatch timer

Th e two in stru ction steps above stop th e stopwatch tim er of

SWL0 to SWL3, an d SWH0 to SWH3 (addresses 0E2H an d

0E3H, respectively).

II-42

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Stopwatch Timer)

• Loadin g t h e st opwat ch t im er

Label

Mnemonic/operand

Comment

LD

Y,0E2H

;Set address of the SWL of

;the stopwatch

LDPY

LD

A,MY

;Read the data of SWL0 to SWL3

;into A register

;Read the data of SWH0 to SWH3

;into B register

B,MY

Th e th ree in stru ction steps above reads th e con ten ts of th e

stopwatch tim er in to A register an d B register. (Also see

Table 3.7.2.)

Table 3.7.2

Data load into A register

and B register

D3

D2

D1

D0

SWL3 SWL2 SWL1 SWL0

SWH3 SWH2 SWH1 SWH0

A register

B register

A read-in error caused by a carry from the SWL is not taken into

account in this program. You are recommended to add a handling

routine in your application.

Note

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-43

CHAPTER 3: PERIPHERAL CIRCUITS (BLD Circuit and Heavy Load Protection Function)

3.8 Ba tte ry Volta g e Low De te c tion (BLD) Circ uit

a nd He a vy Loa d Prote c tion Func tion

Th e S1C62N81 Series h as bu ilt-in battery voltage low detec-

tion circu it an d drop in power battery voltage m ay be de-

tected by con trollin g th e register on th e I/ O m em ory. Crite-

ria voltages are as follows:

Model

Criteria Voltage

2.4 V ± 0.15 V

1.2 V ± 0.10 V

S1C62N81/62A81

S1C62L81/62B81

Moreover, wh en th e battery load becom es h eavy, su ch as

du rin g extern al piezo bu zzer drivin g or extern al lam p ligh t-

in g, h eavy load protection fu n ction is bu ilt-in in case th e

battery voltage drops. S1C62L81/ 62B81 operates at 0.9 V

du e to th e BLD circu it an d h eavy load protection fu n ction .

BLD c irc uit a nd

he a vy loa d p rote c -

tion func tion m e m -

ory m a p

Table 3.8.1 I/O memory map

Register

Address

Comment

*1

D3

D2

D1

D0

Name

SR

0

1

0

HLMOD

0

BLDDT

BLDON

HLMOD

Heavy

load

Normal

load

Heavy load protection mode register

*5

R/W

R

R/W

0

0FAH

Battery

voltage

low

Battery

voltage

normal

BLDDT

BLDON

0

BLD data

ON

OFF

BLD ON/OFF

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

II-44

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (BLD Circuit and Heavy Load Protection Function)

Th e BLD circu it will tu rn ON by writin g "1" on th e BLDON

Control of the BLD

c irc uit

register (address 0FAH, D0, R/ W) an d battery voltage low

detection will be perform ed. By writin g "0" on th e BLDON

register, th e detection resu lt is stored in th e BLDDT register.

However, in order to obtain a stable detection resu lt, it is

n ecessary to tu rn th e BLD circu it ON for at least 100 µs.

Accordin gly, readin g ou t th e detection resu lt from th e

BLDDT register is perform ed th rou gh th e followin g proce-

du res:

➀ Set th e BLDON register to "1".

➀ Provide at least 100 µs waitin g tim e.

➀ Set th e BLDON register to "0".

➀ Read-ou t from th e BLDDT register.

Note, h owever, th at wh en S1C62N81 is to be u sed with th e

n orm al system clock at fosc = 32.768 kHz, th ere is n o n eed

for th e waitin g tim e stated in th e above procedu re ➀ sin ce 1

in stru ction cycle will take lon ger th an 100 µs.

Becau se th e power cu rren t con su m ption of th e IC becom es

large wh en th e BLD circu it is operated, tu rn th e BLD circu it

OFF wh en n ot in u se. Th e operation tim in g ch art is sh own

in Figu re 3.8.1.

Battery voltage

Criteria voltage

100 µs or more

Fig. 3.8.1

BLDON register

BLD circuit

Timing chart of

battery voltage low

detection operation

through the BLDON

register

BLDDT register

HLMOD register

Label

Mnemonic/Operand

Comment

Exa m p le of BLD

c irc uit c ontrol

p rog ra m

LD

X,0FAH

MX,0001B

MX,1110B

A,MX

;Sets the address of BLDON

;Sets BLDON to "1"

;Sets BLDON to "0"

;Loads the detection result

;into the A register

OR

AND

LD

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-45

CHAPTER 3: PERIPHERAL CIRCUITS (BLD Circuit and Heavy Load Protection Function)

Th ere are two ways to operate th e h eavy load protection

He a vy loa d p rote c -

fu n ction :

tion func tion

•

Operat ion t h rou gh t h e HLMOD regist er

Th e h eavy load protection fu n ction m ay be operated by

writin g "1" on th e HLMOD register (address 0FAH, D3,

R/ W). Sim u ltan eou sly, th e BLD circu it will tu rn ON an d

battery voltage low detection by h ardware every 2 Hz (0.5

sec) will au tom atically be perform ed.

Operation th rou gh th e HLMOD register is u sefu l wh en

h eavy load can be an ticipated su ch as wh en S1C62N81

drives th e piezo bu zzer. Th e operation tim in g ch art is

sh own in Figu re 3.8.2.

Battery voltage

Criteria voltage

HLMOD register

Heavy load

protection mode

Fig. 3.8.2

Timing chart of

2 Hz clock

BLD circuit

BLDDT

battery voltage low

detection opera-

tion through the

HLMOD register

BLDON register

•

Operat ion t h rou gh t h e BLDON regist er

Th e BLD circu it will tu rn ON by writin g "1" on th e

BLDON register (address 0FAH, D0, R/ W) an d battery

voltage low detection will be perform ed. By writin g "0" on

th e BLDON register, th e detection resu lt is stored in th e

BLDDT register. If th is resu lts in th e battery voltage bein g

lower th an th e criteria voltage, th e h eavy load protection

fu n ction will operate. In oth er words, th e BLD circu it in

th is case serves as a sen sor for detectin g th e operation al

state of th e h eavy load protection fu n ction .

II-46

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (BLD Circuit and Heavy Load Protection Function)

Operation th rou gh th e BLDON circu it is u sefu l as a

m easu re again st u n foreseen circu m stan ces, su ch as drop

in su pply voltage du e to expirin g battery life, by way of

prom ptly operatin g th e h eavy load protection fu n ction .

Th e followin g procedu res for con trollin g th e BLD circu it

by th e software are th e sam e as th ose described in "Con -

trol of th e BLDON circu it":

➀ Set th e BLDON register to "1".

➀ Provide at least 100 µs waitin g tim e.

➀ Set th e BLDON register to "0".

➀ Read-ou t from th e BLDDT register.

If th e battery voltage is lower th an th e criteria voltage, th e

h eavy load protection fu n ction will au tom atically start

operatin g after th e above procedu re ➀ h as been per-

form ed.

Becau se battery voltage low detection by h ardware every

2 Hz (0.5 sec) will au tom atically be perform ed wh en th e

h eavy load protection fu n ction operates, refrain from

operatin g th e BLD circu it with th e software in order to

m in im ize power cu rren t con su m ption . Th e operation

tim in g ch art is sh own in Figu re 3.8.3.

Battery voltage

Criteria voltage

100 µs or more

BLDON register

2 Hz clock

Fig. 3.8.3

Timing chart of heavy

load protection

BLD circuit

BLDDT register

function operation

through the BLDON

register

Heavy load

protection mode

HLMOD register

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-47

CHAPTER 3: PERIPHERAL CIRCUITS (BLD Circuit and Heavy Load Protection Function)

•

Operat ion t h rou gh t h e HLMOD regist er

Th is is a sam ple program wh en lam p is driven with th e

R00 term in al du rin g perform an ce of h eavy load protec-

tion .

Exa m p le s of he a vy

loa d p rote c tion

func tion c ontrol

p rog ra m

Label

Mnemonic/Operand

Comment

LD

OR

LD

OR

X,0FAH

MX,1000B

Y,0F3H

;Sets the address of HLMOD

;Sets to the heavy protection mode

;Sets the address of R0n port

;Turns lamp ON

MY,0001B

:

LD

Y,0F3H

;Sets the R0n port address

AND

MY,1110B

;Turns the lamp on

CALL WT1S

AND MX,0111B

;1 second waiting time (software timer)

;Cancels the heavy load protection mode

In th e above program , th e h eavy load protection m ode is

can celed after 1 secon d waitin g tim e provided as th e tim e

for th e battery voltage to stabilize after th e lam p is tu rn ed

off; h owever, sin ce th is tim e varies accordin g to th e

n atu re of th e battery, tim e settin g m u st be don e in accor-

dan ce with th e actu al application .

II-48

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (BLD Circuit and Heavy Load Protection Function)

•

Operat ion t h rou gh t h e BLDON regist er

Label

Mnemonic/Operand

Comment

LD

FAN

JP

X,0FAH

;Sets the HLMOD/BLDDT address

;Checks the HLMOD/BLDDT bits

;Heavy load protection mode

;Sets the BLDON to "1"

;Sets the BLDON to "0"

;Checks the BLDDT bit

;Shifts the mode to

MX,1010B

NZ,HLMOD

MX,0001B

MX,1110B

MX,0010B

Z,HLMOD

OR

AND

FAN

JP

;the heavy load protection mode

LD

AND

RET

Y,FLAG

MY,0

;Resets the flag to "0"

;Sets the flag to "1"

;

HLMOD: LD

OR

Y,FLAG

MY,1

RET

Th e above program operates th e h eavy load protection

fu n ction by u sin g th e BLDON register. In th e n orm al

operation m ode, battery voltage low detection is don e

from th e BLDON register an d wh en th e battery voltage

drops below th e criteria voltage, th e m ode sh ifts to th e

h eavy load protection m ode. In th e h eavy load protection

m ode, battery voltage low detection by th e h ardware is

don e every 2 Hz an d th e detection resu lt is stored in th e

BLDDT register. Becau se of th is, th e BLDDT register will

be "1" du rin g th e h eavy load protection m ode. Moreover,

in th e above program , battery voltage low detection by th e

BLDON is h alted du rin g th e h eavy load protection m ode.

If th e battery voltage becom e grater th an th e criteria

voltage, th e BLDDT register valu e will becom e "0" an d

h en ce, battery voltage low detection th rou gh th e BLDON

register will resu m e after ch eckin g th e BLDDT register

valu e. Wh en u sed as a su b-rou tin e, th e above program

will en able th e u ser to determ in e wh eth er th e presen t

operation m ode is th e n orm al operation m ode (flag = "0")

or th e h eavy load protection m ode (flag = "1").

Th e flow ch art for th e above program is sh own in th e n ext

page.

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-49

CHAPTER 3: PERIPHERAL CIRCUITS (BLD Circuit and Heavy Load Protection Function)

Start

=1

HLMOD?

=0

=1

BLDDT?

=0

BLDON

←

1

0

BLDON←

=1

BLDDT?

=0

FLAG←0

FLAG←1

Fig. 3.8.4

Flow chart of operation

RET

through the BLDON register

II-50

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Analog Comparator)

3.9 Ana log Com p a ra tor

Th e S1C62N81 con tain s an an alog com parator (CMP) th e

data of wh ich can be read by software. Th is circu it can be

tu rn ed on an d off to save power. Th e CMPON bit con trols

an alog com parator (CMP) power on / off. At in itial reset, th e

CMP circu it is off. Wh ile th e circu it is n ot in u se, keep th is

bit set to "0" to save power.

Th e ou tpu t data of th e an alog com parator appears in

CMPDT, th is bit is "1" wh en CMPP > CMPM, an d "0" wh en

CMPP < CMPM. If th e CMPON bit is "0", th e CMPDT bit is

fixed at "1".

Ana log c om p a ra tor

m e m ory m a p

Table 3.9.1 I/O memory map

Register

Address

Comment

*1

D3

D2

D1

D0

Name

CSDC

SR

0

1

0

Static

Dynamic

CSDC

0

CMPDT CMPON

R/W

LCD drive switch

*5

R/W

R

0

0FBH

Comparator's voltage condition:

1 = CMPP(+)input > CMPM(-)input,

0 = CMPM(-)input > CMPP(+)input

Analog comparator ON/OFF

+ > -

On

- > +

Off

CMPDT

CMPON

1

0

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-51

CHAPTER 3: PERIPHERAL CIRCUITS (Analog Comparator)

Label

Mnemonic/operand

Comment

Exa m p le of CMP

LD

OR

LD

X,0FBH

MX,0001B

A,08H

;Set CMP circuit address

;CMP circuit on

;

c ontrol p rog ra m

(whe n fosc = 32.768 kHz)

LOOP: ADD

A,01H

NZ,LOOP

A,MX

;

Wait about 3 ms

JP

LD

AND

;A register ← CMPDT

;CMP circuit off

MX,1110B

Execu tion of th e above program loads CMP ou tpu t data

CMPDT in to D1 of th e A register.

It takes abou t 3 m s for th e CMP ou tpu t to becom e stable

wh en th e circu it is tu rn ed on . Th erefore, th e program m u st

in clu de a wait tim e of at least 3 m s before th e ou tpu t data is

loaded after th e CMP circu it h as been tu rn ed on .

II-52

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)

3.10 Me lod y Ge ne ra tor

Me lod y g e ne ra tor

m e m ory m a p

Table 3.10.1 I/O memory map

Register

Address

Comment

*1

D3

0

D2

D1

D0

Name

SR

1

0

*5

0

IMEL

0

*5

*4

R

0ECH

0

Yes

High

No

IMEL

0

Interrupt factor flag (melody)

Melody ROM address (AD3)

Melody ROM address (AD2)

Melody ROM address (AD1)

Melody ROM address (AD0, LSB)

Low

MAD3

MAD2

MAD1

MAD0

MAD3

MAD2

MAD1

MAD0

R/W

0F0H

0F1H

0F2H

*5

0

MAD6

MAD5

R/W

MAD4

0

MAD6

MAD5

MAD4

CLKC1

CLKC0

TEMPC

MELC

0

High

ON

Low

OFF

Melody ROM address (AD6, MSB)

Melody ROM address (AD5)

Melody ROM address (AD4)

R

CLKC1

CLKC0

TEMPC

MELC

CLKC1(0)&CLKC0(0) : melody speed × 1

CLKC1(0)&CLKC0(1) : melody speed × 8

CLKC1(1)&CLKC0(0) : melody speed × 16

CLKC1(1)&CLKC0(1) : melody speed × 32

Tempo change control

R/W

Melody control ON/OFF

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-53

CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)

Th ere are 7 bits for m elody start address settin g.

Ad d re ss se tting

(Ad d re sse s 0F0H a nd

0F1H)

0F1H

0F0H

Fig. 3.10.1

Set of melody ROM

address

–

MSB

AD5

AD4

AD3

AD2

AD1

LSB

↓

MAD6 MAD5 MAD4

MAD3 MAD2 MAD1 MAD0

Note

The user programmable area is from 00H to 04FH (80 words).

Address 0F2H (4 bits) is for m elody con trol.

Pla y m od e c ontrol

Description MELC: (1) Melody start wh en th is bit is set to "1".

(2) Melody stop wh en th is bit is set to "0" an d th ere is

an en d bit com e from m elody ROM.

TEMPC: Selection of tem po (TEMPC0 or TEMPC1); ch osen

by m ask option . Two tem pos (TEMPC0 an d

TEMPC1) can be ch osen ou t of 16 tem pos.

0: TEMPC0

1: TEMPC1

(See S1C62N81 Tech n ical Hardware, 4.11, "Play-

in g tem po".)

CLKC1, CLKC0: Th ese two bits are com bin ed to set th e play

speed.

Table 3.10.2

CLKC1

CLKC0

Play Speed

Set of play speed

0

1

0

1

0

1

Play as normal speed

Play as normal speed × 8

Play as normal speed × 16

Play as normal speed × 32

II-54

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)

Play mode (1) One shot

In th is m ode, on ly on e m elody is played.

Th e con trol procedu re is as follow:

10AH

Jump to

melody subroutine

Set melody address

Melody subroutine

Read interrupt flag

to clear

Set MELC bit to "1"

Set MELC bit to "0"

EI

RET

Set melody interrupt

mask enable

Melody end

interrupt

MELC

MO

Playing

Fig. 3.10.2

Control procedure of

one shot mode

Interrupt generate by END data setting

Wh en th e MELC bit is set to "1", it m akes th e m elody

play. Th e u ser's program sh ou ld set th is bit to "0" before

th e en d bit from th e m elody ROM. If n ot, th e fu n ction

will be like th e level h old m ode (see n ext fu n ction ).

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-55

CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)

(2) Level hold

In th is m ode, after on e m elody h as been played, th e u ser

can ch an ge th e n ext play to an y oth er m elody. If th ere is

n o ch an ge, th e m elody is played repeatedly. Th e con trol

procedu re is as follows:

Set counter n = 0

Set melody1 address

Set MELC bit to "1"

Set melody 2 address

Enable interrupt

10AH

Jump to

melody subroutine

INC n

n = ?

n = N - 1

n = 1

n = 2

N

Set MELC bit to "0"

Set melody 3 address

Set melody 4 address

Select tempo

Read interrupt factor

flag to clear

EI

RET

Melody 1 end

interrupt

Melody 2 end

interrupt

Melody 3 end

interrupt

Melody 4 end

interrupt

MELC

MO

Melody 1

Melody 2

Melody N - 1

Melody N

Interrupt generate

Fig. 3.10.3

Control procedure of level

hold mode

II-56

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)

(3) Retrigger play

In th is m ode, th e m elody can be stopped an ywh ere du r-

in g playin g, an d it can be set to an y an oth er m elody. Th e

con trol procedu re is as follows:

Set melody address

Set MELC bit to "1"

Set MELC bit to "0"

Enable interrupt

10AH

Jump to

Set melody n address

Set MELC bit to "1"

Set MELC bit to "0"

Melody subroutine

melody subroutine

EI

RET

Mid-way of

melody 1

Start of

melody n

Melody n end

interrupt

MELC

MO

Melody 1

Melody n

Fig. 3.10.4

Control procedure of

retriggrer play mode

Melody 1 stopped mid-way

Interrupt generate by END data setting

With th is fu n ction , th e u ser can force th e m elody to stop

if th ere is a rest n ote with th e En d data = "1" in th e

m elody ROM (See m elody ROM data settin g).

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-57

CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)

Tempo and speed control (1) Tempo

Tem po selection is asign ed to address 0F2H bit D1

(TEMPC).

Th is bit sh ou ld be set at th e sam e tim e th at th e MELC bit

is set to "1". Du rin g playin g, th is bit will h ave n o fu n c-

tion for th e m elody playin g. Bu t in th e level h old m ode,

wh en th e n ext m elody is loadin g, TEMPC will also be

loaded. Th e tem po will th en be ch an ged. Th e con trol

procedu re is as follows:

Set melody 1 address

Set TEMPC

bit to "0"

Set MELC bit to "1"

10AH

Jump to

melody subroutine

Set melody 2 address

Set TEMPC bit to "1"

Enable interrupt

Melody subroutine

EI

RET

Melody 1 end

interrupt

Melody 2 end

interrupt

MELC

MO

Melody 1 with tempo 0

Melody 2 with tempo 1

Interrupt generate by END data setting

Fig. 3.10.5

Control procedure

of tempo

II-58

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)

(2) Speed

Speed con trol is asign ed to address 0F2H, bits D2 an d

D3 (CLKC0 an d CLKC1). Th ese two bits are con trolled

in depen den tly. Th e u ser can ch an ge th e speed du rin g

playin g, or start with a differen t speed. Th e con trol

procedu re is as follows:

0F2H D3 D2 D1 D0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1 → Melody start with TEMPC0, speed n orm al

1 → Melody start with TEMPC0, speed × 8

1 → Melody start with TEMPC0, speed × 16

1 → Melody start with TEMPC0, speed × 32

1 → Melody start with TEMPC1, speed n orm al

1 → Melody start with TEMPC1, speed × 8

1 → Melody start with TEMPC1, speed × 16

1 → Melody start with TEMPC1, speed × 32

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-59

CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)

Exam ple of ch an gin g speed du rin g playin g:

Set melody 1 address

Set MELC bit to "1"

Set MELC bit to "0"

Enable interrupt

Set 0F2H to "4"

MELC

CLKC0

CLKC1

MO

Normal speed

Speed x 8

One melody

Interrupt generate by END data setting

Fig. 3.10.6

Control procedure of

play speed

II-60

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)

A m elody in terru pt occu rs wh en th e m elody ROM data is

read ou t with th e en d bit set to "1". Th is in dicates th e en d

of m elody playin g.

Me lod y inte rrup t

0E7H, D0: In terru pt m ask bit

D0: 1 En able in terru pt at th e en d of m elody play.

D0: 0 In terru pt can n ot be gen erated even if play

is en din g.

0ECH, D0: In terru pt factor flag

This bit will be reset to "0" when the u ser reads it.

D0: 1 In terru pt h as occu red already, an d pro-

gram will ju m p to in terru pt vector 10AH.

Becau se th e m elody in terru pt h as th e

h igh est priority, th e in terru pt service will

fin ish first, an d th is flag sh ou ld be read to

be cleared.

D0: 0 In terru pt h as n ot been gen erated yet.

Volume:

Word:

00H–4FH (80 words)

9 bits/ word

Me lod y ROM

Refer to data settin g as below:

Table 3.10.3

D8

D7

D6

D5

D4

D3

D2

D1

D0

Melody ROM data

ATK

data

Note data

Scale address data

En d

(Scale ROM address) data

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-61

CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)

D0: End Data

Melody play will stop after th e n ote playin g wh en th is data is

set to "1".

End data

(D0)

0

1

Read

MO

1 note play

Fig. 3.10.7

End data

Interrupt

D1–D4: Scale Address Data (Scale ROM address)

Wh at pitch is u sed depen ds on th e address poin t of th e

scale ROM an d th e scale data con tain ed. (See scale ROM

data settin g.)

D5–D7: Note Data

Note data table as below:

D5

D6

D7

1

0

1

0

1

0

1

0

1

0

1

0

Table 3.10.4

Note data

+

Note

D8: ATK Data

Th ere will be a sh ort break (≈12 m s) before th e n ote playin g

if th is data is set to "1". Usu ally, two n otes of th e sam e

pitch are separated with th is fu n ction , oth erwise th e two

n otes will play con tin u ou sly with ou t an y break.

In each m elody first word, set th is data to "1". Oth erwise,

th ere will be n o m elody play even if th e u ser starts play.

Next, accordin g to th e u ser's defin ition it can set to "1" or

"0". If th e h ardware m ask option selects th e R12 en velope

fu n ction , th is data also con trols th e n ote ou tpu t by en ve-

lope.

ATK data

(D8)

1

0

Envelope

Fig. 3.10.8

MO

Waveform of envelope

Note 1 play

Note 2 play

Note 3 play

Note 4 play

II-62

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)

Volu m e:

Word:

00H–0FH (16 words)

8 bits/ word

Sc a le ROM

Address 0FH is set to a rest n ote. Th e data con tain ed is n ot

con n ected with th e scale. Th e scale m ay be selected accord-

in g to th e defin ition of th e scale ROM address, wh ich is

defin ed by m elody ROM data D4–D1. Th e scale data defin i-

tion is as th e table on th e n ext page. Th e u ser h as th e

ch oice of 15 types of scale from th is table.

Melody ROM

(D4–D1)

00H

01H

02H

03H

:

Scale ROM data

C major

C4 (Do)

D4 (Re)

E4 (Mi)

F4 (Fa)

04H

20H

3BH

44H

:

→

0EH

0FH

C4H

→

C6 (Do)

Rest

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-63

CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)

For level hold

Exa m p le s of

m e lod y c ontrol

Label

Mnemonic/operand

Comment

p rog ra m

200

LD

INC

LD

INC

LD

EI

:

A,00H

M0,A

X,0F0H

MX,00H

X

MX,00H

Y,0F2H

MY,01H

X,0F0H

MX06H

X

MX,00H

Y,0E7H

MY,01H

;Set counter (melody point)

;Set first melody address (00)

;Start melody with TEMPC0

;Set second melody address (06)

;Enable melody interrupt mask

;Enable interrupt

:

10A

400

PSET

JP

004H

000H

PUSH

INC

LD

XL

XH

YL

YH

A

M0

A,M0

;Melody pointer increment

;Decide which melody

CP

JP

CP

JP

CP

JP

CP

JP

A,01H

Z,MELDY3

A,02H

Z,MELDY4

A,03H

Z,MELDY5

A,04H

Z,MELDY6

A,05H

Z,MELSTP

CP

JP

II-64

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)

JP

MELDY3 LD

LD

INC

LD

JP

MELDY4 LD

LD

INC

LD

JP

MELDY5 LD

LD

MELEND

X,0F0H

MX,0AH

X

MX,00H

MELSTP

X,0F0H

MX,02H

X

MX,01H

MELSTP

X,0F0H

MX,08H

X

;Set MEL3 address (0A)

;Set MEL4 address (12)

;Set MEL5 address (28)

INC

LD

MX,02H

Y,0F2H

MY,03H

MELSTP

X,0F0H

MX,00H

X

;Set TEMPC1 for MEL6

;Set MEL6 address (30)

JP

MELDY6 LD

LD

INC

LD

MELSTP LD

LD

MELEND LD

LD

MX,03H

Y,0F2H

MY,00H

Y,0ECH

A,MY

;Melody stop after end

;Read clear interrupt factor flag

POP

A

POP

EI

YH

YL

XH

XL

RET

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-65

CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)

For one shot

Label

Mnemonic/operand

Comment

:

LD

INC

LD

EI

:

X,0F0H

MX,00H

X

MX,00H

Y,0F2H

MY,01H

MY,00H

X,0E7H

MX,01H

;Set melody address

;Set melody start

;Set MELC to "0"

;Enable melody interrupt mask

;Enable interrupt

For retrigger

Label

Mnemonic/operand

Comment

:

LD

INC

LD

EI

:

X,0F0H

MX,00H

X

MX,00H

Y,0F2H

MY,01H

MY,00H

X,0E7H

MX,01H

;Set melody 1 address

;Set melody start

;Set MELC to "0"

;Enable melody

;Interrupt mask

;Enable interrupt

← Start of m elody 1

:

LD

INC

LD

:

X,0F0H

MX,04H

X

MX,02H

Y,0F2H

MY,07H

MY,06H

;Set melody n address

;Retrigger melody with

;TEMPC1, speed × 8 ← Mid-way th rou gh m elody 1

;Set MELC to "0"

← Start of m elody n

:

II-66

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

3.11 Inte rrup t a nd Ha lt

Inte rrup t m e m ory

m a p

Table 3.11.1 (a) I/O memory map

Register

D2 D1

Address

Comment

*1

D3

D0

Name

KCP03

SR

0

1

0

KCP03

KCP02

KCP01

KCP00

Falling

Rising

Input comparison register (K03)

Input comparison register (K02)

Input comparison register (K01)

Input comparison register (K00)

KCP02

KCP01

KCP00

0

Falling

Rising

R/W

0E5H

0E6H

0E7H

*5

0

KCP10

R/W

0

*5

0

R

*5

0

KCP10

0

Falling

Rising

Input comparison register (K10)

*5

0

EIMEL

R/W

0

*5

R

0

*5

0

EIMEL

0

Enable

Mask

Interrupt mask register (melody)

Enable

Mask

EIK03

EIK02

EIK01

EIK00

EIK03

EIK02

EIK01

EIK00

0

Interrupt mask register (K03)

Interrupt mask register (K02)

Interrupt mask register (K01)

Interrupt mask register (K00)

R/W

0E8H

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-67

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

Table 3.11.1 (b) I/O memory map

Register

Address

Comment

*1

D3

D2

D1

D0

Name

SR

1

0

*5

0

EIK10

0

*5

0

R

0

R/W

0E9H

0EAH

0EBH

*5

0

EIK10

0

Enable

Mask

Interrupt mask register (K10)

*5

0

EISW1

EISW0

0

*5

0

R

R/W

EISW1

EISW0

0

Enable

Mask

Interrupt mask register (stopwatch 1 Hz)

Interrupt mask register (stopwatch 10 Hz)

*5

0

EIT2

EIT8

R/W

EIT32

0

R

EIT2

EIT8

0

Enable

Mask

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

EIT32

*5

0

IMEL

0

*5

*4

R

0ECH

0

Yes

No

IMEL

0

Interrupt factor flag (melody)

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

II-68

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

Table 3.11.1 (c) I/O memory map

Register

Address

Comment

*1

D3

D2

D1

D0

IK0

Name

SR

1

0

*5

0

IK1

0

*5

*4

*5

*4

0

R

0EDH

0EEH

0EFH

IK1

IK0

0

Yes

No

Interrupt factor flag (K10)

Interrupt factor flag (K00–K03)

0

ISW1

ISW0

0

ISW1

0

Yes

No

Interrupt factor flag (stopwatch 1 Hz)

Interrupt factor flag (stopwatch 10 Hz)

*4

ISW0

0

*5

*4

0

IT2

IT8

IT32

IT2

IT8

IT32

0

Yes

No

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-69

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

Th e S1C62N81 su pports fou r types of a total of 11

Control of inte rrup ts

a nd ha lt

in terru pts. Th ere are th ree tim er in terru pts (2 Hz, 8 Hz, 32

Hz), two stopwatch in terru pts (1 Hz, 10 Hz), five in pu t

in terru pts (K00–K03, K10) an d on e m elody in terru pt.

Th e 11 in terru pts are in dividu ally en abled or m asked (dis-

abled) by in terru pt m ask registers. Th e EI an d DI in stru c-

tion s can be u sed to set or reset th e in terru pt flag (I), wh ich

en ables or disables all th e in terru pts at th e sam e tim e.

In dividu al vector addresses are assign ed to th e fou r types of

in terru pt. Th e priority of th e in terru pts is determ in ed by th e

h ardware. Th e priority of th e 2 Hz, 8 Hz, an d 32 Hz tim er

in terru pts wh ere th e vector address is th e sam e is deter-

m in ed by th e software. Th e priority of th e stopwatch in ter-

ru pts between 1 Hz an d 10 Hz is also determ in ed by soft-

ware.

Wh en an in terru pt is accepted, th e in terru pt flag (I) is reset,

an d can n ot accepts an y oth er in terru pts (DI state).

Restart from th e h alt state created by th e HALT in stru ction ,

is don e by in terru pt.

II-70

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

• In t erru pt fact or flags

IK0

Th is flag is set wh en an y of th e K00 to K03 in pu t in terru pts

occu rs. Th e in terru pt factor flag (IK0) is set to "1" wh en th e

con ten ts of th e in pu t (K00–K03) an d th e in pu t com parison

register (KCP00–KCP03) do n ot m atch an d th e data of th e

correspon din g in terru pt m ask register (EIK00–EIK03) is "1".

Th e con ten ts of th e IK0 flag can be loaded by software to

determ in e wh eth er th e K00–K03 in pu t in terru pts h ave

occu red.

Th e flag is reset wh en loaded by software. (See Figu re

3.11.1.)

K00

K01

K02

K03

Input comparison

register (KCP00–KCP03)

Address 0E0H

D0

D1

D2

Input interrupt factor

flag register (IK0)

INT

(Interrupt request)

FF

D3

Address 0E5H

Interrupt flag (I)

D0

D1

D2

Fig. 3.11.1

D3

Input interrupt mask register

(EIK00–EIK03)

K00–K03

input interrupt circuit

Address 0E8H

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-71

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

IK1 Th is flag is set wh en th e K10 in pu t in terru pt occu rs.

Th e in terru pt factor flag (IK1) is set to "1" wh en th e con ten ts

of th e in pu t (K10) an d th e in terru pt differen tial register

(KCP10) do n ot m atch , an d th e correspon din g in terru pt

m ask register (EIK10) is "1".

Th e con ten ts of th e IK1 flag can be loaded by software to

determ in e wh eth er K10 in pu t in terru pt h as occu red.

Th e flag is reset wh en loaded by software. (See Figu re

3.11.2.)

D0

K10

Address 0E1H

Input comparison

register (KCP10)

Input interrupt factor

flag register (IK1)

D0

INT

(Interrupt request)

FF

Address 0E6H

Input interrupt mask register

(EIK10)

D0

Interrupt flag (I)

Address 0E9H

Fig. 3.11.2

K10 input interrupt circuit

II-72

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

IT32 Th is flag is set to "1" wh en a fallin g edge is detected in th e

tim er TM1 (32 Hz) sign al.

Th e con ten ts of th e IT32 flag can be loaded by software to

determ in e wh eth er a 32 Hz tim er in terru pt h as occu red.

Th e flag is reset, wh en it is loaded by software. (See Figu re

3.11.3.)

IT8

Th is flag is set to "1" wh en a fallin g edge is detected in th e

tim er TM1 (8 Hz) sign al.

Th e con ten ts of th e IT8 flag can be loaded by software to

determ in e wh eth er an 8 Hz tim er in terru pt h as occu red.

Th e flag is reset, wh en it is loaded by software. (See Figu re

3.11.3.)

IT2

Th is flag is set to "1" wh en a fallin g edge is detected in th e

tim er TM1 (2 Hz) sign al.

Th e con ten ts of th e IT2 flag can be loaded by software to

determ in e wh eth er a 2 Hz tim er in terru pt h as occu red.

Th e flag is reset, wh en it is loaded by software. (See Figu re

3.11.3.)

Timer interrupt

factor flag (IT)

32 Hz

D0

8 Hz

2 Hz

D1

D2

Address 0EFH

Timer interrupt

mask register (EIT)

D0

INT

D1

D2

(Interrupt request)

Fig. 3.11.3

Address 0EBH

Timer interrupt circuit

Interrupt flag (I)

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-73

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

ISW1 Th is flag is set to "1" wh en a fallin g edge is detected in th e

stopwatch tim er (SWH, 1 Hz).

Th e con ten ts of th e ISW1 flag can be loaded by software to

determ in e wh eth er a 1 Hz stopwatch in terru pt h as occu red.

Th e flag is reset, wh en it is loaded by software. (See Figu re

3.11.4.)

ISW0

Th is flag is set to "1" wh en a fallin g edge is detected in th e

stopwatch tim er (SWH, 10 Hz).

Th e con ten ts of th e ISW0 flag can be loaded by software to

determ in e wh eth er a 10 Hz stopwatch in terru pt h as oc-

cu red.

Th e flag is reset, wh en it is loaded by software. (See Figu re

3.11.4.)

Stopwatch interrupt

factor flag (ISW)

10 Hz

1 Hz

D0

D1

Stopwatch interrupt

mask register (EISW)

D0

D1

INT

(Interrupt request)

Address 0EAH Address 0EEH

Interrupt flag (I)

Fig. 3.11.4

Stopwatch interrupt circuit

Note

The interrupt factor flags must always be loaded under the DI state

(interrupt flag [I] = "0"). Reading under the EI state (interrupt flag

[I] = "1") may cause an operation error.

II-74

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

• In t erru pt m ask regist ers

Th e in terru pt m ask registers are registers th at in dividu ally

specify wh eth er to en able or m ask th e tim er in terru pt (2 Hz,

8 Hz, 32 Hz), stopwatch tim er in terru pt (1 Hz, 10 Hz), or

in pu t in terru pt (K00–K03, K10).

Th e followin g are description s of th e in terru pt m ask regis-

ters.

EIK00 to EIK03 Th is register en ables or m asks th e K00–K03 in pu t in terru pt.

Th e in terru pt con dition flag (IK0) is set to "1" wh en th e

con ten ts of th e in pu t (K00–K03) an d th e in terru pt differen -

tial register (KCP00–KCP03) do n ot m atch an d th e data of

th e correspon din g in terru pt m ask register (EIK00–EIK03) is

"1". Th e CPU is in terru pted if it is in th e EI state (in terru pt

flag [I] = "1"). (See Figu re 3.11.1.)

EIK10

Th is register en ables or m asks th e K10 in pu t in terru pt. Th e

in terru pt con dition flag (IK1) is set to "1" wh en th e con ten ts

of th e in pu t (K10) an d th e in terru pt differen tial register

(KCP10) do n ot m atch an d th e data of th e correspon din g

in terru pt m ask register (EIK10) is "1". Th e CPU is in ter-

ru pted if it is in th e EI state (in terru pt flag [I] = "0"). (See

Figu re 3.11.2.)

Th is register en ables or m asks th e 32 Hz tim er in terru pt.

Th e CPU is in terru pted if it is in th e EI state wh en th e

in terru pt m ask register (EIT32) is set to "1" an d th e in ter-

ru pt con dition flag (IT32) is "1". (See Figu re 3.11.3.)

EIT32

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-75

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

EIT8 Th is register en ables or m asks th e 8 Hz tim er in terru pt. Th e

CPU is in terru pted if it is in th e EI state wh en th e in terru pt

m ask register (EIT8) is set to "1" an d th e in terru pt con dition

flag (IT8) is "1". (See Figu re 3.11.3.)

Th is register en ables or m asks th e 2 Hz tim er in terru pt. Th e

CPU is in tterru pted if it is in th e EI state wh en th e in terru pt

m ask register (EIT2) is set to "1" an d th e in terru pt con dition

flag (IT2) is "1". (See Figu re 3.11.3.)

EIT2

Th is register en ables or m asks th e 1 Hz stopwatch in terru pt.

Th e CPU is in terru pted if it is in th e EI state wh en th e

in terru pt m ask register (EISW1) is set to "1", an d also th e

in terru pt con dition flag (ISW1) is "1". (See Figu re 3.11.4.)

EISW1

EISW0 Th is register en ables or m asks th e 10 Hz stopwatch in ter-

ru pt. Th e CPU is in terru pted if it is in th e EI state wh en th e

in terru pt m ask register (EISW0) is set to "1", an d th e in ter-

ru pt con dition flag (ISW0) is "1". (See Figu re 3.11.4.)

Note

Write to the interrupt mask registers (EIT32, EIT8, EIT2) and read

the interrupt factor flags (IT32, IT8, IT2) in DI states only (interrupt

flag [I] = "0").

II-76

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

• In t erru pt con t rol regist ers

KCP00 to KCP03 Th e data of th e in pu t com parison registers (KCP00–KCP03)

is com pared with th e data of th e correspon din g in pu t ports

(K00–K03). If th e data does n ot m atch an d th e correspon d-

in g in pu t m ask register (EIK00–EIK03) is "1", th e in terru pt

factor flag (IK0) is set to "1".

Th ese registers are u sed to determ in e th e ch an ge in th e

in pu t (K01–K03) level. (See Figu re 3.11.1.)

KCP10 Th e data of th e in pu t com parison register (KCP10) is com -

pared with th e data of th e correspon din g in pu t port (K10). If

th e data does n ot m atch an d th e correspon din g in pu t m ask

register (EIK10) is "1", th e in terru pt factor flag (IK1) is set to

"1".

Th is register is u sed to determ in e th e ch an ge in th e in pu t

(K10) level. (See Figu re 3.11.2.)

Th e in pu t com parison register can effectively be u sed to

determ in e th e on / off state of th e in pu t.

However, as sh own in Figu re 3.11.1, th e resu lt of com pari-

son of th e in pu t (K00–K03) is collected in th e in terru pt

factor flag (IK0), so th e in pu t com parison register can n ot be

u sed to determ in e th e on / off state of th e key m atrix.

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-77

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

• In t erru pt vect or address

Th e S1C62N81 in terru pt vector address is m ade u p of th e

low-order 4 bits of th e program cou n ter (12 bits), each of

wh ich is assign ed a specific fu n ction as sh own in Table

3.11.2.

Table 3.11.2 Assignment of the interrupt vector address

Interrupt

Vector Address

Interrupt Item PCP3 PCP2 PCP1 PCP0 PCS7 PCS6 PCS5 PCS4 PCS3 PCS2 PCS1 PCS0

Priority

Melody

K10

0

1

0

1

0

1

0

1

0

1

0

1

0

10A

108

106

104

102

Highest

K03–K00

Stopwatch

Timer

Lowest

As sh own in Table 3.11.2, th e lower order 4 bits of th e

program cou n ter are set accordin g to wh ich of th e in terru pts

occu rs. In oth er words, th e in terru pt vector address is set

at page 1, steps 02H, 04H, 06H, 08H, 0AH.

Note th at all of th e th ree tim er in terru pts h ave th e sam e

vector address, an d software m u st be u sed to ju dge wh eth er

or n ot a given tim er in terru pt h as occu rred. For in stan ce,

wh en th e 32 Hz tim er in terru pt an d th e 8 Hz tim er in terru pt

are en abled at th e sam e tim e, th e accepted tim er in terru pt

m u st be iden tified by software. (Sim ilarly, th e K00–K03

in pu t in terru pts an d th e 10 Hz/ 1 Hz stopwatch in terru pts

m u st be iden tified by software.)

Wh en an in terru pt is gen erated, th e h ardware resets th e

in terru pt flag (I) to en ter th e DI state. Execu te th e EI in -

stru ction as n ecessary to recover th e EI state after in terru pt

processin g.

II-78

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

Set th e EI state at th e start of th e in terru pt processin g

rou tin e to allow n estin g of th e in terru pts. Th en th e priority

of th e in terru pt or th e n estin g level is determ in ed an d set by

h ardware.

Th e in terru pt factor flags m u st always be reset before set-

tin g th e EI statu s in th e correspon din g in terru pt processin g

rou tin e. (Th e flag is reset wh en th e in terru pt con dition flag

is read by software.)

If th e EI in stru ction is execu ted with ou t resetting th e in ter-

ru pt factor flag after gen eratin g th e tim er in terru pt or th e

stopwatch tim er in terru pt or m elody, an d if th e correspon d-

in g in terru pt m ask register is still "1", th e sam e in terru pt is

gen erated on ce m ore. (See Figu re 3.11.5.)

If th e EI state is set with ou t resetting th e in terru pt con dition

flag after gen eratin g th e in pu t in terru pt (K00–K03, K10), th e

sam e in terru pt is gen erated on ce m ore. (See Figu re 3.11.5.)

Th e in terru pt factor flag m u st always be read (reset) in th e

DI state (in terru pt flag [I] = "0"). Th ere m ay be an operation

error if read in th e EI state.

Th e tim er in terru pt factor flags (IT32, IT8, IT2) an d th e

stopwatch in terru pt factor flags (ISW1, ISW0) are set

wh eth er th e correspon din g in terru pt m ask register is set or

n ot.

Th e in pu t in terru pt factor flags (IK0, IK1) are allowed to be

set in th e con dition wh en th e correspon din g in terru pt m ask

register (EIK00–EIK03, EIK10) is set to "1" (in terru pt is

en abled). (See Figu re 3.11.5.)

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-79

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

Interrupt vector

(low-order 4 bits)

Priority detection circuit

IMEL

(MSB)

EIMEL

Program

counter

K10

KCP10

IK1

EIK10

(LSB)

K00

KCP00

EIK00

K01

KCP01

EIK01

IK0

K02

KCP02

EIK02

K03

KCP03

EIK03

ISW0

EISW0

ISW1

EISW1

IT2

EIT2

IT8

EIT8

IT32

EIT32

Fig. 3.11.5

Internal interrupt circuit

II-80

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

• Rest art from h alt st at e by in t erru pt

Exa m p le s of inte rrup t

a nd ha lt c ontrol

p rog ra m

Main routine

Label

Mnemonic/operand

Comment

LD

X,0E8H

;Set address of K00 to K03

;interrupt mask register

;Enable K00 to K03

;input interrupt

OR

MX,1111B

;

LD

OR

LD

OR

LD

OR

X,0EAH

;Set address of stopwatch

;interrupt mask register

;Enable 1 Hz stopwatch interrupt

MX,0010B

X,0EBH

;Set address of timer interrupt

;mask register

;Enable timer interrupt

;(32 Hz, 8 Hz, 2 Hz)

;Set address of melody interrupt

;mask register

;Enable melody interrupt

;Set interrupt flag (EI state is set)

;Halt mode

MX,0111B

X,E7H

MX,0001B

MAIN: EI

HALT

JP

MAIN

;Jump to MAIN

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-81

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

Interruption vector routine

Label

Mnemonic/operand

Comment

ORG

JP

100H

INIT

;Jump to initial routine

HALT

JP

HALT

JP

HALT

JP

HALT

JP

TIINT

SWINT

K0INT

K1INT

;Jump to timer interrupt routine

;Jump to stopwatch interrupt routine

;Jump to K0 input interrupt routine

;Jump to K1 input interrupt routine

HALT

JP

MELINT LD

MELINT

Y,0ECH

;Jump to melody interrupt routine

;Address of melody interrupt

;factor flag

LD

A,MY

;Reset melody interrupt

;factor flag

RETURN EI

RET

LD

K1INT

K0INT

SWINT

Y,0EDH

A,MY

;Address of K10 input port interrupt

;factor flag

;Reset K10 input port interrupt

;factor flag

LD

JP

LD

RETURN

Y,0EDH

;Address of K0n input port interrupt

;factor flag

;Reset K0n input port interrupt

;factor flag

LD

A,MY

JP

LD

RETURN

Y,0EEH

;Address of stopwatch interrupt

;factor flag

LD

X,SWFSTK

MX,MY

;Address of stopwatch interrupt

;factor flag buffer

;Store stopwatch interrupt

;factor flag in buffer

;Check stopwatch 1 Hz

;factor flag

;Jump if not the 1 Hz request

;interrupt

;Stopwatch 1 Hz interrupt

;service routine

LD

FAN

JP

MX,0010B

Z,SW10RQ

SW1IN

CALL

SW10RQ LD

X,SWFSTK

;Address of stopwatch interrupt

;factor flag buffer

II-82

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

FAN

MX,0001B

;Check stopwatch 10 Hz

;factor flag

JP

CALL

Z,RETURN

SW10IN

;Return

;Stopwatch 10 Hz interrupt

;service routine

JP

LD

RETURN

Y,0EFH

TIINT

;Address of timer interrupt

;factor flag

LD

X,TMFSK

MX,MY

;Address of timer interrupt

;factor flag buffer

;Store timer interrupt factor

;flag in buffer

LD

FAN

CALL

MX,0100B

TINT2

;Check 2 Hz timer interrupt

;factor flag

;Call 2 Hz timer interrupt

;service routine

JP

LD

RETURN

X,TMFSK

;Return

TI8RQ

;Address of timer interrupt factor

;flag buffer

FAN

MX,0010B

;Check 8 Hz timer interrupt

;factor flag

JP

CALL

Z,TI32RQ

TINT8

;Don't request interrupt

;Call 8 Hz timer interrupt

;service routine

TI32RQ LD

FAN

X,TMFSK

;Address of timer interrupt factor

;flag buffer

;Check 32 Hz timer interrupt

;factor flag

MX,0001B

JP

CALL

Z,RETURN

TINT32

;Don't request interrupt

;Call 32 Hz timer interrupt

;service routine

JP

RETURN

Th e above program is n orm ally u sed to restart th e CPU

wh en in th e h alt state by in terru pt an d to retu rn it to th e

h alt state again after th e in terru pt processin g is com pleted.

Th e processin g proceeds by repeatin g th e → h alt in terru pt

→ h alt → in terru pt cycle.

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-83

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

All in terru pts are en abled, an d th e priority wh en all in ter-

ru pts are gen erated sim u ltan eou sly is determ in ed by h ard-

ware as follows:

(h igh est priority) Melody in terru pt → K10 in terru pt → K00–

K03 in terru pt → stopwatch in terru pt → tim er in terru pt

(lowest priority)

Th e two stopwatch in terru pts (1 Hz, 10 Hz) h ave th e sam e

vector address (104H). Th e priority is decided by software;

th e stopwatch in terru pt service rou tin e first ch ecks th e 1 Hz

in terru pt factor flag, so th e priority is (h igh priority) stop-

watch 1 Hz in terru pt → stopwatch 10 Hz in terru pt (low

priority).

Th e th ree tim er in terru pts (2 Hz, 8 Hz, 32 Hz) h ave th e sam e

vector address (102H). Th e priority is decided by software;

th e tim er in terru pt service rou tin e first ch ecks th e 2 Hz

in terru pt factor flag, th en 8 Hz, an d fin ally 32 Hz, so th e

priority is (first priority) tim er 2 Hz in terru pt → (secon d

priority) tim er 8 Hz in terru pt → (th ird priority) tim er 32 Hz

in terru pt.

Always load (reset) th e in terru pt factor flags in th e DI state

(in terru pt flag [I] = "0"). Th ere m ay be an operation error if

loaded in th e EI state.

II-84

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 4: SUMMARY OF PROGRAMMING POINTS

CHAPTER 4

SUMMARY OF PROGRAMMING

POINTS

•

Core CPU

After th e system reset, on ly th e program cou n ter (PC),

n ew page poin ter (NPP) an d in terru pt flag (I) are in itial-

ized by th e h ardware. Th e oth er in tern al circu its wh ose

settin gs are u n defin ed m u st be in itialized with th e pro-

gram .

Memory

Mem ory is n ot m ou n ted in u n u sed area with in th e m em -

ory m ap an d in m em ory area n ot in dicated in th is m an -

u al. For th is reason , n orm al operation can n ot be assu red

for program s th at h ave been prepared with access to

th ese areas.

Input Port

Wh en m odifyin g th e in pu t port from h igh level to low level

with pu ll-down resistan ce, a delay will occu r at th e rise of

th e waveform du e to tim e con stan t of th e pu ll-down

resistan ce an d in pu t gate capacities. Provide appropriate

waitin g tim e in th e program wh en perform in g in pu t port

readin g.

•

LCD Driver

–

Becau se th e display m em ory is for writin g on ly, re-writin g

th e con ten ts with com pu tin g in stru ction s (e.G., AND, OR,

etc.) wh ich com e with read-ou t operation s is n ot possible.

To perform bit operation s, a bu ffer to h old th e display

data is requ ired on th e RAM.

Even wh en 1/ 3 du ty is selected, th e display data corre-

spon din g to COM3 is valid for static drive. Hen ce, for

static drive set th e sam e valu e to all display m em ory

correspon din g COM0–COM3.

–

For caden ce adju stm en t, set th e display data in clu din g

display data correspon din g to COM3.

fosc in dicates th e oscillation frequ en cy of th e oscillation

circu it.

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-85

CHAPTER 4: SUMMARY OF PROGRAMMING POINTS

•

Interrupt

–

Even wh en th e con ten ts of th e in pu t data an d in pu t

com parator register ch an ge from an u n m atch ed state to

an oth er u n m atch ed state or to a m atch ed state, n o

in terru pt will occu r.

Re-start from th e HALT state is perform ed by th e in ter-

ru pt. Th e retu rn address after com pletion of th e in terru pt

processin g in th is case will be th e address followin g th e

HALT in stru ction .

Wh en in terru pt occu rs, th e in terru pt flag will be reset by

th e h ardware an d it will becom e DI state. After com ple-

tion of th e in terru pt processin g, set to th e EI state

th rou gh th e software as n eeded.

Moreover, th e n estin g level m ay be set to be program -

m able by settin g to th e EI state at th e begin n in g of th e

in terru pt processin g rou tin e.

–

Be su re to reset th e in terru pt factor flag before settin g to

th e EI state on th e in terru pt processin g rou tin e. Th e

in terru pt factor flag is reset by readin g th rou gh th e

software. Not resettin g th e in terru pt factor flag an d

in terru pt m ask register bein g "1", will cau se th e sam e

in terru pt to occu r again .

Th e in terru pt factor flag will be reset by readin g th rou gh

th e software. Becau se of th is, wh en m u ltiple in terru pt

factor flags are to be assign ed to th e sam e address,

perform th e flag ch eck after th e con ten ts of th e address

h as been stored in th e RAM. Direct ch eckin g with th e

FAN in stru ction will cau se all th e in terru pt factor flag to

be reset.

–

Be su re to perform th e in terru pt factor flag readin g wh ile

in th e DI (in terru pt flag = "0") state. Perform in g th e read-

in g wh ile in th e EI (in terru pt flag = "1") state m ay cau se

m is-operation .

Be su re to perform th e in terru pt m ask register writin g

wh ile in th e DI (in terru pt flag = "0") state. Writin g wh ile in

th e EI (in terru pt flag = "1") state m ay cau se m is-opera-

tion .

In case m u ltiple in terru pts occu r sim u ltan eou sly, in ter-

ru pt processin g will be don e in th e order of h igh priority

first.

II-86

EPSON

S1C62N81 TECHNICAL SOFTWARE

CHAPTER 4: SUMMARY OF PROGRAMMING POINTS

•

Power Supply

Initial Reset

Extern al load drivin g th rou gh th e ou tpu t voltage of con -

stan t voltage circu it or booster circu it is n ot perm itted.

Wh en u tilizin g th e sim u ltan eou s h igh in pu t reset fu n c-

tion of th e in pu t ports (K00–K03), take care n ot to m ake

th e ports specified du rin g n orm al operation to go h igh

sim u ltan eou sly.

•

Data Memory

–

Sin ce som e portion s of th e RAM are also u sed as stack

area du rin g su b-rou tin e call or register savin g, see to it

th at th e data area an d th e stack area do n ot overlap.

–

Th e stack area con su m es 3 words du rin g a su b-rou tin e

call or in terru pt.

Address 00H–0FH in th e RAM is th e m em ory register area

addressed by th e register poin ter RP.

•

Output Port

I/O Port

Th e FOUT ou tpu t sign al m ay produ ce h azards wh en th e

ou tpu t port R10 is tu rn ed on or off.

–

Wh en th e I/ O port is set to th e ou tpu t m ode an d a low-

im pedan ce load is con n ected to th e port pin , th e data

written to th e register m ay differ from th e data read.

Wh en th e I/ O port is set to th e in pu t m ode an d a low-

level voltage (VSS) is in pu t by th e bu ilt-in pu ll-down

resistan ce, an erron eou s in pu t resu lts if th e tim e con -

stan t of th e capacitive load of th e in pu t lin e an d th e bu ilt-

in pu ll-down resistan ce load is greater th an th e read-ou t

tim e. Wh en th e in pu t data is bein g read, th e tim e th at th e

in pu t lin e is pu lled down is equ ivalen t to 0.5 cycles of th e

CPU system clock.

Hen ce, th e electric poten tial of th e pin s m u st settle with in

0.5 cycles. If th is con dition can n ot be m et, som e m easu re

m u st be devised, su ch as arran gin g a pu ll-down resis-

tan ce extern ally, or perform in g m u ltiple read-ou ts.

•

Analog Comparator

Data in th e CMPDT register becom es "1" wh en CMPON is

"0" (an alog com parator circu it is off), an d u n defin ed wh en

th e CMPP an d/ or CMPM in pu t is discon n ected. Avoid

readin g operation u n der th ose con dition s.

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-87

CHAPTER 4: SUMMARY OF PROGRAMMING POINTS

•

Vacant Register and

Read/Write

Writin g data in to th e addresses wh ere read/ write bits

an d read on ly bits are m ixed in 1 word (4 bits) does n ot

affect th e read on ly bits.

Battery Voltage Low

Detection (BLD)

Circuit

Sin ce battery voltage low detection is au tom atically

perform ed by th e h ardware every 2 Hz (0.5 secon d) wh en

th e h eavy load protection fu n ction operates, do n ot per-

m it th e operation of th e BLD circu it by th e software in

order to m in im ize power cu rren t con su m ption .

•

Heavy Load Protec-

tion Function

In th e h eavy load protection fu n ction (h eavy load protec-

tion m ode flag = "1"), battery voltage low detection

th rou gh th e BLDON register is n ot perm itted in order to

m in im ize power cu rren t con su m ption .

II-88

EPSON

S1C62N81 TECHNICAL SOFTWARE

APPENDIX A: TABLE OF INSTRUCTIONS

APPENDIX

A

Ta b le of Instruc tions

Operation Code

Flag

Mne-

Classification

monic

Operand

Clock

Operation

B

1

0

1

0

A

1

0

1

9

1

0

1

0

8

7

6

5

4

3

2

1

0

I D Z C

Branch

PSET

p

0

1

0 p4 p3 p2 p1 p0

5

7

NBP ←p4, NPP←p3~p0

instructions JP

s

0 s7 s6 s5 s4 s3 s2 s1 s0

1 s7 s6 s5 s4 s3 s2 s1 s0

0 s7 s6 s5 s4 s3 s2 s1 s0

1 s7 s6 s5 s4 s3 s2 s1 s0

PCB ←NBP, PCP←NPP, PCS ←s7~s0

PCB ←NBP, PCP←NPP, PCS ←s7~s0 if C=1

PCB ←NBP, PCP←NPP, PCS ←s7~s0 if C=0

PCB ←NBP, PCP←NPP, PCS ←s7~s0 if Z=1

PCB ←NBP, PCP←NPP, PCS ←s7~s0 if Z=0

PCB ←NBP, PCP←NPP, PCSH ←B, PCSL ←A

M(SP-1) ←PCP, M(SP-2) ←PCSH, M(SP-3) ←PCSL+1

SP←SP-3, PCP←NPP, PCS ←s7~s0

C, s

NC, s

Z, s

NZ, s

JPBA

1 1 1 1 0 1 0 0 0

CALL

CALZ

RET

s

0 s7 s6 s5 s4 s3 s2 s1 s0

0

1

0

1

0

1

0

1 s7 s6 s5 s4 s3 s2 s1 s0

7

M(SP-1) ←PCP, M(SP-2) ←PCSH, M(SP-3)← PCSL+1

SP←SP-3, PCP ←0, PCS ←s7~s0

1

0

1

0

PCSL← M(SP), PCSH←M(SP+1), PCP ←M(SP+2)

SP ←SP+3

RETS

RETD

12 PCSL←M(SP), PCSH←M(SP+1), PCP←M(SP+2)

SP← SP+3, PC← PC+1

l

l7 l6 l5 l4 l3 l2 l1 l0

12 PCSL ←M(SP), PCSH←M(SP+1), PCP←M(SP+2)

SP← SP+3, M(X) ←i3~i0, M(X+1) ←l7~l4, X← X+2

System

control

NOP5

NOP7

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

5

7

5

7

No operation (5 clock cycles)

No operation (7 clock cycles)

Halt (stop clock)

X← X+1

instructions HALT

Index

INC

X

operation

Y

Y← Y+1

instructions LD

X, x

Y, y

XH, r

XL, r

YH, r

YL, r

r, XH

r, XL

r, YH

r, YL

1 x7 x6 x5 x4 x3 x2 x1 x0

0 y7 y6 y5 y4 y3 y2 y1 y0

XH← x7~x4, XL ←x3~x0

YH← y7~y4, YL ←y3~y0

XH← r

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1 r1 r0

0 r1 r0

1 r1 r0

0 r1 r0

1 r1 r0

0 r1 r0

1 r1 r0

0 r1 r0

XL← r

YH← r

YL← r

r ←XH

r ←XL

r ←YH

r ←YL

ADC XH, i

XL, i

i3 i2 i1 i0

↑ ↑

↓ ↓

XH← XH+i3~i0+C

XL← XL+i3~i0+C

YH← YH+i3~i0+C

YL← YL+i3~i0+C

↑ ↑

↓ ↓

YH, i

↑ ↑

↓ ↓

YL, i

↑ ↑

↓ ↓

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-89

APPENDIX A: TABLE OF INSTRUCTIONS

Operation Code

Flag

Mne-

monic

Classification

Operand

Clock

Operation

B

1

A

0

1

0

1

9

1

0

1

8

0

1

0

1

7

0

1

0

1

0

1

6

1

5

0

1

4

0

1

0

1

3

2

1

0

I D Z C

Index

CP

XH, i

XL, i

YH, i

YL, i

r, i

i3 i2 i1 i0

↑ ↑

↓ ↓

7

5

7

5

XH-i3~i0

operation

instructions

↑ ↑

↓ ↓

XL-i3~i0

↑ ↑

↓ ↓

YH-i3~i0

↑ ↑

↓ ↓

YL-i3~i0

Data

LD

0 r1 r0 i3 i2 i1 i0

r ←i3~i0

transfer

instructions

r, q

1

0

1

0

1

0

1

0 r1 r0 q1 q0

0 n3 n2 n1 n0

1 n3 n2 n1 n0

0 n3 n2 n1 n0

1 n3 n2 n1 n0

r ←q

A, Mn

B, Mn

Mn, A

Mn, B

A← M(n3~n0)

B← M(n3~n0)

M(n3~n0)←A

M(n3~n0)←B

LDPX MX, i

r, q

0

i3 i2 i1 i0

0 r1 r0 q1 q0

i3 i2 i1 i0

1 r1 r0 q1 q0

M(X)←i3~i0, X← X+1

r←q, X←X+1

LDPY MY, i

r, q

1

M(Y) ←i3~i0, Y ←Y+1

r ←q, Y←Y+1

LBPX MX, l

l7 l6 l5 l4 l3 l2 l1 l0

M(X) ←l3~l0, M(X+1)← l7~l4, X ←X+2

F←F i3~i0

Flag

SET

RST

F, i

0

1

0

1

0

1

0

1

0

1

0

1

0

1

i3 i2 i1 i0 ↑ ↑ ↑ ↑

i3 i2 i1 i0 ↓ ↓ ↓ ↓

operation

F←F i3~i0

instructions SCF

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

↑

↓

C←1

RCF

SZF

RZF

SDF

RDF

EI

C←0

↑

↓

Z←1

Z←0

↑

↓

D←1 (Decimal Adjuster ON)

D←0 (Decimal Adjuster OFF)

I ←1 (Enables Interrupt)

I ←0 (Disables Interrupt)

SP← SP+1

↑

↓

DI

Stack

INC

SP

operation

DEC SP

SP← SP-1

instructions PUSH

r

0 r1 r0

SP← SP-1, M(SP)←r

SP← SP-1, M(SP)←XH

SP← SP-1, M(SP)←XL

SP← SP-1, M(SP)←YH

SP← SP-1, M(SP)←YL

SP← SP-1, M(SP)←F

r ←M(SP), SP←SP+1

XH← M(SP), SP← SP+1

XL← M(SP), SP← SP+1

XH

XL

YH

YL

F

1

0

1

0

1

0

1

0

POP

r

0 r1 r0

XH

XL

1

0

1

0

II-90

EPSON

S1C62N81 TECHNICAL SOFTWARE

APPENDIX A: TABLE OF INSTRUCTIONS

Operation Code

Flag

Mne-

monic

Classification

Operand

Clock

Operation

B

1

A

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

9

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

8

1

0

1

0

1

0

1

0

1

7

1

0

1

0

1

0

1

0

1

0

1

0

1

0

6

1

5

0

1

4

1

0

1

0

1

3

1

0

2

0

1

0

1

0

1

0

I D Z C

Stack

POP

YH

YL

F

5

7

5

7

YH← M(SP), SP← SP+1

YL← M(SP), SP← SP+1

F←M(SP), SP←SP+1

SPH← r

operation

instructions

↑ ↑ ↑ ↑

↓ ↓ ↓ ↓

LD

SPH, r 1

SPL, r

r, SPH 1

r, SPL

Arithmetic ADD r, i

0 r1 r0

1 r1 r0

1

SPL ← r

r← SPH

1

r← SPL

0 r1 r0 i3 i2 i1 i0

★ ↑ ↑

↓ ↓

r← r+i3~i0

instructions

r, q

ADC r, i

r, q

0

0 r1 r0 q1 q0 ★ ↑ ↑

r← r+q

↓ ↓

1 r1 r0 i3 i2 i1 i0

★ ↑ ↑

↓ ↓

r← r+i3~i0+C

r← r+q+C

0

1

1 r1 r0 q1 q0 ★ ↑ ↑

↓ ↓

SUB r, q

0 r1 r0 q1 q0 ★ ↑ ↑

r← r-q

↓ ↓

SBC

r, i

1 r1 r0 i3 i2 i1 i0

★ ↑ ↑

↓ ↓

r← r-i3~i0-C

r← r-q-C

r, q

0

1

1 r1 r0 q1 q0 ★ ↑ ↑

↓ ↓

AND r, i

r, q

0 r1 r0 i3 i2 i1 i0

0 r1 r0 q1 q0

1 r1 r0 i3 i2 i1 i0

1 r1 r0 q1 q0

0 r1 r0 i3 i2 i1 i0

0 r1 r0 q1 q0

1 r1 r0 i3 i2 i1 i0

0 r1 r0 q1 q0

0 r1 r0 i3 i2 i1 i0

↑

↓

r← r i3~i0

1

0

↑

↓

r← r

r← r i3~i0

r← r

r← r i3~i0

r← r

q

OR

r, i

↑

↓

r, q

1

0

↑

↓

q

XOR r, i

r, q

↑

↓

1

↑

↓

q

CP

r, i

↑ ↑

↓ ↓

r-i3~i0

r-q

r, q

0

↑ ↑

↓ ↓

FAN r, i

r, q

↑

↓

r

i3~i0

q

0

1

0

1

0

1

0

1

1 r1 r0 q1 q0

1 r1 r0 r1 r0

↑

↓

RLC

RRC

INC

r

↑ ↑

↓ ↓

d3 ←d2, d2 ←d1, d1 ←d0, d0 ←C, C← d3

d3 ←C, d2 ←d3, d1 ←d2, d0 ←d1, C← d0

M(n3~n0) ←M(n3~n0)+1

r

0

1

1 r1 r0

↑ ↑

↓ ↓

Mn

0 n3 n2 n1 n0

1 n3 n2 n1 n0

↑ ↑

↓ ↓

DEC Mn

↑ ↑

↓ ↓

M(n3~n0) ←M(n3~n0)-1

ACPX MX, r

ACPY MY, r

SCPX MX, r

SCPY MY, r

0

1

0 r1 r0

1 r1 r0

0 r1 r0

1 r1 r0

★ ↑ ↑

↓ ↓

M(X) ←M(X)+r+C, X ←X+1

M(Y) ←M(Y)+r+C, Y ←Y+1

M(X) ←M(X)-r-C, X← X+1

M(Y) ←M(Y)-r-C, Y← Y+1

r ←r

★ ↑ ↑

↓ ↓

★ ↑ ↑

↓ ↓

★ ↑ ↑

↓ ↓

NOT

r

0 r1 r0 1

1

↑

↓

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-91

APPENDIX A: TABLE OF INSTRUCTIONS

Abbreviation s u sed in th e explan ation s h ave th e followin g

m ean in gs.

A .............. A register

B .............. B register

Symbols associated with

registers and memory

X .............. XHL register (low order eigh t bits of in dex register

IX)

Y .............. YHL register (low order eigh t bits of in dex

register IY)

XH ........... XH register (h igh order fou r bits of XHL register)

XL ............ XL register (low order fou r bits of XHL register)

YH ............ YH register (h igh order fou r bits of YHL register)

YL ............ YL register (low order fou r bits of YHL register)

XP ............ XP register (h igh order fou r bits of in dex

register IX)

YP ............ YP register (h igh order fou r bits of in dex

register IY)

SP ............ Stack poin ter SP

SPH .......... High -order fou r bits of stack poin ter SP

SPL .......... Low-order fou r bits of stack poin ter SP

MX, M(X) .. Data m em ory wh ose address is specified with

in dex register IX

MY, M(Y)... Data m em ory wh ose address is specified with

in dex register IY

Mn , M(n ) .. Data m em ory address 000H–00FH (address

specified with im m ediate data n of 00H–0FH)

M(SP) ....... Data m em ory wh ose address is specified with

stack poin ter SP

r, q ........... Two-bit register code

r, q is two-bit im m ediate data; accordin g to th e

con ten ts of th ese bits, th ey in dicate registers A,

B, an d MX an d MY (data m em ory wh ose ad-

dresses are specified with in dex registers IX an d

IY)

r

q

Registers specified

r1

0

r0

0

q1

0

q0

0

A

B

0

1

0

1

0

1

0

MX

MY

1

II-92

EPSON

S1C62N81 TECHNICAL SOFTWARE

APPENDIX A: TABLE OF INSTRUCTIONS

Symbols associated with NBP ..... New ban k poin ter

program counter NPP ..... New page poin ter

PCB ..... Program cou n ter ban k

PCP ..... Program cou n ter page

PCS ..... Program cou n ter step

PCSH .. Fou r h igh order bits of PCS

PCSL ... Fou r low order bits of PCS

Symbols associated with

flags

F ......... Flag register (I, D, Z, C)

C ......... Carry flag

Z ......... Zero flag

D ......... Decim al flag

I .......... In terru pt flag

↓ ............. Flag reset

↑ ............. Flag set

↕ ......... Flag set or reset

Associated with p ......... Five-bit im m ediate data or label 00H–1FH

immediate data s .......... Eigh t-bit im m ediate data or label 00H–0FFH

l .......... Eigh t-bit im m ediate data 00H–0FFH

i .......... Fou r-bit im m ediate data 00H–0FH

Associated with

arithmetic and other

operations

+ ......... Add

- .......... Su btract

............. Logical AND

............. Logical OR

............ Exclu sive-OR

↕ ........ Add-su btract in stru ction for decim al operation

wh en th e D flag is set

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-93

APPENDIX B: THE S1C62N81 I/O MEMORY MAP

APPENDIX

B

The S1C62N81 I/ O Me m ory Ma p

DATA

AD-

DRESS

COMMENT

D3

K03

R

D2

K02

R

D1

K01

R

D0

K00

R

NAME

K03

K02

K01

K00

0

SR

–

0

–

0

–

0

–

0

–

0

–

0

–

0

–

0

–

0

–

0

1

0

HIGH

–

HIGH

–

LOW

–

LOW

–

LOW

RISING

–

INPORT DATA K03

INPORT DATA K02

INPORT DATA K01

INPORT DATA K00

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

0

R

0

R

0

R

K10

R

0

K10

SWL3

SWL2

SWL1

SWL0

SWH3

SWH2

SWH1

SWH0

TM3

TM2

TM1

TM0

KCP03

KCP02

KCP01

KCP00

0

INPORT DATA K10

SWL3

R

SWL2

R

SWL1

R

SWL0

R

STOPWATCH TIMER DATA 3 (1/100) MSB

STOPWATCH TIMER DATA 2 (1/100)

STOPWATCH TIMER DATA 1 (1/100)

STOPWATCH TIMER DATA 0 (1/100) LSB

STOPWATCH TIMER DATA 3 (1/10) MSB

STOPWATCH TIMER DATA 2 (1/10)

STOPWATCH TIMER DATA 1 (1/10)

STOPWATCH TIMER DATA 0 (1/10) LSB

CLOCK TIMER DATA 2Hz

CLOCK TIMER DATA 4Hz

CLOCK TIMER DATA 8Hz

CLOCK TIMER DATA 16Hz

K03 INPUT COMPARISON REGISTER

K02 INPUT COMPARISON REGISTER

K01 INPUT COMPARISON REGISTER

K00 INPUT COMPARISON REGISTER

SWH3

R

SWH2

R

SWH1

R

SWH0

R

–

TM3

R

TM2

R

TM1

R

TM0

R

HIGH

FALLING

KCP03

R/W

KCP02

R/W

KCP01

R/W

KCP00

R/W

0

R

0

R

0

R

KCP10

R/W

–

0

–

KCP10

0

FALLING

RISING

–

K10 INPUT COMPARISON REGISTER

0

R

0

R

0

R

EIMEL

R/W

–

0

–

EIMEL

EIK03

EIK02

EIK01

EIK00

0

ENABLE

–

ENABLE

–

ENABLE

–

ENABLE

–

YES

–

MASK

MELODY INTERRUPT MASK REGISTER

K03 INTERRUPT MASK REGISTER

K02 INTERRUPT MASK REGISTER

K01 INTERRUPT MASK REGISTER

K00 INTERRUPT MASK REGISTER

EIK03

R/W

EIK02

R/W

EIK01

R/W

EIK00

R/W

0

R

0

R

0

R

EIK10

R/W

0

EIK10

0

EISW1

EISW0

0

EIT2

EIT8

EIT32

0

MASK

–

MASK

–

MASK

–

NO

–

K10 INTERRUPT MASK REGISTER

0

R

0

R

EISW1

R/W

EISW0

R/W

S/W INTERRUPT MASK REGISTER 1Hz

S/W INTERRUPT MASK REGISTER 10Hz

0

R

EIT2

R/W

EIT8

R/W

EIT32

R/W

TIMER INTERRUPT MASK REGISTER 2Hz

TIMER INTERRUPT MASK REGISTER 8Hz

TIMER INTERRUPT MASK REGISTER 32Hz

0

R

0

R

0

R

IMEL

R

0

IMEL

0

IK1

IK0

MELODY INTERRUPT FACTOR FLAG

0

R

0

R

IK1

R

IK0

R

–

YES

–

NO

–

K10 INTERRUPT FACTOR FLAG

K00–K03 INTERRUPT FACTOR FLAG

0

R

0

R

ISW1

R

ISW0

R

0

–

ISW1

ISW0

0

IT2

IT8

YES

–

YES

NO

–

NO

S/W INTERRUPT FACTOR FLAG 1Hz

S/W INTERRUPT FACTOR FLAG 10Hz

0

R

IT2

R

IT8

R

IT32

R

TIMER INTERRUPT FACTOR FLAG 2Hz

TIMER INTERRUPT FACTOR FLAG 8Hz

TIMER INTERRUPT FACTOR FLAG 32Hz

EF

IT32

II-94

EPSON

S1C62N81 TECHNICAL SOFTWARE

APPENDIX B: THE S1C62N81 I/O MEMORY MAP

DATA

AD-

DRESS

COMMENT

D3

MAD3

R/W

D2

MAD2

R/W

D1

D0

MAD0

R/W

NAME

MAD3

MAD2

MAD1

MAD0

0

MAD6

MAD5

MAD4

CLK1

CLK0

TEMPC

MELC

R03

R02

R01

R00

R12

MO

SR

0

–

0

1

HIGH

–

HIGH

ON

HIGH

–

0

MAD1

R/W

LOW

–

MEL. ROM ADDR. SETTING REG. AD3

MEL. ROM ADDR. SETTING REG. AD2

MEL. ROM ADDR. SETTING REG. AD1

MEL. ROM ADDR. SETTING REG. LSB

F0

F1

F2

F3

0

R

MAD6

R/W

MAD5

R/W

MAD4

R/W

LOW

OFF

LOW

–

MEL. ROM ADDR. SETTING REG. MSB

MEL. ROM ADDR. SETTING REG. AD5

MEL. ROM ADDR. SETTING REG. AD4

REG. TO CHANGE MELODY CLOCK

REG. TO CHANGE TWO KINDS OF TEMPO

MELODY ON/OFF CONTROL REGISTER

R03 OUT PORT DATA

CLKC1

R/W

CLKC0

R/W

TEMPC

R/W

MELC

R/W

R03

R/W

R02

R/W

R01

R/W

R00

R/W

R02 OUT PORT DATA

R01 OUT PORT DATA

R00 OUT PORT DATA

R12 OUT PORT DATA

R12

MO

ENV

R/W

R10

FOUT

0

1

Hz

0

–

R11

R/W

MELODY INVERTED OUTPUT

MELODY ENVELOPE CONTROL

R11 OUT PORT DATA

ENV

R11

R10

FOUT

0

–

F4

R/W

HIGH

ON

LOW

OFF

–

R10 OUT PORT DATA

FREQUENCY OUTPUT

0

–

R

0

P03

P02

P01

P00

0

TMRST

SWRUN

SWRST

HLMOD

0

BLDDT

BLDON

CSDC

0

CMPDT

CMPON

0

–

F5

F6

F7

F8

F9

FA

FB

FC

P03

R/W

P02

R/W

P01

R/W

P00

R/W

HIGH

–

LOW

–

P03 I/O PORT DATA

P02 I/O PORT DATA

P01 I/O PORT DATA

P00 I/O PORT DATA

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

TMRST

W

SWRUN

R/W

SWRST

W

RESET

0

RESET

RUN

RESET

HEAVY

–

TIMER RESET

STOPWATCH RUN/STOP CONTROL REG.

STOPWATCH RESET

STOP

–

HLMOD

R/W

0

R

BLDDT

R

BLDON

R/W

0

–

0

–

1

0

–

0

NORMAL HEAVY LOAD PROTECTION MODE

–

LOW

ON

NORMAL BLD DATA

OFF

BLD ON-OFF CONTROL REGISTER

CSDC

R/W

0

R

CMPDT

R

CMPON

R/W

STATIC DYNAMIC LCD DRIVER CONTROL REG.

–

+>-

ON

–

->+

OFF

–

CMP DATA

COMPARATOR ON-OFF CONTROL REG.

0

R

0

R

0

R

IOC

R/W

IOC

OUT

IN

I/O IN-OUT CONTROL REG.

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-95

APPENDIX C: TABLE OF THE ICE COMMANDS

APPENDIX

C

Ta b le of the ICE Com m a nd s

Item No.

Function

Command Format

Outline of Operation

1

2

3

Assemble

Disassemble #L,a1,a2

Dump

Fill

#A,a

Assemble command mnemonic code and store at address "a"

Contents of addresses a1 to a2 are disassembled and displayed

Contents of program area a1 to a2 are displayed

Content of data area a1 to a2 are displayed

Data d is set in addresses a1 to a2 (program area)

Data d is set in addresses a1 to a2 (data area)

Program is executed from the "a" address

Execution time and step counter selection

On-the-fly display selection

#DP,a1,a2

#DD,a1,a2

#FP,a1,a2,d

#FD,a1,a2,d

#G,a

4

5

Set

Run Mode

#TIM

#OTF

6

7

Trace

Break

#T,a,n

Executes program while displaying results of step instruction

from "a" address

Displays only the final step of #T,a,n

Sets Break at program address "a"

Breakpoint is canceled

Break condition is set for data RAM

Breakpoint is canceled

Break condition is set for Evaluation Board CPU internal registers

Breakpoint is canceled

Combined break conditions set for program data RAM address

and registers

#U,a,n

#BA,a

#BAR,a

#BD

#BDR

#BR

#BRR

#BM

#BMR

Cancel combined break conditions for program data ROM

address and registers

#BRES

All break conditions canceled

#BC

Break condition displayed

#BE

Enter break enable mode

#BSYN

#BT

Enter break disable mode

Set break stop/trace modes

#BRKSEL,REM

#MP,a1,a2,a3

Set BA condition clear/remain modes

Contents of program area addresses a1 to a2 are moved to

addresses a3 and after

8

Move

#MD,a1,a2,a3

Contents of data area addresses a1 to a2 are moved to addresses

a3 and after

9

Data Set

#SP,a

#SD,a

Data from program area address "a" are written to memory

Data from data area address "a" are written to memory

Display Evaluation Board CPU internal registers

Set Evaluation Board CPU internal registers

Reset Evaluation Board CPU

10

Change CPU #DR

Internal

Registers

#SR

#I

#DXY

#SXY

Display X, Y, MX and MY

Set data for X and Y display and MX, MY

II-96

EPSON

S1C62N81 TECHNICAL SOFTWARE

APPENDIX C: TABLE OF THE ICE COMMANDS

Item No.

Function

Command Format

Outline of Operation

11

History

#H,p1,p2

Display history data for pointer 1 and pointer 2

#HB

Display upstream history data

#HG

Display 21 line history data

#HP

Display history pointer

#HPS,a

#HC,S/C/E

Set history pointer

Sets up the history information acquisition before (S),

before/after (C) and after (E)

#HA,a1,a2

Sets up the history information acquisition from program area

a1 to a2

#HAR,a1,a2

Sets up the prohibition of the history information acquisition

from program area a1 to a2

#HAD

#HS,a

Indicates history acquisition program area

Retrieves and indicates the history information which executed

a program address "a"

#HSW,a

#HSR,a

Retrieves and indicates the history information which wrote or

read the data area address "a"

12

File

#RF,file

#RFD,file

#VF,file

#VFD,file

#WF,file

#WFD,file

#CL,file

#CS,file

#OPTLD,n,file

#CVD

Move program file to memory

Move data file to memory

Compare program file and contents of memory

Compare data file and contents of memory

Save contents of memory to program file

Save contents of memory to data file

Load ICE set condition from file

Save ICE set condition to file

Load HEXA data flom file

Indicates coverage information

Clears coverage information

13

14

Coverage

#CVR

ROM Access #RP

#VP

Move contents of ROM to program memory

Compare contents of ROM with contents of program memory

Set ROM type

#ROM

#Q

15

16

17

Terminate

ICE

Command

Display

Self

Terminate ICE and return to operating system control

#HELP

#CHK

Display ICE instruction

Report results of ICE self diagnostic test

Diagnosis

means press the RETURN key.

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-97

APPENDIX D: CROSS-ASSEMBLER PSEUDO INSTRUCTION LIST

APPENDIX

D

Cross-a sse m b le r Pse ud o Instruc tion List

Item No. Pseudo-instruction

Meaning

Example of Use

1

EQU

To allocate data to label

ABC

BCD

EQU

9

(Equation)

ABC+1

2

ORG

To define location counter

ORG

100H

256

(Origin)

3

SET

(Set)

To allocate data to label

(data can be changed)

ABC

SET

0001H

0002H

4

DW

To define ROM data

ABC

BCD

DW

'AB'

(Define Word)

0FFBH

5

PAGE

(Page)

To define boundary of page

To define boundary of section

To terminate assembly

To define macro

PAGE

1H

15

6

SECTION

(Section)

SECTION

7

END

(End)

8

MACRO

(Macro)

CHECK

LOCAL

LOOP

MACRO

LOOP

CP

DATA

9

LOCAL

(Local)

To make local specification of label

during macro definition

MX,DATA

NZ,LOOP

JP

10

ENDM

To end macro definition

ENDM

(End Macro)

CHECK

1

II-98

EPSON

S1C62N81 TECHNICAL SOFTWARE

APPENDIX E: THE FORMAT OF MELODY SOURCE FILE

APPENDIX

E

The Form a t of Me lod y Sourc e File

Con ten ts of th e sou rce file, created with an editor su ch as

EDLIN, are con figu red from th e S1C62N81 Series m elody

codes an d th e pseu do-in stru ction s described later.

Sourc e File Na m e

Th e sou rce file can be n am ed with a m axim u m of an y seven

ch aracters. As a ru le, keep to th e followin g form at.

C281YYY.MDT

Th ree alph an u m erics are en tered in th e "YYY" part. Refer to

th e m odel n am e from Seiko Epson . Th e exten sion m u st be

".MDT".

Sta te m e nt (line )

Write each of th e sou rce file statem en ts (lin es) as follows:

Basic format: <attack>

Example: .TEMPC0=5

.TEMPC1=8

<note>

<scale>

.OCTAVE=32

;

1

0

1

0

1

4

2

3

7

5

6

C3

D4

E4#

F5

G5#

A4

B4

A4#

1

;1st Melody

;

ORG

;

10H

1

0

1

0

1

2

3

7

6

5

7

3

C3#

$45

$E3

$97

C6

A5#

$42

1

;2nd Melody

Attack field Note field Scale field End bit field Comment field

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-99

APPENDIX E: THE FORMAT OF MELODY SOURCE FILE

Th e statem en t is m ade u p of th e five fields: attack field, n ote

field, scale field, en d bit field, an d com m en t field. Up to 80

ch aracters can be written in th e statem en t. Th e fields are

separated by on e or m ore spaces or by in sertin g tabs.

Th e en d bit fields an d com m en t fields can be filled in on an

as-n eeded basis.

A blan k lin e is also perm itted for th e CR (carriage retu rn )

code on ly. However, it is n ot perm itted on th e last lin e. Each

of th e fields can be started from an y colu m n .

Con trol of th e attack ou tpu t is written .

Wh en "1" is written , attack ou tpu t is perform ed. Wh en "0"

is written , attack ou tpu t is n ot perform ed.

Atta c k fie ld

Note fie ld

Eigh t n otes can be specified with th e m elody ROM codes D5

th rou gh D7. Fill in th e n ote field with n u m bers from 1 to 8.

No.

1

2

3

4

5

6

7

8

Note

Th e scale field can be filled in with an y scale data (C3

th rou gh C6#).

Sc a le fie ld

Wh en in pu ttin g th e code directly, prefix th e code with "$". In

th is case, th e in pu t code ran ge is 00H th rou gh FDH.

Th e in stru ction in dicatin g th e en d of th e m elody is written

in th e en d bit field. Wh en "1" is written , th e m elody fin ish es

with th e m elody ROM code of th at address. Oth erwise, write

"0", or om it it altogeth er.

End b it fie ld

Com m e nt fie ld

An y com m en t, su ch as th e program in dex or processin g

details, can be written in th e com m en t field, with n o affect

on th e object file created with th e assem bler.

Th e com m en t field is th e area between th e sem icolon ";" an d

th e CR code at th e en d of th e lin e.

A lin e can be m ade u p of a com m en t field alon e. However, if

th e com m en t exten ds in to two or m ore lin es, each lin e m u st

be h eaded with a sem icolon .

II-100

EPSON

S1C62N81 TECHNICAL SOFTWARE

APPENDIX F: DIVIDING TABLE

APPENDIX

F

Divid ing Ta b le

Dividing table at no use of octave 32.768 kHz

Scale ROM Code

S7 S6 S5 S4 S3 S2 S1 S0 Hex.

Dividing

Ratio

Absolute

Error (%) Frequency (Hz)

Standard

Scale Frequency

Data

(Hz)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

04 1/128 x 1/2

12 1/121 x 1/2

20 1/114 x 1/2

0

-0.152

0.031

0.024

0.092

-0.113

0.010

-0.030

0.167

0.143

-0.226

-0.287

0

-0.153

0.031

-0.339

-0.400

-0.113

-0.542

0.503

-0.453

0.144

-0.226

-0.287

0

0.675

0.031

-0.339

-0.400

-0.113

0.563

-0.668

0.787

0.144

-0.226

-0.287

0

128

C3

C3#

D3

D3#

E3

F3

F3#

G3

G3#

A3

A3#

B3

C4

C4#

D4

D4#

E4

F4

F4#

G4

G4#

A4

A4#

B4

C5

C5#

D5

128

135.611

143.675

152.218

161.270

170.860

181.019

191.783

203.187

215.270

228.070

241.632

256

271.222

287.350

304.436

322.540

341.720

362.038

383.566

406.374

430.540

456.140

483.264

512

542.444

574.700

608.872

645.080

683.440

724.076

767.132

812.748

861.080

912.280

966.528

1024

135.405

143.719

152.409

161.419

170.667

181.039

191.626

203.528

215.579

227.556

240.941

256

270.810

287.439

303.407

321.255

341.333

360.088

385.506

404.543

431.158

455.111

481.882

512

546.133

574.877

606.815

642.510

682.667

728.178

762.047

819.200

862.316

910.222

963.765

1024

1 2F 1/107 + 103

1 3B 1/101 + 102

0

1

44 1/96 x 1/2

51 1/90 + 91

1 5B 1/85 + 86

65 1/80 + 81

0 6C 1/76 x 1/2

74 1/72 x 1/2

0 7C 1/68 x 1/2

84 1/64 x 1/2

1 8D 1/60 + 61

1

0

92 1/57 x 1/2

98 1/54 x 1/2

0 9E 1/51 x 1/2

0 A4 1/48 x 1/2

1 AB 1/45 + 46

1 B1 1/42 + 43

1 B5 1/40 + 41

0 B8 1/38 x 1/2

0 BC 1/36 x 1/2

0 C0 1/34 x 1/2

0 C4 1/32 x 1/2

0 C8 1/30 x 1/2

1 CD 1/28 + 29

0 CE 1/27 x 1/2

1 D3 1/25 + 26

0 D4 1/24 x 1/2

1 D9 1/22 + 23

1 DB 1/21 + 22

0 DC 1/20 x 1/2

0 DE 1/19 x 1/2

0 E0 1/18 x 1/2

0 E2 1/17 x 1/2

0 E4 1/16 x 1/2

0 E6 1/15 x 1/2

D5#

E5

F5

F5#

G5

G5#

A5

A5#

B5

C6

0.675

1084.888

C6#

1092.267

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-101

APPENDIX F: DIVIDING TABLE

Dividing table at no use of octave 65.536 kHz

Scale ROM Code

S7 S6 S5 S4 S3 S2 S1 S0 Hex.

Dividing

Ratio

Absolute

Error (%) Frequency (Hz)

Standard

Scale Frequency

Data

(Hz)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

04 1/128 x 1/2

12 1/121 x 1/2

20 1/114 x 1/2

2F 1/107 + 103

0

-0.152

0.031

2.448

0.092

-0.113

0.011

-0.082

0.168

0.143

-0.226

-0.287

0

-0.152

0.031

-0.339

-0.400

-0.113

-0.541

0.503

-0.453

0.143

-0.226

-0.287

0

0.676

0.031

-0.339

-0.399

-0.113

0.563

-0.667

0.788

0.143

-0.226

-0.287

0

256

C4

C4#

D4

D4#

E4

F4

F4#

G4

G4#

A4

A4#

B4

C5

C5#

D5

D5#

E5

F5

F5#

G5

G5#

A5

A5#

B5

C6

C6#

D6

256

271.222

287.350

304.436

322.540

341.720

362.038

383.566

406.374

430.540

456.140

483.264

512

542.444

574.700

608.872

645.080

683.440

724.076

767.132

812.748

861.080

912.280

966.528

1024

1084.888

1149.400

1217.748

1290.160

1366.880

1448.152

1534.264

1625.496

1722.160

1824.560

1933.056

2048

270.810

287.439

304.819

322.837

341.333

362.077

383.251

407.056

431.158

455.111

481.882

512

541.620

574.877

606.815

642.510

682.667

720.176

771.012

809.086

862.316

910.222

963.765

1024

1092.267

1149.754

1213.630

1285.020

1365.333

1456.356

1524.093

1638.400

1724.632

1820.444

1927.529

2048

1 3B 1/101 + 102

0

1

44 1/96 x 1/2

51 1/90 + 91

1 5B 1/85 + 86

65 1/80 + 81

0 6C 1/76 x 1/2

74 1/72 x 1/2

0 7C 1/68 x 1/2

84 1/64 x 1/2

1 8D 1/60 + 61

1

0

92 1/57 x 1/2

98 1/54 x 1/2

0 9E 1/51 x 1/2

0 A4 1/48 x 1/2

1 AB 1/45 + 46

1 B1 1/42 + 43

1 B5 1/40 + 41

0 B8 1/38 x 1/2

0 BC 1/36 x 1/2

0 C0 1/34 x 1/2

0 C4 1/32 x 1/2

0 C8 1/30 x 1/2

1 CD 1/28 + 29

0 CE 1/27 x 1/2

1 D3 1/25 + 26

0 D4 1/24 x 1/2

1 D9 1/22 + 23

1 DB 1/21 + 22

0 DC 1/20 x 1/2

0 DE 1/19 x 1/2

0 E0 1/18 x 1/2

0 E2 1/17 x 1/2

0 E4 1/16 x 1/2

0 E6 1/15 x 1/2

D6#

E6

F6

F6#

G6

G6#

A6

A6#

B6

C7

0.676

2169.776

C7#

2194.533

II-102

EPSON

S1C62N81 TECHNICAL SOFTWARE

APPENDIX G: RAM MAP

APPENDIX

G

RAM Ma p

S1C62N81 TECHNICAL SOFTWARE

EPSON

II-103

APPENDIX G: RAM MAP

II-104

EPSON

S1C62N81 TECHNICAL SOFTWARE

International Sales Operations

AMERICA

ASIA

EPSON ELECTRONICS AMERICA, INC.

EPSON (CHINA) CO., LTD.

28F, Beijing Silver Tower 2# North RD DongSanHuan

ChaoYang District, Beijing, CHINA

- HEADQUARTERS -

150 River Oaks Parkway

San Jose, CA 95134, U.S.A.

Phone: 64106655

Fax: 64107319

Phone: +1-408-922-0200

Fax: +1-408-922-0238

SHANGHAI BRANCH

4F, Bldg., 27, No. 69, Gui Jing Road

Caohejing, Shanghai, CHINA

- SALES OFFICES -

West

Phone: 21-6485-5552

Fax: 21-6485-0775

1960 E. Grand Avenue

EPSON HONG KONG LTD.

20/F., Harbour Centre, 25 Harbour Road

Wanchai, Hong Kong

EI Segundo, CA 90245, U.S.A.

Phone: +1-310-955-5300

Fax: +1-310-955-5400

Central

Phone: +852-2585-4600 Fax: +852-2827-4346

Telex: 65542 EPSCO HX

101 Virginia Street, Suite 290

Crystal Lake, IL 60014, U.S.A.

Phone: +1-815-455-7630

Fax: +1-815-455-7633

EPSON TAIWAN TECHNOLOGY & TRADING LTD.

10F, No. 287, Nanking East Road, Sec. 3

Taipei

Northeast

301 Edgewater Place, Suite 120

Phone: 02-2717-7360

Fax: 02-2712-9164

Wakefield, MA 01880, U.S.A.

Telex: 24444 EPSONTB

Phone: +1-781-246-3600

Fax: +1-781-246-5443

HSINCHU OFFICE

13F-3, No. 295, Kuang-Fu Road, Sec. 2

HsinChu 300

Southeast

3010 Royal Blvd. South, Suite 170

Alpharetta, GA 30005, U.S.A.

Phone: +1-877-EEA-0020 Fax: +1-770-777-2637

Phone: 03-573-9900

Fax: 03-573-9169

EPSON SINGAPORE PTE., LTD.

No. 1 Temasek Avenue, #36-00

EUROPE

Millenia Tower, SINGAPORE 039192

Phone: +65-337-7911

Fax: +65-334-2716

EPSON EUROPE ELECTRONICS GmbH

SEIKO EPSON CORPORATION KOREA OFFICE

50F, KLI 63 Bldg., 60 Yoido-dong

Youngdeungpo-Ku, Seoul, 150-763, KOREA

- HEADQUARTERS -

Riesstrasse 15

80992 Munich, GERMANY

Phone: 02-784-6027

Fax: 02-767-3677

Phone: +49-(0)89-14005-0

Fax: +49-(0)89-14005-110

SALES OFFICE

Altstadtstrasse 176

51379 Leverkusen, GERMANY

Phone: +49-(0)2171-5045-0

SEIKO EPSON CORPORATION

ELECTRONIC DEVICES MARKETING DIVISION

Fax: +49-(0)2171-5045-10

Electronic Device Marketing Department

IC Marketing & Engineering Group

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

UK BRANCH OFFICE

Unit 2.4, Doncastle House, Doncastle Road

Bracknell, Berkshire RG12 8PE, ENGLAND

Phone: +81-(0)42-587-5816

Fax: +81-(0)42-587-5624

Phone: +44-(0)1344-381700

Fax: +44-(0)1344-381701

ED International Marketing Department Europe & U.S.A.

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

FRENCH BRANCH OFFICE

1 Avenue de l' Atlantique, LP 915 Les Conquerants

Phone: +81-(0)42-587-5812

Fax: +81-(0)42-587-5564

Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE

ED International Marketing Department Asia

Phone: +33-(0)1-64862350

Fax: +33-(0)1-64862355

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

Phone: +81-(0)42-587-5814

Fax: +81-(0)42-587-5110

BARCELONA BRANCH OFFICE

Barcelona Design Center

Edificio Prima Sant Cugat

Avda. Alcalde Barrils num. 64-68

E-08190 Sant Cugat del Vallès, SPAIN

Phone: +34-93-544-2490

Fax: +34-93-544-2491

In pursuit of “Saving”Technology, Epson electronic devices.

Our lineup of semiconductors, liquid crystal displays and quartz devices

assists in creating the products of our customers’ dreams.

Epson IS energy savings.

S1C62N81

Technical Manual

ELECTRONIC DEVICES MARKETING DIVISION

EPSON Electronic Devices Website

http://www.epson.co.jp/device/

First issue March, 1990

M

Printed March, 2001 in Japan

B


型号：	S1C62N81F
厂家：	SEIKO EPSON CORPORATION
描述：	4-BIT, MROM, 0.032MHz, MICROCONTROLLER, PQFP64, PLASTIC, QFP6-64 时钟微控制器外围集成电路
文件：	总257页 (文件大小：1519K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S1C62N81F [SEIKO]

相关型号：

S1C62N82D

S1C62N82F

S1C63004

S1C63008

S1C63016

S1C63158

S1C63158B0A010A

S1C63158D0A0100

S1C63158D0A010D

S1C63158D0A010L

S1C63158D0A010Q

S1C63158D0A0199