S1C6S3L7D_技术文档

CHAPTER 1: INTRODUCTION

CHAPTER 1

INTRODUCTION

Each m em ber of th e S1C6S3N7 Series of sin gle ch ip m icro-

com pu ters featu re a 4-bit S1C6200A core CPU, 1,024 words

of ROM (12 bits per word), 80 words of RAM (4 bits per

word), an LCD driver, 4 bits for in pu t ports (K00–K03), 4

bits for ou tpu t ports (R00–R03), on e 4-bit I/ O port (P00–

P03) an d two tim er (clock tim er an d stopwatch tim er).

Becau se of th eir low voltage operation an d low power con -

su m ption , th e S1C6S3N7 Series are ideal for a wide ran ge of

application s.

1.1 Config ura tion

Th e S1C6S3N7 Series are con figu red as follows, depen din g

on th e su pply voltage.

Table 1.1.1

Model

Supply Voltage Supply Voltage Range Oscillation Circuits

Configuration of the

S1C6S3N7 Series

S1C6S3N7

S1C6S3L7

S1C6S3B7

3.0 V

1.5 V

3.0 V

1.8–3.6 V

0.9–2.0 V

0.9–3.6 V

Crystal or CR

S1C6S3N7 TECHNICAL HARDWARE

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CHAPTER 1: INTRODUCTION

1.2 Fe a ture s

Built-in oscillation circuit

Instruction set

Crystal or CR oscillation circu it, 32.768 kHz (typ.)

100 in stru ction s

ROM capacity

1,024 words ×12 bits

RAM capacity (data RAM) 80 words × 4 bits

Input port

4 bits (Su pplem en tary pu ll-down resistors m ay be u sed )

Output port

4 bits (Piezo bu zzer an d program m able frequ en cy ou tpu t

can be driven directry by m ask option )

Input/output port

LCD driver

Timer

4 bits

26 segm en ts × 4, 3 or 2 com m on du ty

2 system s: clock tim er/ stopwatch tim er

Supply voltage detection

circuit (SVD)

1.2 V / 2.4 V

Interrupts:

External interrupt In pu t port in terru pt

Internal interrupt Tim er in terru pt

1 system

2 system s

Supply voltage

1.5 V (0.9–2.0 V)

3.0 V (1.8–3.6 V)

3.0 V (0.9–3.6 V)

S1C6S3L7

S1C6S3N7

S1C6S3B7

Current consumption (typ.) 1.0 µA (Crystal oscillation CLK = 32.768 kHz, wh en h alted)

2.5 µA (Crystal oscillation CLK = 32.768 kHz, wh en execu tin g)

Supply form

QFP6-60pin (plastic) or ch ip

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S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 1: INTRODUCTION

1.3 Bloc k Dia g ra m

System

Reset

Control

ROM

1,024x12

OSC

Core CPU S1C6200A

RAM

80x4

Interrupt

Generator

COM0

|

COM3

SEG0

|

K00~K03

TEST

LCD

Driver

I Port

Test Port

SEG25

VDD

VL1

|

P00~P03

R00~R03

I/O Port

O Port

VL3

Power

Controller

CA

CB

VS1

VSS

SVD

Timer

(FOUT/BUZZER)

(BUZZER)

FOUT

&

BUZZER

Stop

Watch

Fig. 1.3.1

Block diagram

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CHAPTER 1: INTRODUCTION

1.4 Pin La yout Dia g ra m

QFP6-60pin

45

31

46

30

Index

60

16

1

15

Pin No

Pin Name

OSC1

OSC2

N.C.

Pin No

Pin Name

COM2

COM3

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

Pin No

31

Pin Name

Pin No

46

Pin Name

P01

1

2

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

TEST

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

P00

32

47

P02

3

33

48

P03

4

VS1

34

49

RESET

K00

5

N.C.

CA

35

50

6

36

51

K01

7

CB

37

52

K02

8

N.C.

38

53

K03

9

39

54

R00

10

11

12

13

14

15

40

55

R01

V

L1

L2

L3

41

56

R02

V

42

57

R03

V

43

58

N.C.

COM0

COM1

44

59

VSS

45

60

VDD

Fig. 1.4.1

N.C. = No Connection

Pin assignment

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S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 1: INTRODUCTION

1.5 Pin De sc rip tion

Table 1.5.1 Pin description

Terminal Name Pin No. Input/Output

Function

VDD

VSS

VS1

60

59

4

(I)

O

Power source (+) terminal

Power source (-) terminal

Oscillation and internal logic system regulated

voltage output terminal

V

L1

L2

L3

11

12

13

O

LCD system regulated voltage output terminal (approx. -1.05 V)

/ LCD system reducer output terminal (VL2 × 1/2)

LCD system booster output terminal (VL1 × 2)

/ LCD system booster output terminal (approx. -2.10 V)

LCD system booster output terminal (VL1 × 3)

/ LCD system booster output terminal (VL2 × 3/2)

Booster capacitor connecting terminal

Crystal or CR oscillation input terminal

Crystal or CR oscillation output terminal

Input terminal

CA–CB

OSC1

6, 7

1

–

I

OSC2

2

O

I

K00–K03

P00–P03

R00–R03

SEG0–25

50–53

45–48

54–57

18–30

32–44

14–17

49

I/O

O

I/O terminal

Output terminal

LCD segment output terminal

(convertible to DC output terminal by mask option)

LCD common output terminal

COM0–3

RESET

TEST

O

I

Initial setting input terminal

31

I

Test input terminal

S1C6S3N7 TECHNICAL HARDWARE

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CHAPTER 2: POWER SUPPLY AND INITIAL RESET

CHAPTER 2

POWER SUPPLY AND INITIAL RESET

2.1 Powe r Sup p ly

With a sin gle extern al power su pply (*1) su pplied to VDD

th rou gh VSS, th e S1C6S3N7 Series gen erate th e n ecessary

in tern al voltages with th e regu lated voltage circu it (<VS1> for

oscillators an d in tern al circu it, <VL1 or VL2> for LCDs) an d

th e voltage booster/ redu cer (<VL2, VL3 or VL1, VL3> for

LCDs).

Th e S1C6S3N7 gen erates <VL2> with th e regu lated voltage

circu it an d <VL1, VL3> with th e voltage booster/ redu cer. Th e

S1C6S3L7 an d th e S1C6S3B7 gen erate <VL1> with th e

regu lated voltage circu it an d <VL2, VL3> with th e voltage

booster. Th e voltage <VS1> for th e in tern al circu it th at is

gen erated by th e regu lated voltage circu it is -1.2 V (VDD

stan dard).

Figu re 2.1.1 sh ows th e power su pply con figu ration of th e

S1C6S3N7. Figu re 2.1.2 sh ows th e power su pply con figu ra-

tion of th e S1C6S3L7 an d th e S1C6S3B7.

*1 Su pply voltage: S1C6S3N7, S1C6S3B7...3 V

S1C6S3L7...1.5 V

Note - External loads cannot be driven by the output voltage of the

regulated voltage circuit and the voltage booster/reducer.

-

See Chapter 6, "ELECTRICAL CHARACTERISTICS", for

voltage values.

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S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

V

DD

S1

Internal

circuit

VS1

Internal system

regulated voltage

circuit

C5

V

Oscillation

circuit

OSC1, 2

LCD system

regulated voltage

circuit

C3

VL2

V

L2

V

L2

C

2

4

V

CA

CB

L1

L3

LCD system

voltage

booster/reducer

COM0–3

SEG0–25

LCD driver

circuit

V

L1

L3

External

power

supply

C1

VSS

Fig. 2.1.1 Configuration of S1C6S3N7 power supply system

(when LCD system regulated voltage circuit is used)

V

DD

S1

Internal

circuit

VS1

Internal system

regulated voltage

circuit

C5

V

Oscillation

circuit

OSC1, 2

LCD system

regulated voltage

circuit

C2

VL1

V

L1

V

L1

C

3

4

V

CA

CB

L2

L3

COM0–3

SEG0–25

LCD driver

circuit

V

L2

L3

LCD system

voltage booster

External

power

supply

C1

VSS

Fig. 2.1.2 Configuration of S1C6S3L7/S1C6S3B7 power supply system

(when LCD system regulated voltage circuit is used)

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CHAPTER 2: POWER SUPPLY AND INITIAL RESET

Th e LCD system regu lated voltage circu it u se can be proh ib-

ited by settin g th e m ask option . In th is case, extern al ele-

m en ts can be m in im ized becau se th e extern al capacitors for

th e LCD system regu lated voltage circu it are n ot n ecessary.

However wh en th e LCD system regu lated voltage circu it is

n ot u sed, th e display qu ality of th e LCD pan el, wh en th e

su pply voltage flu ctu ates (drops), is in ferior to wh en th e LCD

system regu lated voltage circu it is u sed. Th e S1C6S3B7

always u ses th e th e LCD system regu lated voltage circu it,

th erefore th e extern al capacitors are requ ired.

Figu re 2.1.3 sh ows th e extern al elem en ts wh en th e th e LCD

system regu lated voltage circu it is n ot u sed.

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S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

• S1C6S3N7

4.5 V LCD panel

1/4, 1/3, 1/2 duty, 1/3 bias

V

CA

DD

S1

C

5

2

L1

L2

L3

C

4

1

C

3 V

CB

V

SS

Note: VL2 is shorted to VSS inside the IC.

3 V LCD panel

1/4, 1/3, 1/2 duty, 1/3 bias

1/4, 1/3, 1/2 duty, 1/2 bias

V

DD

S1

V

DD

S1

C5

C2

C3

C

5

2

L1

L2

L3

L1

L2

L3

V

CA

C1

3 V

C1

3 V

CB

V

SS

VSS

Note: VL3 is shorted to VSS inside the IC.

• S1C6S3L7

4.5 V LCD panel

3 V LCD panel

1/4, 1/3, 1/2 duty, 1/2 bias

1/4, 1/3, 1/2 duty, 1/3 bias

V

DD

V

DD

C5

S1

V

L1

L2

L3

V

L1

L2

L3

C

3

4

C4

CA

C1

1.5 V

C1

CB

VSS

Note: VL1 is shorted to VSS inside the IC.

Fig. 2.1.3 External elements when LCD system regulated voltage circuit is not used

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CHAPTER 2: POWER SUPPLY AND INITIAL RESET

2.2 Initia l Re se t

To in itialize th e S1C6S3N7 Series circu its, an in itial reset

m u st be execu ted. Th ere are th ree ways of doin g th is.

(1) In itial reset by th e oscillation detection circu it (Note)

(2) Extern al in itial reset via th e RESET pin

(3) Extern al in itial reset by sim u ltan eou s h igh in pu t to pin s

K00–K03 (depen din g on m ask option )

Figu re 2.2.1 sh ows th e con figu ration of th e in itial reset

circu it.

OSC1

Oscillation

circuit

OSC2

Oscillation

detection

circuit

K00

K01

K02

K03

Noise

rejection

circuit

Vss

Initial

reset

Noise

rejection

circuit

Fig. 2.2.1

Configuration of

initial reset circuit

RESET

Vss

Note Be sure to use reset function (2) or (3) at power-on because the

initial reset function by the oscillation detection circuit (1) may not

operate normally depending on the power-on procedure.

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S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

Th e oscillation detection circu it ou tpu ts th e in itial reset

sign al at power-on u n til th e crystal oscillation circu it starts

oscillatin g, or wh en th e crystal oscillation circu it stops

oscillatin g for som e reason .

Osc illa tion d e te c tion

c irc uit

However, u se th e followin g reset fu n ction s at power-on

becau se th e in itial reset fu n ction by th e oscillation detection

circu it m ay n ot operate n orm ally depen din g on th e power-on

procedu re.

An in itial reset can be in voked extern ally by m akin g th e

reset pin h igh . Th is h igh level m u st be m ain tain ed for at

least 5 m s (wh en oscillatin g frequ en cy, fosc = 32 kHz),

becau se th e in itial reset circu it con tain s a n oise rejection

circu it. Wh en th e reset pin goes low th e CPU begin s to

operate.

Re se t p in (RESET)

An oth er way of in vokin g an in itial reset extern ally is to in pu t

a h igh sign al sim u ltan eou sly to th e in pu t ports (K00–K03)

selected with th e m ask option . Th e specified in pu t port pin s

m u st be kept h igh for at least 4 sec (wh en oscillatin g fre-

qu en cy fosc = 32 kHz), becau se of th e n oise rejection circu it.

Table 2.2.1 sh ows th e com bin ation s of in pu t ports (K00–

K03) th at can be selected with th e m ask option .

Sim ulta ne ous hig h

inp ut to inp ut p orts

(K00–K03)

Table 2.2.1

A

B

C

D

Not used

Input port combinations

K00*K01

K00*K01*K02

K00*K01*K02*K03

Wh en , for in stan ce, m ask option D (K00*K01*K02*K03) is

selected, an in itial reset is execu ted wh en th e sign als in pu t

to th e fou r ports K00–K03 are all h igh at th e sam e tim e.

If you u se th is fu n ction , m ake su re th at th e specified ports

do n ot go h igh at th e sam e tim e du rin g n orm al operation .

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CHAPTER 2: POWER SUPPLY AND INITIAL RESET

An in itial reset in itializes th e CPU as sh own in th e table

below.

Inte rna l re g iste r fol-

lowing initia liza tion

Table 2.2.2

Initial values

CPU Core

Name

Signal

PCS

PCP

NPP

SP

X

Number of Bits

Setting Value

00H

Program counter step

Program counter page

New page pointer

Stack pointer

8

4

8

4

1

1H

Undefined

0

Index register X

Index register Y

Register pointer

General register A

General register B

Interrupt flag

Y

RP

A

B

I

Decimal flag

D

0

Zero flag

Z

Undefined

Carry flag

C

Peripheral Circuits

Name

RAM

Number of Bits

Setting Value

Undefined

*1

80 × 4

26 × 4

–

Display memory

Other peripheral circuit

*1: See section 4.1, "Mem ory Map"

2.3 Te st Pin (TEST)

Th is pin is u sed wh en IC is in spected for sh ipm en t.

Du rin g n orm al operation con n ect it to VSS.

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S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 3: CPU, ROM, RAM

CHAPTER 3

CPU, ROM, RAM

3.1 CPU

Th e S1C6S3N7 Series em ploys th e S1C6200A core CPU, so

th at register con figu ration , in stru ction s, an d so forth are

virtu ally iden tical to th ose in oth er processors in th e fam ily

u sin g th e S1C6200A. Refer to th e "S1C6200/ 6200A Core

CPU Man u al" for details of th e S1C6200A.

Note th e followin g poin ts with regard to th e S1C6S3N7

Series:

(1) Th e SLEEP operation is n ot provided, so th e SLP in stru c-

tion can n ot be u sed.

(2) Becau se th e ROM capacity is 1,024 words, 12 bits per

word, ban k bits are u n n ecessary, an d PCB an d NBP are

n ot u sed.

(3) Th e RAM page is set to 0 on ly, so th e page part (XP, YP)

of th e in dex register th at specifies addresses is in valid.

PUSH XP

PUSH YP

POP

LD

XP

POP

LD

YP

XP,r

r,XP

YP,r

r,YP

LD

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CHAPTER 3: CPU, ROM, RAM

3.2 ROM

Th e bu ilt-in ROM, a m ask ROM for th e program , h as a

capacity of 1,024 × 12-bit steps. Th e program area is 4

pages (0–3), each con sistin g of 256 steps (00H–FFH). After

an in itial reset, th e program start address is page 1, step

00H. Th e in terru pt vector is allocated to page l, steps 01H–

07H.

Bank 0

00H step

01H step

Program start address

Interrupt vector area

0 page

1 page

2 page

3 page

07H step

08H step

Program area

FFH step

12 bits

Fig. 3.2.1

ROM configuration

RAM

3.3

Th e RAM, a data m em ory for storin g a variety of data, h as a

capacity of 80 words, 4-bit words. Wh en program m in g,

keep th e followin g poin ts in m in d:

(1) Part of th e data m em ory is u sed as stack area wh en

savin g su brou tin e retu rn addresses an d registers, so be

carefu l n ot to overlap th e data area an d stack area.

(2) Su brou tin e calls an d in terru pts take u p th ree words on

th e stack.

(3) Data m em ory 000H–00FH is th e m em ory area poin ted by

th e register poin ter (RP).

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S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

CHAPTER 4

PERIPHERAL CIRCUITS

AND OPERATION

Periph eral circu its (tim er, I/ O, an d so on ) of th e S1C6S3N7

Series are m em ory m apped. Th u s, all th e periph eral circu its

can be con trolled by u sin g m em ory operation s to access th e

I/ O m em ory. Th e followin g section s describe h ow th e pe-

riph eral circu its operate.

4.1 Me m ory Ma p

Th e data m em ory of th e S1C6S3N7 Series h as an address

space of 154 words, of wh ich 32 words are allocated to

display m em ory an d 26 words, to I/ O m em ory. Figu re 4.1.1

sh ow th e overall m em ory m ap for th e S1C6S3N7 Series, an d

Tables 4.1.1(a)–(e), th e m em ory m aps for th e periph eral

circu its (I/ O space).

Address

Page

Low

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

High

0

M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF

1

2

RAM area (000H–04FH)

80 words x 4 bits (R/W)

3

4

5

6

7

0

8

9

Display memory area (090H–0AFH)

32 words x 4 bits (Write only)

A

B

C

D

E

F

I/O memory area Tables 4.1.1(a)–(e)

Fig. 4.1.1

Memory map

Unused area

Note Memory is not mounted in unused area within the memory map

and in memory area not indicated in this chapter. For this reason,

normal operation cannot be assured for programs that have been

prepared with access to these areas.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1(a) I/O memory map

Register

Address

Comment

*1

*2

D3

D2

D1

D0

Name

K03

SR

1

0

High

Low

K03

K02

K01

K00

–

*2

High

Low

R

K02

K01

–

0E0H

0E2H

Input port (K00–K03)

K00

–

SWL3

SWH3

TM3

SWL2

SWH2

TM2

SWL1

SWH1

TM1

SWL0

SWH0

TM0

SWL3

0

MSB

SWL2

SWL1

SWL0

SWH3

SWH2

SWH1

SWH0

TM3

0

–

Stopwatch timer

1/100 sec (BCD)

LSB

MSB

Stopwatch timer

1/10 sec (BCD)

0E3H

LSB

High

Low

Timer data (clock timer 2 Hz)

Timer data (clock timer 4 Hz)

Timer data (clock timer 8 Hz)

Timer data (clock timer 16 Hz)

R

TM2

0E4H

TM1

TM0

* 1

* 2

* 3

* 4

* 5

* 6

In itial valu e followin g in itial reset

Not set in th e circu it

Un defin ed

Reset (0) im m ediately after bein g read

Con stan tly 0 wh en bein g read

Refer to m ain m an u al

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S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1(b) I/O memory map

Register

Address

Comment

*1

D3

D2

D1

D0

Name

EIK03

SR

0

1

0

Enable

Mask

EIK03

EIK02

EIK01

EIK00

Interrupt mask register (K03)

Interrupt mask register (K02)

Interrupt mask register (K01)

Interrupt mask register (K00)

Enable

Mask

R/W

EIK02

EIK01

EIK00

0

0E8H

0EAH

0EBH

0EDH

*5

0

EIT2

0

EISW1

EISW0

EIT32

IK0

0

*5

0

R

R/W

EISW1

EISW0

0

Enable

Mask

Interrupt mask register (stopwatch 1 Hz)

Interrupt mask register (stopwatch 10 Hz)

*5

0

EIT8

R/W

0

R

EIT2

EIT8

0

Enable

Mask

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

EIT32

*5

0

*5

*4

R

0

IK0

0

Yes

No

Interrupt factor flag (K00–K03)

* 1

* 2

* 3

* 4

* 5

* 6

In itial valu e followin g in itial reset

Not set in th e circu it

Un defin ed

Reset (0) im m ediately after bein g read

Con stan tly 0 wh en bein g read

Refer to m ain m an u al

S1C6S3N7 TECHNICAL HARDWARE

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1(c) I/O memory map

Register

Address

Comment

*1

D3

D2

D1

D0

Name

SR

1

0

*5

0

ISW1

ISW0

0

*5

*4

R

0EEH

ISW1

0

Yes

No

Interrupt factor flag (stopwatch 1 Hz)

Interrupt factor flag (stopwatch 10 Hz)

*4

ISW0

*5

0

IT2

R02

P02

IT8

IT32

0

*4

R

IT2

IT8

IT32

0

Yes

No

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

0EFH

R01

R00

R03

R02

R01

0

High

ON

Low

OFF

Low

OFF

R03 output port data

R03

BUZZER

FOUT

R02 output port data

R/W

R01 output port data

0F3H

0F6H

BUZZER

R00

Buzzer ON/OFF control register

R00 output port data

High

ON

FOUT

Frequency output ON/OFF control register

*2

P03

P02

P01

P00

High

Low

P03

P01

P00

R/W

I/O port (P00–P03)

0

* 1

In itial valu e followin g in itial reset

Not set in th e circu it

Un defin ed

* 2

* 3

* 4

* 5

* 6

Reset (0) im m ediately after bein g read

Con stan tly 0 wh en bein g read

Refer to m ain m an u al

I-18

EPSON

S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1(d) I/O memory map

Register

Address

Comment

*1

D3

D2

D1

D0

Name

SR

1

0

*5

0

TMRST SWRUN SWRST

0

TMRST

SWRUN

Reset

0

Reset

Run

–

Stop

–

Clock timer reset

R

W

R/W

W

0F9H

Stopwatch timer RUN/STOP

Stopwatch timer reset

*5

SWRST

Reset

0

HLMOD

R/W

0

SVDDT SVDON

R/W

HLMOD

Heavy

load

Normal

load

Heavy load protection mode register

*5

R

0

0FAH

0FBH

0FCH

Supply

voltage

low

Supply

voltage

normal

SVDDT

SVDON

CSDC

0

Supply voltage detection data

ON

OFF

Supply voltage detection ON/OFF

Static

Dynamic LCD drive switch

CSDC

R/W

0

*5

R

0

*5

0

IOC

R/W

0

R

IOC

0

Output

Input

I/O port P00–P03 Input/Output

* 1

In itial valu e followin g in itial reset

Not set in th e circu it

Un defin ed

* 2

* 3

* 4

* 5

* 6

Reset (0) im m ediately after bein g read

Con stan tly 0 wh en bein g read

Refer to m ain m an u al

S1C6S3N7 TECHNICAL HARDWARE

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I-19

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1(e) I/O memory map

Register

Address

Comment

Buzzer frequency control

*1

D3

D2

D1

D0

Name

XBZR

SR

0

1

0

XBZR

0

XFOUT1 XFOUT0

R/W

2 kHz

4 kHz

*5

0

R/W

R

0FDH

XFOUT1

XFOUT0

0

High

Low

FOUT frequency control:

XFOUT1(0), XFOUT0(0) -> F1

XFOUT1(0), XFOUT0(1) -> F2

XFOUT1(1), XFOUT0(0) -> F3

XFOUT1(1), XFOUT0(1) -> F4

* 1

* 2

* 3

* 4

* 5

* 6

In itial valu e followin g in itial reset

Not set in th e circu it

Un defin ed

Reset (0) im m ediately after bein g read

Con stan tly 0 wh en bein g read

Refer to m ain m an u al

I-20

EPSON

S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

4.2 Osc illa tion Circ uit

Th e S1C6S3N7 Series h ave a bu ilt-in crystal oscillation

circu it. Th is circu it gen erates th e operatin g clock for th e

CPU an d periph eral circu it on con n ection to an extern al

crystal oscillator (typ. 32.768 kHz) an d trim m er capacitor

(5–25 pF).

Crysta l osc illa tion

c irc uit

Figu re 4.2.1 is th e block diagram of th e crystal oscillation

circu it.

V

DD

CG

OSC1

OSC2

To CPU and

peripheral circuits

V

DD

CD

Fig. 4.2.1

Crystal oscillation circuit

The S1C6S3N7 Series

As Figu re 4.2.1 in dicates, th e crystal oscillation circu it can

be con figu red sim ply by con n ectin g th e crystal oscillator

(X'tal) between th e OSC1 an d OSC2 pin s an d th e trim m er

capacitor (CG) between th e OSC1 an d VDD pin s.

Note

The OSC1 and OSC2 terminals on the board should be shielded

with the VDD (+ side).

S1C6S3N7 TECHNICAL HARDWARE

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I-21

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

For th e S1C6S3N7 Series, CR oscillation circu it (typ. 65

CR osc illa tion c irc uit

kHz) m ay also be selected by a m ask option . Figu re 4.2.2 is

th e block diagram of th e CR oscillation circu it.

OSC1

To CPU and

peripheral circuits

R

C

OSC2

Fig. 4.2.2

The S1C6S3N7 Series

CR oscillation circuit

As Figu re 4.2.2 in dicates, th e CR oscillation circu it can be

con figu red sim ply by con n ectin g th e register (R) between

pin s OSC1 an d OSC2 sin ce capacity (C) is bu ilt-in .

See Ch apter 6, "ELECTRICAL CHARACTERISTICS" for R

valu e.

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S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

4.3 Inp ut Ports (K00–K03)

Th e S1C6S3N7 Series h ave a 4-bit gen eral-pu rpose in pu t

port. Each of th e in pu t port pin s (K00–K03) h as an in tern al

pu ll-down resistan ce. Th e pu ll-down resistan ce can be

selected for each bit with th e m ask option .

Config ura tion of

inp ut p ort

Figu re 4.3.1 sh ows th e con figu ration of in pu t port.

V

DD

Interrupt

request

Kxx

Address

Fig. 4.3.1

V

SS

Configuration of input port

Mask option

Selectin g "pu ll-down resistan ce en abled" with th e m ask

option allows in pu t from a pu sh bu tton , key m atrix, an d so

forth . Wh en "pu ll-down resistan ce disabled" is selected, th e

port can be u sed for slide switch in pu t an d in terfacin g with

oth er LSIs.

All fou r in pu t port bits (K00–K03) provide th e in terru pt

fu n ction . Th e con dition s for issu in g an in terru pt can be set

by th e software for th e fou r bits. Also, wh eth er to m ask th e

in terru pt fu n ction can be selected in dividu ally for all fou r

bits by th e software. Figu re 4.3.2 sh ows th e con figu ration of

K00–K03.

Inte rrup t func tion

S1C6S3N7 TECHNICAL HARDWARE

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I-23

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

Kxx

One for each pin series

Address

Noise

rejector

Interrupt factor

flag (IK)

Interrupt

request

Address

Fig. 4.3.2

Mask option

(K00–K03)

Interrupt mask

register (EIK)

Input interrupt circuit

configuration

Address

(K00–K03)

Th e in terru pt m ask registers (EIK00–EIK03) en able th e

in terru pt m ask to be selected in dividu ally for K00–K03. An

in terru pt occu rs wh en th e in pu t valu e wh ich are n ot

m asked ch an ge an d th e in terru pt factor flag (IK0) is set to 1.

Input interrupt programing related precautions

Port K input

Active status

Mask register

➀

Factor flag set Not set

When the content of the mask register is rewritten, while

the port K input is in the active status. The input interrupt

factor flag is set at ➀.

Fig. 4.3.3

Input interrupt timing

Wh en u sin g an in pu t in terru pt, if you rewrite th e con ten t of

th e m ask register, wh en th e valu e of th e in pu t term in al

wh ich becom es th e in terru pt in pu t is in th e active statu s

(in pu t term in al = h igh statu s), th e factor flag for in pu t

in terru pt m ay be set.

For exam ple, a factor flag is set with th e tim in g of ➀ sh own

in Figu re 4.3.3. However, wh en clearin g th e con ten t of th e

m ask register with th e in pu t term in al kept in th e h igh

statu s an d th en settin g it, th e factor flag of th e in pu t in ter-

ru pt is again set at th e tim in g th at h as been set.

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EPSON

S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

Con sequ en tly, wh en th e in pu t term in al is in th e active

statu s (h igh statu s), do n ot rewrite th e m ask register (clear-

in g, th en settin g th e m ask register), so th at a factor flag will

on ly set at th e risin g edge in th is case. Wh en clearin g, th en

settin g th e m ask register, set th e m ask register, wh en th e

in pu t term in al is n ot in th e active statu s (low statu s).

Th e con ten ts th at can be selected with th e in pu t port m ask

option are as follows:

Ma sk op tion

(1) An in tern al pu ll-down resistan ce can be selected for each

of th e fou r bits of th e in pu t ports (K00–K03). Havin g

selected "pu ll-down resistan ce disabled", take care th at

th e in pu t does n ot float. Select "pu ll-down resistan ce

en abled" for in pu t ports th at are n ot bein g u sed.

(2) Th e in pu t in terru pt circu it con tain s a n oise rejection

circu it to preven t in terru pts form occu rrin g th rou gh

n oise. Th e m ask option en ables selection of th e n oise

rejection circu it for each separate pin series. Wh en "u se"

is selected, a m axim u m delay of 0.5 m s (fosc = 32 kHz)

occu rs from th e tim e an in terru pt con dition is establish ed

u n til th e in terru pt factor flag (IK) is set to 1.

S1C6S3N7 TECHNICAL HARDWARE

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I-25

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

Table 4.3.1 list th e in pu t port con trol bits an d th eir ad-

dresses.

Control of inp ut p ort

Table 4.3.1 Input port control bits

Register

Address

Comment

D3

D2

D1

D0

Name

K03

SR

1

0

High

Low

K03

K02

K01

K00

–

High

Low

R

K02

K01

K00

EIK03

EIK02

EIK01

EIK00

0

–

0

0E0H

0E8H

0EDH

Input port (K00–K03)

High

Low

Enable

Mask

EIK03

EIK02

EIK01

EIK00

Interrupt mask register (K03)

Interrupt mask register (K02)

Interrupt mask register (K01)

Interrupt mask register (K00)

R/W

0

IK0

0

R

0

IK0

0

Yes

No

Interrupt factor flag (K00–K03)

K00–K03 Input port data (0E0H)

Th e in pu t data of th e in pu t port pin s can be read with th ese

registers.

Wh en 1 is read: High level

Wh en 0 is read: Low level

Writin g:

In valid

Th e valu e read is 1 wh en th e pin voltage of th e fou r bits of

th e in pu t port (K00–K03) goes h igh (VDD), an d 0 wh en th e

voltage goes low (VSS). Th ese bits are readin g, so writin g

can n ot be don e.

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EPSON

S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

EIK00–EIK03 Interrupt mask registers (0E8H)

Maskin g th e in terru pt of th e in pu t port pin s can be don e

with th ese registers.

Wh en 1 is written : En able

Wh en 0 is written : Mask

Readin g:

Valid

With th ese registers, m askin g of th e in pu t port bits can be

don e for each of th e fou r bits. After an in itial reset, th ese

registers are all set to 0.

IK0 Interrupt factor flag (0EDH)

Th is flag in dicates th e occu rren ce of an in pu t in terru pt.

Wh en 1 is read: In terru pt h as occu rred

Wh en 0 is read: In terru pt h as n ot occu rred

Writin g:

In valid

Th e in terru pt factor flag IK0 is associated with K00–K03.

From th e statu s of th is flag, th e software can decide wh eth er

an in pu t in terru pt h as occu rred.

Th is flag is reset wh en th e software h as read it.

Readin g of in terru pt factor flag is available at EI, bu t be

carefu l in th e followin g cases.

If th e in terru pt m ask register valu e correspon din g to th e

in terru pt factor flag to be read is set to 1, an in terru pt

requ est will be gen erated by th e in terru pt factor flag set

tim in g, or an in terru pt requ est will n ot be gen erated.

After an in itial reset, th is flag is set to 0.

S1C6S3N7 TECHNICAL HARDWARE

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I-27

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

4.4 Outp ut Ports (R00–R03)

Th e S1C6S3N7 Series h ave a 4-bit gen eral ou tpu t port (R00–

Config ura tion of

outp ut p ort

R03).

Ou tpu t specification of th e ou tpu t port can be selected in a

bit u n it with th e m ask option . Two kin ds of ou tpu t specifi-

cation s are available: com plem en tary ou tpu t an d Pch open

drain ou tpu t. Also, th e m ask option en ables th e ou tpu t

ports R00 an d R01 to be u sed as special ou tpu t ports.

Figu re 4.4.1 sh ows th e con figu ration of th e ou tpu t port.

VDD

Register

Rxx

Complementary

Pch open drain

Address

VSS

Fig. 4.4.1

Configuration of output port

Mask option

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EPSON

S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

Th e m ask option en ables th e followin g ou tpu t port selection .

Ma sk op tion

(1) Output specification of output port

Th e ou tpu t specification s for th e ou tpu t port (R00–R03)

m ay be eith er com plem en tary ou tpu t or Pch open drain

ou tpu t for each of th e fou r bits. However, even wh en Pch

open drain ou tpu t is selected, a voltage exceedin g th e

sou rce voltage m u st n ot be applied to th e ou tpu t port.

(2) Special output

In addition to th e regu lar DC ou tpu t, special ou tpu t can

be selected for ou tpu t ports R00 an d R01, as sh own in

Table 4.4.1. Figu re 4.4.2 sh ows th e stru ctu re of ou tpu t

ports R00–R03.

Table 4.4.1

Pin Name

R00

When Special Output is Selected

Special output

FOUT or BUZZER

BUZZER

R01

Register

(R03)

R03

Register

(R02)

R02

R01

BUZZER

Register

(R01)

BUZZER

FOUT

Register

(R00)

R00

Fig. 4.4.2

Structure of output ports

R00–R03

Address

(0F3H)

Mask option

S1C6S3N7 TECHNICAL HARDWARE

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I-29

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

FOUT (R00) Wh en ou tpu t port R00 is set for FOUT ou tpu t, th is port will

gen erate fosc (CPU operatin g clock frequ en cy) or clock

frequ en cy divided in to fosc. Clock frequ en cy m ay be se-

lected in dividu ally for F1–F4, from am on g 5 types by m ask

option ; on e am on g F1–F4 is selected by software an d u sed.

Th e types of frequ en cy wh ich m ay be selected are sh own in

Table 4.4.2.

Table 4.4.2

Clock Frequency (Hz) fosc = 32.768 kHz

F2 F3 F4

(D1,D0)=(0,0) (D1,D0)=(0,1) (D1,D0)=(1,0) (D1,D0)=(1,1)

Mask

Option

Sets

FOUT clock frequency

F1

256

(fosc/128)

512

(fosc/64)

1,024

(fosc/32)

2,048

(fosc/16)

Set 1

Set 2

Set 3

Set 4

Set 5

4,096

(fosc/8)

512

(fosc/64)

1,024

(fosc/32)

2,048

(fosc/16)

8,192

(fosc/4)

1,024

(fosc/32)

2,048

(fosc/16)

4,096

(fosc/8)

2,048

(fosc/16)

4,096

(fosc/8)

8,192

(fosc/4)

16,384

(fosc/2)

4,096

(fosc/8)

8,192

(fosc/4)

16,384

(fosc/2)

32,768

(fosc/1)

(D1, D0) = (XFOUT1, XFOUT0)

Note A hazard may occur when the FOUT signal is turned on or off.

BUZZER, BUZZER

Ou tpu t ports R01 an d R00 m ay be set to BUZZER ou tpu t

an d BUZZER ou tpu t (BUZZER reverse ou tpu t), respectively,

allowin g for direct drivin g of th e piezo-electric bu zzer.

BUZZER ou tpu t (R00) m ay on ly be set if R01 is set to

BUZZER ou tpu t. In su ch case, wh eth er ON/ OFF of th e

BUZZER ou tpu t is don e th rou gh R00 register or is con -

trolled th rou gh R01 sim u ltan eou sly with BUZZER ou tpu t is

also selected by m ask option .

(R01, R00)

Th e frequ en cy of bu zzer ou tpu t m ay be selected by software

to be eith er 2 kHz or 4 kHz.

I-30

EPSON

S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

Table 4.4.3 lists th e ou tpu t port con trol bits an d th eir ad-

dresses.

Control of outp ut

p ort

Table 4.4.3 Control bits of output port

Register

Address

Comment

R03 output port data

D3

D2

D1

R01

D0

R00

Name

R03

SR

0

1

0

High

ON

Low

OFF

Low

OFF

R03

R02

BUZZER

FOUT

R02

0

R02 output port data

R/W

R01

0

R01 output port data

0F3H

BUZZER

R00

0

Buzzer ON/OFF control register

R00 output port data

0

High

ON

FOUT

0

Frequency output ON/OFF control register

XBZR

R/W

0

XFOUT1 XFOUT0

R/W

XBZR

0

2 kHz

4 kHz

Buzzer frequency control

R

0FDH

XFOUT1

XFOUT0

0

High

Low

FOUT frequency control:

XFOUT1(0), XFOUT0(0) -> F1

XFOUT1(0), XFOUT0(1) -> F2

XFOUT1(1), XFOUT0(0) -> F3

XFOUT1(1), XFOUT0(1) -> F4

R00–R03 Output port data (0F3H)

Sets th e ou tpu t data for th e ou tpu t ports.

Wh en 1 is written :

Wh en 0 is written :

Readin g:

High ou tpu t

Low ou tpu t

Valid

Th e ou tpu t port pin s ou tpu t th e data written to th e corre-

spon din g registers (R00–R03) with ou t ch an gin g it. Wh en 1

is written to th e register, th e ou tpu t port pin goes h igh

(VDD), an d wh en 0 is written , th e ou tpu t port pin goes low

(VSS). After an in itial reset, all th e registers are set to 0.

S1C6S3N7 TECHNICAL HARDWARE

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I-31

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

R00 (when FOUT is Special output port data (0F3H D0)

selected) Con trols th e FOUT (clock) ou tpu t.

Wh en 1 is written :

Wh en 0 is written :

Readin g:

Clock ou tpu t

Low level (DC) ou tpu t

Valid

FOUT ou tpu t can be con trolled by writin g data to R00. After

an in itial reset, th is register is set to 0.

Figu re 4.4.3 sh ows th e ou tpu t waveform for FOUT ou tpu t.

R00 register

0

1

FOUT output

waveform

Fig. 4.4.3

FOUT output waveform

XFOUT0, XFOUT1 FOUT frequency control (0FDH D0, 0FDH D1)

Selects th e ou tpu t frequ en cy wh en R00 port is set for FOUT

ou tpu t.

Table 4.4.4

XFOUT1

XFOUT0

Frequency Selection

FOUT frequency selection

0

1

0

1

0

1

F1

F2

F3

F4

After an in itial reset, th ese registers are set to 0.

I-32

EPSON

S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

R00, R01 (when BUZZER Special output port data (0F3H D0, 0F3H D1)

and BUZZER is Con trols th e bu zzer ou tpu t.

selected)

Wh en 1 is written :

Bu zzer ou tpu t

Low level (DC) ou tpu t

Valid

Wh en 0 is written :

Readin g:

BUZZER an d BUZZER ou tpu t can be con trolled by writin g

data to R00 an d R01.

Wh en BUZZER ou tpu t by R01 register con trol is selected by

m ask option , BUZZER ou tpu t an d BUZZER ou tpu t can be

con trolled sim u ltan eou sly by writin g data to R01 register.

After an in itial reset, th ese registers are set to 0.

Figu re 4.4.4 sh ows th e ou tpu t waveform for bu zzer ou tpu t.

R01 (R00) register

0

1

BUZZER output

waveform

BUZZER output

waveform

Fig. 4.4.4

Buzzer output waveform

XBZR Buzzer frequency control (0FDH D3)

Selects th e frequ en cy of th e bu zzer sign al.

Wh en 1 is written :

Wh en 0 is written :

Readin g:

2 kHz

4 kHz

Valid

Wh en R00 an d R01 port is set to bu zzer ou tpu t, th e fre-

qu en cy of th e bu zzer sign al can be selected by th is register.

Wh en 1 is written to th is register, th e frequ en cy is set in 2

kHz, an d in 4 kHz wh en 0 is written .

After an in itial reset, th is register is set to 0.

S1C6S3N7 TECHNICAL HARDWARE

EPSON

I-33

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

4.5 I/ O Ports (P00–P03)

Th e S1C6S3N7 Series h ave a 4-bit gen eral-pu rpose I/ O port.

Config ura tion of I/ O

p ort

Figu re 4.5.1 sh ows th e con figu ration of th e I/ O port. Th e

fou r bits of th e I/ O port P00–P03 can be set to eith er in pu t

m ode or ou tpu t m ode. Th e m ode can be set by writin g data

to th e I/ O con trol register (IOC).

Input

control

Register

Pxx

Address

I/O control

register

(IOC)

Fig. 4.5.1

Address

Vss

Configuration of I/O port

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S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

In pu t or ou tpu t m ode can be set for th e fou r bits of I/ O port

P00–P03 by writin g data in to I/ O con trol register IOC.

To set th e in pu t m ode, 0 is written to th e I/ O con trol regis-

ter. Wh en an I/ O port is set to in pu t m ode, its im pedan ce

becom es h igh an d it works as an in pu t port. However, th e

in pu t lin e is pu lled down wh en in pu t data is read.

I/ O c ontrol re g iste r

a nd I/ O m od e

Th e ou tpu t m ode is set wh en 1 is written to th e I/ O con trol

register (IOC). Wh en an I/ O port set to ou tpu t m ode works

as an ou tpu t port, it ou tpu ts a h igh sign al (VDD) wh en th e

port ou tpu t data is 1, an d a low sign al (VSS) wh en th e port

ou tpu t data is 0.

After an in itial reset, th e I/ O con trol register is set to 0, an d

th e I/ O port en ters th e in pu t m ode.

Th e ou tpu t specification du rin g ou tpu t m ode (IOC = 1) of th e

I/ O port can be set with th e m ask option for eith er com ple-

m en tary ou tpu t or Pch open drain ou tpu t. Th is settin g can

be perform ed for each bit of th e I/ O port. However, wh en

Pch open drain ou tpu t h as been selected, voltage in excess

of th e su pply voltage m u st n ot be applied to th e port.

Ma sk op tion

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

Table 4.5.1 lists th e I/ O port con trol bits an d th eir ad-

dresses.

Control of I/ O p ort

Table 4.5.1 I/O port control bits

Register

Address

Comment

D3

D2

D1

D0

Name

P03

SR

1

0

P03

P02

P01

P00

–

High

Low

P02

P01

P00

0

–

High

Low

R/W

0F6H

I/O port (P00–P03)

0

IOC

R/W

0

R

0FCH

0

IOC

0

Output

Input

I/O port P00–P03 Input/Output

P00–P03 I/O port data (0F6H)

I/ O port data can be read an d ou tpu t data can be written

th rou gh th e port.

• Wh en writin g data

Wh en 1 is written :

Wh en 0 is written :

High level

Low level

Wh en an I/ O port is set to th e ou tpu t m ode, th e written

data is ou tpu t from th e I/ O port pin u n ch an ged. Wh en 1

is written as th e port data, th e port pin goes h igh (VDD),

an d wh en 0 is written , th e level goes low (VSS). Port data

can also be written in th e in pu t m ode.

• Wh en readin g data

Wh en 1 is read:

Wh en 0 is read:

High level

Low level

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S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

Th e pin voltage level of th e I/ O port is read. Wh en th e I/

O port is in th e in pu t m ode th e voltage level bein g in pu t

to th e port pin can be read; in th e ou tpu t m ode th e

ou tpu t voltage level can be read. Wh en th e pin voltage is

h igh (VDD) th e port data read is 1, an d wh en th e pin

voltage is low (VSS) th e data is 0. Also, th e bu ilt-in pu ll-

down resistan ce fu n ction s du rin g readin g, so th e I/ O port

pin is pu lled down .

Note - When the I/O port is set to the output mode and a low-imped-

ance load is connected to the port pin, the data written to the

register may differ from the data read.

-

When the I/O port is set to the input mode and a low-level

voltage (Vss) is input by the built-in pull-down resistance, an

erroneous input results if the time constant of the capacitive

load of the input line and the built- in pull-down resistance load

is greater than the read-out time. When the input data is being

read, the time that the input line is pulled down is equivalent to

0.5 cycles of the CPU system clock. Hence, the electric poten-

tial of the pins must settle within 0.5 cycles. If this condition

cannot be met, some measure must be devised, such as

arranging a pull-down resistance externally, or performing

multiple read-outs.

IOC I/O control register (0FCH D0)

Th e in pu t or ou tpu t I/ O port m ode can be set with th is

register.

Wh en 1 is written :

Wh en 0 is written :

Readin g:

Ou tpu t m ode

In pu t m ode

Valid

Th e in pu t or ou tpu t m ode of th e I/ O port is set in u n its of

fou r bits. For in stan ce, IOC sets th e m ode for P00–P03.

Writin g 1 to th e I/ O con trol register m akes th e I/ O port

en ter th e ou tpu t m ode, an d writin g 0, th e in pu t m ode.

After an in itial reset, th e IOC register is set to 0, so th e I/ O

port is in th e in pu t m ode.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

4.6 LCD Drive r (COM0–COM3, SEG0–SEG25)

Th e S1C6S3N7 Series h ave fou r com m on pin s an d 26

(SEG0–SEG25) segm en t pin s, so th at an LCD with a m axi-

m u m of 104 (26 × 4) segm en ts can be driven . Th e power for

drivin g th e LCD is gen erated by th e CPU in tern al circu it, so

th ere is n o n eed to su pply power extern ally.

Config ura tion of LCD

d rive r

Th e drivin g m eth od is 1/ 4 du ty (or 1/ 3, 1/ 2 du ty by m ask

option ) dyn am ic drive, adoptin g th e fou r types of poten tial

(1/ 3 bias), VDD, VL1, VL2 an d VL3. Moreover, th e 1/ 2 bias

dyn am ic drive th at u ses th ree types of poten tial, VDD, VL1 =

VL2 an d VL3, can be selected by settin g th e m ask option

(drive du ty can also be selected from 1/ 4, 1/ 3 or 1/ 2). 1/ 2

bias drive is effective wh en th e LCD system regu lated voltage

circu it is n ot u sed. Th e VL1 term in al an d th e VL2 term in al

sh ou ld be con n ected ou tside of th e IC.

Th e fram e frequ en cy is 32 Hz for 1/ 4 du ty an d 1/ 2 du ty,

an d 42.7 Hz for 1/ 3 du ty (in th e case of fosc = 32.768 kHz).

Figu re 4.6.1 sh ows th e drive waveform for 1/ 4 du ty (1/ 3 bias),

Figu re 4.6.2 sh ows th e drive waveform for 1/ 3 du ty (1/ 3 bias),

Figu re 4.6.3 sh ows th e drive waveform for 1/ 2 du ty (1/ 3 bias),

Figu re 4.6.4 sh ows th e drive waveform for 1/ 4 du ty (1/ 2 bias),

Figu re 4.6.5 sh ows th e drive waveform for 1/ 3 du ty (1/ 2 bias)

an d Figu re 4.6.6 sh ows th e drive waveform for 1/ 2 du ty (1/ 2

bias).

Note fosc indicates the oscillation frequency of the oscillation circuit.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

LCD lighting status

COM0

-VDD

-VL1

COM0

-VL2

-VL3

COM1

COM2

COM3

COM1

COM2

COM3

SEG0–25

Not lit

Lit

-VDD

-VL1

-VL2

-VL3

SEG

0–25

Fig. 4.6.1

Frame frequency

Drive waveform for

1/4 duty (1/3 bias)

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

COM0

-VDD

-VL1

-VL2

-VL3

LCD lighting status

COM0

COM1

COM2

COM1

COM2

COM3

SEG0–25

Not lit

Lit

-VDD

-VL1

-VL2

-VL3

SEG

0–25

Fig. 4.6.2

Drive waveform for

1/3 duty (1/3 bias)

Frame frequency

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S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

-VDD

-VL1

LCD lighting status

COM0

COM1

COM2

COM3

-VL2

COM0

-VL3

COM1

SEG0–25

Not lit

Lit

-VDD

-VL1

-VL2

-VL3

SEG

0–25

Fig. 4.6.3

Drive waveform for

1/2 duty (1/3 bias)

Frame frequency

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

LCD lighting status

-VDD

-VL1, L2

-VL3

COM0

COM1

COM2

COM3

COM0

COM1

COM2

COM3

SEG0–25

Not lit

Lit

-VDD

-VL1, L2

-VL3

SEG

0–25

Fig. 4.6.4

Frame frequency

Drive waveform for

1/4 duty (1/2 bias)

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

LCD lighting status

-VDD

-VL1, L2

COM0

COM1

COM2

COM3

COM0

-VL3

COM1

COM2

SEG0–25

Not lit

Lit

-VDD

-VL1, L2

-VL3

SEG

0–25

Fig. 4.6.5

Frame frequency

Drive waveform for

1/3 duty (1/2 bias)

LCD lighting status

-VDD

-VL1, L2

-VL3

COM0

COM1

COM2

COM3

COM0

COM1

SEG0–25

Not lit

Lit

-VDD

-VL1, L2

-VL3

SEG

0–25

Fig. 4.6.6

Frame frequency

Drive waveform for

1/2 duty (1/2 bias)

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

In th e S1C6S3N7 Series, th e LCD drive du ty can be set to

Ca d e nc e a d just-

m e nt of osc illa tion

fre q ue nc y

1/ 1 du ty by software. Th is fu n ction en ables easy adju st-

m en t (caden ce adju stm en t) of th e oscillation frequ en cy of

th e OSC circu it.

Th e procedu re to set to 1/ 1 du ty drive is as follows:

➀ Write 1 to th e CSDC register at address 0FBH D3.

➀ Write th e sam e valu e to all registers correspon din g to

COMs 0 th rou gh 3 of th e display m em ory.

Th e fram e frequ en cy is 32 Hz (fOSC1/ 1,024, wh en fOSC1 =

32.768 kHz).

Note - Even when l/3 or 1/2 duty is selected by the mask option, the

display data corresponding to all COM are valid during 1/1 duty

driving. Hence, for 1/1 duty drive, set the same value for all

display memory corresponding to COMs 0 through 3.

-

For cadence adjustment, set the display data corresponding to

COMs 0 through 3, so that all the LCD segments go on.

Figu re 4.6.7 sh ows th e 1/ 1 du ty drive waveform (1/ 3 bias).

Figu re 4.6.8 sh ows th e 1/ 1 du ty drive waveform (1/ 2 bias).

LCD lighting status

-VDD

-VL1

-VL2

-VL3

COM0

COM1

COM2

COM3

COM

0–3

Frame frequency

SEG0–25

Not lit

Lit

-VDD

-VL1

-VL2

-VL3

SEG

0–25

Fig. 4.6.7

-VDD

-VL1

-VL2

-VL3

1/1 duty drive waveform

(1/3 bias)

LCD lighting status

COM0

COM1

COM2

COM3

-VDD

-VL1,

-VL3

V

L2

COM

0–3

SEG0–25

Not lit

Frame frequency

Lit

-VDD

-VL1,

-VL3

V

L2

SEG

0–25

-VDD

-VL1,

-VL3

Fig. 4.6.8

1/1 duty drive waveform

(1/2 bias)

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

(1) Segment allocation

Ma sk op tion

(se g m e nt a lloc a tion)

As sh own in Figu re 4.l.1, th e S1C6S3N7 Series display

data is decided by th e display data written to th e display

m em ory (write-on ly) at address 090H–0AFH.

Th e address an d bits of th e display m em ory can be m ade

to correspon d to th e segm en t pin s (SEG0–SEG25) in an y

com bin ation th rou gh m ask option . Th is sim plifies design

by in creasin g th e degree of freedom with wh ich th e liqu id

crystal pan el can be design ed.

Figu re 4.6.9 sh ows an exam ple of th e relation sh ip be-

tween th e LCD segm en ts (on th e pan el) an d th e display

m em ory in th e case of 1/ 3 du ty.

Common 0

9A, D0

(a)

Common 1

9B, D1

(f)

Common 2

9B, D0

(e)

Data

Address

D3

d

D2

c

D1

b

D0

a

SEG10

SEG11

SEG12

09AH

09BH

09CH

09DH

p

g

f

e

9A, D1

(b)

9B, D2

(g)

9A, D3

(d)

d'

p'

c'

g'

b'

f'

a'

e'

9D, D1

(f')

9A, D2

(c)

9B, D3

(p)

Display data memory allocation

Pin address allocation

a

a'

g'

b'

b

f'

f

g

c'

e

c

e'

p'

p

d'

d

SEG10 SEG11 SEG12

Common 0

Common 1

Common 2

Fig. 4.6.9

Segment allocation

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

(2) Drive duty

Accordin g to th e m ask option , eith er 1/ 4, 1/ 3 or 1/ 2

du ty can be selected as th e LCD drive du ty.

Table 4.6.1 sh ows th e differen ces in th e n u m ber of seg-

m en ts accordin g to th e selected du ty.

Table 4.6.1

Differences according to

selected duty

Pins Used

in Common

Maximum Number

of Segments

Frame Frequency

(when fosc = 32 kHz)

Duty

1/ 4

1/ 3

1/ 2

COM0–3

COM0–2

COM0–1

104 (26 × 4)

78 (26 × 3)

52 (26 × 2)

32 Hz

42.7 Hz

32 Hz

(3) Output specification

➀ Th e segm en t pin s (SEG0–SEG25) are selected by m ask

option in pairs for eith er segm en t sign al ou tpu t or DC

ou tpu t (VDD an d VSS bin ary ou tpu t). Wh en DC ou tpu t

is selected, th e data correspon din g to COM0 of each

segm en t pin is ou tpu t.

➀ Wh en DC ou tpu t is selected, eith er com plem en tary

ou tpu t or Pch open drain ou tpu t can be selected for

each pin by m ask option .

Note

The pin pairs are the combination of SEG (2*n) and SEG (2*n +

1) (where n is an integer from 0 to 12).

(4) Drive bias

For th e drive bias of th e S1C6S3N7 or th e S1C6S3L7,

eith er 1/ 3 bias or 1/ 2 bias can be selected by th e m ask

option . Wh en u sin g th e LCD system regu lated voltage

circu it, it is fixed at 1/ 3 bias.

Th e S1C6S3B7 can on ly u se 1/ 3 bias.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

Table 4.6.2 sh ows th e con trol bits of th e LCD driver an d

th eir addresses. Figu re 4.6.10 sh ows th e display m em ory

m ap.

Control of LCD

d rive r

Table 4.6.2 Control bits of LCD driver

Register

Address

Comment

D3

D2

D1

D0

0

Name

CSDC

SR

0

1

0

Static

Dynamic LCD drive switch

CSDC

0

R/W

R

0

0FBH

Address

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

Fig. 4.6.10

Display

090

0A0

Display memory (Write only)

32 words x 4 bits

memory map

CSDC LCD drive switch (0FBH D3)

Th e LCD drive form at can be selected with th is switch .

Wh en 1 is written :

Wh en 0 is written :

Readin g:

Static drive

Dyn am ic drive

Valid

After an in itial reset, dyn am ic drive (CSDC = 0) is selected.

Display memory (090H–0AFH)

Th e LCD segm en ts are tu rn ed on or off accordin g to th is

data.

Wh en 1 is written :

Wh en 0 is written :

Readin g:

On

Off

In valid

By writin g data in to th e display m em ory allocated to th e

LCD segm en t (on th e pan el), th e segm en t can be tu rn ed on

or off. After an in itial reset, th e con ten ts of th e display

m em ory are u n defin ed.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

4.7 Cloc k Tim e r

Th e S1C6S3N7 Series h ave a bu ilt-in clock tim er driven by

Config ura tion of

c loc k tim e r

th e sou rce oscillator. Th e clock tim er is con figu red as a

seven -bit bin ary cou n ter th at serves as a frequ en cy divider

takin g a 256 Hz sou rce clock from th e dividin g circu it. Th e

fou r h igh -order bits (16 Hz–2 Hz) can be read by th e soft-

ware.

Figu re 4.7.1 is th e block diagram of th e clock tim er.

Data bus

OSC

(oscillation circuit)

256 Hz

128 Hz–32 Hz

16 Hz–2 Hz

and

dividing circuit

32 Hz, 8 Hz, 2 Hz

Fig. 4.7.1

Clock timer reset signal

Block diagram of

clock timer

Interrupt

request

Interrupt

control

Norm ally, th is clock tim er is u sed for all kin ds of tim in g

pu rpose, su ch as clocks.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

Th e clock tim er can in terru pt on th e fallin g edge of th e 32

Hz, 8 Hz, an d 2 Hz sign als. Th e software can m ask an y of

th ese in terru pt sign als.

Inte rrup t func tion

Figu re 4.7.2 is th e tim in g ch art of th e clock tim er.

Register

Address

Frequency

16 Hz

8 Hz

Clock timer timing chart

bits

D0

D1

D2

D3

0E4H

4 Hz

2 Hz

Occurrence of

32 Hz interrupt request

Occurrence of

8 Hz interrupt request

Occurrence of

2 Hz interrupt request

Fig. 4.7.2 Timing chart of the clock timer

As sh own in Figu re 4.7.2, an in terru pt is gen erated on th e

fallin g edge of th e 32 Hz, 8 Hz, an d 2 Hz frequ en cies. Wh en

th is h appen s, th e correspon din g in terru pt even t flag (IT32,

IT8, IT2) is set to 1. Maskin g th e separate in terru pts can be

don e with th e in terru pt m ask register (EIT32, EIT8, EIT2).

However, regardless of th e in terru pt m ask register settin g,

th e in terru pt even t flags will be set to 1 on th e fallin g edge of

th eir correspon din g sign al (e.g. th e fallin g edge of th e 2 Hz

sign al sets th e 2 Hz in terru pt factor flag to 1).

Note Write to the interrupt mask register (EIT32, EIT8, EIT2) and read

the interrupt factor flags (IT32, IT8, IT2) only in the DI status

(interrupt flag = 0). Otherwise, it causes malfunction.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

Table 4.7.1 sh ows th e clock tim er con trol bits an d th eir

addresses.

Control of c loc k

tim e r

Table 4.7.1 Control bits of clock timer

Register

Address

Comment

D3

D2

D1

D0

Name

TM3

SR

1

0

High

Low

TM3

TM2

TM1

TM0

–

Timer data (clock timer 2 Hz)

Timer data (clock timer 4 Hz)

Timer data (clock timer 8 Hz)

Timer data (clock timer 16 Hz)

High

Low

R

TM2

TM1

TM0

0

–

0E4H

0EBH

0EFH

0F9H

0

EIT2

EIT8

R/W

EIT32

R

EIT2

EIT8

EIT32

0

Enable

Mask

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

0

IT2

IT8

IT32

R

IT2

0

Yes

No

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

IT8

IT32

0

TMRST SWRUN SWRST

TMRST

SWRUN

SWRST

Reset

0

Reset

Run

–

Stop

–

Clock timer reset

R

W

R/W

W

Stopwatch timer RUN/STOP

Stopwatch timer reset

Reset

TM0–TM3 Timer data (0E4H)

Th e l6 Hz to 2 Hz tim er data of th e clock tim er can be read

from th is register. Th ese fou r bits are read-on ly, an d write

operation s are in valid.

After an in itial reset, th e tim er data is in itialized to 0H.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

EIT32, EIT8, EIT2 Interrupt mask registers (0EBH D0–D2)

Th ese registers are u sed to m ask th e clock tim er in terru pt.

Wh en 1 is written : En abled

Wh en 0 is written : Masked

Readin g:

Valid

Th e in terru pt m ask register bits (EIT32, EIT8, EIT2) m ask

th e correspon din g in terru pt frequ en cies (32 Hz, 8 Hz, 2 Hz).

After an in itial reset, th ese registers are all set to 0.

IT32, IT8, IT2 Interrupt factor flags (0EFH D0–D2)

Th ese flags in dicate th e statu s of th e clock tim er in terru pt.

Wh en 1 is read:

Wh en 0 is read:

Writin g:

In terru pt h as occu rred

In terru pt h as n ot occu rred

In valid

Th e in terru pt factor flags (IT32, IT8, IT2) correspon d to th e

clock tim er in terru pts (32 Hz, 8 Hz, 2 Hz). Th e software can

determ in e from th ese flags wh eth er th ere is a clock tim er

in terru pt. However, even if th e in terru pt is m asked, th e

flags are set to 1 on th e fallin g edge of th e sign al. Th ese

flags can be reset wh en th e register is read by th e software.

Readin g of in terru pt factor flags is available at EI, bu t be

carefu l in th e followin g cases.

If th e in terru pt m ask register valu e correspon din g to th e

in terru pt factor flags to be read is set to 1, an in terru pt

requ est will be gen erated by th e in terru pt factor flags set

tim in g, or an in terru pt requ est will n ot be gen erated. Be

very carefu l wh en in terru pt factor flags are in th e sam e

address.

After an in itial reset, th ese flags are set to 0.

Clock timer reset (0F9H D2)

TMRST

Th is bit resets th e clock tim er.

Wh en 1 is written : Clock tim er reset

Wh en 0 is written : No operation

Readin g:

Always 0

Th e clock tim er is reset by writin g 1 to TMRST. Th e clock

tim er starts im m ediately after th is. No operation resu lts

wh en 0 is written to TMRST.

Th is bit is write-on ly, an d so is always 0 wh en read.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

4.8 Stop wa tc h Tim e r

Th e S1C6S3N7 Series in corporate a 1/ 100 sec an d 1/ 10 sec

Config ura tion of

stop wa tc h tim e r

stopwatch tim er. Th e stopwatch tim er is con figu red as a

two-stage, fou r-bit BCD tim er servin g as th e clock sou rce for

an approxim ately 100 Hz sign al (obtain ed by approxim ately

dividin g th e 256 Hz sign al ou tpu t from th e dividin g circu it).

Data can be read ou t fou r bits at a tim e by th e software.

Figu re 4.8.1 is th e block diagram of th e stopwatch tim er.

Data bus

OSC

(oscillation circuit)

and

10 Hz

256 Hz

SWL timer

SWH timer

dividing circuit

10 Hz, 1 Hz

Fig. 4.8.1

Stopwatch timer reset signal

Interrupt

control

Interrupt

request

Block diagram of

stopwatch timer

Stopwatch timer RUN/STOP signal

Th e stopwatch tim er can be u sed separately from th e clock

tim er. In particu lar, digital stopwatch fu n ction s can be

easily realized by software.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

Th e stopwatch tim er is con figu red as two fou r-bit BCD

tim ers, SWL an d SWH. Th e SWL tim er, at th e stage preced-

in g th e stopwatch tim er, h as an approxim ate l00 Hz sign al

as its in pu t clock. It cou n ts u p every 1/ 100 sec an d gen er-

ates an approxim ate 10 Hz sign al. Th e SWH tim er h as an

approxim ate 10 Hz sign al gen erated by th e SWL tim er for its

in pu t clock. It cou n ts u p every 1/ 10 sec an d gen erates a 1

Hz sign al.

Count-up p a tte rn

Figu re 4.8.2 sh ows th e cou n t-u p pattern of th e stopwatch

tim er.

SWH count-up pattern

SWH count value

0

1

2

3

4

5

6

7

8

9

0

1 Hz

signal

26

26 25 25 26

26 25 25 26 26

Counting time (S)

256 256 256 256 256 256 256 256 256 256

generation

26

256

25

256

x 4 = 1 (S)

x 6 +

SWL count-up pattern 1

SWL count value

0

1

2

3

4

2

5

6

7

8

9

0

Approximate

10 Hz

signal

3

2

3

2

3

2

3

2

Counting time (S)

256 256 256 256 256 256 256 256 256 256

generation

25

256

(S)

SWL count-up pattern 2

SWL count value

0

1

2

3

4

5

6

7

8

9

0

Approximate

10 Hz

signal

3

2

3

2

3

2

3

2

Counting time (S)

256 256 256 256 256 256 256 256 256 256

Fig. 4.8.2

Count-up pattern of

stopwatch timer

generation

26

(S)

256

SWL gen erates an approxim ate 10 Hz sign al from th e 256

Hz based sign al. Th e cou n t-u p in tervals are 2/ 256 sec an d

3/ 256 sec, so th at two fin al pattern s are gen erated: a 25/

256 sec in terval an d a 26/ 256 sec in terval. Con sequ en tly,

th e cou n t-u p in tervals are 2/ 256 sec an d 3/ 256 sec, wh ich

do n ot am ou n t to an accu rate 1/ 100 sec. SWH cou n ts th e

approxim ate 10 Hz sign als gen erated by th e 25/ 256 sec an d

26/ 256 sec in tervals in th e ratio of 4:6 to gen erate a l Hz

sign al. Th e cou n t-u p in tervals are 25/ 256 sec an d 26/ 256

sec, wh ich do n ot am ou n t to an accu rate 1/ 10 sec.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

Th e 10 Hz (approxim ate 10 Hz) an d 1 Hz in terru pts can be

Inte rrup t func tion

gen erated by th e overflow of th e SWL an d SWH stopwatch

tim ers, respectively. Also, software can separately m ask th e

frequ en cies as described earlier.

Figu re 4.8.3 is th e tim in g ch art for th e stopwatch tim er.

Register

Stopwatch timer (SWL) timing chart

bits

Address

0E2H

D0

D1

(1/100 sec BCD)

D2

D3

Occurrence of

10 Hz interrupt request

Register

bits

Address

Stopwatch timer (SWH) timing chart

D0

D1

D2

D3

0E3H

(1/10 sec BCD)

Fig. 4.8.3

Timing chart for

stopwatch timer

Occurrence of

1 Hz interrupt request

As sh own in Figu re 4.8.3, th e in terru pts are gen erated by

th e overflow of th e respective tim ers (9 ch an gin g to 0). Also

wh en th is h appen s, th e correspon din g in terru pt factor flags

(ISW0, ISW1) are set to 1. Th e respective in terru pts can be

m asked separately with th e in terru pt m ask registers

(EISW0, EISW1). However, regardless of th e settin g of th e

in terru pt m ask registers, th e in terru pt factor flags are set to

1 by th e overflow of th e correspon din g tim ers.

Write to the interrupt mask registers (EISW0, EISW1) and read the

interrupt factor flags (ISW0, ISW1) only in the DI status (interrupt

flag = 0). Otherwise, it causes malfunction.

Note

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

Table 4.8.1 sh ows th e stopwatch tim er con trol bits an d th eir

addresses.

Control of stop wa tc h

tim e r

Table 4.8.1 Stopwatch timer control bits

Register

Address

Comment

D3

D2

D1

D0

Name

SWL3

SR

0

1

0

SWL3

SWL2

SWL1

SWL0

MSB

SWL2

SWL1

SWL0

SWH3

SWH2

SWH1

SWH0

0

Stopwatch timer

1/100 sec (BCD)

R

0E2H

0E3H

0EAH

0EEH

0F9H

LSB

SWH3

SWH2

SWH1

SWH0

EISW0

ISW0

MSB

R

Stopwatch timer

1/10 sec (BCD)

LSB

0

EISW1

0

R

R/W

EISW1

EISW0

0

Enable

Mask

Interrupt mask register (stopwatch 1 Hz)

Interrupt mask register (stopwatch 10 Hz)

0

ISW1

0

R

ISW1

ISW0

0

Yes

No

Interrupt factor flag (stopwatch 1 Hz)

Interrupt factor flag (stopwatch 10 Hz)

0

TMRST SWRUN SWRST

TMRST

SWRUN

SWRST

Reset

0

Reset

Run

–

Stop

–

Clock timer reset

R

W

R/W

W

Stopwatch timer RUN/STOP

Stopwatch timer reset

Reset

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

SWL0–SWL3 1/100 sec stopwatch timer (0E2H)

Data (BCD) of th e 1/ 100 sec colu m n of th e stopwatch tim er

can be read. Th ese fou r bits are read-on ly, an d can n ot be

written to.

After an in itial reset, th e tim er data is set to 0H.

SWH0–SWH3 1/10 sec stopwatch timer (0E3H)

Data (BCD) of th e 1/ 10 sec colu m n of th e stopwatch tim er

can be read. Th ese fou r bits are read-on ly, an d can n ot be

written to.

After an in itial reset, th e tim er data is set to 0H.

EISW0, EISW1 Interrupt mask register (0EAH D0 and D1)

Th ese registers m ask th e stopwatch tim er in terru pt.

Wh en 1 is written : En abled

Wh en 0 is written : Masked

Readin g:

Valid

Th e in terru pt m ask register bits (EISW0, EISW1) are u sed to

m ask th e 10 Hz an d 1 Hz in terru pts, respectively.

After an in itial reset, th ese registers are both set to 0.

ISW0, ISW1 Interrupt factor flags (0EEH D0 and D1)

Th ese flags in dicate th e statu s of th e stopwatch tim er in ter-

ru pt.

Wh en 1 is read:

Wh en 0 is read:

Writin g:

In terru pt h as occu rred

In terru pt h as n ot occu rred

In valid

Th e in terru pt factor flags (ISW0, ISW1) correspon d to th e 10

Hz an d 1 Hz in terru pts, respectively. With th ese flags, th e

software can determ in e wh eth er a stopwatch tim er in terru pt

h as occu rred. However, regardless of th e in terru pt m ask

register settin g, th ese flags are set to 1 by th e tim er over-

flow.

Th ey are reset wh en th e register is read by th e software.

Readin g of in terru pt factor flags is available at EI, bu t be

carefu l in th e followin g cases.

If th e in terru pt m ask register valu e correspon din g to th e

in terru pt factor flags to be read is set to 1, an in terru pt

requ est will be gen erated by th e in terru pt factor flags set

tim in g, or an in terru pt requ est will n ot be gen erated.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

Be very carefu l wh en in terru pt factor flags are in th e sam e

address.

After an in itial reset, th ese flags are set to 0.

SWRST Stopwatch timer reset (0F9H D0)

Th is bit resets th e stopwatch tim er.

Wh en 1 is written : Stopwatch tim er reset

Wh en 0 is written : No operation

Readin g:

Always 0

Th e stopwatch tim er is reset wh en 1 is written to SWRST.

Wh en th e stopwatch tim er is reset wh ile ru n n in g, operation

restarts im m ediately. Also, wh ile stopped, th e reset data is

m ain tain ed.

Th is bit is write-on ly, an d is always 0 wh en read.

SWRUN Stopwatch timer run/stop (0F9H D1)

Th is bit con trols ru n / stop of th e stopwatch tim er.

Wh en 1 is written : Ru n

Wh en 0 is written : Stop

Readin g:

Valid

Th e stopwatch tim er ru n s wh en 1 is written to SWRUN, an d

stops wh en 0 is written .

Wh en stopped, th e tim er data is m ain tain ed u n til th e tim er

n ext Ru n or is reset. Also, wh en th e tim er ru n s after bein g

stopped, th e data th at was m ain tain ed can be u sed to res-

u m e th e cou n t.

If th e tim er data is read wh ile ru n n in g, a correct read m ay

be im possible becau se of th e carry from th e low-order bit

(SWL) to th e h igh -order bit (SWH). Th is occu rs if readin g

h as exten ded over th e SWL an d SWH bits wh en th e carry

occu rs. To preven t th is, read after stoppin g, an d th en

con tin u e ru n n in g. Also, th e stopped du ration m u st be

with in 976 µs (256 Hz, 1/ 4 cycle).

After an in itial reset, th is register is set to 0.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

4.9 Sup p ly Volta g e De te c tion (SVD) Circ uit a nd

He a vy Loa d Prote c tion Func tion

Th e S1C6S3N7 Series h ave a bu ilt-in su pply voltage detec-

tion (SVD) circu it an d a h eavy load protection fu n ction .

Config ura tion of SVD

c irc uit a nd he a vy

loa d p rote c tion

func tion

Figu re 4.9.1 sh ows th e con figu ration of th e circu it.

SVD circuit

Th e SVD circu it m on itors th e con dition s of th e su pply volt-

age (battery voltage), an d software can ch eck wh eth er th e

su pply voltage h as dropped below th e detectin g voltage level

of th e SVD circu it: 2.4 V for th e S1C6S3N7 (su pply voltage is

3.0 V), or l.2 V for th e S1C6S3L7 (1.5 V) an d th e S1C6S3B7

(3.0 V). Registers SVDON (SVD con trol on / off) an d SVDDT

(SVD data) are u sed for th e SVD circu it. Th e software can

tu rn SVD operation on an d off. Wh en SVD is on , th e IC

draws a large cu rren t, so keep SVD off u n less it is.

Sin ce su pply voltage detection is au tom atically perform ed by

th e h ardware every 2 Hz (0.5 sec) wh en th e h eavy load

protection fu n ction operates, do n ot perm it th e operation of

th e SVD circu it by th e software in order to m in im ize power

cu rren t con su m ption .

Heavy load protection function

Note th at th e h eavy load protection fu n ction on th e

S1C6S3L7/ S1C6S3B7 are differen t from th e S1C6S3N7.

(1) In case of S1C6S3L7/S1C6S3B7

Th e S1C6S3L7/ S1C6S3B7 h ave th e h eavy load protec-

tion fu n ction for wh en th e battery load becom es h eavy

an d th e sou rce voltage drops, su ch as wh en an extern al

bu zzer sou n ds or an extern al lam p ligh ts. Th e state

wh ere th e h eavy load protection fu n ction is in effect is

called th e h eavy load protection m ode. In th is m ode,

operation with a lower voltage th an n orm al is possible.

Th e n orm al m ode ch an ges to th e h eavy load protection

m ode in th e followin g two cases:

➀ Wh en th e software ch an ges th e m ode to th e h eavy load

protection m ode (HLMOD = 1)

➀ Wh en su pply voltage drop (SVDDT = 1) in th e SVD

circu it is detected, th e m ode will au tom atically sh ift to

th e h eavy load protection m ode u n til th e su pply volt-

age is recovered (SVTDT = 0)

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

In th e h eavy load protection m ode, th e in tern ally regu -

lated voltage is gen erated by th e liqu id crystal driver

sou rce ou tpu t VL2 so as to operate th e in tern al circu it.

Con sequ en tly, m ore cu rren t is con su m ed in th e h eavy

load protection m ode th an in th e n orm al m ode. Un less it

is n ecessary, be carefu l n ot to set th e h eavy load protec-

tion m ode with th e software. Also, to redu ce cu rren t

con su m ption , do n ot set th e SVDON to ON in th e h eavy

load protection m ode.

Note th at in S1C6S3L7/ S1C6S3B7, th e ran ge of operat-

in g voltage differs du rin g CR oscillation an d du rin g

crystal oscillation .

(2) In case of S1C6S3N7

Th e S1C6S3N7 h as th e h eavy load protection fu n ction for

wh en th e battery load becom es h eavy an d th e sou rce

voltage ch an ges, su ch as wh en an extern al bu zzer sou n ds

or an extern al lam p ligh ts. Th e state wh ere th e h eavy load

protection fu n ction is in effect is called th e h eavy load

protection m ode. Com pared with th e n orm al operation

m ode, th is m ode can redu ce th e ou tpu t voltage variation of

th e con stan t voltage or voltage booster/ redu cer of th e LCD

system .

Th e n orm al m ode ch an ges to th e h eavy load protection

m ode in th e followin g case:

•

Wh en th e software ch an ges th e m ode to th e h eavy load

protection m ode (HLMOD = 1)

Th e h eavy load protection m ode switch es th e con stan t

voltage circu it of th e LCD system to th e h igh -stability

m ode from th e low cu rren t con su m ption m ode. Con se-

qu en tly, m ore cu rren t is con su m ed in th e h eavy load

protection m ode th an in th e n orm al m ode. Un less it is

n ecessary, be carefu l n ot to set th e h eavy load protection

m ode with th e software.

VDD

Regurated

voltage circuit

SVD

circuit

V

S1

L1

V

VSS

Address 0FAH

HLMOD

D3

D1

SVD sampling

control

Fig. 4.9.1

Configuration of SVD and

heavy load protection circuits

SVDDT

VSS

D0

SVDON

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

Th e followin g explain s th e tim in g wh en th e SVD circu it

writes th e resu lt of su pply voltage detection to th e SVDDT

register.

Op e ra tion of SVD

d e te c tion tim ing

Th e resu lt of su pply voltage detection is written to th e

SVDDT register by th e SVD circu it, an d th is data can be

read by th e software to determ in e th e su pply voltage.

Th ere are two m eth ods, explain ed below, for execu tin g th e

detection by th e SVD circu it.

(1) Sampling with HLMOD set to 1

Wh en HLMOD is set to 1 an d SVD sam plin g is execu ted,

th e detection resu lts can be written to th e SVDDT regis-

ter with th e followin g tim in g:

Im m ediately after sam plin g with th e 2 Hz cycle ou tpu t by

th e oscillation circu it wh ile HLMOD = 1 (sam plin g tim e is

122 µs in th e case of fosc = 32.768 kHz).

Con sequ en tly, after HLMOD h as been set to 1, th e n ew

detection resu lt is written in a 2 Hz.

(2) Sampling with SVDON set to 1

Wh en SVDON is set to 1, SVD detection is execu ted. As

soon as SVDON is reset to 0, th e resu lt is loaded to in th e

SVDDT register. To obtain a stable SVD detection resu lt,

th e SVD circu it m u st be on for at least l00 µs. So, to

obtain th e SVD detection resu lt, follow th e program m in g

sequ en ce below.

➀ Set SVDON to 1

➀ Main tain for 100 µs m in im u m

➀ Set SVDON to 0

➀ Read SVDDT

However, at 32 kHz for th e S1C6S3N7, S1C6S3L7 an d

S1C6S3B7, th e in stru ction cycles are lon g en ou gh , so

th ere is n o n eed to worry abou t m ain tain in g 100 µs for

SVDON = 1 in th e software.

Notice th at even if th e SVD circu it detects a drop in th e

su pply voltage (l.2 V/ 2.4 V or less) an d in vokes th e h eavy

load protection m ode, th is will be th e sam e as wh en th e

software in vokes th e h eavy load protection m ode, in th at th e

SVD circu it will be sam pled with a tim in g syn ch ron ized to

th e 2 Hz ou tpu t from th e prescaler. If th e SVD circu it

detects a voltage drop an d en ters th e h eavy load protection

m ode, it will retu rn to th e n orm al m ode on ce th e su pply

voltage recovers an d th e SVD circu it determ in es th at th e

su pply voltage is l.2 V/ 2.4 V or m ore.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

Th e S1C6S3N7 Series h ave a h eavy load protection fu n ction

for wh en th e battery load becom es h eavy an d th e su pply

Op e ra tion of he a vy

loa d p rote c tion

func tion

voltage drops, su ch as wh en a m elody is played or an exter-

n al lam p ligh ts. Th is fu n ction s works in th e h eavy load

protection m ode.

(1) In cace of S1C6S3L7/S1C6S3B7

Th e n orm al m ode ch an ges to th e h eavy load protection

m ode in th e followin g two cases:

➀ Wh en th e software ch an ges th e m ode to th e h eavy load

protection m ode

➀ Wh en th e SVD circu it detects a su pply voltage less

th an l.2 V, in wh ich case th e m ode is au tom atically

ch an ged to th e h eavy load protection m ode

(2) In case of S1C6S3N7

Th e n orm al m ode ch an ges to th e h eavy load protection

m ode in th e followin g case:

•

Wh en th e software ch an ges th e m ode to th e h eavy load

protection m ode (HLMOD = 1)

Based on th e operation of th e SVD circu it an d th e h eavy

load protection fu n ction , th e S1C6S3L7/ S1C6S3B7 obtain s

an operation su pply voltage as low as 0.9 V. See th e

electrical ch aracteristics for th e precision of voltage detec-

tion by th e SVD circu it.

In th e h eavy load protection m ode, th e in tern ally regu lated

voltage is gen erated by th e liqu id crystal driver su pply

ou tpu t, VL2, in order to operate th e in tern al circu it

(S1C6S3L7/ S1C6S3B7). Con sequ en tly, m ore cu rren t is

con su m ed in th e h eavy load protection m ode th an in th e

n orm al m ode. Un less n ecessary, do n ot select th e h eavy

load protection m ode with th e software.

Note Activation of the SVD circuit by software in the heavy load protec-

tion mode causes a malfunction. Avoid such activation if possible.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

Table 4.9.1 sh ows th e con trol bits an d th eir addresses for

Control of SVD c ir-

th e SVD circu it an d th e h eavy load protection fu n ction .

c uit a nd he a vy loa d

p rote c tion func tion

Table 4.9.1 Control bits for SVD circuit and heavy load protection function

Register

Address

0FAH

Comment

D3

D2

D1

D0

Name

SR

0

1

0

HLMOD

0

SVDDT SVDON

R R/W

HLMOD

Heavy

load

Normal

load

Heavy load protection mode register

R/W

0

Supply

voltage

low

Supply

voltage

normal

SVDDT

SVDON

0

Supply voltage detection data

ON

OFF

Supply voltage detection ON/OFF

HLMOD Heavy load protection mode on/off (0FAH D3)

Wh en 1 is written : Heavy load protection m ode on

Wh en 0 is written : Heavy load protection m ode off

Readin g: Valid

Wh en HLMOD is set to 1, th e IC en ters th e h eavy load

protection m ode, an d sam plin g con trol is execu ted for th e

tim e th e SVD circu it is on . Th e sam plin g tim in g is as fol-

lows:

Sam plin g in cycles of 2 Hz ou tpu t by th e oscillation circu it

wh ile HLMOD = 1 (sam plin g tim e is 122 µs in th e case of

fosc = 32.768 kHz).

Wh en SVD sam plin g is don e with HLMOD set to 1, th e

resu lts are written to th e SVDDT register with th e as follow-

in g tim in g:

Im m ediately on com pletion of sam plin g in cycles of 2 Hz

ou tpu t by th e oscillation circu it wh ile HLMOD = 1.

Con sequ en tly, after HLMOD is set to 1, th e n ew detected

resu lt is written in 2 Hz.

In th e h eavy load protection m ode, th e con su m ed cu rren t

becom es larger. Un less n ecessary, do n ot select th e h eavy

load protection m ode with th e software.

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SVDON SVD control on/off (0FAH D0)

Wh en 0 is written : SVD detection off

Wh en 1 is written : SVD detection on

Readin g:

Valid

Wh en th is bit is written , th e SVD detection on / off operation

is con trolled. Large cu rren t is drawn du rin g SVD detection ,

so keep SVD detection off except wh en n ecessary. Wh en

SVDON is set to 1, SVD detection is execu ted. As soon as

SVDON is reset to 0, th e detected resu lt is loaded in to th e

SVDDT register.

SVDDT SVD data (0FAH D1)

Wh en 0 is read:

Wh en 1 is read:

Su pply voltage ≥ Criteria voltage

Su pply voltage < Criteria voltage

Wh en SVDDT is 1, th e S1C6S3N7 en ters th e h eavy load

protection m ode. In th is m ode, th e detection operation of

th e SVD circu it is sam pled in 2 Hz cycles an d th e respective

detection resu lts are written to th e SVDDT register.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

4.10 Inte rrup t a nd HALT

Th e S1C6S3N7 Series provide th e followin g in terru pt set-

tin gs, each of wh ich is m askable.

Extern al in terru pt:

In tern al in terru pt:

In pu t in terru pt (on e)

Tim er in terru pt (on e)

Stopwatch in terru pt (on e)

To en able in terru pts, th e in terru pt flag m u st be set to 1 (EI)

an d th e n ecessary related in terru pt m ask registers m u st be

set to 1 (en able). Wh en an in terru pt occu rs, th e in terru pt

flag is au tom atically reset to 0 (DI) an d in terru pts after th at

are in h ibited.

Wh en a HALT in stru ction is in pu t, th e CPU operatin g clock

stops an d th e CPU en ters th e h alt state. Th e CPU is reacti-

vated from th e h alt state wh en an in terru pt requ est occu rs.

Figu re 4.10.1 sh ows th e con figu ration of th e in terru pt

circu it.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Interrupt vector

(MSB)

:

Program counter of CPU

:

(three low-order bits)

K00

(LSB)

EIK00

K01

INT

EIK01

(Interrupt request)

IK0

K02

EIK02

K03

EIK03

ISW0

EISW0

ISW1

EISW1

IT2

Interrupt factor flag

EIT2

Interrupt mask register

IT8

EIT8

IT32

EIT32

Fig. 4.10.1 Configuration of interrupt circuit

S1C6S3N7 TECHNICAL HARDWARE

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Table 4.10.1 sh ows th e factors th at gen erate in terru pt

Inte rrup t fa c tors

requ ests.

Th e in terru pt factor flags are set to 1 depen din g on th e

correspon din g in terru pt factors.

Th e CPU is in terru pted wh en th e followin g two con dition s

occu r an d an in terru pt factor flag is set to 1.

• Th e correspon din g m ask register is 1 (en abled)

• Th e in terru pt flag is 1 (EI)

Th e in terru pt factor flag is a read-on ly register, bu t can be

reset to 0 wh en th e register data is read.

After an in itial reset, th e in terru pt factor flags are reset to 0.

Note Reading of interrupt factor flags is available at EI, but be careful in

the following cases.

If the interrupt mask register value corresponding to the interrupt

factor flags to be read is set to 1, an interrupt request will be

generated by the interrupt factor flags set timing, or an interrupt

request will not be generated. Be very careful when interrupt factor

flags are in the same address.

Table 4.10.1

Interrupt factors

Interrupt Factor

Colck timer 2 Hz falling edge

Colck timer 8 Hz falling edge

Colck timer 32 Hz falling edge

Stopwatch timer

Interrupt Factor Flag

IT2

(0EFH D2)

(0EFH D1)

(0EFH D0)

IT8

IT32

ISW1

ISW0

IK0

(0EEH D1)

(0EEH D0)

(0EDH D0)

1 Hz falling edge

Stopwatch timer

10 Hz falling edge

Input data (K00–K03)

rising edge

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S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Th e in terru pt factor flags can be m asked by th e correspon d-

in g in terru pt m ask registers. Th e in terru pt m ask registers

are read/ write registers. Th ey are en abled (in terru pt en -

abled) wh en 1 is written to th em , an d m asked (in terru pt

disabled) wh en 0 is written to th em . After an in itial reset,

th e in terru pt m ask register is set to 0.

Sp e c ific m a sks a nd

fa c tor fla g s for inte r-

rup t

Table 4.10.2 sh ows th e correspon den ce between in terru pt

m ask registers an d in terru pt factor flags.

Table 4.10.2

Interrupt mask registers and

interrupt factor flags

Interrupt Mask Register

Interrupt Factor Flag

EIT2

(0EBH D2)

(0EBH D1)

(0EBH D0)

(0EAH D1)

(0EAH D0)

(0E8H D3)

(0E8H D2)

(0E8H D1)

(0E8H D0)

IT2

(0EFH D2)

(0EFH D1)

(0EFH D0)

(0EEH D1)

(0EEH D0)

EIT8

IT8

EIT32

EISW1

EISW0

EIK03*

EIK02*

EIK01*

EIK00*

IT32

ISW1

ISW0

IK0

(0EDH D0)

* Th ere is an in terru pt m ask register for each in pu t port pin .

S1C6S3N7 TECHNICAL HARDWARE

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Wh en an in terru pt requ est is in pu t to th e CPU, th e CPU

Inte rrup t ve c tors

begin s in terru pt processin g. After th e program bein g exe-

cu ted is su spen ded, in terru pt processin g is execu ted in th e

followin g order:

➀ Th e address data (valu e of th e program cou n ter) of th e

program step to be execu ted n ext is saved on th e stack

(RAM).

➀ Th e in terru pt requ est cau ses th e valu e of th e in terru pt

vector (page 1, 01H–07H) to be loaded in to th e program

cou n ter.

➀ Th e program at th e specified address is execu ted (execu -

tion of in terru pt processin g rou tin e).

Note

The processing in steps 1 and 2, above, takes 12 cycles of the

CPU system clock.

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S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Tables 4.10.3 (a) an d (b) sh ows th e in terru pt con trol bits

an d th eir addresses.

Control of inte rrup t

Table 4.10.3 (a) Interrupt control bits (1)

Register

Address

Comment

D3

D2

D1

D0

Name

EIK03

SR

0

1

0

Enable

Mask

EIK03

EIK02

EIK01

EIK00

Interrupt mask register (K03)

Interrupt mask register (K02)

Interrupt mask register (K01)

Interrupt mask register (K00)

Enable

Mask

R/W

EIK02

EIK01

EIK00

0

0E8H

0EAH

0EBH

0EDH

0

EIT2

0

EISW1

EISW0

EIT32

IK0

0

R

R/W

EISW1

EISW0

0

Enable

Mask

Interrupt mask register (stopwatch 1 Hz)

Interrupt mask register (stopwatch 10 Hz)

0

EIT8

R/W

0

EIT2

EIT8

EIT32

0

R

0

Enable

Mask

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

0

R

0

IK0

0

Yes

No

Interrupt factor flag (K00–K03)

S1C6S3N7 TECHNICAL HARDWARE

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Table 4.10.3 (b) Interrupt control bits (2)

Register

Address

Comment

D3

D2

D1

D0

Name

0

SR

1

0

ISW1

ISW0

0

R

0EEH

ISW1

ISW0

0

Yes

No

Interrupt factor flag (stopwatch 1 Hz)

Interrupt factor flag (stopwatch 10 Hz)

0

IT2

IT8

IT32

R

IT2

0

Yes

No

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

0EFH

IT8

IT32

EIT32, EIT8, EIT2 Interrupt mask registers (0EBH D0–D2)

IT32, IT8, IT2 Interrupt factor flags (0EFH D0–D2)

See 4.7, "Clock Tim er".

EISW0, EISW1 Interrupt mask registers (0EAH D0–D1)

ISW0, ISW1 Interrupt factor flags (0EEH D0–D1)

See 4.8, "Stopwatch Tim er".

EIK00–EIK03 Interrupt mask registers (0E8H)

IK0 Interrupt factor flag (0EDH D0)

See 4.3, "In pu t Ports".

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S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM

CHAPTER 5

BASIC EXTERNAL WIRING DIAGRAM

(1) Pie zo Buzze r Sing le Te rm ina l Driving

(Whe n LCD syste m re g ula te d volta g e c irc uit is use d )

LCD

PANEL

CA

K00

C1

CB

I

Connection depending

on power supply and

LCD panel specification.

Please refer to pages

I-7 to I-9.

V

L1

L2

L3

K03

P00

P03

VDD

I/O

CG

OSC1

X'tal

OSC2

1.5 V

or

3.0 V

C5

VS1

RESET

TEST

R00

R02

R03

Cp

O

VSS

Piezo

Buzzer

Coil

X'tal

Crystal oscillator

Trimmer capacitor

Capacitor

32.768 kHz CI(MAX) = 35 kΩ

CG

5–25 pF

0.1 µF

3.3 µF

C1–C

5

Cp

Capacitor

S1C6S3N7 TECHNICAL HARDWARE

EPSON

I-71

CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM

(2) Pie zo Buzze r Dire c t Driving

(Whe n LCD syste m re g ula te d volta g e c irc uit is use d )

LCD

PANEL

CA

K00

K03

P00

P03

C1

CB

I

Connection depending

on power supply and

LCD panel specification.

Please refer to pages

I-7 to I-9.

V

L1

L2

L3

V

DD

I/O

CG

OSC1

X'tal

OSC2

1.5 V

or

3.0 V

C5

V

S1

RESET

TEST

Cp

R02

R03

O

V

SS

Piezo

Buzzer

X'tal

Crystal oscillator

Trimmer capacitor

Capacitor

32.768 kHz CI(MAX) = 35 kΩ

CG

5–25 pF

0.1 µF

3.3 µF

C1–C5

Cp

Capacitor

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S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 6: ELECTRICAL CHARACTERISTICS

CHAPTER 6

ELECTRICAL CHARACTERISTICS

6.1 Ab solute Ma xim um Ra ting

(VDD=0V)

Item

Power voltage

Input voltage (1)

Symbol

Rated Value

-5.0 to 0.5

Vss-0.3 to 0.5

10

Unit

V

SS

I

Input voltage (2)

IOSC

V

*1

Permissible total output current

Operating temperature

Storage temperature

Soldering temperature / Time

Allowable dissipation

∑IVSS

Topr

Tstg

mA

°C

–

-20 to 70

-65 to 150

260°C, 10sec (lead section)

250

Tsol

*2

PD

mW

1 Th e perm issible total ou tpu t cu rren t is th e su m total of th e

cu rren t (average cu rren t) th at sim u ltan eou sly flows from th e

ou tpu t pin s (or is draw in ).

2 In case of QFP6-60pin plastic package

S1C6S3N7 TECHNICAL HARDWARE

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CHAPTER 6: ELECTRICAL CHARACTERISTICS

6.2 Re c om m e nd e d Op e ra ting Cond itions

S1 C6 S3 N7

(Ta=-20 to 70°C)

Item

Symbol

Condition

DD=0V

Min

-3.6

Typ

-3.0

Max

-1.8

Unit

V

Power voltage

VSS

V

Oscillation frequency

f

OSC1 Crystal oscillation

OSC2 CR oscillation, R=470kΩ

32.768

65

kHz

µF

50

0.1

80

Booster capacitor

C1

C2

C3

C4

C5

Capacitor between VDD and VL1

Capacitor between VDD and VL2

Capacitor between VDD and VL3

Capacitor between VDD and VS1

µF

S1 C6 S3 L7

(Ta=-20 to 70°C)

Item

Symbol

Condition

Min

-2.0

Typ

-1.5

Max

-1.1

Unit

V

3

Power voltage

VSS

V

DD=0V

2

-0.9

1

With software control

OSC1 Crystal oscillation

Oscillation frequency

f

32.768

65

kHz

µF

OSC2 CR oscillation, R=470kΩ

50

0.1

80

Booster capacitor

C1

C2

C3

C4

C5

Capacitor between VDD and VL1

Capacitor between VDD and VL2

Capacitor between VDD and VL3

Capacitor between VDD and VS1

µF

1 Wh en th e h eavy load protection m ode is set by software an d th e SVD circu it is

tu rn ed OFF. Can n ot be operated wh en th e CR oscillation circu it is u sed.

(For details, refer to Section 4.9).

2 Th e voltage wh ich can be displayed on th e LCD pan el will differ accordin g to th e

ch aracteristics of th e LCD pan el.

3 Wh en th ere is n o software con trol du rin g CR oscillation or crystal oscillation .

I-74

EPSON

S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1 C6 S3 B7

(Ta=-20 to 70°C)

Item

Symbol

Condition

Min

-3.6

Typ

-1.5

Max

-1.1

Unit

V

3

Power voltage

VSS

V

DD=0V

2

-0.9

1

With software control

OSC1 Crystal oscillation

Oscillation frequency

f

32.768

65

kHz

µF

OSC2 CR oscillation, R=470kΩ

50

0.1

80

Booster capacitor

C1

C2

C3

C4

C5

Capacitor between VDD and VL1

Capacitor between VDD and VL2

Capacitor between VDD and VL3

Capacitor between VDD and VS1

µF

1 Wh en th e h eavy load protection m ode is set by software an d th e SVD circu it is

tu rn ed OFF. Can n ot be operated wh en th e CR oscillation circu it is u sed.

(For details, refer to Section 4.9).

2 Th e voltage wh ich can be displayed on th e LCD pan el will differ accordin g to th e

ch aracteristics of th e LCD pan el.

3 Wh en th ere is n o software con trol du rin g CR oscillation or crystal oscillation .

S1C6S3N7 TECHNICAL HARDWARE

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I-75

CHAPTER 6: ELECTRICAL CHARACTERISTICS

6.3 DC Cha ra c te ristic s

S1 C6 S3 N7 / S1 C6 S3 B7

Un less oth erwise specified

VDD=0 V, VSS=-3.0 V, fosc=32.768 kHz, Ta=25°C, VS1, VL1, VL2 an d VL3 are in tern al

voltages, an d C1=C2=C3=C4=C5=0.1 µF

Item

Symbol

Condition

Min

0.2•Vss

0.15•Vss

Vss

Typ

Max

Unit

V

High level input voltage (1)

High level input voltage (2)

Low level input voltage (1)

Low level input voltage (2)

High level input current (1)

High level input current (2)

High level input current (3)

Low level input current

VIH1

VIH2

VIL1

VIL2

K00–K03, P00–P03

RESET

0

V

K00–K03, P00–P03

RESET

0.8•Vss

0.85•Vss

0.5

V

Vss

V

I

IH1

V

IH1=0V Without pull down resistor

IH2=0V With pull down resistor

IH3=0V With pull down resistor

IL=VSS

K00–K03, P00–P03

K00–K03

0

µA

IH2

10

40

IH3

IL

P00–P03, RESET

K00–K03, P00–P03,

RESET, TEST

R02, R03, P00–P03

30

100

-0.5

0

High level output current (1)

High level output current (2)

Low level output current (1)

Low level output current (2)

Common output current

IOH1

IOH2

IOL1

IOL2

IOH3

IOL3

IOH4

IOL4

IOH5

IOL5

V

OH1=0.1•VSS

-1.0

mA

µA

OH2=0.1•VSS (built-in protection resistance) R00, R01

OL1=0.9•VSS

R02, R03, P00–P03

3.0

OL2=0.9•VSS (built-in protection resistance) R00, R01

OH3=-0.05V

COM0–COM3

-3

OL3=VL3+0.05V

OH4=-0.05V

3

Segment output current

(during LCD output)

Segment output current

(during DC output)

SEG0–SEG25

OL4=VL3+0.05V

OH5=0.1•VSS

OL5=0.9•VSS

-300

300

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S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1 C6 S3 L7

Un less oth erwise specified

VDD=0 V, VSS=-1.5 V, fosc=32.768 kHz, Ta=25°C, VS1, VL1, VL2 an d VL3 are in tern al

voltages, an d C1=C2=C3=C4=C5=0.1 µF

Item

Symbol

Condition

Min

0.2•Vss

0.15•Vss

Vss

Typ

Max

Unit

V

High level input voltage (1)

High level input voltage (2)

Low level input voltage (1)

Low level input voltage (2)

High level input current (1)

High level input current (2)

High level input current (3)

Low level input current

VIH1

VIH2

VIL1

VIL2

K00–K03, P00–P03

RESET

0

V

K00–K03, P00–P03

RESET

0.8•Vss

0.85•Vss

0.5

V

Vss

V

I

IH1

V

IH1=0V Without pull down resistor

IH2=0V With pull down resistor

IH3=0V With pull down resistor

IL=VSS

K00–K03, P00–P03

K00–K03

0

µA

IH2

5.0

20

IH3

IL

P00–P03, RESET

K00–K03, P00–P03,

RESET, TEST

R02, R03, P00–P03

9.0

100

-0.5

0

High level output current (1)

High level output current (2)

Low level output current (1)

Low level output current (2)

Common output current

IOH1

IOH2

IOL1

IOL2

IOH3

IOL3

IOH4

IOL4

IOH5

IOL5

V

OH1=0.1•VSS

-200

µA

OH2=0.1•VSS (built-in protection resistance) R00, R01

OL1=0.9•VSS

R02, R03, P00–P03

700

OL2=0.9•VSS (built-in protection resistance) R00, R01

OH3=-0.05V

COM0–COM3

-3

OL3=VL3+0.05V

OH4=-0.05V

3

Segment output current

(during LCD output)

Segment output current

(during DC output)

SEG0–SEG25

OL4=VL3+0.05V

OH5=0.1•VSS

OL5=0.9•VSS

-100

130

S1C6S3N7 TECHNICAL HARDWARE

EPSON

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CHAPTER 6: ELECTRICAL CHARACTERISTICS

6.4 Ana log Circ uit Cha ra c te ristic s a nd Powe r Curre nt Con-

sum p tion

S1 C6 S3 N7 (Norm al Operat in g Mode)

Un less oth erwise specified

VDD=0 V, VSS=-3.0 V, fosc=32.768 kHz (crystal oscillation ), Ta=25°C, CG=25 pF,

VS1, VL1, VL2 an d VL3 are in tern al voltages, an d C1=C2=C3=C4=C5=0.1 µF

Item

Symbol

Condition

Min

Typ

Max

Unit

Internal voltage

V

L1

Connect 1MΩ load resistor between VDD and VL1 1/2•VL2

1/2•VL2

V

(without panel load)

-0.1

× 0.9

L2

Connect 1MΩ load resistor between VDD and VL2

(without panel load)

-2.25

-2.10

-1.95

V

L3

Connect 1MΩ load resistor between VDD and VL3 3/2•VL2

3/2•VL2

(without panel load)

-0.1

× 0.9

SVD voltage

SVD

-2.55

-2.40

-2.25

100

2.5

V

µs

SVD circuit response time

Power current

t

SVD

I

OP

During HALT

1.0

2.5

µA

Without panel load

1

consumption

During execution

5.0

1 Th e SVD circu it is tu rn ed OFF.

S1 C6 S3 N7 (Heavy Load Prot ect ion Mode)

Un less oth erwise specified

VDD=0 V, VSS=-3.0 V, fosc=32.768 kHz (crystal oscillation ), Ta=25°C, CG=25 pF,

VS1, VL1, VL2 an d VL3 are in tern al voltages, an d C1=C2=C3=C4=C5=0.1 µF

Item

Symbol

Condition

Min

Typ

Max

Unit

Internal voltage

V

L1

Connect 1MΩ load resistor between VDD and VL1 1/2•VL2

1/2•VL2

V

(without panel load)

-0.1

× 0.85

L2

Connect 1MΩ load resistor between VDD and VL2

(without panel load)

-2.25

-2.10

-1.95

V

L3

Connect 1MΩ load resistor between VDD and VL3 3/2•VL2

3/2•VL2

(without panel load)

-0.1

× 0.85

SVD voltage

SVD

-2.55

-2.40

-2.25

100

5.5

V

µs

SVD circuit response time

Power current

t

SVD

I

OP

During HALT

2.0

5.5

µA

Without panel load

1

consumption

During execution

10.0

1 Th e SVD circu it is tu rn ed OFF.

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S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1 C6 S3 L7 (Norm al Operat in g Mode)

Un less oth erwise specified

VDD=0 V, VSS=-1.5 V, fosc=32.768 kHz (crystal oscillation ), Ta=25°C, CG=25 pF,

VS1, VL1, VL2 an d VL3 are in tern al voltages, an d C1=C2=C3=C4=C5=0.1 µF

Item

Symbol

Condition

Min

Typ

Max

Unit

Internal voltage

V

L1

Connect 1MΩ load resistor between VDD and VL1

(without panel load)

-1.15

-1.05

-0.95

V

L2

Connect 1MΩ load resistor between VDD and VL2

(without panel load)

2•VL1

-0.1

2•VL1

V

×

0.9

3•VL1

0.9

L3

Connect 1MΩ load resistor between VDD and VL3

(without panel load)

3•VL1

-0.1

×

SVD voltage

SVD

-1.30

-1.20

-1.10

100

2.5

V

µs

SVD circuit response time

Power current

t

SVD

I

OP

During HALT

1.0

2.5

µA

Without panel load

1

consumption

During execution

5.0

1 Th e SVD circu it is tu rn ed OFF.

S1 C6 S3 L7 (Heavy Load Prot ect ion Mode)

Un less oth erwise specified

VDD=0 V, VSS=-1.5 V, fosc=32.768 kHz (crystal oscillation ), Ta=25°C, CG=25 pF,

VS1, VL1, VL2 an d VL3 are in tern al voltages, an d C1=C2=C3=C4=C5=0.1 µF

Item

Symbol

Condition

Min

Typ

Max

Unit

Internal voltage

V

L1

Connect 1MΩ load resistor between VDD and VL1

(without panel load)

-1.15

-1.05

-0.95

V

L2

Connect 1MΩ load resistor between VDD and VL2

(without panel load)

2•VL1

-0.1

2•VL1

V

×

0.85

3•VL1

0.85

L3

Connect 1MΩ load resistor between VDD and VL3

(without panel load)

3•VL1

-0.1

×

SVD voltage

SVD

-1.30

-1.20

-1.10

100

5.5

V

µs

SVD circuit response time

Power current

t

SVD

I

OP

During HALT

2.0

5.5

µA

Without panel load

1

consumption

During execution

10.0

1 Th e SVD circu it is tu rn ed OFF.

S1C6S3N7 TECHNICAL HARDWARE

EPSON

I-79

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1 C6 S3 B7 (Norm al Operat in g Mode)

Un less oth erwise specified

VDD=0 V, VSS=-3.0 V, fosc=32.768 kHz (crystal oscillation ), Ta=25°C, CG=25 pF,

VS1, VL1, VL2 an d VL3 are in tern al voltages, an d C1=C2=C3=C4=C5=0.1 µF

Item

Symbol

Condition

Min

Typ

Max

Unit

Internal voltage

V

L1

Connect 1MΩ load resistor between VDD and VL1

(without panel load)

-1.15

-1.05

-0.95

V

L2

Connect 1MΩ load resistor between VDD and VL2

(without panel load)

2•VL1

-0.1

2•VL1

V

×

0.9

3•VL1

0.9

L3

Connect 1MΩ load resistor between VDD and VL3

(without panel load)

3•VL1

-0.1

×

SVD voltage

SVD

-1.30

-1.20

-1.10

100

2.5

V

µs

SVD circuit response time

Power current

t

SVD

I

OP

During HALT

1.0

2.5

µA

Without panel load

1

consumption

During execution

5.0

1 Th e SVD circu it is tu rn ed OFF.

S1 C6 S3 B7 (Heavy Load Prot ect ion Mode)

Un less oth erwise specified

VDD=0 V, VSS=-3.0 V, fosc=32.768 kHz (crystal oscillation ), Ta=25°C, CG=25 pF,

VS1, VL1, VL2 an d VL3 are in tern al voltages, an d C1=C2=C3=C4=C5=0.1 µF

Item

Symbol

Condition

Min

Typ

Max

Unit

Internal voltage

V

L1

Connect 1MΩ load resistor between VDD and VL1

(without panel load)

-1.15

-1.05

-0.95

V

L2

Connect 1MΩ load resistor between VDD and VL2

(without panel load)

2•VL1

-0.1

2•VL1

V

×

0.85

3•VL1

0.85

L3

Connect 1MΩ load resistor between VDD and VL3

(without panel load)

3•VL1

-0.1

×

SVD voltage

SVD

-1.30

-1.20

-1.10

100

5.5

V

µs

SVD circuit response time

Power current

t

SVD

I

OP

During HALT

2.0

5.5

µA

Without panel load

1

consumption

During execution

10.0

1 Th e SVD circu it is tu rn ed OFF.

I-80

EPSON

S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1 C6 S3 N7 (CR, Norm al Operat in g Mode)

Un less oth erwise specified

VDD=0 V, VSS=-3.0 V, fosc=65 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 an d VL3 are

in tern al voltages, an d C1=C2=C3=C4=C5=0.1 µF, Recom m en ded extern al resistan ce

for CR oscillation =470 kΩ

Item

Symbol

Condition

Min

Typ

Max

Unit

Internal voltage

V

L1

Connect 1MΩ load resistor between VDD and VL1 1/2•VL2

1/2•VL2

V

(without panel load)

-0.1

× 0.9

L2

Connect 1MΩ load resistor between VDD and VL2

(without panel load)

-2.25

-2.10

-1.95

V

L3

Connect 1MΩ load resistor between VDD and VL3 3/2•VL2

3/2•VL2

(without panel load)

-0.1

× 0.9

SVD voltage

SVD

-2.55

-2.40

-2.25

100

V

µs

SVD circuit response time

Power current

t

SVD

I

OP

During HALT

8.0

15.0

20.0

µA

Without panel load

1

consumption

During execution

15.0

1 Th e SVD circu it is tu rn ed OFF.

S1 C6 S3 N7 (CR, Heavy Load Prot ect ion Mode)

Un less oth erwise specified

VDD=0 V, VSS=-3.0 V, fosc=65 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 an d VL3 are

in tern al voltages, an d C1=C2=C3=C4=C5=0.1 µF, Recom m en ded extern al resistan ce

for CR oscillation =470 kΩ

Item

Symbol

Condition

Min

Typ

Max

Unit

Internal voltage

V

L1

Connect 1MΩ load resistor between VDD and VL1 1/2•VL2

1/2•VL2

V

(without panel load)

-0.1

× 0.85

L2

Connect 1MΩ load resistor between VDD and VL2

(without panel load)

-2.25

-2.10

-1.95

V

L3

Connect 1MΩ load resistor between VDD and VL3 3/2•VL1

3/2•VL1

(without panel load)

-0.1

× 0.85

SVD voltage

SVD

-2.55

-2.40

-2.25

100

V

µs

SVD circuit response time

Power current

t

SVD

I

OP

During HALT

16.0

30.0

40.0

µA

Without panel load

1

consumption

During execution

1 Th e SVD circu it is tu rn ed OFF.

S1C6S3N7 TECHNICAL HARDWARE

EPSON

I-81

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1 C6 S3 L7 (CR, Norm al Operat in g Mode)

Un less oth erwise specified

VDD=0 V, VSS=-1.5 V, fosc=65 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 an d VL3 are

in tern al voltages, an d C1=C2=C3=C4=C5=0.1 µF, Recom m en ded extern al resistan ce

for CR oscillation =470 kΩ

Item

Symbol

Condition

Min

Typ

Max

Unit

Internal voltage

V

L1

Connect 1MΩ load resistor between VDD and VL1

(without panel load)

-1.15

-1.05

-0.95

V

L2

Connect 1MΩ load resistor between VDD and VL2

(without panel load)

2•VL1

-0.1

2•VL1

V

×

0.9

3•VL1

0.9

L3

Connect 1MΩ load resistor between VDD and VL3

(without panel load)

3•VL1

-0.1

×

SVD voltage

SVD

-1.30

-1.20

-1.10

100

V

µs

SVD circuit response time

Power current

t

SVD

I

OP

During HALT

8.0

15.0

20.0

µA

Without panel load

1

consumption

During execution

15.0

1 Th e SVD circu it is tu rn ed OFF.

S1 C6 S3 L7 (CR, Heavy Load Prot ect ion Mode)

Un less oth erwise specified

VDD=0 V, VSS=-1.5 V, fosc=65 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 an d VL3 are

in tern al voltages, an d C1=C2=C3=C4=C5=0.1 µF, Recom m en ded extern al resistan ce

for CR oscillation =470 kΩ

Item

Symbol

Condition

Min

Typ

Max

Unit

Internal voltage

V

L1

Connect 1MΩ load resistor between VDD and VL1

(without panel load)

-1.15

-1.05

-0.95

V

L2

Connect 1MΩ load resistor between VDD and VL2

(without panel load)

2•VL1

-0.1

2•VL1

V

×

0.85

3•VL1

0.85

L3

Connect 1MΩ load resistor between VDD and VL3

(without panel load)

3•VL1

-0.1

×

SVD voltage

SVD

-1.30

-1.20

-1.10

100

V

µs

SVD circuit response time

Power current

t

SVD

I

OP

During HALT

16.0

30.0

40.0

µA

Without panel load

1

consumption

During execution

1 Th e SVD circu it is tu rn ed OFF.

I-82

EPSON

S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1 C6 S3 B7 (CR, Norm al Operat in g Mode)

Un less oth erwise specified

VDD=0 V, VSS=-3.0 V, fosc=65 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 an d VL3 are

in tern al voltages, an d C1=C2=C3=C4=C5=0.1 µF, Recom m en ded extern al resistan ce

for CR oscillation =470 kΩ

Item

Symbol

Condition

Min

Typ

Max

Unit

Internal voltage

V

L1

Connect 1MΩ load resistor between VDD and VL1

(without panel load)

-1.15

-1.05

-0.95

V

L2

Connect 1MΩ load resistor between VDD and VL2

(without panel load)

2•VL1

-0.1

2•VL1

V

×

0.9

3•VL1

0.9

L3

Connect 1MΩ load resistor between VDD and VL3

(without panel load)

3•VL1

-0.1

×

SVD voltage

SVD

-1.30

-1.20

-1.10

100

V

µs

SVD circuit response time

Power current

t

SVD

I

OP

During HALT

8.0

15.0

20.0

µA

Without panel load

1

consumption

During execution

15.0

1 Th e SVD circu it is tu rn ed OFF.

S1 C6 S3 B7 (CR, Heavy Load Prot ect ion Mode)

Un less oth erwise specified

VDD=0 V, VSS=-3.0 V, fosc=65 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 an d VL3 are

in tern al voltages, an d C1=C2=C3=C4=C5=0.1 µF, Recom m en ded extern al resistan ce

for CR oscillation =470 kΩ

Item

Symbol

Condition

Min

Typ

Max

Unit

Internal voltage

V

L1

Connect 1MΩ load resistor between VDD and VL1

(without panel load)

-1.15

-1.05

-0.95

V

L2

Connect 1MΩ load resistor between VDD and VL2

(without panel load)

2•VL1

-0.1

2•VL1

V

×

0.85

3•VL1

0.85

L3

Connect 1MΩ load resistor between VDD and VL3

(without panel load)

3•VL1

-0.1

×

SVD voltage

SVD

-1.30

-1.20

-1.10

100

V

µs

SVD circuit response time

Power current

t

SVD

I

OP

During HALT

16.0

30.0

40.0

µA

Without panel load

1

consumption

During execution

1 Th e SVD circu it is tu rn ed OFF.

S1C6S3N7 TECHNICAL HARDWARE

EPSON

I-83

CHAPTER 6: ELECTRICAL CHARACTERISTICS

6.5 Osc illa tion Cha ra c te ristic s

Oscillation ch aracteristics will vary accordin g to differen t con dition s. Use th e

followin g ch aracteristics are as referen ce valu es.

S1 C6 S3 N7

Un less oth erwise specified

VDD=0 V, VSS=-3.0 V, Crystal : Q13MC146, CG=25 pF, CD=bu ilt-in , Ta=25°C

Item

Oscillation start

voltage

Symbol

Condition

Min

-1.8

Typ Max Unit

Vsta tsta≤5sec

(Vss)

V

Oscillation stop

voltage

Vstp tstp≤10sec

(Vss)

-1.8

V

Built-in capacity (drain)

C

D

Including the parasitic capacity inside the IC

Vss=-1.8 to -3.6V

20

pF

ppm

V

Frequency voltage deviation f/V

Frequency IC deviation f/I

Frequency adjustment range f/C

Higher harmonic oscillation

start voltage

5

10

C

-10

40

G

CG=5–25pF

V

hho

CG=5pF

-3.6

(Vss)

leak Between OSC1 and VDD

Allowable leak resistance

R

200

MΩ

S1 C6 S3 L7

Un less oth erwise specified

VDD=0 V, VSS=-1.5 V, Crystal : Q13MC146, CG=25 pF, CD=bu ilt-in , Ta=25°C

Item

Oscillation start

voltage

Symbol

Condition

Min

-1.1

Typ Max Unit

Vsta tsta≤5sec

(Vss)

V

Oscillation stop

voltage

Vstp tstp≤10sec

(Vss)

-1.1

(-0.9)

V

1

Built-in capacity (drain)

C

D

Including the parasitic capacity inside the IC

20

pF

ppm

V

1

Frequency voltage deviation f/V

Frequency IC deviation f/I

Frequency adjustment range f/C

Higher harmonic oscillation

start voltage

Vss=-1.1 to -2.0V (-0.9)

5

10

C

-10

40

G

CG=5–25pF

V

hho

CG=5pF

-2.0

(Vss)

leak Between OSC1 and VDD

Allowable leak resistance

R

200

MΩ

1 Item s en closed in paren th eses ( ) are th ose u sed wh en operatin g at h eavy load

protection m ode.

I-84

EPSON

S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1 C6 S3 B7

Un less oth erwise specified

VDD=0 V, VSS=-3.0 V, Crystal : Q13MC146, CG=25 pF, CD=bu ilt-in , Ta=25°C

Item

Oscillation start

voltage

Oscillation stop

voltage

Symbol

Vsta

(Vss)

Vstp

Condition

Min

-1.1

Typ Max Unit

t

sta≤5sec

V

stp≤10sec

-1.1

(-0.9)

V

1

(Vss)

Built-in capacity (drain)

C

D

Including the parasitic capacity inside the IC

20

pF

ppm

V

1

Frequency voltage deviation f/V

Frequency IC deviation f/I

Frequency adjustment range f/C

Higher harmonic oscillation

start voltage

Vss=-1.1 to -3.6V (-0.9)

5

10

C

-10

40

G

C

G

=5–25pF

V

hho

G=5pF

-3.6

(Vss)

leak Between OSC1 and VDD

Allowable leak resistance

R

200

MΩ

1 Item s en closed in paren th eses ( ) are th ose u sed wh en operatin g at h eavy load

protection m ode.

S1C6S3N7 TECHNICAL HARDWARE

EPSON

I-85

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1 C6 S3 N7 (CR)

Un less oth erwise specified

VDD=0 V, VSS=-3.0 V, RCR=470 kΩ, Ta=25°C

Item

Symbol

fosc

Vsta

Condition

Min

-20

-1.8

Typ

65kHz

Max

20

Unit

%

V

ms

V

Oscillation frequency dispersion

Oscillation start voltage

Oscillation start time

t

sta Vss=-1.8 to -3.6V

Vstp

3

Oscillation stop voltage

-1.8

S1 C6 S3 L7 (CR)

Un less oth erwise specified

VDD=0 V, VSS=-1.5 V, RCR=470 kΩ, Ta=25°C

Item

Symbol

fosc

Vsta

Condition

Min

-20

-1.1

Typ

65kHz

Max

20

Unit

%

V

ms

V

Oscillation frequency dispersion

Oscillation start voltage

Oscillation start time

t

sta Vss=-1.1 to -2.0V

Vstp

3

Oscillation stop voltage

-1.1

S1 C6 S3 B7 (CR)

Un less oth erwise specified

VDD=0 V, VSS=-3.0 V, RCR=470 kΩ, Ta=25°C

Item

Symbol

fosc

Vsta

Condition

Min

-20

-1.1

Typ

65kHz

Max

20

Unit

%

V

ms

V

Oscillation frequency dispersion

Oscillation start voltage

Oscillation start time

t

sta Vss=-1.1 to -3.6V

Vstp

3

Oscillation stop voltage

-1.1

I-86

EPSON

S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 7: PACKAGE

CHAPTER 7

PACKAGE

7.1 Pla stic Pa c ka g e

QFP6-60pin

±0.4

±0.2

17.6

14.0

45

31

46

30

Index

60

16

1

15

±0.15

0.8

0.35

0~12°

0.8 ^±0.3

1.8

S1C6S3N7 TECHNICAL HARDWARE

EPSON

I-87

CHAPTER 7: PACKAGE

7.2 Ce ra m ic Pa c ka g e for Te st Sa m p le s

QFP6-60pin

±0.3

17.00

±0.15

13.97

45

31

46

30

Index

60

16

1

15

±0.1

0.80

0.35 ^±0.1

0~12°

0.70 ^±0.1

1.515 ^±0.30

I-88

EPSON

S1C6S3N7 TECHNICAL HARDWARE

CHAPTER 8: PAD LAYOUT

CHAPTER 8

PAD LAYOUT

8.1 Dia g ra m of Pa d La yout

10

5

1

15

50

Y

20

X

(0, 0)

25

45

30

35

40

Chip size: 3,090 µm (X) x 3,020 µm (Y)

S1C6S3N7 TECHNICAL HARDWARE

EPSON

I-89

CHAPTER 8: PAD LAYOUT

8.2 Pa d Coord ina te s

Pad No Pad Name

X

Y

Pad No Pad Name

X

Y

1

COM3

SEG0

789

1,344

1,079

885

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

SEG25

P00

-1,378

-747

2

655

-1,245 -1,344

-1,114 -1,344

-984 -1,344

-854 -1,344

-703 -1,344

-568 -1,344

-438 -1,344

-308 -1,344

-177 -1,344

64 -1,344

3

SEG1

525

P01

4

SEG2

395

P02

5

SEG3

264

P03

6

SEG4

134

RESET

K00

K01

K02

K03

R00

7

SEG5

3

8

SEG6

-126

9

SEG7

-256

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

SEG8

-386

SEG9

-517

SEG10

SEG11

SEG12

TEST

-647

R01

193 -1,344

434 -1,344

564 -1,344

994 -1,344

1,121 -1,344

-778

R02

-908

R03

-1,378

VSS

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

VDD

755

OSC1

OSC2

1,378

-942

-789

-625

-65

624

494

VS1

364

CA

CB

234

65

103

VL1

VL2

VL3

561

-26

692

-157

-356

-486

-616

850

COM0

COM1

COM2

1,009

1,138

1,270

(Unit: µm)

I-90

EPSON

S1C6S3N7 TECHNICAL HARDWARE

S1C6S3N7

II. Technical Software

CONTENTS

CHAPTER 1

CONFIGURATION ........................................................... II-1

1.1 S1C6S3N7 Block Diagram ............................................. II-1

1.2 ROM Map ....................................................................... II-2

1.3 Interrupt Vectors ............................................................. II-3

1.4 Data Memory Map .......................................................... II-4

CHAPTER 2

CHAPTER 3

INITIAL RESET .................................................................. II-10

2.1 Internal Register Status on Initial Reset ........................ II-10

2.2 Initialize Program Example............................................ II-12

PERIPHERAL CIRCUITS .................................................... II-14

3.1 Input Ports ..................................................................... II-14

In pu t port m em ory m ap .......................................... II-14

Con trol of th e in pu t port ......................................... II-15

Exam ples of in pu t port con trol program .................. II-15

3.2 Output Ports .................................................................. II-17

Ou tpu t port m em ory m ap ........................................ II-17

Con trol of th e ou tpu t port ....................................... II-17

Exam ples of ou tpu t port con trol program ................ II-18

3.3 Special Use Output Ports .............................................. II-20

Special u se ou tpu t port m em ory m ap ...................... II-20

Con trol of th e special u se ou tpu t port ..................... II-21

Exam ples of special u se ou tpu t port

con trol program ...................................................... II-22

S1C6S3N7 TECHNICAL SOFTWARE

EPSON

II-i

CONTENTS

3.4 I/O Ports ........................................................................ II-24

I/ O port m em ory m ap ............................................. II-24

Con trol of th e I/ O port ............................................ II-25

Exam ples of I/ O port con trol program ..................... II-26

3.5 LCD Driver..................................................................... II-29

LCD driver m em ory m ap ......................................... II-29

Con trol of th e LCD driver ........................................ II-30

Exam ples of LCD driver con trol program ................. II-32

3.6 Timer ............................................................................. II-34

Tim er m em ory m ap ................................................. II-34

Con trol of th e tim er ................................................. II-35

Exam ples of tim er con trol program .......................... II-36

3.7 Stopwatch Timer ........................................................... II-38

Stopwatch tim er m em ory m ap ................................. II-38

Con trol of th e stopwatch tim er ................................ II-39

Exam ples of stopwatch tim er con trol program ......... II-40

3.8 Supply Voltage Detection (SVD) Circuit

and Heavy Load Protection Function ............................ II-42

SVD circu it an d h eavy load protection

fu n ction m em ory m ap ............................................. II-42

Con trol of th e SVD circu it ....................................... II-43

Exam ple of SVD circu it con trol program .................. II-43

Heavy load protection fu n ction ................................ II-44

Exam ples of h eavy load protection

fu n ction con trol program ......................................... II-46

3.9 Interrupt and Halt........................................................... II-49

In terru pt m em ory m ap ............................................ II-49

Con trol of in terru pts an d h alt ................................. II-51

Exam ples of in terru pt an d h alt con trol program ...... II-60

II-ii

EPSON

S1C6S3N7 TECHNICAL SOFTWARE

CONTENTS

CHAPTER 4

APPENDIX

SUMMARY OF PROGRAMMING POINTS....................... II-63

A

B

C

D

Table of Instructions ...................................................... II-67

The S1C6S3N7 I/O Memory Map ................................. II-72

Table of the ICE Commands ......................................... II-74

Cross-assembler Pseudo-instruction List ...................... II-76

S1C6S3N7 TECHNICAL SOFTWARE

EPSON

II-iii

CHAPTER 1: CONFIGURATION

CHAPTER 1

CONFIGURATION

1.1 S1C6S3N7 Bloc k Dia g ra m

System

Reset

Control

ROM

OSC

1,024x12

Core CPU S1C6200A

RAM

80x4

Interrupt

Generator

COM0

|

COM3

SEG0

|

K00~K03

TEST

LCD

Driver

I Port

Test Port

SEG25

V

DD

L1

|

L3

P00~P03

R00~R03

I/O Port

O Port

V

CA

Power

Controller

CB

V

S1

SS

SVD

Timer

(FOUT/BUZZER)

(BUZZER)

FOUT

&

BUZZER

Stop

Watch

Fig. 1.1.1

S1C6S3N7 block diagram

S1C6S3N7 TECHNICAL SOFTWARE

EPSON

II-1

CHAPTER 1: CONFIGURATION

1.2 ROM Ma p

Th e S1C6S3N7 h as a bu ilt-in m ask ROM with a capacity of

1,024 steps × 12 bits for program storage. Th e con figu ration

of th e ROM is sh own in Figu re 1.2.1.

Bank 0

00H step

01H step

Program start address

Interrupt vector area

0 page

1 page

2 page

3 page

07H step

08H step

Program area

FFH step

12 bits

Fig. 1.2.1

Configuration of built-in ROM

II-2

EPSON

S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 1: CONFIGURATION

1.3 Interrupt Vectors

Wh en an in terru pt requ est is received by th e CPU, th e CPU

in itiates th e followin g in terru pt processin g after com pletin g

th e in stru ction bein g execu ted.

(1) Th e address of th e n ext in stru ction to be execu ted (th e

valu e of th e program cou n ter) is saved on th e stack

(RAM).

(2) Th e in terru pt vector address correspon din g to th e in ter-

ru pt requ est is loaded in to th e program cou n ter.

(3) Th e bran ch in stru ction written in th e vector is execu ted

to bran ch to th e software in terru pt processin g rou tin e.

Note Steps 1 and 2 require 12 cycles of the CPU system clock.

Th e in terru pt vectors are sh own in Table 1.3.1.

Table 1.3.1

Page

Step

00H

01H

02H

03H

04H

05H

06H

07H

Interrupt Vector

Interrupt requests and vectors

Initial reset

Clock timer interrupt

Stopwatch interrupt

Clock timer interrupt and stopwatch interrupt

Input (K00–K03) interrupt

1

Input interrupt and clock timer interrupt

Input interrupt and stopwatch interrupt

Generation of all interrupt

Addesses (start address of in terru pt processin g rou tin es) to

ju m p to are written in to th e addresses available for in terru pt

vector allocation .

S1C6S3N7 TECHNICAL SOFTWARE

EPSON

II-3

CHAPTER 1: CONFIGURATION

1.4 Da ta Me m ory Ma p

Th e S1C6S3N7 bu ilt-in RAM h as 80 words of data m em ory,

32 words of display m em ory for th e LCD, an d I/ O m em ory

for con trollin g th e periph eral circu it. Wh en writin g pro-

gram s, n ote th e followin g:

(1) Sin ce th e stack area is in th e data m em ory area, take

care n ot to overwrite th e stack with data. Su brou tin e

calls or in terru pts u se 3 words on th e stack.

(2) Data m em ory addresses 000H–00FH are m em ory register

areas th at are addressed with register poin ter RP.

Address

Page

Low

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

High

0

M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF

1

2

RAM (80 words x 4 bits)

R/W

3

4

5

6

Unused area

7

0

8

9

Display memory

Unused area

I/O memory

A

B

C

D

E

F

Fig. 1.4.1

Data memory map

Note Memory is not mounted in unused area within the memory map

and in memory area not indicated in this chapter. For this reason,

normal operation cannot be assured for programs that have been

prepared with access to these areas.

II-4

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S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 1: CONFIGURATION

Table 1.4.1(a) I/O memory map 1

Register

Address

Comment

*1

*2

D3

D2

D1

D0

Name

K03

SR

–

1

0

High

Low

K03

K02

K01

K00

*2

High

Low

R

K02

K01

–

0E0H

0E2H

Input port (K00–K03)

K00

–

0

SWL3

SWH3

TM3

SWL2

SWH2

TM2

SWL1

SWH1

TM1

SWL0

SWH0

TM0

SWL3

MSB

SWL2

SWL1

SWL0

SWH3

SWH2

SWH1

SWH0

TM3

0

–

Stopwatch timer

1/100 sec (BCD)

LSB

MSB

Stopwatch timer

1/10 sec (BCD)

0E3H

LSB

High

Low

Timer data (clock timer 2 Hz)

Timer data (clock timer 4 Hz)

Timer data (clock timer 8 Hz)

Timer data (clock timer 16 Hz)

R

TM2

0E4H

TM1

TM0

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

S1C6S3N7 TECHNICAL SOFTWARE

EPSON

II-5

CHAPTER 1: CONFIGURATION

Table 1.4.1(b) I/O memory map 2

Register

Address

Comment

*1

D3

D2

D1

D0

Name

EIK03

SR

0

1

0

Enable

Mask

EIK03

EIK02

EIK01

EIK00

Interrupt mask register (K03)

Interrupt mask register (K02)

Interrupt mask register (K01)

Interrupt mask register (K00)

Enable

Mask

R/W

EIK02

EIK01

EIK00

0

0E8H

0EAH

0EBH

0EDH

*5

0

EIT2

0

EISW1

EISW0

EIT32

IK0

0

*5

0

R

R/W

EISW1

EISW0

0

Enable

Mask

Interrupt mask register (stopwatch 1 Hz)

Interrupt mask register (stopwatch 10 Hz)

*5

0

EIT8

R/W

0

R

EIT2

EIT8

0

Enable

Mask

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

EIT32

*5

0

*5

*4

R

0

IK0

0

Yes

No

Interrupt factor flag (K00–K03)

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

II-6

EPSON

S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 1: CONFIGURATION

Table 1.4.1(c) I/O memory map 3

Register

Address

Comment

*1

D3

D2

D1

D0

Name

SR

1

0

*5

0

ISW1

ISW0

0

*5

*4

R

0EEH

ISW1

0

Yes

No

Interrupt factor flag (stopwatch 1 Hz)

Interrupt factor flag (stopwatch 10 Hz)

*4

ISW0

*5

0

IT2

R02

P02

IT8

IT32

0

*4

R

IT2

IT8

IT32

0

Yes

No

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

0EFH

R01

R00

R03

R02

R01

0

High

ON

Low

OFF

Low

OFF

R03 output port data

R03

BUZZER

FOUT

R02 output port data

R/W

R01 output port data

0F3H

0F6H

BUZZER

R00

Buzzer ON/OFF control register

R00 output port data

High

ON

FOUT

Frequency output ON/OFF control register

*2

P03

P02

P01

P00

–

High

Low

P03

P01

P00

R/W

I/O port (P00–P03)

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

S1C6S3N7 TECHNICAL SOFTWARE

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II-7

CHAPTER 1: CONFIGURATION

Table 1.4.1(d) I/O memory map 4

Register

Address

Comment

*1

D3

D2

D1

D0

Name

SR

1

0

*5

0

TMRST SWRUN SWRST

0

TMRST

Reset

0

Reset

Run

–

Stop

–

Clock timer reset

R

W

R/W

W

0F9H

SWRUN

Stopwatch timer RUN/STOP

Stopwatch timer reset

*5

SWRST

Reset

0

HLMOD

R/W

0

SVDDT SVDON

R/W

HLMOD

Heavy

load

Normal

load

Heavy load protection mode register

*5

R

0

0FAH

0FBH

0FCH

Supply

voltage

low

Supply

voltage

normal

SVDDT

SVDON

CSDC

0

Supply voltage detection data

ON

OFF

Supply voltage detection ON/OFF

Static

Dynamic LCD drive switch

CSDC

R/W

0

*5

R

0

*5

0

IOC

R/W

0

R

IOC

0

Output

Input

I/O port P00–P03 Input/Output

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

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S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 1: CONFIGURATION

Table 1.4.1(e) I/O memory map 5

Register

Address

Comment

*1

D3

D2

D1

D0

Name

XBZR

SR

0

1

0

XBZR

0

XFOUT1 XFOUT0

R/W

2 kHz

4 kHz

Buzzer frequency control

*5

0

R/W

R

0FDH

XFOUT1

XFOUT0

0

High

Low

FOUT frequency control:

XFOUT1(0), XFOUT0(0) -> F1

XFOUT1(0), XFOUT0(1) -> F2

XFOUT1(1), XFOUT0(0) -> F3

XFOUT1(1), XFOUT0(1) -> F4

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

S1C6S3N7 TECHNICAL SOFTWARE

EPSON

II-9

CHAPTER 2: INITIAL RESET

CHAPTER 2

INITIAL RESET

2.1 Inte rna l Re g iste r Sta tus on Initia l Re se t

Followin g an in itial reset, th e in tern al registers an d in tern al

data m em ory area are in itialized to th e valu es sh own in

Tables 2.1.1 an d 2.1.2.

Table 2.1.1

Internal Register

Bit Length

Initial Value Following Reset

Initial values of internal

registers

Program counter step PCS

Program counter page PCP

8

4

8

4

1

00H

1H

New page pointer

Stack pointer

Index register

Register pointer

General register

Interrupt flag

Decimal flag

Zero flag

NPP

SP

X

1H

Undefined

0

Y

RP

A

B

I

D

0

Z

Undefined

Carry flag

C

Table 2.1.2

Initial values of internal data

memory area

Internal Data

Memory Area

RAM data

Initial Value

Following Reset

Bit Length

Address

4 × 80

4 × 26

Undefined

000H–05FH

090H–0AFH

0E0H–0FDH

Display memory

Internal I/O register See Tables 1.4.1(a)–1.4.1(e)

II-10

EPSON

S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 2: INITIAL RESET

After an in itial reset, th e program cou n ter page (PCP) is

in itialized to 1H, an d th e program cou n ter step (PCS), to

00H. Th is is wh y th e program is execu ted from step 00H of

th e first page.

Th e in itial valu es of som e in tern al registers an d in tern al

data m em ory area location s are u n defin ed after a reset. Set

th em as n ecessary to th e proper in itial valu es in th e pro-

gram .

Th e periph eral I/ O fu n ction s (m em ory-m apped I/ O) are

assign ed to in tern al data m em ory area addresses 0E0H to

0FDH. Each address represen ts a 4-bit in tern al I/ O register,

allowin g access to th e periph eral fu n ction s in 1-word (4-bit)

read/ write u n its.

S1C6S3N7 TECHNICAL SOFTWARE

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II-11

CHAPTER 2: INITIAL RESET

2.2 Initia lize Prog ra m Exa m p le

Th e followin g is a program th at clears th e RAM an d LCD,

resets th e flags, registers, tim er, an d stopwatch tim er, an d

sets th e stack poin ter im m ediately after resettin g th e sys-

tem .

Label

Mnemonic/operand

Comment

ORG

JP

100H

INIT

;Jump to "INIT"

;

ORG

RST

110H

F,0011B

INIT

;

;Interrupt mask, decimal

;adjustment off

LD

X,0

MX,0

;

RAMCLR LDPX

CP

JP

LD

XH,5H

NZ,RAMCLR

X,90H

MX,0

XM,0BH

NZ,LCDCLR

;

Clear RAM (00H–4FH)

Clear LCD (90H–AFH)

LCDCLR LDPX

CP

JP

;

LD

;

A,0

B,4

SPL,A

SPH,B

;

Set stack pointer to 40H

LD

OR

;

X,0F9H

MX,0101B

;

Reset timer and stopwatch

timer

LD

OR

;

X,0EBH

MX,0111B

;

Enable timer interrupt

LD

OR

X,0EBH

MX,1111B

;

Enable input interrupt

(K03–K00)

II-12

EPSON

S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 2: INITIAL RESET

;

LD

RST

EI

X,0

Y,0

A,0

B,0

F,0

;

Reset register flags

;Enable interrupt

Th e above program is a basic in itialization program for th e

S1C6S3N7. Th e settin g data are all in itialized as sh own in

Table 2.1.1 by execu tin g th is program . Wh en u sin g th is

program , add settin g item s n ecessary for each specific

application . (Figu re 2.2.1 is th e flow ch art for th is program .)

Initialization

Reset

I : Interrupt flag

I (Interrupt flag)

D : Decimal adjustment flag

D (Decimal adjustment flag)

Clear data RAM (00H to 04FH)

Clear segment RAM (90H to 0AFH)

Clear RAM

Set SP

Set stack pointer to 40H

Reset timer,

stopwatch timer

Enable timer interrupt 2 Hz, 8 Hz, 32 Hz

Stopwatch timer interrupt is masked

Enable timer interrupt

Enable input interrupt

Enable K03–K00 input port interrupt

Reset registers (X, Y, A, B)

flags (I, Z, D, C)

EI (enable interrupt)

Fig. 2.2.1

Flow chart of the initialization

program

To next process

S1C6S3N7 TECHNICAL SOFTWARE

EPSON

II-13

CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports)

CHAPTER 3

PERIPHERAL CIRCUITS

Details on h ow to con trol th e S1C6S3N7 periph eral circu it is

given in th is ch apter.

3.1

Inp ut Ports

Inp ut p ort m e m ory

m a p

Table 3.1.1 I/O memory map

Register

Address

Comment

*1

*2

D3

D2

D1

D0

Name

K03

SR

–

1

0

High

Low

K03

K02

K01

K00

*2

High

Low

R

K02

K01

–

0

0E0H

0E8H

0EDH

Input port (K00–K03)

High

Low

K00

Enable

Mask

EIK03

EIK02

EIK01

EIK00

EIK03

EIK02

EIK01

EIK00

Interrupt mask register (K03)

Interrupt mask register (K02)

Interrupt mask register (K01)

Interrupt mask register (K00)

R/W

*5

0

IK0

*5

*4

R

0

IK0

0

Yes

No

Interrupt factor flag (K00–K03)

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

II-14

EPSON

S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports)

Th e S1C6S3N7 h as on e 4-bit in pu t port (K00–K03). In pu t

port data can be read as a 4-bit u n it (K00–K03).

Control of

the inp ut p ort

Th e state of th e in pu t ports can be obtain ed by readin g th e

data (bits D3, D2, D1, D0) of address 0E0H. Th e in pu t ports

can be u sed to sen d an in terru pt requ est to th e CPU via th e

in pu t in terru pt con dition flag. See Section 3.9 "In terru pt

an d Halt", for details.

• Loadin g K0 0 –K0 3 in t o t h e A regist er

Exa m p le s of inp ut

p ort c ontrol

p rog ra m

Label

Mnemonic/operand

Comment

LD

Y,0E0H

A,MY

;Set address of port

;A register ← K00–K03

As sh own in Figu re 3.1.1, th e two in stru ction steps above

load th e data of th e in pu t port in to th e A register.

D3

D2

D1

D0

A register

K03 K02 K01 K00

Fig. 3.1.1

Loading the A register

Th e data of th e in pu t port can be loaded in to th e B register

or MX in stead of th e A register.

S1C6S3N7 TECHNICAL SOFTWARE

EPSON

II-15

CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports)

• Bit -u n it ch eck in g of in pu t port s

Label

Mnemonic/operand

Comment

DI

;Disable interrupt

LD

Y,0E0H

;Set address of port

INPUT1: FAN

MY,0010B

NZ,INPUT1

MY,0010B

Z,INPUT2

;

JP

INPUT2: FAN

JP

;Loop until K01 becomes "0"

;

;Loop until K01 becomes "1"

Th is program loopes u n til a risin g edge is in pu t to in pu t port

K01.

Th e in pu t port can be addressed u sin g th e X register in stead

of th e Y register.

Note When the input port is changed from high level to low level with a

pull-down resistor, the signal falls following a certain delay caused

by the time constants of the pull-down resistance and the input

gate capacitance. It is therefore necessary to observe a proper

wait time before the input port data is read.

II-16

EPSON

S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports)

3.2 Outp ut Ports

Outp ut p ort

m e m ory m a p

Table 3.2.1 I/O memory map

Register

Address

D3

Comment

*1

D2

D1

D0

R00

Name

R03

SR

0

1

0

R01

High

ON

Low

OFF

Low

OFF

R03 output port data

R03

R02

BUZZER

FOUT

R02

0

R02 output port data

R/W

R01

0

R01 output port data

0F3H

BUZZER

R00

0

Buzzer ON/OFF control register

R00 output port data

0

High

ON

FOUT

0

Frequency output ON/OFF control register

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

Th e S1C6S3N7 Series h ave 4 bits for gen eral ou tpu t ports

(R00–R03). R00 an d R01 alth ou gh can be u se for special u se

ou tpu t port as sh own in later of th is section . Th e ou tpu t

port is a read/ write register, ou tpu t pin s provide th e con -

ten ts of th e register. Th e states of th e ou tpu t ports (R00–

R03) are decided by th e data of address 0F3H. Ou tpu t ports

can also be read, an d ou tpu t con trol is possible u sin g th e

operation in stru ction s (AND, OR, etc.). Th e ou tpu t ports are

all in itialized to low level (0) after an in itial reset.

Control of

the outp ut p ort

S1C6S3N7 TECHNICAL SOFTWARE

EPSON

II-17

CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports)

• Loadin g B regist er dat a in t o R0 0 –R0 3

Exa m p le s of outp ut

p ort c ontrol

Label

Mnemonic/operand

Comment

p rog ra m

LD

Y,0F3H

MY,B

;Set address of port

;R00–R03 ← B register

As sh own in Figu re 3.2.1, th e two in stru ction steps above

load th e data of th e B register in to th e ou tpu t ports.

D3

D2

D1

D0

B register

R00

R01

R02

R03

Data register

Fig. 3.2.1

Control of the output port

Th e ou tpu t data can be taken from th e A register, MX, or

im m ediate data in stead of th e B register.

II-18

EPSON

S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports)

• Bit -u n it operat ion of ou t pu t port s

Label

Mnemonic/operand

Comment

LD

OR

AND

Y,0F3H

MY,0010B

MY,1011B

;Set address of port

;Set R01 to 1

;Set R02 to 0

Th e th ree in stru ction steps above cau se th e ou tpu t port to

be set, as sh own in Figu re 3.2.2.

D3

D2

D1

D0

Address 0F3H

R03 R02 R01 R00

No change

Sets "1"

Sets "0"

No change

Fig. 3.2.2

Setting of the output port

S1C6S3N7 TECHNICAL SOFTWARE

EPSON

II-19

CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports)

3.3 Sp e c ia l Use Outp ut Ports

Sp e c ia l use outp ut

p ort m e m ory m a p

Table 3.3.1 I/O memory map

Register

Address

Comment

R03 output port data

*1

D3

D2

D1

R01

D0

R00

Name

R03

SR

0

1

0

High

ON

Low

OFF

Low

OFF

R03

R02

BUZZER

FOUT

R02

0

R02 output port data

R/W

R01

0

R01 output port data

0F3H

BUZZER

R00

0

Buzzer ON/OFF control register

R00 output port data

0

High

ON

FOUT

0

Frequency output ON/OFF control register

XBZR

R/W

0

XFOUT1 XFOUT0

R/W

XBZR

0

2 kHz

4 kHz

Buzzer frequency control

*5

0

R

0FDH

XFOUT1

XFOUT0

0

High

Low

FOUT frequency control:

XFOUT1(0), XFOUT0(0) -> F1

XFOUT1(0), XFOUT0(1) -> F2

XFOUT1(1), XFOUT0(0) -> F3

XFOUT1(1), XFOUT0(1) -> F4

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

II-20

EPSON

S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports)

In addition to th e regu lar DC, special ou tpu t can be selected

for ou tpu t ports R00 an d R01, as sh own in Table 3.3.2.

Figu re 3.3.1 sh ows th e stru ctu re of ou tpu t ports R00–R03.

Control of the sp e -

c ia l use outp ut p ort

Table 3.3.2

Pin Name

R00

When Special Output is Selected

FOUT or BUZZER

BUZZER

Special output

R01

Register

(R03)

R03

Register

(R02)

R02

R01

BUZZER

Register

(R01)

BUZZER

FOUT

Register

(R00)

R00

Address

(0F3H)

Mask option

Fig. 3.3.1

Structure of output ports

R00–R03

S1C6S3N7 TECHNICAL SOFTWARE

EPSON

II-21

CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports)

• Bu zzer driver ou t pu t (BUZZER)

Exa m p le s of sp e c ia l

use outp ut p ort

Wh en ou tpu t port R01 is set for BUZZER an d R00 is set for

BUZZER, it perform s 2,048 Hz or 4,096 Hz selected by

register XBZR (0FDH D3).

c ontrol p rog ra m

Label

Mnemonic/operand

Comment

LD

Y,0FDH

;Set address of BUZZER

;frequency control register

;Select 2,048 Hz

;Set address of output port

;Turn on BUZZER

LD

OR

:

MY,1000B

Y,0F3H

MY,0010B

:

AND

MY,1101B

;Turn off BUZZER

II-22

EPSON

S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports)

• In t ern al divided frequ en cy ou t pu t (FOUT)

Wh en ou tpu t port R00 is set to FOUT ou tpu t, fosc or clock

frequ en cy divided in to fosc is gen erated. Clock frequ en cy

m ay be selected in dividu ally for F1–F4, from am on g 5 types

by m ask option ; a clock frequ en cy is th en selected from 4

types (i.e., F1–F4) th rou gh XFOUT0 an d XFOUT1 (0FDH D0

an d D1) registers an d is gen erated.

Th e clock frequ en cy types are sh own in Table 3.3.3.

Table 3.3.3

Mask option and register

selection

Clock Frequency (Hz) fosc = 32.768 kHz

F2 F3 F4

(D1,D0)=(0,0) (D1,D0)=(0,1) (D1,D0)=(1,0) (D1,D0)=(1,1)

Mask

Option

Sets

F1

256

(fosc/128)

512

(fosc/64)

1,024

(fosc/32)

2,048

(fosc/16)

Set 1

Set 2

Set 3

Set 4

Set 5

4,096

(fosc/8)

512

(fosc/64)

1,024

(fosc/32)

2,048

(fosc/16)

8,192

(fosc/4)

1,024

(fosc/32)

2,048

(fosc/16)

4,096

(fosc/8)

2,048

(fosc/16)

4,096

(fosc/8)

8,192

(fosc/4)

16,384

(fosc/2)

4,096

(fosc/8)

8,192

(fosc/4)

16,384

(fosc/2)

32,768

(fosc/1)

For exam ple m ask option is set to Set 4:

Label

Mnemonic/operand

Comment

LD

Y,0FDH

;Set address of FOUT

;frequency control register

;Select 16,384 Hz

;Set address of output port

;Turn on FOUT

LD

OR

:

MY,0011B

Y,0F3H

MY,0001B

:

AND

MY,1110B

;Turn off FOUT

S1C6S3N7 TECHNICAL SOFTWARE

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II-23

CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)

3.4 I/ O Ports

I/ O p ort m e m ory

m a p

Table 3.4.1 I/O memory map

Register

Address

Comment

*1

*2

D3

D2

D1

D0

Name

P03

SR

–

1

0

P03

P02

P01

P00

High

Low

*2

P02

P01

P00

–

High

Low

R/W

0F6H

I/O port (P00–P03)

*5

0

IOC

R/W

0

*5

R

0FCH

0

IOC

0

Output

Input

I/O port P00–P03 Input/Output

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

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EPSON

S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)

Th e S1C6S3N7 con tain s a 4-bit gen eral I/ O port (4 bits × 1).

Th is port can be u sed as an in pu t port or an ou tpu t port,

accordin g to I/ O port con trol register IOC. Wh en IOC is "0",

th e port is set for in pu t, wh en it is "1", th e port is set for

ou tpu t.

Control of

the I/ O p ort

• How t o set an in pu t port

Set "0" in th e I/ O port con trol register (D0 of address 0FCH),

an d th e I/ O port is set as an in pu t port. Th e state of th e I/ O

port (P00–P03) is decided by th e data of address 0F6H. (In

th e in pu t m ode, th e port level is read directly.)

• How t o set an ou t pu t port

Set "1" in th e I/ O port con trol register, an d th e I/ O port is

set as an ou tpu t port. Th e state of th e I/ O port is decided by

th e data of address 0F6H. Th is data is h eld by th e register,

an d can be set regardless of th e con ten ts of th e I/ O con trol

register. (Th e data can be set wh eth er P00 to P03 ports are

in pu t ports or ou tpu t ports.)

Th e I/ O con trol registers are cleared to "0" (in pu t/ ou tpu t

ports are set as in pu t ports), an d th e data registers are also

cleared to "0" after an in itial reset.

S1C6S3N7 TECHNICAL SOFTWARE

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II-25

CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)

• Loadin g P0 0 –P0 3 in pu t dat a in t o A regist er

Exa m p le s of I/ O p ort

c ontrol p rog ra m

Label

Mnemonic/operand

Comment

LD

AND

LD

Y,0FCH

MY,1110B

Y,0F6H

A,MY

;Set address of I/O control port

;Set port as input port

;Set address of port

;A register ← P00–P03

LD

As sh own in Figu re 3.4.1, th e fou r in stru ction steps above

load th e data of th e I/ O ports in to th e A register.

D3

D2

D1

D0

A register

Fig. 3.4.1

P03 P02 P01 P00

Loading into the A register

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S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)

• Loadin g P0 0 –P0 3 ou t pu t dat a in t o A regist er

Label

Mnemonic/operand

Comment

LD

Y,0FCH

;Set the address of input/output

;port control register

;Set as output port

;Set the address of port

;A register ← P00–P03

OR

LD

MY,0001B

Y,0F6H

A,MY

As sh own in Figu re 3.4.2, th e fou r in stru ction steps above

load th e data of th e I/ O ports in to th e A register.

D3

D2

D1

D0

P03 P02 P01 P00

A register

P00

P01

P02

P03

Data register

Fig. 3.4.2

Control of I/O port (input)

Data can be loaded from th e I/ O port in to th e B register or

MX in stead of th e A register.

S1C6S3N7 TECHNICAL SOFTWARE

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II-27

CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)

• Loadin g con t en t s of B regist er in t o P0 0 –P0 3

Label

Mnemonic/operand

Comment

LD

Y,0FCH

;Set the address of input/output

;port control register

;Set port as output port

;Set the address of port

;P00–P03 ← B register

OR

LD

MY,0001B

Y,0F6H

MY,B

As sh own in Figu re 3.4.3, th e fou r in stru ction steps above

load th e data of th e B register in to th e I/ O ports.

D3

D2

D1

D0

B register

P00

P01

P02

P03

Data register

Fig. 3.4.3

Control of the I/O port (output)

Th e ou tpu t data can be taken from th e A register, MX, or

im m ediate data in stead of th e B register.

Bit-u n it operation for th e I/ O port is iden tical to th at for th e

in pu t ports (K00–K03) or ou tpu t ports (R00–R03).

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EPSON

S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)

3.5 LCD Drive r

LCD d rive r m e m ory

m a p

Table 3.5.1 I/O memory map

Register

Address

Comment

*1

D3

D2

D1

D0

0

Name

CSDC

SR

0

1

0

Static

Dynamic LCD drive switch

CSDC

0

*5

R/W

R

0

0FBH

*5

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

Address

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

090

0A0

Display memory (write only)

32 words x 4 bits

Fig. 3.5.1

Display memory map

S1C6S3N7 TECHNICAL SOFTWARE

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II-29

CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)

Th e S1C6S3N7 con tain s 128 bits of display m em ory in

Control of the LCD

d rive r

addresses 090H to 0AFH of th e data m em ory. Each display

m em ory can be assign ed to an y 104 bits of th e 128 bits for

th e LCD driver (26 SEG × 4 COM), 78 bits of th e 128 bits (26

SEG × 3 COM) or 52 bits of th e 128 bits (26 SEG × 2 COM)

by u sin g a m ask option . Th e rem ain in g 24 bits, 50 bits or 76

bits of display m em ory are n ot con n ected to th e LCD driver,

an d are n ot ou tpu t even wh en data is written . An LCD

segm en t is on with "1" set in th e display m em ory, an d off

with "0" set in th e display m em ory. Note th at th e display

m em ory is a write-on ly.

• LCD drive con t rol regist er (CSDC)

Th e LCD drive con trol register (CSDC: address 0FBH, D3)

can set th e 1/ 1 du ty drive. Set "0" in CSDC for 1/ 4 du ty, 1/ 3

du ty or 1/ 1 du ty drive. Set "1" in CSDC an d th e sam e valu e

in th e registers correspon din g to COMs 0 th rou gh 3 for 1/ 1

du ty drive.

Figu re 3.5.2 sh ows th e 1/ 1 du ty drive waveform (1/ 3 bias)

an d Figu re 3.5.3 sh ows an exam ple of th e 7-segm en t LCD

assign m en t.

See page I-44 for th e 1/ 1 du ty drive waveform (1/ 2 bias).

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S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)

LCD lighting status

-VDD

-VL1

-VL2

-VL3

COM0

COM1

COM2

COM3

COM

0–3

Frame frequency

SEG0–25

Not lit

-VDD

-VL1

-VL2

-VL3

Lit

SEG

0–25

-VDD

-VL1

-VL2

-VL3

Fig. 3.5.2

1/1 duty drive control

(1/3 bias)

a

f

b

Register

Address

D3

D2

c

D1

D0

a

g

d

b

f

090H

091H

g

e

c

Fig. 3.5.3

d

7-segment LCD assignment

In th e assign m en t sh own in Figu re 3.5.3, th e 7-segm en t

display pattern is con trolled by writin g data to display

m em ory addresses 090H an d 091H.

S1C6S3N7 TECHNICAL SOFTWARE

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II-31

CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)

• Displayin g 7 -segm en t

Exa m p le s of

LCD d rive r c ontrol

p rog ra m

Th e LCD display rou tin e u sin g th e assign m en t of Figu re

3.5.3 can be program m ed as follows.

Label

Mnemonic/operand

Comment

ORG

000H

3FH

06H

5BH

4FH

66H

6DH

7DH

27H

7FH

6FH

RETD

;0 is displayed

;1 is displayed

;2 is displayed

;3 is displayed

;4 is displayed

;5 is displayed

;6 is displayed

;7 is displayed

;8 is displayed

;9 is displayed

SEVENS: LD

LD

B,0

X,090H

;Set the address of jump

;Set address of display memory

JPBA

Wh en th e above rou tin e is called (by th e CALL or CALZ

in stru ction ) with an y n u m ber from "0" to "9" set in th e A

register for th e assign m en t of Figu re 3.5.4, seven segm en ts

are displayed accordin g to th e con ten ts of th e A register.

A resister Display A resister Display A resister Display A resister Display A resister Display

Fig. 3.5.4

0

1

2

3

4

5

6

7

8

9

Data set in A register and

displayed patterns

Th e RETD in stru ction can be u sed to write data to th e

display m em ory on ly if it is addressed u sin g th e X register.

(Addressin g u sin g th e Y register is in valid.)

Note th at th e stack poin ter m u st be set to a proper valu e

before th e CALL (CALZ) in stru ction is execu ted.

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S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)

• Bit -u n it operat ion of t h e display m em ory

Data

Address

090H

Fig. 3.5.5

Example of segment

assignment

D3

D2

D1

D0

●

● : SEG-A

● : SEG-B

Label

Mnemonic/operand

Comment

LD

X,SEGBUF

;Set address display

;memory buffer

LD

Y,090H

MX,3

;Set address display memory

;Set buffer data

LD

AND

LD

AND

LD

MY,MX

MX,1110B

MY,MX

MX,1101B

MY,MX

;SEG-A, B ON (●, ●)

;Change buffer data

;SEG-A OFF (●, ●)

;Change buffer data

;SEG-B OFF (●, ●)

For m an ipu lation of th e display m em ory in bit-u n its for th e

assign m en t of Figu re 3.5.5, a bu ffer m u st be provided in

RAM to h old data. Note th at, sin ce th e display m em ory is

write-on ly, data can n ot be ch an ged directly u sin g an ALU

in stru ction (for exam ple, AND or OR).

After m an ipu latin g th e data in th e bu ffer, write it in to th e

correspon din g display m em ory u sin g th e tran sfer com m an d.

S1C6S3N7 TECHNICAL SOFTWARE

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II-33

CHAPTER 3: PERIPHERAL CIRCUITS (Timer)

3.6 Tim e r

Tim e r m e m ory m a p

Table 3.6.1 I/O memory map

Register

Address

Comment

*1

D3

D2

D1

D0

Name

TM3

SR

–

1

0

High

Low

TM3

TM2

TM1

TM0

Timer data (clock timer 2 Hz)

Timer data (clock timer 4 Hz)

Timer data (clock timer 8 Hz)

Timer data (clock timer 16 Hz)

High

Low

R

TM2

TM1

TM0

–

0E4H

*5

0

EIT2

EIT8

R/W

EIT32

0

R

EIT2

EIT8

0

Enable

Mask

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

0EBH

EIT32

*5

0

IT2

IT8

IT32

0

*4

R

IT2

IT8

IT32

0

Yes

No

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

0EFH

*5

0

TMRST SWRUN SWRST

0

TMRST

Reset

0

Reset

Run

–

Stop

–

Clock timer reset

R

W

R/W

W

0F9H

SWRUN

Stopwatch timer RUN/STOP

Stopwatch timer reset

*5

SWRST

Reset

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

II-34

EPSON

S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Timer)

Th e S1C6S3N7 con tain s a tim er with a basic oscillation of

32.768 kHz (typical). Th is tim er is a 4-bit bin ary cou n ter,

an d th e cou n ter data can be read as n ecessary. Th e cou n ter

data of th e 16 Hz clock can be read by readin g TM3 to TM0

(address 0E4H, D3 to D0). ("1" to "0" are set in TM3 to TM0,

correspon din g to th e h igh -low levels of th e 2 Hz, 4 Hz, 8 Hz,

an d 16 Hz 50 % du ty waveform . See Figu re 3.6.1.) Th e tim er

can also in terru pt th e CPU on th e fallin g edges of th e 32 Hz,

8 Hz, an d 2 Hz sign als. For details, see Section 3.9, "In ter-

ru pt an d Halt".

Control of the tim e r

Register

Address

Frequency

16 Hz

8 Hz

Clock timer timing chart

bit

D0

D1

D2

D3

0E4H

4 Hz

2 Hz

Occurrence of

32 Hz interrupt request

Occurrence of

8 Hz interrupt request

Occurrence of

2 Hz interrupt request

Fig. 3.6.1

Output waveform of

timer and interrupt timing

Th e tim er is reset by settin g "1" in TMRST (address 0F9H,

D2).

Note The 128 Hz to 2 Hz of the internal divider is initialized by resetting

the timer, and 128 Hz to 1 Hz of the internal divider is reset by

resetting the stopwatch timer.

Th e dividers of th e tim er an d stopwatch tim ers are in divid-

u al circu its, so resettin g on e circu it does n ot affect th e

oth er.

S1C6S3N7 TECHNICAL SOFTWARE

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II-35

CHAPTER 3: PERIPHERAL CIRCUITS (Timer)

• In it ializin g t h e t im er

Exa m p le s of tim e r

c ontrol p rog ra m

Label

Mnemonic/operand

Comment

LD

Y,0F9H

;Set address of the timer

;reset register

OR

MY,0100B

;Reset the timer

Th e two in stru ction steps above are u sed to reset (clear

TM0–TM3 to 0) an d restart th e tim er. Th e TMRST register is

cleared to "0" by h ardware 1 clock after it is set to "1".

• Loadin g t h e t im er

Label

Mnemonic/operand

Comment

LD

Y,0E4H

;Set address of

;the timer data (TM0 to TM3)

;Load the data of

LD

A,MY

;TM0 to TM3 into A register

As sh own in Table 3.6.2, th e two in stru ction steps load th e

data of TM0 to TM3 in to th e A register.

Table 3.6.2

Loading the timer data

D3

D2

D1

D0

A register

TM3 (2 Hz) TM2 (4 Hz) TM1 (8 Hz) TM0 (16 Hz)

II-36

EPSON

S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Timer)

• Ch eck in g t im er edge

Label

Mnemonic/operand

Comment

LD

CP

X,TMSTAT

MX,0

;Set address of the timer edge counter

;Check whether the timer edge

;counter is "0"

JP

LD

Z,RETURN

Y,0E4H

A,MY

;Jump if "0" (Z-flag is "1")

;Set address of the timer

;Read the data of TM0 to TM3

;into A register

LD

XOR

Y,TMDTBF

MY,A

;Set address of the timer data buffer

;Did the count on the timer

;change?

FAN

LD

MX,0100B

MY,A

;Check bit D2 of the timer data buffer

;Set the data of A register into

;the timer data buffer

JP

ADD

Z,RETURN

MX,0FH

;Jump, if the Z-flag is "1"

;Decrement the timer edge counter

;

RETURN: RET

;Return

Th is program takes a su brou tin e form . It is called at sh ort

in tervals, an d decrem en ts th e data at address TMSTAT every

125 m s u n til th e data reach es "0". Th e tim in g ch art is

sh own in Figu re 3.6.2. Th e tim er can be addressed u sin g

th e X register in stead of th e Y register.

Note

TMSTAT and TMDTBF may be any address in RAM and not

involve a hardware function.

TM2

125 ms

Fig. 3.6.2

Timing of the timer

edge counter

Timer edge counter (TMSTAT) decrementing timing

S1C6S3N7 TECHNICAL SOFTWARE

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II-37

CHAPTER 3: PERIPHERAL CIRCUITS (Stopwatch Timer)

3.7 Stop wa tc h Tim e r

Stop wa tc h tim e r

m e m ory m a p

Table 3.7.1 I/O memory map

Register

Address

Comment

*1

D3

D2

D1

D0

Name

SWL3

SR

0

1

0

SWL3

SWL2

SWL1

SWL0

MSB

SWL2

SWL1

SWL0

SWH3

SWH2

SWH1

SWH0

0

Stopwatch timer

1/100 sec (BCD)

R

0E2H

0E3H

LSB

SWH3

SWH2

SWH1

SWH0

EISW0

ISW0

MSB

R

Stopwatch timer

1/10 sec (BCD)

LSB

*5

0

EISW1

0

*5

0

R

R/W

0EAH

EISW1

EISW0

0

Enable

Mask

Interrupt mask register (stopwatch 1 Hz)

Interrupt mask register (stopwatch 10 Hz)

*5

0

ISW1

0

*5

R

0EEH

*4

ISW1

0

Yes

No

Interrupt factor flag (stopwatch 1 Hz)

Interrupt factor flag (stopwatch 10 Hz)

*4

ISW0

*5

0

TMRST SWRUN SWRST

0

TMRST

SWRUN

Reset

0

Reset

Run

–

Stop

–

Clock timer reset

R

W

R/W

W

0F9H

Stopwatch timer RUN/STOP

Stopwatch timer reset

*5

SWRST

Reset

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

II-38

EPSON

S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Stopwatch Timer)

Th e S1C6S3N7 con tain s 1/ 100 sec an d 1/ 10 sec stopwatch

tim ers.

Control of the stop -

wa tc h tim e r

Th is tim er can be loaded in 4-bit u n its. Startin g, stoppin g,

an d resettin g th e tim er can be con trolled by register.

Figu re 3.7.1 sh ows th e operation of th e stopwatch tim er.

Register

bits

Stopwatch timer (SWL) timing chart

Address

D0

D1

D2

D3

0E2H

(1/100 sec BCD)

Occurrence of

10 Hz interrupt request

Register

bits

Address

Stopwatch timer (SWH) timing chart

D0

D1

D2

D3

0E3H

(1/10 sec BCD)

Fig. 3.7.1

Stopwatch timer

operating timing

Occurrence of

1 Hz interrupt request

S1C6S3N7 TECHNICAL SOFTWARE

EPSON

II-39

CHAPTER 3: PERIPHERAL CIRCUITS (Stopwatch Timer)

• In it ializin g t h e st opwat ch t im er

Exa m p le s of stop -

wa tc h tim e r c ontrol

p rog ra m

Label

Mnemonic/operand

Comment

LD

OR

Y,0F9H

MY,0001B

;Set address of the SWRST register

;Reset the stopwatch timer

Th e two in stru ction steps above reset th e stopwatch tim er.

(SWL3 to SWL0, SWH3 to SWH0 are all cleared to "0".)

Note The stopwatch timer is reset by setting "1" in the SWRST register.

However, the SWRST register is cleared to "0" by hardware 1

clock after it is set to "1".

• St art in g t h e st opwat ch t im er

Label

Mnemonic/operand

Comment

LD

OR

Y,0F9H

;Set address of SWRUN register

;Start the stopwatch timer

MY,0010B

Th e two in stru ction steps above ru n th e stopwatch tim er of

SWL0 to SWL3, an d SWH0 to SWH3 (addresses 0E2H an d

0E3H, respectively).

• St oppin g t h e st opwat ch t im er

Label

Mnemonic/operand

Comment

LD

Y,0F9H

;Set address of SWRUN register

;Stop the stopwatch timer

AND MY,1101B

Th e two in stru ction steps above stop th e stopwatch tim er of

SWL0 to SWL3, an d SWH0 to SWH3 (addresses 0E2H an d

0E3H, respectively).

II-40

EPSON

S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Stopwatch Timer)

• Loadin g t h e st opwat ch t im er

Label

Mnemonic/operand

Comment

LD

Y,0E2H

;Set address of the SWL of

;the stopwatch

LDPY

LD

A,MY

;Read the data of SWL0 to SWL3

;into A register

;Read the data of SWH0 to SWH3

;into B register

B,MY

Th e th ree in stru ction steps above reads th e con ten ts of th e

stopwatch tim er in to A register an d B register. (Also see

Table 3.7.2.)

Table 3.7.2

Data load into A register

and B register

D3

D2

D1

D0

SWL3 SWL2 SWL1 SWL0

SWH3 SWH2 SWH1 SWH0

A register

B register

Note A read-in error caused by a carry from the SWL is not taken into

account in this program. You are recommended to add a handling

routine in your application.

S1C6S3N7 TECHNICAL SOFTWARE

EPSON

II-41

CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

3.8 Sup p ly Volta g e De te c tion (SVD) Circ uit a nd

He a vy Loa d Prote c tion Func tion

Th e S1C6S3N7 Series h as bu ilt-in su pply voltage detection

circu it an d drop in su pply voltage m ay be detected by con -

trollin g th e register on th e I/ O m em ory. Criteria voltages are

as follows:

Model

Criteria Voltage

2.4 V ± 0.15 V

1.2 V ± 0.10 V

S1C6S3N7

S1C6S3L7

S1C6S3B7

Moreover, wh en th e battery load becom es h eavy, su ch as

du rin g extern al piezo bu zzer drivin g or extern al lam p ligh t-

in g, h eavy load protection fu n ction is bu ilt-in in case th e

su pply voltage drops.

S1C6S3L7/ S1C6S3B7 operate at 0.9 V du e to th e SVD

circu it an d h eavy load protection fu n ction .

SVD c irc uit a nd

he a vy loa d p rote c -

tion func tion m e m -

ory m a p

Table 3.8.1 I/O memory map

Register

Address

Comment

*1

D3

D2

D1

D0

Name

SR

0

1

0

Heavy load protection mode register

HLMOD

0

SVDDT SVDON

R R/W

HLMOD

Heavy

load

Normal

load

*5

R/W

0

0FAH

Supply

voltage

low

Supply

voltage

normal

Supply voltage detection data

SVDDT

SVDON

0

Supply voltage detection ON/OFF

ON

OFF

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

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CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

Th e SVD circu it will tu rn ON by writin g "1" on th e SVDON

Control of the SVD

c irc uit

register (address 0FAH, D0, R/ W) an d su pply voltage detec-

tion will be perform ed. By writin g "0" on th e SVDON regis-

ter, th e detection resu lt is stored in th e SVDDT register.

However, in order to obtain a stable detection resu lt, it is

n ecessary to tu rn th e SVD circu it ON for at least 100 µs.

Accordin gly, readin g ou t th e detection resu lt from th e

SVDDT register is perform ed th rou gh th e followin g proce-

du res:

➀ Set th e SVDON register to "1".

➀ Provide at least 100 µs waitin g tim e.

➀ Set th e SVDON register to "0".

➀ Read-ou t from th e SVDDT register.

Note, h owever, th at wh en S1C6S3N7 is to be u sed with th e

n orm al system clock at fosc = 32.768 kHz, th ere is n o n eed

for th e waitin g tim e stated in th e above procedu re ➀ sin ce 1

in stru ction cycle will take lon ger th an 100 µs.

Becau se th e power cu rren t con su m ption of th e IC becom es

large wh en th e SVD circu it is operated, tu rn th e SVD circu it

OFF wh en n ot in u se. Th e operation tim in g ch art is sh own

in Figu re 3.8.1.

Supply voltage

Criteria voltage

100 µs or more

Fig. 3.8.1

SVDON register

SVD circuit

Timing chart of

supply voltage

detection operation

through the SVDON

register

SVDDT register

HLMOD register

Label

Mnemonic/operand

Comment

Exa m p le of SVD

c irc uit c ontrol

p rog ra m

LD

X,0FAH

MX,0001B

MX,1110B

A,MX

;Sets the address of SVDON

;Sets SVDON to "1"

;Sets SVDON to "0"

;Loads the detection result

;into the A register

OR

AND

LD

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CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

Note th at th e h eavy load protection fu n ction on th e

He a vy loa d p rote c -

S1C6S3L7/ S1C6S3B7 are differen t from th e S1C6S3N7.

tion func tion

(1) In case of S1C6S3L7/S1C6S3B7

Th e S1C6S3L7/ S1C6S3B7 h ave th e h eavy load protec-

tion fu n ction for wh en th e battery load becom es h eavy

an d th e sou rce voltage drops, su ch as wh en an extern al

bu zzer sou n ds or an extern al lam p ligh ts. Th e state

wh ere th e h eavy load protection fu n ction is in effect is

called th e h eavy load protection m ode. In th is m ode,

operation with a lower voltage th an n orm al is possible.

Th e n orm al m ode ch an ges to th e h eavy load protection

m ode in th e followin g two cases:

➀ Wh en th e software ch an ges th e m ode to th e h eavy load

protection m ode (HLMOD = "1")

➀ Wh en su pply voltage drop (SVDDT = "1") in th e SVD

circu it is detected, th e m ode will au tom atically sh ift to

th e h eavy load protection m ode u n til th e su pply volt-

age is recovered (SVTDT = "0")

In th e h eavy load protection m ode, th e in tern ally regu -

lated voltage is gen erated by th e liqu id crystal driver

sou rce ou tpu t VL2 so as to operate th e in tern al circu it.

Con sequ en tly, m ore cu rren t is con su m ed in th e h eavy

load protection m ode th an in th e n orm al m ode. Un less it

is n ecessary, be carefu l n ot to set th e h eavy load protec-

tion m ode with th e software. Also, to redu ce cu rren t

con su m ption , do n ot set th e SVDON to ON in th e h eavy

load protection m ode.

(2) In case of S1C6S3N7

Th e S1C6S3N7 h as th e h eavy load protection fu n ction for

wh en th e battery load becom es h eavy an d th e sou rce

voltage ch an ges, su ch as wh en an extern al bu zzer sou n ds

or an extern al lam p ligh ts. Th e state wh ere th e h eavy load

protection fu n ction is in effect is called th e h eavy load

protection m ode. Com pared with th e n orm al operation

m ode, th is m ode can redu ce th e ou tpu t voltage variation

of th e con stan t voltage or voltage booster/ redu cer of th e

LCD system .

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CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

Th e n orm al m ode ch an ges to th e h eavy load protection

m ode in th e followin g case:

•

Wh en th e software ch an ges th e m ode to th e h eavy

load protection m ode (HLMOD = "1")

Th e h eavy load protection m ode switch es th e con stan t

voltage circu it of th e LCD system to th e h igh -stability

m ode from th e low cu rren t con su m ption m ode. Con se-

qu en tly, m ore cu rren t is con su m ed in th e h eavy load

protection m ode th an in th e n orm al m ode. Un less it is

n ecessary, be carefu l n ot to set th e h eavy load protection

m ode with th e software.

Supply voltage

Criteria voltage

HLMOD register

Heavy load

protection mode

Fig. 3.8.2

Timing chart of

2 Hz clock

SVD circuit

supply voltage

detection operation

through the HLMOD

SVDDT register

register SVDON register

Supply voltage

Criteria voltage

100 µs or more

SVDON register

2 Hz clock

Fig. 3.8.3

SVD circuit

Timing chart of heavy

load protection

SVDDT register

Heavy load

function operation

through the SVDON protection mode

register

HLMOD register

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CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

•

Operat ion t h rou gh t h e HLMOD regist er

Th is is a sam ple program wh en lam p is driven with th e

R00 term in al du rin g perform an ce of h eavy load protec-

tion .

Exa m p le s of he a vy

loa d p rote c tion

func tion c ontrol

p rog ra m

Label

Mnemonic/operand

Comment

LD

OR

LD

OR

X,0FAH

;Sets the address of HLMOD

MX,1000B ;Sets to the heavy protection mode

Y,0F3H ;Sets the address of R0n port

MY,0001B ;Turns lamp ON

:

LD

Y,0F3H

;Sets the R0n port address

AND

MY,1110B ;Turns the lamp OFF

CALL WT1S

;1 second waiting time (software timer)

AND MX,0111B ;Cancels the heavy load protection mode

In th e above program , th e h eavy load protection m ode is

can celed after 1 sec waitin g tim e provided as th e tim e for

th e battery voltage to stabilize after th e lam p is tu rn ed

off; h owever, sin ce th is tim e varies accordin g to th e

n atu re of th e battery, tim e settin g m u st be don e in accor-

dan ce with th e actu al application .

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S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

•

Operat ion t h rou gh t h e SVDON regist er

Label

Mnemonic/operand

Comment

LD

FAN

JP

X,0FAH

;Sets the HLMOD/SVDDT address

;Checks the HLMOD/SVDDT bits

;Heavy load protection mode

;Sets the SVDON to "1"

;Sets the SVDON to "0"

;Checks the SVDDT bit

;Shifts the mode to

MX,1010B

NZ,HLMOD

MX,0001B

MX,1110B

A,0010B

Z,HLMOD

OR

AND

FAN

JP

;the heavy load protection mode

LD

AND

RET

Y,FLAG

MY,0

;Resets the flag to "0"

;Sets the flag to "1"

;

HLMOD: LD

OR

Y,FLAG

MY,1

RET

Th e above program operates th e h eavy load protection

fu n ction by u sin g th e SVDON register. In th e n orm al

operation m ode, su pply voltage detection is don e from th e

SVDON register an d wh en th e su pply voltage drops below

th e criteria voltage, th e m ode sh ifts to th e h eavy load

protection m ode. In th e h eavy load protection m ode,

su pply voltage detection by th e h ardware is don e every 2

Hz an d th e detection resu lt is stored in th e SVDDT regis-

ter. Becau se of th is, th e SVDDT register will be "1" du rin g

th e h eavy load protection m ode. Moreover, in th e above

program , su pply voltage detection by th e SVDON is

h alted du rin g th e h eavy load protection m ode. If th e

su pply voltage becom e grater th an th e criteria voltage,

th e SVDDT register valu e will becom e "0" an d h en ce,

su pply voltage detection th rou gh th e SVDON register will

resu m e after ch eckin g th e SVDDT register valu e. Wh en

u sed as a su b-rou tin e, th e above program will en able th e

u ser to determ in e wh eth er th e presen t operation m ode is

th e n orm al operation m ode (flag = "0") or th e h eavy load

protection m ode (flag = "1").

Th e flowch art for th e above program is sh own in th e n ext

page.

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CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

Start

=1

HLMOD?

=0

=1

SVDDT?

=0

SVDON←1

SVDON←0

=1

SVDDT?

=0

FLAG←0

FLAG←1

Fig. 3.8.4

Flowchart of operation

RET

through the SVDON register

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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

3.9 Inte rrup t a nd Ha lt

Inte rrup t m e m ory

m a p

Table 3.9.1(a) I/O memory map

Register

D2 D1

Address

Comment

*1

D3

D0

Name

EIK03

SR

0

1

0

Enable

Mask

EIK03

EIK02

EIK01

EIK00

Interrupt mask register (K03)

Interrupt mask register (K02)

Interrupt mask register (K01)

Interrupt mask register (K00)

Enable

Mask

R/W

EIK02

EIK01

EIK00

0

0E8H

0EAH

0EBH

0EDH

*5

0

EISW1

EISW0

EIT32

IK0

0

*5

R

R/W

EISW1

EISW0

0

Enable

Mask

Interrupt mask register (stopwatch 1 Hz)

Interrupt mask register (stopwatch 10 Hz)

*5

0

EIT2

EIT8

R/W

0

R

EIT2

EIT8

EIT32

0

Enable

Mask

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

*5

0

*5

*4

R

0

IK0

0

Yes

No

Interrupt factor flag (K00–K03)

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

Table 3.9.1(b) I/O memory map

Register

Address

Comment

*1

D3

D2

D1

D0

Name

SR

1

0

*5

0

ISW1

ISW0

0

*5

R

0EEH

*4

ISW1

0

Yes

No

Interrupt factor flag (stopwatch 1 Hz)

Interrupt factor flag (stopwatch 10 Hz)

*4

ISW0

*5

0

IT2

IT8

IT32

0

*4

R

IT2

IT8

IT32

0

Yes

No

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

0EFH

*1 In itial valu e followin g in itial reset

*2 Not set in th e circu it

*3 Un defin ed

*4 Reset (0) im m ediately after bein g read

*5 Always 0 wh en bein g read

*6 Refer to m ain m an u al

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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

Th e S1C6S3N7 su pports fou r types of a total of 9 in terru pts.

Th ere are th ree tim er in terru pts (2 Hz, 8 Hz, 32 Hz), two

stopwatch in terru pts (1 Hz, 10 Hz) an d fou r in pu t in terru pts

(K00–K03).

Control of inte rrup ts

a nd ha lt

Th e 9 in terru pts are in dividu ally en abled or m asked (dis-

abled) by in terru pt m ask registers. Th e EI an d DI in stru c-

tion s can be u sed to set or reset th e in terru pt flag (I), wh ich

en ables or disables all th e in terru pts at th e sam e tim e.

Wh en an in terru pt is accepted, th e in terru pt flag (I) is reset,

an d can n ot accepts an y oth er in terru pts (DI state).

Restart from th e h alt state created by th e HALT in stru ction ,

is don e by in terru pt.

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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

• In t erru pt fact or flags

IK0

Th is flag is set wh en an y of th e K00 to K03 in pu t in terru pts

occu rs. Th e in terru pt factor flag (IK0) is set to "1" wh en th e

con ten ts of th e in pu t (K00–K03) becom e "1" an d th e data of

th e correspon din g in terru pt m ask register (EIK00–EIK03) is

"1".

Th e con ten ts of th e IK0 flag can be loaded by software to

determ in e wh eth er th e K00–K03 in pu t in terru pts h ave

occu red.

Th e flag is reset wh en loaded by software. (See Figu re

3.9.1.)

K00

K01

K02

K03

Address 0E0H

Input interrupt factor

flag register (IK0)

INT

(Interrupt request)

FF

Interrupt flag (I)

D0

D1

D2

D3

Input interrupt mask register

(EIK00–EIK03)

Address 0E8H

Fig. 3.9.1

K00–K03

Input interrupt circuit

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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

IT32 Th is flag is set to "1" wh en a fallin g edge is detected in th e

tim er TM1 (32 Hz) sign al.

Th e con ten ts of th e IT32 flag can be loaded by software to

determ in e wh eth er a 32 Hz tim er in terru pt h as occu red.

Th e flag is reset, wh en it is loaded by software. (See Figu re

3.9.2.)

IT8 Th is flag is set to "1" wh en a fallin g edge is detected in th e

tim er TM1 (8 Hz) sign al.

Th e con ten ts of th e IT8 flag can be loaded by software to

determ in e wh eth er an 8 Hz tim er in terru pt h as occu red.

Th e flag is reset, wh en it is loaded by software. (See Figu re

3.9.2.)

IT2 Th is flag is set to "1" wh en a fallin g edge is detected in th e

tim er TM1 (2 Hz) sign al.

Th e con ten ts of th e IT2 flag can be loaded by software to

determ in e wh eth er a 2 Hz tim er in terru pt h as occu red.

Th e flag is reset, wh en it is loaded by software. (See Figu re

3.9.2.)

Timer interrupt

factor flag (IT)

32 Hz

D0

8 Hz

2 Hz

D1

D2

Address 0EFH

Timer interrupt

mask register (EIT)

D0

INT

D1

D2

(Interrupt request)

Address 0EBH

Interrupt flag (I)

Fig. 3.9.2

Timer interrupt circuit

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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

ISW1 Th is flag is set to "1" wh en a fallin g edge is detected in th e

stopwatch tim er (SWH, 1 Hz).

Th e con ten ts of th e ISW1 flag can be loaded by software to

determ in e wh eth er a 1 Hz stopwatch in terru pt h as occu red.

Th e flag is reset, wh en it is loaded by software. (See Figu re

3.9.3.)

ISW0

Th is flag is set to "1" wh en a fallin g edge is detected in th e

stopwatch tim er (SWH, 10 Hz).

Th e con ten ts of th e ISW0 flag can be loaded by software to

determ in e wh eth er a 10 Hz stopwatch in terru pt h as oc-

cu red.

Th e flag is reset, wh en it is loaded by software. (See Figu re

3.9.3.)

Stopwatch interrupt

factor flag (ISW)

10 Hz

1 Hz

D0

D1

Stopwatch interrupt

mask register (EISW)

D0

D1

INT

(Interrupt request)

Address 0EAH Address 0EEH

Fig. 3.9.3

Interrupt flag (I)

Stopwatch interrupt circuit

Reading of interrupt factor flags is available at EI, but be careful in

the following cases.

Note

If the interrupt mask register value corresponding to the interrupt

factor flags to be read is set to "1", an interrupt request will be

generated by the interrupt factor flags set timing, or an interrupt

request will not be generated. Be very careful when interrupt factor

flags are in the same address.

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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

• In t erru pt m ask regist ers

Th e in terru pt m ask registers are registers th at in dividu ally

specify wh eth er to en able or m ask th e tim er in terru pt (2 Hz,

8 Hz, 32 Hz), stopwatch tim er in terru pt (1 Hz, 10 Hz), or

in pu t in terru pt (K00–K03).

Th e followin g are description s of th e in terru pt m ask regis-

ters.

EIK00 to EIK03 Th is register en ables or m asks th e K00–K03 in pu t in terru pt.

Th e in terru pt con dition flag (IK0) is set to "1" wh en th e

con ten ts of th e in pu t (K00–K03) becom e "1" an d th e data of

th e correspon din g in terru pt m ask register (EIK00–EIK03) is

"1". Th e CPU is in terru pted if it is in th e EI state (in terru pt

flag [I] = "1"). (See Figu re 3.9.1.)

Port K input

Active status

Mask register

➀

Factor flag set Not set

When the content of the mask register is rewritten, while

the port K input is in the active status. The input interrupt

factor flag is set at ➀.

Fig. 3.9.4

Input interrupt timing

Wh en u sin g an in pu t in terru pt, if you rewrite th e con ten t of

th e m ask register, wh en th e valu e of th e in pu t term in al

wh ich becom es th e in terru pt in pu t is in th e active statu s

(in pu t term in al = h igh statu s), th e factor flag for in pu t

in terru pt m ay be set.

For exam ple, a factor flag is set with th e tim in g of ➀ sh own

in Figu re 3.9.4. However, wh en clearin g th e con ten t of th e

m ask register with th e in pu t term in al kept in th e h igh

statu s an d th en settin g it, th e factor flag of th e in pu t in ter-

ru pt is again set at th e tim in g th at h as been set.

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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

Con sequ en tly, wh en th e in pu t term in al is in th e active

statu s (h igh statu s), do n ot rewrite th e m ask register (clear-

in g, th en settin g th e m ask register), so th at a factor flag will

on ly set at th e risin g edge in th is case. Wh en clearin g, th en

settin g th e m ask register, set th e m ask register, wh en th e

in pu t term in al is n ot in th e active statu s (low statu s).

EIT32 Th is register en ables or m asks th e 32 Hz tim er in terru pt.

Th e CPU is in terru pted if it is in th e EI state wh en th e

in terru pt m ask register (EIT32) is set to "1" an d th e in ter-

ru pt con dition flag (IT32) is "1". (See Figu re 3.9.2.)

EIT8 Th is register en ables or m asks th e 8 Hz tim er in terru pt. Th e

CPU is in terru pted if it is in th e EI state wh en th e in terru pt

m ask register (EIT8) is set to "1" an d th e in terru pt con dition

flag (IT8) is "1". (See Figu re 3.9.2.)

EIT2 Th is register en ables or m asks th e 2 Hz tim er in terru pt. Th e

CPU is in tterru pted if it is in th e EI state wh en th e in terru pt

m ask register (EIT2) is set to "1" an d th e in terru pt con dition

flag (IT2) is "1". (See Figu re 3.9.2.)

EISW1 Th is register en ables or m asks th e 1 Hz stopwatch in terru pt.

Th e CPU is in terru pted if it is in th e EI state wh en th e

in terru pt m ask register (EISW1) is set to "1", an d also th e

in terru pt con dition flag (ISW1) is "1". (See Figu re 3.9.3.)

EISW0 Th is register en ables or m asks th e 10 Hz stopwatch in ter-

ru pt. Th e CPU is in terru pted if it is in th e EI state wh en th e

in terru pt m ask register (EISW0) is set to "1", an d th e in ter-

ru pt con dition flag (ISW0) is "1". (See Figu re 3.9.3.)

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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

• In t erru pt vect or address

Th e S1C6S3N7 in terru pt vector address is m ade u p of th e

low-order 3 bits of th e program cou n ter (12 bits), each of

wh ich is assign ed a specific fu n ction as sh own in Figu re

3.9.5.

PCP3 PCP2 PCP1 PCP0 PCS7 PCS6 PCS5 PCS4 PCS3 PCS2 PCS1 PCS0

0

1

0

×

Fig. 3.9.5

Assignment of the

interrupt vector

address

Input (K00–K03) interrupt

Stopwatch interrupt

Clock timer interrupt

Note th at all of th e th ree tim er in terru pts h ave th e sam e

vector address, an d software m u st be u sed to ju dge wh eth er

or n ot a given tim er in terru pt h as occu rred. For in stan ce,

wh en th e 32 Hz tim er in terru pt an d th e 8 Hz tim er in terru pt

are en abled at th e sam e tim e, th e accepted tim er in terru pt

m u st be iden tified by software. (Sim ilarly, th e K00–K03

in pu t in terru pts an d th e 10 Hz/ 1 Hz stopwatch in terru pts

m u st be iden tified by software.)

Wh en an in terru pt is gen erated, th e h ardware resets th e

in terru pt flag (I) to en ter th e DI state. Execu te th e EI in -

stru ction as n ecessary to recover th e EI state after in terru pt

processin g.

Set th e EI state at th e start of th e in terru pt processin g

rou tin e to allow n estin g of th e in terru pts.

Th e in terru pt factor flags m u st always be reset before set-

tin g th e EI statu s in th e correspon din g in terru pt processin g

rou tin e. (Th e flag is reset wh en th e in terru pt con dition flag

is read by software.)

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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

If th e EI in stru ction is execu ted with ou t resetting th e in ter-

ru pt factor flag after gen eratin g th e tim er in terru pt or th e

stopwatch tim er in terru pt, an d if th e correspon din g in ter-

ru pt m ask register is still "1", th e sam e in terru pt is gen er-

ated on ce m ore. (See Figu re 3.9.6.)

If th e EI state is set with ou t resetting th e in terru pt con dition

flag after gen eratin g th e in pu t in terru pt (K00–K03), th e sam e

in terru pt is gen erated on ce m ore. (See Figu re 3.9.6.)

Th e in terru pt factor flag m u st always be read (reset) in th e

DI state (in terru pt flag [I] = "0"). Th ere m ay be an operation

error if read in th e EI state.

Th e tim er in terru pt factor flags (IT32, IT8, IT2) an d th e

stopwatch in terru pt factor flags (ISW1, ISW0) are set

wh eth er th e correspon din g in terru pt m ask register is set or

n ot.

Th e in pu t in terru pt factor flag (IK0) is allowed to be set in

th e con dition wh en th e correspon din g in terru pt m ask regis-

ter (EIK00–EIK03) is set to "1" (in terru pt is en abled). (See

Figu re 3.9.6.)

Table 3.9.2 sh ows th e in terru pt vector m ap.

Table 3.9.2

Page

Step

00H

01H

02H

03H

04H

05H

06H

07H

Interrupt vector

Interrupt vector map

Initial reset

Clock timer interrupt

Stopwatch interrupt

1

Clock timer interrupt and stopwatch interrupt

Input (K00–K03) interrupt

Input interrupt and clock timer interrupt

Input interrupt and stopwatch interrupt

Generation of all interrupt

Addesses (start address of in terru pt processin g rou tin es) to

ju m p to are written in to th e addresses available for in terru pt

vector allocation .

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S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

Interrupt vector

(MSB)

:

Program counter of CPU

:

(three low-order bits)

K00

(LSB)

EIK00

K01

INT

EIK01

(Interrupt request)

IK0

K02

EIK02

K03

EIK03

ISW0

EISW0

ISW1

EISW1

IT2

Interrupt factor flag

EIT2

Interrupt mask register

IT8

EIT8

IT32

EIT32

Fig. 3.9.6

Internal interrupt circuit

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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

• Rest art from h alt st at e by in t erru pt

Exa m p le s of inte rrup t

a nd ha lt c ontrol

p rog ra m

Main routine

Label

Mnemonic/operand

Comment

LD

X,0E8H

;Set address of K00 to K03

;interrupt mask register

;Enable K00 to K03

;input interrupt

OR

MX,1111B

;

LD

OR

LD

OR

X,0EAH

;Set address of stopwatch

;interrupt mask register

;Enable 1 Hz, 10 Hz stopwatch interrupt

MX,0011B

X,0EBH

;Set address of timer interrupt

;mask register

;Enable timer interrupt

;(32 Hz, 8 Hz, 2 Hz)

;Set interrupt flag (EI state is set)

;Halt mode

MX,0111B

MAIN: EI

HALT

JP

MAIN

;Jump to MAIN

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S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

Interruption vector routine

Label

Mnemonic/operand

Comment

ORG

JP

100H

INIT

INTR

;Timer interrupt is generated

;Stopwatch interrupt is generated

;Timer interrupt, stopwatch interrupt

;are generated

JP

INTR

;K00 to K03 interrupt is generated

;Timer interrupt, K00 to K03 interrupt

;are generated

JP

INTR

;Stopwatch interrupt, K00 to K03 interrupt

;are generated

;Timer interrupt, stopwatch interrupt,

;K00 to K03 interrupt are generated

;

INTR:

LD

X,0EFH

;Address of timer interrupt factor flag

LD

Y,TMFSK ;Address of timer interrupt factor flag buffer

MY,MX

FAN

JP

MY,0100B ;Check 2 Hz timer interrupt

Z,TI8RQ ;Jump if not 2 Hz timer interrupt

CALL

TINT2

;Call 2 Hz timer interrupt service routine

TI8RQ:

TI32RQ:

SW1RQ:

LD

FAN

JP

Y,TMFSK ;Address of timer factor flag buffer

MY,0010B ;Check 8 Hz timer interrupt

Z,TI32RQ ;Jump if not 8 Hz timer interrupt

CALL

TINT8

;Call 8 Hz timer interrupt service routine

LD

FAN

JP

Y,TMFSK ;Address of timer factor flag buffer

MY,0001B ;Check 8 Hz timer interrupt

Z,SW1RQ ;Jump if not 32 Hz timer interrupt

CALL

TINT32

;Call 32 Hz timer interrupt service routine

LD

X,0EEH

;Address of stopwatch interrupt factor flag

Y,SWFSK ;Address of stopwatch interrupt

;factor flag buffer

FAN

JP

MY,0010B ;Check 1 Hz stopwatch interrupt

Z,SW10RQ ;Jump if not 1 Hz stopwatch interrupt

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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

CALL

LD

SW1IN

;Call 1 Hz stopwatch interrupt service routine

SW10RQ:

Y,SWFSK ;Address of stopwatch interrupt

;factor flag buffer

FAN

JP

MY,0010B ;Check 10 Hz stopwatch interrupt

Z,IK0RQ ;Jump if not 10 Hz stopwatch interrupt

CALL

SW10IN

;Call 10 Hz stopwatch interrupt service

;routine

IK0RQ:

LD

X,0EDH

;Address of K00 to K03 input interrupt flag

FAN

JP

MX,0001B ;Check K00 to K03 input interrupt

Z,INTEND ;Jump if not K00 to K03 input interrupt

CALL

IK0INT

;Call K00 to K03 input interrupt service

;routine

INTEND:

EI

RET

Th e above program is n orm ally u sed to restart th e CPU

wh en in th e h alt state by in terru pt an d to retu rn it to th e

h alt state again after th e in terru pt processin g is com pleted.

Th e processin g proceeds by repeatin g th e → h alt in terru pt

→ h alt → in terru pt cycle.

Th e in terru pt factor flag is reset wh en load by th e software.

Th u s, wh en u sin g in terru pts wh ich in terru pt factor flags are

in th e sam e address at th e sam e tim e, flag ch eck m u st be

don e after storin g th e data. For exam ple, store th e 1 word

in clu din g th e factor flag in th e RAM. (If ch eck is directly

don e by th e FAN in stru ction , th e factor flags of th e sam e

address are all reset.)

Readin g of in terru pt factor flags is available at EI, bu t be

carefu l in th e followin g cases.

If th e in terru pt m ask register valu e correspon din g to th e

in terru pt factor flags to be read is set to "1", an in terru pt

requ est will be gen erated by th e in terru pt factor flags set

tim in g, or an in terru pt requ est will n ot be gen erated.

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S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 4: SUMMARY OF PROGRAMMING POINTS

CHAPTER 4

SUMMARY OF PROGRAMMING

POINTS

•

Core CPU

After th e system reset, on ly th e program cou n ter (PC),

n ew page poin ter (NPP) an d in terru pt flag (I) are in itial-

ized by th e h ardware. Th e oth er in tern al circu its wh ose

settin gs are u n defin ed m u st be in itialized with th e pro-

gram .

•

Power Supply

Data Memory

Extern al load drivin g th rou gh th e ou tpu t voltage of

con stan t voltage circu it or voltage booster/ redu cer is n ot

perm itted.

– Sin ce som e portion s of th e RAM are also u sed as stack

area du rin g su b-rou tin e call or register savin g, see to it

th at th e data area an d th e stack area do n ot overlap.

– Th e stack area con su m es 3 words du rin g a su b-rou tin e

call or in terru pt.

– Address 00H–0FH in th e RAM is th e m em ory register

area addressed by th e register poin ter RP.

– Mem ory is n ot m ou n ted in u n u sed area with in th e m em -

ory m ap an d in m em ory area n ot in dicated in th is m an -

u al. For th is reason , n orm al operation can n ot be assu red

for program s th at h ave been prepared with access to

th ese areas.

•

Initial Reset

– Main tain th e in itial reset circu it at h igh level for at least

4 secon ds (in case of oscillation frequ en cy fosc = 32 kHz)

becau se n oise rejector is bu ilt-in .

– Wh en u tilizin g th e sim u ltan eou s h igh in pu t reset fu n c-

tion of th e in pu t ports (K00–K03), take care n ot to m ake

th e ports specified du rin g n orm al operation to go h igh

sim u ltan eou sly.

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CHAPTER 4: SUMMARY OF PROGRAMMING POINTS

•

Input Port

– Wh en m odifyin g th e in pu t port from h igh level to low level

with pu ll-down resistan ce, a delay will occu r at th e rise of

th e waveform du e to tim e con stan t of th e pu ll-down

resistan ce an d in pu t gate capacities. Provide appropriate

waitin g tim e in th e program wh en perform in g in pu t port

readin g.

– In pu t in terru pt program in g related precau tion s

Port K input

Active status

Mask register

➀

Factor flag set Not set

When the content of the mask register is rewritten, while

the port K input is in the active status. The input interrupt

factor flag is set at ➀.

Fig. 4.1

Input interrupt timing

Wh en u sin g an in pu t in terru pt, if you rewrite th e con ten t

of th e m ask register, wh en th e valu e of th e in pu t term in al

wh ich becom es th e in terru pt in pu t is in th e active statu s

(in pu t term in al = h igh statu s), th e factor flag for in pu t

in terru pt m ay be set.

For exam ple, a factor flag is set with th e tim in g of ➀

sh own in Figu re 4.1. However, wh en clearin g th e con ten t

of th e m ask register with th e in pu t term in al kept in th e

h igh statu s an d th en settin g it, th e factor flag of th e in pu t

in terru pt is again set at th e tim in g th at h as been set.

Con sequ en tly, wh en th e in pu t term in al is in th e active

statu s (h igh statu s), do n ot rewrite th e m ask register

(clearin g, th en settin g th e m ask register), so th at a factor

flag will on ly set at th e risin g edge in th is case. Wh en

clearin g, th en settin g th e m ask register, set th e m ask

register, wh en th e in pu t term in al is n ot in th e active

statu s (low statu s).

•

Output Port

Th e FOUT an d BUZZER ou tpu t sign al m ay produ ce

h azards wh en th e ou tpu t ports R00 an d R01 are tu rn ed

on or off.

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S1C6S3N7 TECHNICAL SOFTWARE

CHAPTER 4: SUMMARY OF PROGRAMMING POINTS

•

I/O Port

– Wh en th e I/ O port is set to th e ou tpu t m ode an d a low-

im pedan ce load is con n ected to th e port pin , th e data

written to th e register m ay differ from th e data read.

– Wh en th e I/ O port is set to th e in pu t m ode an d a low-

level voltage (VSS) is in pu t by th e bu ilt-in pu ll-down

resistan ce, an erron eou s in pu t resu lts if th e tim e con -

stan t of th e capacitive load of th e in pu t lin e an d th e

bu ilt-in pu ll-down resistan ce load is greater th an th e

read-ou t tim e. Wh en th e in pu t data is bein g read, th e

tim e th at th e in pu t lin e is pu lled down is equ ivalen t to

0.5 cycles of th e CPU system clock.

Hen ce, th e electric poten tial of th e pin s m u st settle

with in 0.5 cycles. If th is con dition can n ot be m et, som e

m easu re m u st be devised, su ch as arran gin g a pu ll-down

resistan ce extern ally, or perform in g m u ltiple read-ou ts.

•

LCD Driver

– Becau se th e display m em ory is for writin g on ly, re-

writin g th e con ten ts with com pu tin g in stru ction s (e.g.,

AND, OR, etc.) wh ich com e with read-ou t operation s is

n ot possible. To perform bit operation s, a bu ffer to h old

th e display data is requ ired on th e RAM.

– Even wh en 1/ 2 du ty is selected, th e display data corre-

spon din g to COM0, COM3 are valid for static drive.

Hen ce, for static drive set th e sam e valu e to all display

m em ory correspon din g COM0–COM3.

– Even wh en 1/ 3 du ty is selected, th e display data corre-

spon din g to COM3 is valid for static drive. Hen ce, for

static drive set th e sam e valu e to all display m em ory

correspon din g COM0–COM3.

– For caden ce adju stm en t, set th e display data in clu din g

display data correspon din g to COM3.

– fosc in dicates th e oscillation frequ en cy of th e oscillation

circu it.

•

Supply Voltage Detec-

tion (SVD) Circuit

Sin ce su pply voltage detection is au tom atically perform ed

by th e h ardware every 2 Hz (0.5 sec) wh en th e h eavy load

protection fu n ction operates, do n ot perm it th e operation

of th e SVD circu it by th e software in order to m in im ize

power cu rren t con su m ption .

S1C6S3N7 TECHNICAL SOFTWARE

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II-65

CHAPTER 4: SUMMARY OF PROGRAMMING POINTS

•

Heavy Load Protec-

tion Function

In th e h eavy load protection fu n ction (h eavy load protec-

tion m ode flag = "1"), su pply voltage detection th rou gh

th e SVDON register is n ot perm itted in order to m in im ize

power cu rren t con su m ption .

Interrupt

– Re-start from th e HALT state is perform ed by th e in ter-

ru pt. Th e retu rn address after com pletion of th e in terru pt

processin g in th is case will be th e address followin g th e

HALT in stru ction .

– Wh en in terru pt occu rs, th e in terru pt flag will be reset by

th e h ardware an d it will becom e DI state. After com ple-

tion of th e in terru pt processin g, set to th e EI state

th rou gh th e software as n eeded.

Moreover, th e n estin g level m ay be set to be program -

m able by settin g to th e EI state at th e begin n in g of th e

in terru pt processin g rou tin e.

– Be su re to reset th e in terru pt factor flag before settin g to

th e EI state on th e in terru pt processin g rou tin e. Th e

in terru pt factor flag is reset by readin g th rou gh th e

software. Not resettin g th e in terru pt factor flag an d

in terru pt m ask register bein g "1", will cau se th e sam e

in terru pt to occu r again .

– Th e in terru pt factor flag will be reset by readin g th rou gh

th e software. Becau se of th is, wh en m u ltiple in terru pt

factor flags are to be assign ed to th e sam e address,

perform th e flag ch eck after th e con ten ts of th e address

h as been stored in th e RAM. Direct ch eckin g with th e

FAN in stru ction will cau se all th e in terru pt factor flag to

be reset.

– Readin g of in terru pt factor flags is available at EI, bu t be

carefu l in th e followin g cases.

If th e in terru pt m ask register valu e correspon din g to th e

in terru pt factor flags to be read is set to "1", an in terru pt

requ est will be gen erated by th e in terru pt factor flags set

tim in g, or an in terru pt requ est will n ot be gen erated.

•

Vacant Register and

Read/Write

Writin g data in to th e addresses wh ere read/ write bits

an d read on ly bits are m ixed in 1 word (4 bits) does n ot

affect th e read on ly bits.

II-66

EPSON

S1C6S3N7 TECHNICAL SOFTWARE

APPENDIX A TABLE OF INSTRUCTIONS

APPENDIX A

Ta b le of Instruc tions

Operation Code

Flag

Mne-

monic

Classification

Operand

Clock

Operation

B

1

0

1

0

A

1

0

1

9

1

0

1

0

8

7

6

5

4

3

2

1

0

I D Z C

Branch

PSET

p

0

1

0 p4 p3 p2 p1 p0

5

7

NBP ←p4, NPP←p3~p0

instructions JP

s

0 s7 s6 s5 s4 s3 s2 s1 s0

1 s7 s6 s5 s4 s3 s2 s1 s0

0 s7 s6 s5 s4 s3 s2 s1 s0

1 s7 s6 s5 s4 s3 s2 s1 s0

PCB ←NBP, PCP←NPP, PCS ←s7~s0

PCB ←NBP, PCP←NPP, PCS ←s7~s0 if C=1

PCB ←NBP, PCP←NPP, PCS ←s7~s0 if C=0

PCB ←NBP, PCP←NPP, PCS ←s7~s0 if Z=1

PCB ←NBP, PCP←NPP, PCS ←s7~s0 if Z=0

PCB ←NBP, PCP←NPP, PCSH ←B, PCSL ←A

M(SP-1) ←PCP, M(SP-2) ←PCSH, M(SP-3) ←PCSL+1

SP←SP-3, PCP←NPP, PCS ←s7~s0

C, s

NC, s

Z, s

NZ, s

JPBA

1 1 1 1 0 1 0 0 0

CALL

CALZ

RET

s

0 s7 s6 s5 s4 s3 s2 s1 s0

0

1

0

1

0

1

0

1 s7 s6 s5 s4 s3 s2 s1 s0

7

M(SP-1) ←PCP, M(SP-2) ←PCSH, M(SP-3)← PCSL+1

SP←SP-3, PCP ←0, PCS ←s7~s0

1

0

1

0

PCSL← M(SP), PCSH←M(SP+1), PCP ←M(SP+2)

SP ←SP+3

RETS

RETD

12 PCSL←M(SP), PCSH←M(SP+1), PCP←M(SP+2)

SP← SP+3, PC← PC+1

l

l7 l6 l5 l4 l3 l2 l1 l0

12 PCSL ←M(SP), PCSH←M(SP+1), PCP←M(SP+2)

SP← SP+3, M(X) ←i3~i0, M(X+1) ←l7~l4, X← X+2

System

control

NOP5

NOP7

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

5

7

5

7

No operation (5 clock cycles)

No operation (7 clock cycles)

Halt (stop clock)

X← X+1

instructions HALT

Index

INC

X

operation

Y

Y← Y+1

instructions LD

X, x

Y, y

XH, r

XL, r

YH, r

YL, r

r, XH

r, XL

r, YH

r, YL

1 x7 x6 x5 x4 x3 x2 x1 x0

0 y7 y6 y5 y4 y3 y2 y1 y0

XH← x7~x4, XL ←x3~x0

YH← y7~y4, YL ←y3~y0

XH← r

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1 r1 r0

0 r1 r0

1 r1 r0

0 r1 r0

1 r1 r0

0 r1 r0

1 r1 r0

0 r1 r0

XL← r

YH← r

YL← r

r ←XH

r ←XL

r ←YH

r ←YL

ADC XH, i

XL, i

i3 i2 i1 i0

↑ ↑

↓ ↓

XH← XH+i3~i0+C

XL← XL+i3~i0+C

YH← YH+i3~i0+C

YL← YL+i3~i0+C

↑ ↑

↓ ↓

YH, i

↑ ↑

↓ ↓

YL, i

↑ ↑

↓ ↓

S1C6S3N7 TECHNICAL SOFTWARE

EPSON

II-67

APPENDIX A TABLE OF INSTRUCTIONS

Operation Code

Flag

Mne-

monic

Classification

Operand

Clock

Operation

B

1

A

0

1

0

1

9

1

0

1

8

0

1

0

1

7

0

1

0

1

0

1

6

1

5

0

1

4

0

1

0

1

3

2

1

0

I D Z C

Index

CP

XH, i

XL, i

YH, i

YL, i

r, i

i3 i2 i1 i0

↑ ↑

↓ ↓

7

5

7

5

XH-i3~i0

operation

instructions

↑ ↑

↓ ↓

XL-i3~i0

↑ ↑

↓ ↓

YH-i3~i0

↑ ↑

↓ ↓

YL-i3~i0

Data

LD

0 r1 r0 i3 i2 i1 i0

r ←i3~i0

transfer

instructions

r, q

1

0

1

0

1

0

1

0 r1 r0 q1 q0

0 n3 n2 n1 n0

1 n3 n2 n1 n0

0 n3 n2 n1 n0

1 n3 n2 n1 n0

r ←q

A, Mn

B, Mn

Mn, A

Mn, B

A← M(n3~n0)

B← M(n3~n0)

M(n3~n0)←A

M(n3~n0)←B

LDPX MX, i

r, q

0

i3 i2 i1 i0

0 r1 r0 q1 q0

i3 i2 i1 i0

1 r1 r0 q1 q0

M(X)←i3~i0, X← X+1

r←q, X←X+1

LDPY MY, i

r, q

1

M(Y) ←i3~i0, Y ←Y+1

r ←q, Y←Y+1

LBPX MX, l

l7 l6 l5 l4 l3 l2 l1 l0

M(X) ←l3~l0, M(X+1)← l7~l4, X ←X+2

F←F i3~i0

Flag

SET

RST

F, i

0

1

0

1

0

1

0

1

0

1

0

1

0

1

i3 i2 i1 i0 ↑ ↑ ↑ ↑

i3 i2 i1 i0 ↓ ↓ ↓ ↓

operation

F←F i3~i0

instructions SCF

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

↑

↓

C←1

RCF

SZF

RZF

SDF

RDF

EI

C←0

↑

↓

Z←1

Z←0

↑

↓

D←1 (Decimal Adjuster ON)

D←0 (Decimal Adjuster OFF)

I ←1 (Enables Interrupt)

I ←0 (Disables Interrupt)

SP← SP+1

↑

↓

DI

Stack

INC

SP

operation

DEC SP

SP← SP-1

instructions PUSH

r

0 r1 r0

SP← SP-1, M(SP)←r

SP← SP-1, M(SP)←XH

SP← SP-1, M(SP)←XL

SP← SP-1, M(SP)←YH

SP← SP-1, M(SP)←YL

SP← SP-1, M(SP)←F

r ←M(SP), SP←SP+1

XH← M(SP), SP← SP+1

XL← M(SP), SP← SP+1

XH

XL

YH

YL

F

1

0

1

0

1

0

1

0

POP

r

0 r1 r0

XH

XL

1

0

1

0

II-68

EPSON

S1C6S3N7 TECHNICAL SOFTWARE

APPENDIX A TABLE OF INSTRUCTIONS

Operation Code

Flag

Mne-

monic

Classification

Operand

Clock

Operation

B

1

A

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

9

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

8

1

0

1

0

1

0

1

0

1

7

1

0

1

0

1

0

1

0

1

0

1

0

1

0

6

1

5

0

1

4

1

0

1

0

1

3

1

0

2

0

1

0

1

0

1

0

I D Z C

Stack

POP

YH

YL

F

5

7

5

7

YH← M(SP), SP← SP+1

YL← M(SP), SP← SP+1

F←M(SP), SP←SP+1

SPH← r

operation

instructions

↑ ↑ ↑ ↑

↓ ↓ ↓ ↓

LD

SPH, r 1

SPL, r

r, SPH 1

r, SPL

Arithmetic ADD r, i

0 r1 r0

1 r1 r0

1

SPL ← r

r← SPH

1

r← SPL

0 r1 r0 i3 i2 i1 i0

ꢀ ↑ ↑

↓ ↓

r← r+i3~i0

instructions

r, q

ADC r, i

r, q

0

0 r1 r0 q1 q0 ꢀ ↑ ↑

r← r+q

↓ ↓

1 r1 r0 i3 i2 i1 i0

ꢀ ↑ ↑

↓ ↓

r← r+i3~i0+C

r← r+q+C

0

1

1 r1 r0 q1 q0 ꢀ ↑ ↑

↓ ↓

SUB r, q

0 r1 r0 q1 q0 ꢀ ↑ ↑

r← r-q

↓ ↓

SBC

r, i

1 r1 r0 i3 i2 i1 i0

ꢀ ↑ ↑

↓ ↓

r← r-i3~i0-C

r← r-q-C

r, q

0 1 1 r1 r0 q1 q0 ꢀ ↑ ↑

↓ ↓

AND r, i

r, q

0 r1 r0 i3 i2 i1 i0

0 r1 r0 q1 q0

1 r1 r0 i3 i2 i1 i0

1 r1 r0 q1 q0

0 r1 r0 i3 i2 i1 i0

0 r1 r0 q1 q0

1 r1 r0 i3 i2 i1 i0

0 r1 r0 q1 q0

0 r1 r0 i3 i2 i1 i0

↑

↓

r← r i3~i0

1

0

↑

↓

r← r

r← r i3~i0

r← r

r← r i3~i0

r← r

q

OR

r, i

↑

↓

r, q

1

0

↑

↓

q

XOR r, i

r, q

↑

↓

1

↑

↓

q

CP

r, i

↑ ↑

↓ ↓

r-i3~i0

r-q

r, q

0

↑ ↑

↓ ↓

FAN r, i

r, q

↑

↓

r

i3~i0

q

0

1

0

1

0

1

0

1

1 r1 r0 q1 q0

1 r1 r0 r1 r0

↑

↓

RLC

RRC

INC

r

↑ ↑

↓ ↓

d3 ←d2, d2 ←d1, d1 ←d0, d0 ←C, C← d3

d3 ←C, d2 ←d3, d1 ←d2, d0 ←d1, C← d0

M(n3~n0) ←M(n3~n0)+1

r

0

1

1 r1 r0

↑ ↑

↓ ↓

Mn

0 n3 n2 n1 n0

1 n3 n2 n1 n0

↑ ↑

↓ ↓

DEC Mn

↑ ↑

↓ ↓

M(n3~n0) ←M(n3~n0)-1

ACPX MX, r

ACPY MY, r

SCPX MX, r

SCPY MY, r

0

1

0 r1 r0

1 r1 r0

0 r1 r0

1 r1 r0

ꢀ ↑ ↑

↓ ↓

M(X) ←M(X)+r+C, X ←X+1

M(Y) ←M(Y)+r+C, Y ←Y+1

M(X) ←M(X)-r-C, X← X+1

M(Y) ←M(Y)-r-C, Y← Y+1

r ←r

ꢀ ↑ ↑

↓ ↓

ꢀ ↑ ↑

↓ ↓

ꢀ ↑ ↑

↓ ↓

NOT

r

0 r1 r0 1

1

↑

↓

S1C6S3N7 TECHNICAL SOFTWARE

EPSON

II-69

APPENDIX A TABLE OF INSTRUCTIONS

Abbreviation s u sed in th e explan ation s h ave th e followin g

m ean in gs.

A .............. A register

B .............. B register

Symbols associated with

registers and memory

X .............. XHL register (low order eigh t bits of in dex register

IX)

Y .............. YHL register (low order eigh t bits of in dex

register IY)

XH ........... XH register (h igh order fou r bits of XHL register)

XL ............ XL register (low order fou r bits of XHL register)

YH ............ YH register (h igh order fou r bits of YHL register)

YL ............ YL register (low order fou r bits of YHL register)

XP ............ XP register (h igh order fou r bits of in dex

register IX)

YP ............ YP register (h igh order fou r bits of in dex

register IY)

SP ............ Stack poin ter SP

SPH .......... High -order fou r bits of stack poin ter SP

SPL .......... Low-order fou r bits of stack poin ter SP

MX, M(X) .. Data m em ory wh ose address is specified with

in dex register IX

MY, M(Y)... Data m em ory wh ose address is specified with

in dex register IY

Mn , M(n ) .. Data m em ory address 000H–00FH (address

specified with im m ediate data n of 00H–0FH)

M(SP) ....... Data m em ory wh ose address is specified with

stack poin ter SP

r, q ........... Two-bit register code

r, q is two-bit im m ediate data; accordin g to th e

con ten ts of th ese bits, th ey in dicate registers A,

B, an d MX an d MY (data m em ory wh ose ad-

dresses are specified with in dex registers IX an d

IY)

r

q

Registers specified

r1

0

r0

0

q1

0

q0

0

A

B

0

1

0

1

0

1

0

MX

MY

1

II-70

EPSON

S1C6S3N7 TECHNICAL SOFTWARE

APPENDIX A TABLE OF INSTRUCTIONS

Symbols associated with NBP ..... New ban k poin ter

program counter NPP ..... New page poin ter

PCB ..... Program cou n ter ban k

PCP ..... Program cou n ter page

PCS ..... Program cou n ter step

PCSH .. Fou r h igh order bits of PCS

PCSL ... Fou r low order bits of PCS

Symbols associated with

flags

F ......... Flag register (I, D, Z, C)

C ......... Carry flag

Z ......... Zero flag

D ......... Decim al flag

I .......... In terru pt flag

↓ ............. Flag reset

↑ ............. Flag set

ꢀ ......... Flag set or reset

Associated with p ......... Five-bit im m ediate data or label 00H–1FH

immediate data s .......... Eigh t-bit im m ediate data or label 00H–0FFH

l .......... Eigh t-bit im m ediate data 00H–0FFH

i .......... Fou r-bit im m ediate data 00H–0FH

Associated with

arithmetic and other

operations

+ ......... Add

- .......... Su btract

............. Logical AND

............. Logical OR

............ Exclu sive-OR

ꢀ......... Add-su btract in stru ction for decim al operation

wh en th e D flag is set

S1C6S3N7 TECHNICAL SOFTWARE

EPSON

II-71

APPENDIX B THE S1C6S3N7 I/O MEMORY MAP

APPENDIX B

The S1C6S3N7 I/ O Me m ory Ma p

DATA

AD-

DRESS

COMMENT

D3

K03

R

D2

K02

R

D1

K01

R

D0

K00

R

NAME

K03

K02

K01

K00

SR

–

0

–

0

–

0

–

0

–

0

–

0

–

0

1

0

LOW

–

HIGH

INPORT DATA K03

INPORT DATA K02

INPORT DATA K01

INPORT DATA K00

E0

E2

E3

E4

E8

EA

EB

ED

EE

EF

SWL3

R

SWL2

R

SWL1

R

SWL0

R

SWL3

SWL2

SWL1

SWL0

SWH3

SWH2

SWH1

SWH0

TM3

TM2

TM1

TM0

EIK03

EIK02

EIK01

EIK00

0

–

STOPWATCH TIMER DATA 3 (1/100) MSB

STOPWATCH TIMER DATA 2 (1/100)

STOPWATCH TIMER DATA 1 (1/100)

STOPWATCH TIMER DATA 0 (1/100) LSB

STOPWATCH TIMER DATA 3 (1/10) MSB

STOPWATCH TIMER DATA 2 (1/10)

STOPWATCH TIMER DATA 1 (1/10)

STOPWATCH TIMER DATA 0 (1/10) LSB

CLOCK TIMER DATA 2 Hz

CLOCK TIMER DATA 4 Hz

CLOCK TIMER DATA 8 Hz

CLOCK TIMER DATA 16 Hz

K03 INTERRUPT MASK REGISTER

K02 INTERRUPT MASK REGISTER

K01 INTERRUPT MASK REGISTER

K00 INTERRUPT MASK REGISTER

SWH3

R

SWH2

R

SWH1

R

SWH0

R

–

TM3

R

TM2

R

TM1

R

TM0

R

HIGH

ENABLE

–

LOW

MASK

–

EIK03

R/W

EIK02

R/W

EIK01

R/W

EIK00

R/W

0

R

0

R

EISW1

R/W

EISW0

R/W

0

–

EISW1

EISW0

0

EIT2

EIT8

EIT32

0

IK0

0

ENABLE

–

ENABLE

–

YES

–

YES

–

YES

MASK

–

MASK

–

NO

–

NO

–

NO

S/W INTERRUPT MASK REGISTER 1 Hz

S/W INTERRUPT MASK REGISTER 10 Hz

0

R

EIT2

R/W

EIT8

R/W

EIT32

R/W

TIMER INTERRUPT MASK REGISTER 2 Hz

TIMER INTERRUPT MASK REGISTER 8 Hz

TIMER INTERRUPT MASK REGISTER 32 Hz

0

R

0

R

0

R

IK0

R

K00–K03 INTERRUPT FACTOR FLAG

0

R

0

R

ISW1

R

ISW0

R

0

ISW1

ISW0

0

IT2

IT8

S/W INTERRUPT FACTOR FLAG 1 Hz

S/W INTERRUPT FACTOR FLAG 10 Hz

0

R

IT2

R

IT8

R

IT32

R

TIMER INTERRUPT FACTOR FLAG 2 Hz

TIMER INTERRUPT FACTOR FLAG 8 Hz

TIMER INTERRUPT FACTOR FLAG 32 Hz

IT32

II-72

EPSON

S1C6S3N7 TECHNICAL SOFTWARE

APPENDIX B THE S1C6S3N7 I/O MEMORY MAP

DATA

AD-

DRESS

COMMENT

D3

R03

D2

R02

D1

R01

D0

R00

FOUT

R/W

NAME

R03

R02

R01

BUZZER

R00

FOUT

P03

P02

P01

P00

SR

0

–

1

0

HIGH

ON

HIGH

ON

HIGH

–

RESET

RUN

RESET

HEAVY

–

LOW

OFF

LOW

OFF

LOW

–

R03 OUTPUT PORT DATA

R02 OUTPUT PORT DATA

R01 OUTPUT PORT DATA

BUZZER ON/OFF CONTROL REGISTER

R00 OUTPUT PORT DATA

FREQUENCY OUTPUT ON/OFF CONTROL REGISTER

P03 I/O PORT DATA

BUZZER

R/W

F3

P03

R/W

P02

R/W

P01

R/W

P00

R/W

P02 I/O PORT DATA

P01 I/O PORT DATA

P00 I/O PORT DATA

F6

F9

FA

FB

FC

0

R

TMRST

W

SWRUN

R/W

SWRST

W

0

TMRST

SWRUN

SWRST

HLMOD

0

SVDDT

SVDON

CSDC

0

IOC

XBZR

0

XFOUT1

XFOUT0

RESET

0

RESET

–

TIMER RESET

STOP

–

STOPWATCH RUN/STOP CONTROL REG.

STOPWATCH RESET

NORMAL HEAVY LOAD PROTECTION MODE

HLMOD

R/W

0

R

SVDDT

R

SVDON

R/W

0

–

0

–

0

–

0

–

LOW

ON

NORMAL SVD DATA

OFF

SVD ON-OFF CONTROL REGISTER

STATIC DYNAMIC LCD DRIVER CONTROL REG.

CSDC

R/W

0

R

0

R

0

R

–

0

R

0

R

0

R

IOC

R/W

–

IN

4 kHz

–

LOW

OUT

2 kHz

–

HIGH

I/O IN-OUT CONTROL REG.

BUZZER FREQUENCY CONTROL

XBZR

R/W

0

R

XFOUT1

R/W

XFOUT0

R/W

FOUT FREQUENCY CONTROL:

XFOUT1(0), XFOUT0(0) -> F1

XFOUT1(0), XFOUT0(1) -> F2

XFOUT1(1), XFOUT0(0) -> F3

XFOUT1(1), XFOUT0(1) -> F4

FD

S1C6S3N7 TECHNICAL SOFTWARE

EPSON

II-73

APPENDIX C TABLE OF THE ICE COMMANDS

APPENDIX C

Ta b le of the ICE Com m a nd s

Item No.

Function

Command Format

Outline of Operation

Assemble command mnemonic code and store at address "a"

Contents of addresses a1 to a2 are disassembled and displayed

Contents of program area a1 to a2 are displayed

Content of data area a1 to a2 are displayed

Data d is set in addresses a1 to a2 (program area)

Data d is set in addresses a1 to a2 (data area)

Program is executed from the "a" address

Execution time and step counter selection

On-the-fly display selection

1

2

3

Assemble

Disassemble #L,a1,a2

Dump

Fill

#A,a

#DP,a1,a2

#DD,a1,a2

#FP,a1,a2,d

#FD,a1,a2,d

#G,a

4

5

Set

Run Mode

#TIM

#OTF

6

7

Trace

Break

#T,a,n

Executes program while displaying results of step instruction

from "a" address

Displays only the final step of #T,a,n

Sets Break at program address "a"

Breakpoint is canceled

Break condition is set for data RAM

Breakpoint is canceled

Break condition is set for Evaluation Board CPU internal registers

Breakpoint is canceled

Combined break conditions set for program data RAM address

and registers

#U,a,n

#BA,a

#BAR,a

#BD

#BDR

#BR

#BRR

#BM

#BMR

Cancel combined break conditions for program data ROM

address and registers

#BRES

All break conditions canceled

#BC

Break condition displayed

#BE

Enter break enable mode

#BSYN

#BT

Enter break disable mode

Set break stop/trace modes

#BRKSEL,REM

#MP,a1,a2,a3

Set BA condition clear/remain modes

Contents of program area addresses a1 to a2 are moved to

addresses a3 and after

8

Move

#MD,a1,a2,a3

Contents of data area addresses a1 to a2 are moved to addresses

a3 and after

9

Data Set

#SP,a

#SD,a

Data from program area address "a" are written to memory

Data from data area address "a" are written to memory

Display Evaluation Board CPU internal registers

Set Evaluation Board CPU internal registers

Reset Evaluation Board CPU

10

Change CPU #DR

Internal

Registers

#SR

#I

#DXY

#SXY

Display X, Y, MX and MY

Set data for X and Y display and MX, MY

II-74

EPSON

S1C6S3N7 TECHNICAL SOFTWARE

APPENDIX C TABLE OF THE ICE COMMANDS

Item No.

Function

Command Format

Outline of Operation

11

History

#H,p1,p2

Display history data for pointer 1 and pointer 2

#HB

Display upstream history data

#HG

Display 21 line history data

#HP

Display history pointer

#HPS,a

#HC,S/C/E

Set history pointer

Sets up the history information acquisition before (S),

before/after (C) and after (E)

#HA,a1,a2

Sets up the history information acquisition from program area

a1 to a2

#HAR,a1,a2

Sets up the prohibition of the history information acquisition

from program area a1 to a2

#HAD

#HS,a

Indicates history acquisition program area

Retrieves and indicates the history information which executed

a program address "a"

#HSW,a

#HSR,a

#RF,file

#RFD,file

#VF,file

#VFD,file

#WF,file

#WFD,file

#CL,file

#CS,file

#CVD

Retrieves and indicates the history information which wrote or

read the data area address "a"

Move program file to memory

12

File

Move data file to memory

Compare program file and contents of memory

Compare data file and contents of memory

Save contents of memory to program file

Save contents of memory to data file

Load ICE set condition from file

Save ICE set condition to file

Indicates coverage information

Clears coverage information

13

14

Coverage

#CVR

ROM Access #RP

#VP

Move contents of ROM to program memory

Compare contents of ROM with contents of program memory

Set ROM type

#ROM

#Q

15

16

17

Terminate

ICE

Command

Display

Self

Terminate ICE and return to operating system control

#HELP

#CHK

Display ICE instruction

Report results of ICE self diagnostic test

Diagnosis

means press the RETURN key.

S1C6S3N7 TECHNICAL SOFTWARE

EPSON

II-75

APPENDIX D CROSS-ASSEMBLER PSEUDO-INSTRUCTION LIST

APPENDIX D

Cross-a sse m b le r Pse ud o-instruc tion List

Item No. Pseudo-instruction

Meaning

Example of Use

1

EQU

To allocate data to label

ABC

BCD

EQU

9

(Equation)

ABC+1

2

ORG

To define location counter

ORG

100H

256

(Origin)

3

SET

(Set)

To allocate data to label

(data can be changed)

ABC

SET

0001H

0002H

4

DW

To define ROM data

ABC

BCD

DW

'AB'

(Define Word)

0FFBH

5

PAGE

(Page)

To define boundary of page

To define boundary of section

To terminate assembly

To define macro

PAGE

1H

3

6

SECTION

(Section)

SECTION

7

END

(End)

8

MACRO

(Macro)

CHECK

LOCAL

LOOP

MACRO

LOOP

CP

DATA

9

LOCAL

(Local)

To make local specification of label

during macro definition

MX,DATA

NZ,LOOP

JP

10

ENDM

To end macro definition

ENDM

(End Macro)

CHECK

1

II-76

EPSON

S1C6S3N7 TECHNICAL SOFTWARE

International Sales Operations

AMERICA

ASIA

EPSON ELECTRONICS AMERICA, INC.

EPSON (CHINA) CO., LTD.

28F, Beijing Silver Tower 2# North RD DongSanHuan

ChaoYang District, Beijing, CHINA

- HEADQUARTERS -

1960 E. Grand Avenue

EI Segundo, CA 90245, U.S.A.

Phone: 64106655

Fax: 64107319

Phone: +1-310-955-5300

Fax: +1-310-955-5400

SHANGHAI BRANCH

4F, Bldg., 27, No. 69, Gui Jing Road

Caohejing, Shanghai, CHINA

- SALES OFFICES -

West

Phone: 21-6485-5552

Fax: 21-6485-0775

150 River Oaks Parkway

San Jose, CA 95134, U.S.A.

Phone: +1-408-922-0200

EPSON HONG KONG LTD.

20/F., Harbour Centre, 25 Harbour Road

Wanchai, Hong Kong

Phone: +852-2585-4600 Fax: +852-2827-4346

Telex: 65542 EPSCO HX

Fax: +1-408-922-0238

Fax: +1-815-455-7633

Central

101 Virginia Street, Suite 290

Crystal Lake, IL 60014, U.S.A.

Phone: +1-815-455-7630

EPSON TAIWAN TECHNOLOGY & TRADING LTD.

10F, No. 287, Nanking East Road, Sec. 3

Taipei

Northeast

301 Edgewater Place, Suite 120

Phone: 02-2717-7360

Fax: 02-2712-9164

Wakefield, MA 01880, U.S.A.

Telex: 24444 EPSONTB

Phone: +1-781-246-3600

Fax: +1-781-246-5443

HSINCHU OFFICE

13F-3, No. 295, Kuang-Fu Road, Sec. 2

HsinChu 300

Southeast

3010 Royal Blvd. South, Suite 170

Alpharetta, GA 30005, U.S.A.

Phone: +1-877-EEA-0020 Fax: +1-770-777-2637

Phone: 03-573-9900

Fax: 03-573-9169

EPSON SINGAPORE PTE., LTD.

No. 1 Temasek Avenue, #36-00

EUROPE

Millenia Tower, SINGAPORE 039192

Phone: +65-337-7911

Fax: +65-334-2716

EPSON EUROPE ELECTRONICS GmbH

SEIKO EPSON CORPORATION KOREA OFFICE

50F, KLI 63 Bldg., 60 Yoido-dong

Youngdeungpo-Ku, Seoul, 150-763, KOREA

- HEADQUARTERS -

Riesstrasse 15

80992 Munich, GERMANY

Phone: 02-784-6027

Fax: 02-767-3677

Phone: +49-(0)89-14005-0

Fax: +49-(0)89-14005-110

SALES OFFICE

Altstadtstrasse 176

51379 Leverkusen, GERMANY

Phone: +49-(0)2171-5045-0

SEIKO EPSON CORPORATION

ELECTRONIC DEVICES MARKETING DIVISION

Fax: +49-(0)2171-5045-10

Electronic Device Marketing Department

IC Marketing & Engineering Group

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

UK BRANCH OFFICE

Unit 2.4, Doncastle House, Doncastle Road

Bracknell, Berkshire RG12 8PE, ENGLAND

Phone: +81-(0)42-587-5816

Fax: +81-(0)42-587-5624

Phone: +44-(0)1344-381700

Fax: +44-(0)1344-381701

ED International Marketing Department Europe & U.S.A.

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

FRENCH BRANCH OFFICE

1 Avenue de l' Atlantique, LP 915 Les Conquerants

Phone: +81-(0)42-587-5812

Fax: +81-(0)42-587-5564

Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE

ED International Marketing Department Asia

Phone: +33-(0)1-64862350

Fax: +33-(0)1-64862355

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

Phone: +81-(0)42-587-5814

Fax: +81-(0)42-587-5110

BARCELONA BRANCH OFFICE

Barcelona Design Center

Edificio Prima Sant Cugat

Avda. Alcalde Barrils num. 64-68

E-08190 Sant Cugat del Vallès, SPAIN

Phone: +34-93-544-2490

Fax: +34-93-544-2491

In pursuit of “Saving”Technology, Epson electronic devices.

Our lineup of semiconductors, liquid crystal displays and quartz devices

assists in creating the products of our customers’ dreams.

Epson IS energy savings.

S1C6S3N7

Technical Manual

ELECTRONIC DEVICES MARKETING DIVISION

EPSON Electronic Devices Website

http://www.epson.co.jp/device/

First issue March, 1995

M

Printed March, 2001 in Japan

A


型号：	S1C6S3L7D
厂家：	SEIKO EPSON CORPORATION
描述：	Microcontroller, 4-Bit, MROM, 0.08MHz, CMOS, 3.09 X 3.02 MM, DIE-54 微控制器
文件：	总187页 (文件大小：1073K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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