S1D15705D10B000 [SEIKO]
Liquid Crystal Driver, 233-Segment, CMOS, DIE-337;
| 型号： | S1D15705D10B000 |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | Liquid Crystal Driver, 233-Segment, CMOS, DIE-337 驱动 接口集成电路 |
| 文件： | 总83页 (文件大小：596K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S1D15705 Series
Technical Manual
Rev.3.2
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written
permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material
or due to its application or use in any product or circuit and, further, there is no representation that this material is
applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any
intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that
anything made in accordance with this material will be free from any patent or copyright infringement of a third
party. This material or portions thereof may contain technology or the subject relating to strategic products
under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license
from the Ministry of International Trade and Industry or other approval from another government agency.
All other product names mentioned herein are trademarks and/or registered trademarks of their respective
companies.
©SEIKO EPSON CORPORATION 2005, All rights reserved.
Configuration of product number
●DEVICES
S1 D 15705 D 00B0 00
Packing specification
Specifications
Shape (D:Chip, T:TCP, F:QFP)
Model number
Model name (D:LCD Driver)
Product classification (S1:Semiconductors)
Contents
1. DESCRIPTION ................................................................................................................................................... 1
2. FEATURES......................................................................................................................................................... 1
3. BLOCK DIAGRAM .............................................................................................................................................. 3
4. PAD .................................................................................................................................................................... 4
5. PIN DESCRIPTION .......................................................................................................................................... 14
6. FUNCTION DESCRIPTION.............................................................................................................................. 18
7. COMMAND ....................................................................................................................................................... 38
8. COMMAND SETTING ...................................................................................................................................... 50
9. ABSOLUTE MAXIMUM RATINGS ................................................................................................................... 54
10. DC CHARACTERISTICS.................................................................................................................................. 55
11. MICROPROCESSOR (MPU) INTERFACE: REFERENCE .............................................................................. 70
12. CONNECTION BETWEEN LCD DRIVERS: REFERENCE ............................................................................. 71
13. LCD PANEL WIRING: REFERENCE ............................................................................................................... 72
14. TCP PIN LAYOUT ............................................................................................................................................ 73
15. TCP DIMENSIONS ........................................................................................................................................... 74
16. TEMPERATURE SENSOR CIRCUIT ............................................................................................................... 75
17. CAUTIONS ....................................................................................................................................................... 78
– i –
Rev. 3.2
S1D15705 Series Technical Manual
The S1D15707 Series
33 circuits for the common output and 200 circuits
1. DESCRIPTION
The S1D15705 series is a 1-chip dot matrix liquid
crystal driver that can be connected to the bus of a
microcomputer. It stores the 8-bit parallel or serial
display data sent from the microcomputer in the built-in
display data RAM and generates liquid crystal drive
signals independently of the microcomputer. Since it
incorporates 65 × 200 bits of the display data RAM and
the one-dot pixel of the liquid crystal panel and one bit
of the built-in RAM have a one-to-one correspondence,
it enables display with the high degree of freedom.
The S1D15705 series incorporates 65 circuits of the
common output and 168 circuits of the segment output
and can display 65 × 168 dots (capable of displaying 10
columns × 4 rows of a 16 × 16 dot kanji font) using the
single chip. The S1D15707 Series incorporates 33
circuits of the common output and 200 circuits of the
segment output and can display 33 × 200 dots (capable
of displaying 12 columns × 2 rows of a 16 × 16 dot kanji
font). The S1D15708 series incorporates 17 circuits of
the common output and 200 circuits of the segment
output and can display 17 × 200 dots (capable of
displaying 12 columns × 1 rows of a 16 × 16 dot kanji
font). It can also expand the display capacity by using
the two chips for the master and slave configuration.
Incorporating an analog temperature sensor circuit, the
for the segment output
The S1D15708 Series
17 circuits for the common output and 200 circuits
for the segment output
• High-speed 8-bit MPU interface (Both the 80 and 68
series MUPs can directly be connected.)/serial
interface enabled
• Abundant command functions
Display Data Read/Write, Display ON/OFF, Display
Normal Rotation/Reversal, Page Address Set, Display
Start Line Set, column address set, Status Read,
Power Supply Save Display All Lighting ON/OFF,
LCD Bias Set, Read Modify Write, Segment Driver
Direction Select, Electronic Control, V5 Voltage
Adjusting Built-in Resistance Ratio Set, Static
Indicator, n Line Alternating Current Reversal Drive,
Common Output State Selection, and Built-in
Oscillator Circuit ON
• Built-in static drive circuit for indicators (One set,
blinking speed variable)
• Built-in power supply circuit for low power supply
liquid crystal drive
Booster circuit (Boosting magnification - double,
triple, quadruple, boosting reference power supply
external input enabled)
S1D15705*10** can be used to constitute a system to
• 3% high accuracy alternating current voltage adjusting
circuit (Temperature gradient: –0.05%/°C)
Built-in V5 voltage adjusting resistor, built-in V1 to
V4 voltage generation split resistors, built-in
electronic control function, and voltage follower
• Built-in CR oscillator circuit (external clock input
enabled)
• Ultra-low power consumption
• Built-in temperature sensor circuit (S1D15705D10B )
• Power supplies
provide optimum LCD contrast throughout a wide
temperature range without need for use of supplementary
parts such as the thermistor, under controls of a
microcomputer.
Since the read/write operation of the display data RAM
does not require external operation clocks, the S1D15705
series can be operated with the minimum current
consumption. Since it also incorporates a liquid crystal
drive power supply with low current consumption,
liquid crystal drive power supply voltage adjusting
resistor, and display clock CR oscillator circuit, it can
provide a display system for high performance handy
equipment with the minimum current consumption and
the minimum parts configuration.
*
Logic power supply: VDD – VSS = 2.4 to 3.6 V
(S1D157V05D*D0–3*V*SS, S=13D.165t7o057.*50V3**)
(S1D15705*00**, S1D15707*00**, S1D15708*00**)
Boosting reference power supply: VDD – VSS = 1.8 to
6.0 V
2. FEATURES
Liquid crystal drive power supply: V5 – VDD = –4.5 to
• Direct display of RAM data using the display data
RAM
–18.0 V (S1D15705*****) /–4.5 V to –16.0 V
(S1D15707
*****)/–4.5 V to –10.0 (S1D15708*****)
RAM bit data “1” .... goes on.
“0” .... goes off (at display normal
rotation).
• Wide operating temperature range –40 to 85°C
• CMOS process
• Shipping form Bare chip, TCP
• No light-resistant and radiation-resistant design are
provided.
• RAM capacity
65 × 200 = 13,000 bits
• Liquid crystal drive circuit
The S1D15705 Series
65 circuits for the common output and 168 circuits
for the segment output
Rev. 3.2
EPSON
1
S1D15705 Series Technical Manual
Series specification
Product
name
Voltage
[V]
VREG temperature Shipping
Duty
Bias
SEG Dr COM Dr
gradient
–0.05%/°C
–0.05%/°C
–0.05%/°C
–0.05%/°C
–0.05%/°C
–0.05%/°C
–0.05%/°C
–0.05%/°C
–0.05%/°C
–0.05%/°C
form
Bare chip
Bare chip
Bare chip
TCP
S1D15705D00B –3.6 to –5.5 1/65 1/9, 1/7
168
168
168
168
168
200
200
200
200
200
65
65
65
65
65
33
33
33
33
17
*
*
*
*
*
*
*
S1D15705D10B –3.6 to –5.5 1/65 1/9, 1/7
S1D15705D03B –2.4 to –3.6 1/65 1/9, 1/7
S1D15705T00A –3.6 to –5.5 1/65 1/9, 1/7
S1D15705T03A –2.4 to –3.6 1/65 1/9, 1/7
TCP
S1D15707D00B –3.6 to –5.5 1/33 1/6, 1/5
Bare chip
Bare chip
TCP
S1D15707D03B –2.4 to –3.6 1/33 1/6, 1/5
S1D15707T00** –3.6 to –5.5
1/33 1/6, 1/5
S1D15707T03** –2.4 to –3.6
1/33 1/6, 1/5
TCP
S1D15708D00B –3.6 to –5.5 1/17 1/6, 1/5
Bare chip
*
Specifications for circuits other than the temperature sensor circuit are the same as those of the
S1D15705D00B .
*
2
EPSON
Rev. 3.2
S1D15705 Series Technical Manual
3. BLOCK DIAGRAM
Example : S1D15705*****
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • • • • • • • • •
V
SS
V
DD
V
1
2
3
4
5
V
SEG Drivers
COM Drivers
Shift register
V
V
V
Display data latch circuit
CAP1+
CAP1–
CAP2+
CAP2–
CAP3–
FRS
FR
SYNC
CL
Display data RAM
200 x 65
V
OUT
DOF
M/S
V
SS2
V
R
V
RS
IRS
HPM
Column address
CLS
Bus holder
Command decoder
MPU Interface
Status
Rev. 3.2
EPSON
3
S1D15705 Series Technical Manual
4. PAD
Pad layout
93
1
94
337
303
S1D15705 Series
(0, 0)
Die No.
(ex. S1D15705D00B )
*
128
129
302
Size
Item
Unit
mm
X
Y
Chip size
13.30
×
2.81
Chip thickness
Bump pitch
0.625
mm
71 (Min.)
µm
Bump size
PAD No.1 to 93
PAD No.94
PAD No.95 to 127
PAD No.128
PAD No.129
PAD No.130 to 301
PAD No.302
PAD No.303
PAD No.304 to 336
PAD No.337
85
85
×
×
×
×
×
×
×
×
×
×
85
73
47
73
85
85
85
73
47
73
µm
µm
µm
µm
µm
µm
µm
µm
µm
µm
85
85
73
47
73
86
85
85
Bump height
17 (Typ.)
µm
4
EPSON
Rev. 3.2
S1D15705 Series Technical Manual
S1D15705***** Pad Central Coordinates
Unit: µm
PAD
No.
PIN
Name
PAD
No.
PIN
Name
PAD
No.
PIN
Name
X
Y
X
Y
X
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
(NC)
(NC)
SYNC 5922
FRS
FR
CL
DOF
SYNC 5240
VSS
CS1
CS2
VDD
RES
A0
6195 1246
6059
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
CAP2– –567 1246
CAP2+ –701
CAP2+ –835
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
COM25 –6474 727
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
COMS
(NC)
654
581
509
436
363
291
218
145
73
5786
5649
5513
5376
VSS
VSS
VRS
VRS
VDD
VDD
V1
V1
V2
V2
–969
–1103
–1237
–1371
–1505
–1639
–1772
–1906
–2040
–2174
5103
4967
4830
4694
4557
4421
4284
0
–73
–145
–218
–291
–363
–436
–509
–581
–654
–727
–800
–872
–945
–1018
–1090
–1163
–1248
(NC) –2308
VSS
V3
V3
V4
V4
V5
V5
–2442
–2576
–2710
–2844
–2978
–3111
16 WR, R/W 4148
17
18
19
20
21
22
23
24
RD, E 4011
VDD
D0
D1
D2
D3
D4
D5
3875
3738
3602
3465
3329
3192
3056
(NC) –3245
VR
–3379
TEST1 –3513
TEST2 –3647
TEST3 –3781
TEST4 –3915
25 D6 (SCL) 2919
D7 (SI) 2783
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS2
VSS2
VSS2
VSS2
VSS2
(NC)
VOUT
VOUT
CAP3–
CAP3–
(NC)
CAP1+
CAP1+
2646
2512
2378
2245
2111
1977
1843
1709
1575
1441
1307
1173
1039
906
772
638
504
370
236
102
–32
VDD
M/S
CLS
VSS
C86
P/S
–4049
–4185
–4322
–4458
–4595
–4731
–4868
(NC) –6232 –1246
(NC) –6147
(NC) –6075
SEG0 –6002
SEG1 –5930
SEG2 –5859
SEG3 –5787
SEG4 –5715
SEG5 –5643
SEG6 –5571
SEG7 –5499
SEG8 –5427
SEG9 –5355
SEG10 –5283
SEG11 –5212
SEG12 –5140
SEG13 –5068
SEG14 –4996
SEG15 –4924
SEG16 –4852
SEG17 –4780
SEG18 –4708
VDD
HPM –5004
VSS
IRS
VDD
–5141
–5277
–5414
TEST5 –5550
TEST6 –5687
TEST7 –5836
TEST8 –5956
TEST9 –6076
(NC) –6195
(NC) –6474 1248
COM31
COM30
COM29
COM28
COM27
COM26
1163
1090
1017
945
872
799
CAP1– –166
CAP1– –300
CAP2– –433
Rev. 3.2
EPSON
5
S1D15705 Series Technical Manual
Unit: µm
PAD
No.
PIN
Name
PAD
No.
PIN
Name
PAD
No.
PIN
Name
X
Y
X
Y
X
Y
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
SEG19 –4636 –1246
SEG20 –4564
SEG21 –4493
SEG22 –4421
SEG23 –4349
SEG24 –4277
SEG25 –4205
SEG26 –4133
SEG27 –4061
SEG28 –3989
SEG29 –3917
SEG30 –3846
SEG31 –3774
SEG32 –3702
SEG33 –3630
SEG34 –3558
SEG35 –3486
SEG36 –3414
SEG37 –3342
SEG38 –3270
SEG39 –3199
SEG40 –3127
SEG41 –3055
SEG42 –2983
SEG43 –2911
SEG44 –2839
SEG45 –2767
SEG46 –2695
SEG47 –2623
SEG48 –2552
SEG49 –2480
SEG50 –2408
SEG51 –2336
SEG52 –2264
SEG53 –2192
SEG54 –2120
SEG55 –2048
SEG56 –1976
SEG57 –1905
SEG58 –1833
SEG59 –1761
SEG60 –1689
SEG61 –1617
SEG62 –1545
SEG63 –1473
SEG64 –1401
SEG65 –1329
SEG66 –1258
SEG67 –1186
SEG68 –1114
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
SEG69 –1042 –1246
SEG70 –970
SEG71 –898
SEG72 –826
SEG73 –754
SEG74 –682
SEG75 –611
SEG76 –539
SEG77 –467
SEG78 –395
SEG79 –323
SEG80 –251
SEG81 –179
SEG82 –107
SEG83 –35
251 SEG119 2553 –1246
252 SEG120 2625
253 SEG121 2696
254 SEG122 2768
255 SEG123 2840
256 SEG124 2912
257 SEG125 2984
258 SEG126 3056
259 SEG127 3128
260 SEG128 3200
261 SEG129 3272
262 SEG130 3343
263 SEG131 3415
264 SEG132 3487
265 SEG133 3559
266 SEG134 3631
267 SEG135 3703
268 SEG136 3775
269 SEG137 3847
270 SEG138 3919
271 SEG139 3990
272 SEG140 4062
273 SEG141 4134
274 SEG142 4206
275 SEG143 4278
276 SEG144 4350
277 SEG145 4422
278 SEG146 4494
279 SEG147 4566
280 SEG148 4637
281 SEG149 4709
282 SEG150 4781
283 SEG151 4853
284 SEG152 4925
285 SEG153 4997
286 SEG154 5069
287 SEG155 5141
288 SEG156 5213
289 SEG157 5284
290 SEG158 5356
291 SEG159 5428
292 SEG160 5500
293 SEG161 5572
294 SEG162 5644
295 SEG163 5716
296 SEG164 5788
297 SEG165 5860
298 SEG166 5931
299 SEG167 6003
SEG84
36
SEG85 108
SEG86 180
SEG87 252
SEG88 324
SEG89 396
SEG90 468
SEG91 540
SEG92 612
SEG93 683
SEG94 755
SEG95 827
SEG96 899
SEG97 971
SEG98 1043
SEG99 1115
232 SEG100 1187
233 SEG101 1259
234 SEG102 1330
235 SEG103 1402
236 SEG104 1474
237 SEG105 1546
238 SEG106 1618
239 SEG107 1690
240 SEG108 1762
241 SEG109 1834
242 SEG110 1906
243 SEG111 1977
244 SEG112 2049
245 SEG113 2121
246 SEG114 2193
247 SEG115 2265
248 SEG116 2337
249 SEG117 2409
250 SEG118 2481
300
(NC)
6075
6
EPSON
Rev. 3.2
S1D15705 Series Technical Manual
Unit: µm
PAD
No.
PIN
Name
X
Y
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
(NC)
(NC)
(NC)
6147 –1246
6232
↓
6474 –1248
–1163
–1090
–1018
–945
–872
–800
–727
–654
–581
–509
–436
–363
–291
–218
–145
–73
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COMS
0
73
145
218
291
363
436
509
581
654
727
799
872
945
1017
1090
1163
1248
(NC)
Rev. 3.2
EPSON
7
S1D15705 Series Technical Manual
S1D15707***** Pad Central Coordinates
Unit: µm
PAD
No.
PIN
Name
PAD
No.
PIN
Name
PAD
No.
PIN
Name
X
Y
X
Y
X
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
(NC)
(NC)
SYNC 5922
FRS
FR
CL
DOF
SYNC 5240
VSS
CS1
CS2
VDD
RES
A0
6195 1246
6059
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
CAP2– –567 1246
CAP2+ –701
CAP2+ –835
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
COM25 –6474 727
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
COMS
(NC)
654
581
509
436
363
291
218
145
73
5786
5649
5513
5376
VSS
VSS
VRS
VRS
VDD
VDD
V1
V1
V2
V2
–969
–1103
–1237
–1371
–1505
–1639
–1772
–1906
–2040
–2174
5103
4967
4830
4694
4557
4421
4284
0
–73
–145
–218
–291
–363
–436
–509
–581
–654
–727
–800
–872
–945
–1018
–1090
–1163
–1248
(NC) –2308
VSS
V3
V3
V4
V4
V5
V5
–2442
–2576
–2710
–2844
–2978
–3111
16 WR, R/W 4148
17
18
19
20
21
22
23
24
RD, E 4011
VDD
D0
D1
D2
D3
D4
D5
3875
3738
3602
3465
3329
3192
3056
(NC) –3245
VR
–3379
TEST1 –3513
TEST2 –3647
TEST3 –3781
TEST4 –3915
25 D6 (SCL) 2919
D7 (SI) 2783
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS2
VSS2
VSS2
VSS2
VSS2
(NC)
VOUT
VOUT
CAP3–
CAP3–
(NC)
CAP1+
CAP1+
2646
2512
2378
2245
2111
1977
1843
1709
1575
1441
1307
1173
1039
906
772
638
504
370
236
102
–32
VDD
M/S
CLS
VSS
C86
P/S
–4049
–4185
–4322
–4458
–4595
–4731
–4868
(NC) –6232 –1246
(NC) –6147
(NC) –6075
SEG0 –6002
SEG1 –5930
SEG2 –5859
SEG3 –5787
SEG4 –5715
SEG5 –5643
SEG6 –5571
SEG7 –5499
SEG8 –5427
SEG9 –5355
SEG10 –5283
SEG11 –5212
SEG12 –5140
SEG13 –5068
SEG14 –4996
SEG15 –4924
SEG16 –4852
SEG17 –4780
SEG18 –4708
VDD
HPM –5004
VSS
IRS
VDD
–5141
–5277
–5414
TEST5 –5550
TEST6 –5687
TEST7 –5836
TEST8 –5956
TEST9 –6076
(NC) –6195
(NC) –6474 1248
COM31
COM30
COM29
COM28
COM27
COM26
1163
1090
1017
945
872
799
CAP1– –166
CAP1– –300
CAP2– –433
8
EPSON
Rev. 3.2
S1D15705 Series Technical Manual
Unit: µm
PAD
No.
PIN
Name
PAD
No.
PIN
Name
PAD
No.
PIN
Name
X
Y
X
Y
X
Y
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
SEG19 –4636 –1246
SEG20 –4564
SEG21 –4493
SEG22 –4421
SEG23 –4349
SEG24 –4277
SEG25 –4205
SEG26 –4133
SEG27 –4061
SEG28 –3989
SEG29 –3917
SEG30 –3846
SEG31 –3774
SEG32 –3702
SEG33 –3630
SEG34 –3558
SEG35 –3486
SEG36 –3414
SEG37 –3342
SEG38 –3270
SEG39 –3199
SEG40 –3127
SEG41 –3055
SEG42 –2983
SEG43 –2911
SEG44 –2839
SEG45 –2767
SEG46 –2695
SEG47 –2623
SEG48 –2552
SEG49 –2480
SEG50 –2408
SEG51 –2336
SEG52 –2264
SEG53 –2192
SEG54 –2120
SEG55 –2048
SEG56 –1976
SEG57 –1905
SEG58 –1833
SEG59 –1761
SEG60 –1689
SEG61 –1617
SEG62 –1545
SEG63 –1473
SEG64 –1401
SEG65 –1329
SEG66 –1258
SEG67 –1186
SEG68 –1114
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
SEG69 –1042 –1246
SEG70 –970
SEG71 –898
SEG72 –826
SEG73 –754
SEG74 –682
SEG75 –611
SEG76 –539
SEG77 –467
SEG78 –395
SEG79 –323
SEG80 –251
SEG81 –179
SEG82 –107
SEG83 –35
251 SEG119 2553 –1246
252 SEG120 2625
253 SEG121 2696
254 SEG122 2768
255 SEG123 2840
256 SEG124 2912
257 SEG125 2984
258 SEG126 3056
259 SEG127 3128
260 SEG128 3200
261 SEG129 3272
262 SEG130 3343
263 SEG131 3415
264 SEG132 3487
265 SEG133 3559
266 SEG134 3631
267 SEG135 3703
268 SEG136 3775
269 SEG137 3847
270 SEG138 3919
271 SEG139 3990
272 SEG140 4062
273 SEG141 4134
274 SEG142 4206
275 SEG143 4278
276 SEG144 4350
277 SEG145 4422
278 SEG146 4494
279 SEG147 4566
280 SEG148 4637
281 SEG149 4709
282 SEG150 4781
283 SEG151 4853
284 SEG152 4925
285 SEG153 4997
286 SEG154 5069
287 SEG155 5141
288 SEG156 5213
289 SEG157 5284
290 SEG158 5356
291 SEG159 5428
292 SEG160 5500
293 SEG161 5572
294 SEG162 5644
295 SEG163 5716
296 SEG164 5788
297 SEG165 5860
298 SEG166 5931
299 SEG167 6003
SEG84
36
SEG85 108
SEG86 180
SEG87 252
SEG88 324
SEG89 396
SEG90 468
SEG91 540
SEG92 612
SEG93 683
SEG94 755
SEG95 827
SEG96 899
SEG97 971
SEG98 1043
SEG99 1115
232 SEG100 1187
233 SEG101 1259
234 SEG102 1330
235 SEG103 1402
236 SEG104 1474
237 SEG105 1546
238 SEG106 1618
239 SEG107 1690
240 SEG108 1762
241 SEG109 1834
242 SEG110 1906
243 SEG111 1977
244 SEG112 2049
245 SEG113 2121
246 SEG114 2193
247 SEG115 2265
248 SEG116 2337
249 SEG117 2409
250 SEG118 2481
300
(NC)
6075
Rev. 3.2
EPSON
9
S1D15705 Series Technical Manual
Unit: µm
PAD
No.
PIN
Name
X
Y
301
302
303
(NC)
(NC)
(NC)
6147 –1246
6232
↓
6474 –1248
–1163
–1090
–1018
–945
–872
–800
–727
–654
–581
–509
–436
–363
–291
–218
–145
–73
304 SEG168
305 SEG169
306 SEG170
307 SEG171
308 SEG172
309 SEG173
310 SEG174
311 SEG175
312 SEG176
313 SEG177
314 SEG178
315 SEG179
316 SEG180
317 SEG181
318 SEG182
319 SEG183
320 SEG184
321 SEG185
322 SEG186
323 SEG187
324 SEG188
325 SEG189
326 SEG190
327 SEG191
328 SEG192
329 SEG193
330 SEG194
331 SEG195
332 SEG196
333 SEG197
334 SEG198
335 SEG199
0
73
145
218
291
363
436
509
581
654
727
799
872
945
1017
1090
1163
1248
336
337
COMS
(NC)
10
EPSON
Rev. 3.2
S1D15705 Series Technical Manual
S1D15708***** Pad Central Coordinates
Unit: µm
PAD
No.
PIN
Name
PAD
No.
PIN
Name
PAD
No.
PIN
Name
X
Y
X
Y
X
Y
1
2
3
4
5
6
7
8
(NC)
(NC)
SYNC 5922
FRS
FR
CL
6159 1246
6059
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
CAP2– –567 1246
CAP2+ –701
CAP2+ –835
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
COM12 –6474 727
COM12
COM11
COM11
COM10
COM10
COM9
COM9
COM8
COM8
COM7
COM7
COM6
COM6
COM5
COM5
COM4
COM4
COM3
COM3
COM2
COM2
COM1
COM1
COM0
COM0
COMS
(NC)
654
581
509
436
363
291
218
145
73
5786
5649
5513
5376
VSS
VSS
VRS
VRS
VDD
VDD
V1
V1
V2
V2
(NC)
V3
V3
V4
V4
V5
V5
(NC)
VR
–969
–1103
–1237
–1371
–1505
–1639
–1772
–1906
–2040
–2174
–2308
–2442
–2576
–2710
–2844
–2978
–3111
–3245
–3379
DOF
SYNC 5240
9
VSS
CS1
CS2
VDD
RES
A0
5103
4967
4830
4694
4557
4421
4284
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
0
–73
–145
–218
–291
–363
–436
–509
–581
–654
–727
–800
–872
–945
–1018
–1090
–1163
–1248
–6232 –1246
–6147
–6075
VSS
WR,R/W 4148
RD, E 4011
VDD
D0
D1
D2
D3
D4
D5
3875
3738
3602
3465
3329
3192
3056
TEST1 –3513
TEST2 –3647
TEST3 –3781
TEST4 –3915
25 D6 (SCL) 2919
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
D7 (SI) 2783
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS2
VSS2
VSS2
VSS2
VSS2
(NC)
VOUT
VOUT
CAP3–
CAP3–
(NC)
CAP1+
CAP1+
2646
2512
2378
2245
2111
1977
1843
1709
1575
1441
1307
1173
1039
906
772
638
504
370
236
102
–32
VDD
M/S
CLS
VSS
C86
P/S
–4049
–4185
–4322
–4458
–4595
–4731
–4868
(NC)
(NC)
(NC)
SEG0 –6002
SEG1 –5930
SEG2 –5859
SEG3 –5787
SEG4 –5715
SEG5 –5643
SEG6 –5571
SEG7 –5499
SEG8 –5427
SEG9 –5355
SEG10 –5283
SEG11 –5212
SEG12 –5140
SEG13 –5068
SEG14 –4996
SEG15 –4924
SEG16 –4852
SEG17 –4780
SEG18 –4708
VDD
HPM –5004
VSS
IRS
VDD
–5141
–5277
–5414
TEST5 –5550
TEST6 –5687
TEST7 –5836
TEST8 –5956
TEST9 –6076
(NC)
(NC)
–6195
–6474 1248
1163
COM15
COM15
COM14
COM14
COM13
COM13
1090
1017
945
872
CAP1– –166
CAP1– –300
CAP2– –433
799
Rev. 3.2
EPSON
11
S1D15705 Series Technical Manual
Unit: µm
PAD
No.
PIN
Name
PAD
No.
PIN
Name
PAD
No.
PIN
Name
X
Y
X
Y
X
Y
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
SEG19 –4636 –1246
SEG20 –4564
SEG21 –4493
SEG22 –4421
SEG23 –4349
SEG24 –4277
SEG25 –4205
SEG26 –4133
SEG27 –4061
SEG28 –3989
SEG29 –3917
SEG30 –3846
SEG31 –3774
SEG32 –3702
SEG33 –3630
SEG34 –3558
SEG35 –3486
SEG36 –3414
SEG37 –3342
SEG38 –3270
SEG39 –3199
SEG40 –3127
SEG41 –3055
SEG42 –2983
SEG43 –2911
SEG44 –2839
SEG45 –2767
SEG46 –2695
SEG47 –2623
SEG48 –2552
SEG49 –2480
SEG50 –2408
SEG51 –2336
SEG52 –2264
SEG53 –2192
SEG54 –2120
SEG55 –2048
SEG56 –1976
SEG57 –1905
SEG58 –1833
SEG59 –1761
SEG60 –1689
SEG61 –1617
SEG62 –1545
SEG63 –1473
SEG64 –1401
SEG65 –1329
SEG66 –1258
SEG67 –1186
SEG68 –1114
251 SEG119 2553 –1246
252 SEG120 2625
253 SEG121 2696
254 SEG122 2768
255 SEG123 2840
256 SEG124 2912
257 SEG125 2984
258 SEG126 3056
259 SEG127 3128
260 SEG128 3200
261 SEG129 3272
262 SEG130 3343
263 SEG131 3415
264 SEG132 3487
265 SEG133 3559
266 SEG134 3631
267 SEG135 3703
268 SEG136 3775
269 SEG137 3847
270 SEG138 3919
271 SEG139 3990
272 SEG140 4062
273 SEG141 4134
274 SEG142 4206
275 SEG143 4278
276 SEG144 4350
277 SEG145 4422
278 SEG146 4494
279 SEG147 4566
280 SEG148 4637
281 SEG149 4709
282 SEG150 4781
283 SEG151 4853
284 SEG152 4925
285 SEG153 4997
286 SEG154 5069
287 SEG155 5141
288 SEG156 5213
289 SEG157 5284
290 SEG158 5356
291 SEG159 5428
292 SEG160 5500
293 SEG161 5572
294 SEG162 5644
295 SEG163 5716
296 SEG164 5788
297 SEG165 5860
298 SEG166 5931
299 SEG167 6003
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
SEG69 –1042 –1246
SEG70 –970
SEG71 –898
SEG72 –826
SEG73 –754
SEG74 –682
SEG75 –611
SEG76 –539
SEG77 –467
SEG78 –395
SEG79 –323
SEG80 –251
SEG81 –179
SEG82 –107
SEG83 –35
SEG84
36
SEG85 108
SEG86 180
SEG87 252
SEG88 324
SEG89 396
SEG90 468
SEG91 540
SEG92 612
SEG93 683
SEG94 755
SEG95 827
SEG96 899
SEG97 971
SEG98 1043
SEG99 1115
232 SEG100 1187
233 SEG101 1259
234 SEG102 1330
235 SEG103 1402
236 SEG104 1474
237 SEG105 1546
238 SEG106 1618
239 SEG107 1690
240 SEG108 1762
241 SEG109 1834
242 SEG110 1906
243 SEG111 1977
244 SEG112 2049
245 SEG113 2121
246 SEG114 2193
247 SEG115 2265
248 SEG116 2337
249 SEG117 2409
250 SEG118 2481
300
(NC)
6075
12
EPSON
Rev. 3.2
S1D15705 Series Technical Manual
Unit: µm
PAD
No.
PIN
Name
X
Y
301
302
303
(NC)
(NC)
(NC)
6147 –1246
6232
↓
6474 –1248
–1163
–1090
–1018
–945
–872
–800
–727
–654
–581
–509
–436
–363
–291
–218
–145
–73
304 SEG168
305 SEG169
306 SEG170
307 SEG171
308 SEG172
309 SEG173
310 SEG174
311 SEG175
312 SEG176
313 SEG177
314 SEG178
315 SEG179
316 SEG180
317 SEG181
318 SEG182
319 SEG183
320 SEG184
321 SEG185
322 SEG186
323 SEG187
324 SEG188
325 SEG189
326 SEG190
327 SEG191
328 SEG192
329 SEG193
330 SEG194
331 SEG195
332 SEG196
333 SEG197
334 SEG198
335 SEG199
0
73
145
218
291
363
436
509
581
654
727
799
872
945
1017
1090
1163
1248
336
337
COMS
(NC)
Rev. 3.2
EPSON
13
S1D15705 Series Technical Manual
5. PIN DESCRIPTION
Power Supply Pin
Number of
pins
Pin name
I/O
Description
VDD
Power Commonly used with the MPU power supply pin VCC.
supply
12
VSS
VSS2
VRS
Power 0 V pin connected to the system ground (GND).
supply
9
Power Boosting circuit reference power supply for liquid crystal drive.
supply
5
Power External input pin for liquid crystal power supply voltage
supply adjusting circuit.
2
They are set to OPEN.
V1, V2
V3, V4
V5
Power Multi-level power supply for liquid crystal drive. The voltage
supply specified according to liquid crystal cells is impedance-converted
by a split resistor or operation amplifier (OP amp) and applied.
The potential needs to be specified based on VDD to establish the
relationship of dimensions shown below:
10
VDD (=V0) ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5
Master operation When the power supply is ON, the following
voltages are applied to V1 to V4 from the built-in power supply
circuit. The selection of the voltages is determined using the LCD
bias set command.
S1D15705*** S1D15707***, S1D15708***
V1 1/9•V5
V2 2/9•V5
V3 7/9•V5
V4 8/9•V5
1/7•V5
2/7•V5
5/7•V5
6/7•V5
1/6•V5
2/6•V5
4/6•V5
5/6•V5
1/5•V5
2/5•V5
3/5•V5
4/5•V5
LCD Power Supply Circuit Pin
Number of
pins
Pin name
I/O
Description
CAP1+
O
Boosting capacitor positive side connecting pin. Connects
a capacitor between the pin and CAP1– pin.
2
2
2
2
2
CAP1–
CAP2+
CAP2–
CAP3–
O
O
O
O
Boosting capacitor negative side connecting pin. Connects
a capacitor between the pin and CAP1+ pin.
Boosting capacitor positive side connecting pin. Connects
a capacitor between the pin and CAP2– pin.
Boosting capacitor negative side connecting pin. Connects
a capacitor between the pin and CAP2+ pin.
Boosting capacitor negative side connecting pin. Connects
a capacitor between the pin and CAP1+ pin.
VOUT
VR
O
I
Boosting output pin. Connects a capacitor between the pin and VSS2.
2
1
Voltage adjusting pin. Applies voltage between VDD and V5 using
a split resistor.
Valid only when the V5 voltage adjusting built-in resistor is not used
(IRS=LOW)
Do not use VR when the V5 voltage adjusting built-in resistor is
used (IRS=HIGH)
14
EPSON
Rev. 3.2
S1D15705 Series Technical Manual
System Bus Connecting Pins
Number of
pins
Pin name
I/O
Description
D7 to D0
(SI)
(SCL)
I/O
An 8-bit bidirectional data bus is used to connect an 8-bit or 16-bit
standard MPU data bus.
When the serial interface is selected (P/S=LOW),
D7: Serial data entry pin (SI)
8
D6: Serial clock input pin (SCL)
In this case, D0 to D5 are set to high impedance.
When Chip Select is in the non-active state, D0 to D7 are set to
high impedance.
A0
I
Normally the lowest order bit of the MPU address bus is connected
to discriminate data / commands.
1
A0=HIGH: Indicates that D0 to D7 are display data.
A0=LOW: Indicates that D0 to D7 are control data.
RES
I
I
I
Initialized by setting RES to LOW.
Reset operation is performed at the RES signal level.
1
2
1
CS1
CS2
Chip Select signal. When CS1=LOW and CS2=HIGH, this signal
becomes active and the input/output of data/commands is enabled.
RD
(E)
• When the 80 series MPU is connected, active LOW is set.
Pin that connects the RD signal of the 80 series MPU. When this
signal is LOW, the S1D15705 series data bus is set in the output state.
• When the 68 series MPU is connected, active HIGH is set.
68 series MPU enable clock input pin
WR
(R/W)
I
• When the 80 series MPU is connected, active LOW is set.
Pin that connects the WR signal of the 80 series MPU. The data
bus signal is latched on the leading edge of the WR signal.
• When the 68 series MPU is connected,
1
Read/write control signal input pin
R/W=HIGH: Read operation
R/W=LOW: Write operation
FRS
C86
O
I
Output pin for static drive
Used together with the SYNC pin
1
1
MPU interface switching pin
C86=HIGH: 68 series MPU interface
C86=LOW: 80 series MPU interface
P/S
I
Switching pin for parallel data entry/serial data entry
P/S=HIGH: Parallel data entry
1
P/S=LOW: Serial data entry
According to the P/S state, the following table is given.
P/S
Data/
command
Data
Read/write Serial clock
HIGH
LOW
A0
A0
D0 to D7
SI (D7)
RD, WR
Write-only
SCL (D6)
When P/S=LOW, D0 to D5 are set to high impedance. D0 to D5 can
be HIGH, LOW, or “OPEN”.
RD(E) and WR (R/W) are fixed to HIGH or LOW.
For the serial data entry, RAM display data cannot be read.
Rev. 3.2
EPSON
15
S1D15705 Series Technical Manual
Number of
Pin name
I/O
Description
pins
CLS
I
Pin that selects the validity/invalidity of the built-in oscillator circuit
for display clocks.
CLS=HIGH: Built-in oscillator circuit valid
1
CLS=LOW: Built-in oscillator circuit invalid (external input)
When CLS=LOW, display clocks are input from the CL pin.
When the S1D15705 series is used for the master/slave
configuration, each of the CLS pins is set to the same level together.
Display clock
Master
Slave
Built-in oscillator circuit used
External input
HIGH
LOW
HIGH
LOW
M/S
I
Pin that selects the master/slave operation for the S1D15705 series.
The liquid crystal display system is synchronized by outputting the
timing signal required for the liquid crystal display for the master
operation and inputting the timing signal required for the liquid
crystal display for the slave operation.
1
M/S=HIGH : Master operation
M/S=LOW : Slave operation
According to the M/S and CLS states, the following table is given.
M/S CLS Oscillator Power supply CL
FR SYNC FRS
DOF
circuit
circuit
HIGH HIGH Valid
LOW Invalid
Valid
Valid
Output Output Output Output Output
Input Output Output Output Output
LOW HIGH Invalid
LOW Invalid
Invalid
Invalid
Input Input Input Output Input
Input Input Input Output Input
CL
I/O
Display clock I/O pin
According to the M/S and CLS states, the following table is given.
1
M/S CLS
CL
HIGH HIGH Output
LOW Input
LOW HIGH Input
LOW Input
When the S1D15705 series is used for the master/slave
configuration, each CL pin is connected.
FR
I/O
I/O
I/O
I
Liquid crystal alternating current signal I/O pin
M/S=HIGH : Output
1
2
1
1
M/S=LOW : Input
When the S1D15705 series is used for the master/slave
configuration, each FR pin is connected.
SYNC
DOF
IRS
Liquid crystal synchronizing current signal I/O pin
M/S=HIGH : Output
M/S=LOW : Input
When the S1D15705 series is used for the master/slave
configuration, each SYNC pin is connected.
Liquid crystal display blanking control pin
M/S=HIGH : Output
M/S=LOW : Input
When the S1D15705 series is used for the master/slave
configuration, each DOF pin is connected.
V5 voltage adjusting resistor selection pin
IRS=HIGH: Built-in resistor used
IRS=LOW: Built-in resistor not used. The V5 voltage is adjusted
by the VR pin and stand-alone split resistor.
Valid only at master operation. The pin is fixed to HIGH or LOW at
slave operation.
HPM
I
Power supply control pin of the power supply circuit for liquid
crystal drive
HPM=HIGH : Normal mode
1
HPM=LOW : High power supply mode
Valid only at master operation. The pin is fixed to HIGH or LOW at
slave operation.
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S1D15705 Series Technical Manual
Liquid Crystal Drive Pin
Number of
pins
Pin name
I/O
Description
SEG0
to
SEGn
O
Output pins for the LCD segment drive.
168 or 200
For the pin assignment by model, refer to the table below.
Product name
SEG
Number of pins
SEG0 to SEG167
SEG0 to SEG199
168
200
S1D15705*****
S1D15707*****/S1D15708*****
Contents of the display RAM and FR signal are combined to select
a desired level among VDD, V2, V3 and V5.
Output voltage
RAM data
FR
Display
Display reversal
normal operation
HIGH
HIGH
HIGH
LOW
HIGH
LOW
—
VDD
V5
V2
V3
LOW
V2
VDD
V5
LOW
V3
Power save
VDD
COM0
to
COMn
Output pins for the LCD common drive.
For the pin assignment by model, refer to the table below.
64 or 32
or 16
Product name
SEG
Number of pins
COM0 to COM63
COM0 to COM31
COM0 to COM15
64
32
16
S1D15705*****
S1D15707*****
S1D15708*****
Scan data and FR signal are combined to select a desired level
among VDD, V1, V4 and V5.
Scanning data
HIGH
FR
HIGH
LOW
HIGH
LOW
—
Output voltage
V5
VDD
V1
HIGH
LOW
LOW
V4
Power save
VDD
COMS
O
Indicator dedicated COM output pin. Set to OPEN when not used.
When COMS is used for the master/slave configuration, the same
signal is output to both the master and slave.
2
Test Pin
Number of
pins
Pin name
I/O
Description
TEST1
to 6
I/O
IC chip test pin. Fix the pin to HIGH.
6
When using the temperature sensor with the S1D15705*10**, refer
to “Section 17. Temperature Sensor Circuit”.
TEST7
to 9
I/O
IC chip test pin. Take into consideration so that the capacity of
lines cannot be exhausted by setting the pin to OPEN.
3
Rev. 3.2
EPSON
17
S1D15705 Series Technical Manual
6. FUNCTION DESCRIPTION
MPU Interface
Selection of interface type
The S1D15705 series transfers data through 8-bit bidirectional data buses (D7 to D0) or serial data input (SI). By setting
the polarity of the P/S pin to either HIGH or LOW, the 8-bit parallel data entry or serial data entry can be selected as
listed in Table 1.
Table 1
P/S
CS1
CS2
CS2
CS2
A0
A0
A0
RD
RD
—
WR
WR
—
C86
C86
—
D7
D7
SI
D6
D6
D5 to D0
D5 to D0
(HZ)
HIGH: Parallel data entry CS1
LOW: Serial data entry CS1
SCL
Fix — to HIGH or LOW. HZ indicates the high impedance state.
Parallel interface
When the parallel interface is selected (P/S=HIGH), the S1D15705 series can directly be connected to the MPU bus
of either the 80 or 68 series MPU by setting the C86 pin to HIGH or LOW as listed in Table 2.
Table 2
C86
CS1
CS1
CS1
CS2
CS2
CS2
A0
A0
A0
RD
E
WR
R/W
WR
D7 to D0
D7 to D0
D7 to D0
H: 68 series MPU bus
L: 80 series MPU bus
RD
In addition, the data bus signal can be identified according to the combinations of the A0, RD (E), WR (R/W) signals
as listed in Table 3.
Table 3
Common
A0
68 series
R/W
80 series
RD
WR
Function
1
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
Display data read
Display data write
Status read
Control data write (command)
18
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Rev. 3.2
S1D15705 Series Technical Manual
converted into 8-bit parallel data on the leading edge of
the 8th serial clock, then processed.
Serial interface
When the serial interface is selected (P/S=LOW), the
serial data entry (SI) and serial clock input(SCL) can be
accepted with the chip in the non-active state (CS1=LOW
or CS2=HIGH. The serial interface consists of an 8-bit
shift register and a 3-bit counter. Serial data is fetched
from the serial data entry pin in the order of D7, D6, ....,
and D0 on the leading edge of the serial clock and
Whether to identify that the serial data entry is display
data or command is judged by the A0 input, and
A0=HIGH indicates display data and A0=LOW indicates
the command. After the chip is set to the non-active
state, the A0 input is read and identified at the timing on
the 8 × n-th leading edge of the serial clock. Fig. 1 shows
the signal chart of the serial interface.
CS1
CS2
SI
D7
1
D6
2
D5
3
D4
4
D3
5
D2
6
D1
7
D0 D7
D6
10
D5
D4
D3
13
D2
14
SCL
8
9
11
12
A0
Fig. 1
• When the chip is in the non-active state, both the shift register and counter are reset to the initial state.
• Cannot be read for the serial interface.
• For the SCL signal, pay careful attention to the terminating reflection of lines and external noise. The operation
confirmation using actual equipment is recommended.
on the display data RAM up to the next data write cycle.
Further, when the MPU reads the contents of display
data RAM, the read data at the first data read cycle
(dummy) is held in the bus holder and read on the system
bus from the bus holder up to the next data read cycle.
The read sequence of the display data RAM is restricted.
When the address is set, note that the specified address
data is not output to the subsequent read instruction and
output at the second data read. Therefore single dummy
read is required after the address set and write cycle.
Fig. 2 shows this relationship.
Chip select
The S1D15705 series has two chip select pins CS1 and
CS2 and enables the MPU interface or serial interface
only when CS1=LOW and CS2=HIGH.
When Chip Select is in the non-active state, D0 to D7 are
in the high impedance state and the A0, RD, and WR
inputs become invalid. When the serial interface is
selected, the shift register and counter are reset.
Display data RAM and internal register
access
Busy flag
Since the S1D15705 series access viewed from the
MUP side satisfies the cycle time and does not require
the wait time, high-speed data transfer is enabled.
The S1D15705 series performs a kind of inter-LSI
pipeline processing through the bus holder attached to
the internal data bus when it performs the data transfer
with the MPU.
When the busy flag is “1”, it indicates that the S1D15705
series is performing an internal operation, and only the
status read instruction can be accepted. The busy flag is
output to the D7 pin using the status read command. If
the cycle time (tCYC) is ensured, the MPU throughput
can be improved greatly since this flag needs not be
checked before each command.
For example, when data is written on the display data
RAM, the data is first held in the bus holder and written
Rev. 3.2
EPSON
19
S1D15705 Series Technical Manual
• Write
WR
DATA
N
N+1
N+2
N+3
Latch
N
N+1
N+2
N+3
BUS Holder
Write Signal
• Read
WR
RD
DATA
N
N
n
n+1
Address Preset
Read Signal
Column Address
Bus Holder
Preset N
N
Increment N+1
n
N+2
n+1
n+2
Address Set
#n
Dummy
Read
Data Read
#n
Data Read
#n+1
Fig. 2
20
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Rev. 3.2
S1D15705 Series Technical Manual
display configuration with the high degree of freedom
can easily be obtained when the S1D15705 series is
used for the multiple chip configuration.
Besides, the read/write operation to the display data
RAM is performed through the I/O buffer from the
MPU side independently of the liquid crystal drive
signal read. Therefore even when the display data RAM
is asynchronously accessed during liquid crystal display,
the access will not have any adverse effect on the
display such as flickering.
Display Data RAM
Display data RAM
This display data RAM stores display dot data and
consists of 65 (8 pages × one 8 bit + 1) × 200 bits.
Desired bits can be accessed by specifying page and
column addresses.
Since the MPU display data D7 to D0 correspond to the
common direction of the liquid crystal display, the
restrictions at display data transfer is reduced and the
D0 0 1 1 1
D1 1 0 0 0
D2 0 0 0 0
D3 0 1 1 1
D4 1 0 0 0
—
0
0
0
0
0
COM0
COM1
COM2
COM3
COM4
—
Display data RAM
Liquid crystal display
Fig. 3
by 1 whenever the display data read/write command is
input, the MPU can successively access the display
data.
Page address circuit
As shown in Fig. 4, the page address of the display data
RAM is specified using the page address set command.
To access the data using a new page, the page address is
respecified.
The page address 8 (D3,D2,D1,D0=1,0,0,0) is an
indicator dedicated RAM area and only the display data
D0 is valid.
Besides, the column address stops the increment at the
column C7H. Since the column and page addresses are
independent each other, for example, the page and
column addresses need to be respecified respectively to
move from the column C7H of page 0 and column 00H.
Further, as shown in Fig. 4, the correspondence
relationship between the column address of the display
data RAM and the segment address can be reversed
using the ADC command (segment driver direction
select command). Therefore the IC assignment
restrictions at LCD module assembly are reduced.
Column address circuit
As shown in Fig. 4, an address on the column side of the
display data RAM is specified using the column address
set command. Since the specified address is incremented
Table 4
S1D15705*****
S1D15707***** / S1D15708*****
SEG output
ADC “0”
(D0) “1”
SEG0
SEG167
SEG0
SEG199
0 (H)→ Column Address→ A7 (H)
C7 (H)←Column Address← 20 (H)
0 (H)→ Column Address→ C7 (H)
C7 (H)←Column Address ← 0 (H)
S1D15708*****outputs COM15).
For the
Line address circuit
S1D15705*****, the display area of 65 lines is secured
When displaying contents of the display data RAM, the
line address circuit is used for specifying the
corresponding addresses. See Figure 4-1 and 4-2.
Using the display start line address set command, the
top line is normally selected (when the common output
state is normal, COM0 is output. And, when reversed,
starting from the specified display start line address in
the address incrementing direction. And, 33 lines are
provided for the S1D15707*****, 17 lines are provided
for the S1D15708*****.
Dynamically changing the line address using the display
start line address set command enables screen scrolling
the
outputs COM63,
outputs COM31 and
S1D15705 *****
and page change.
S1D15707 *****
Rev. 3.2
EPSON
21
S1D15705 Series Technical Manual
Common
output state:
Normal rotation
Page Address
Data
Line
COM
Address
Output
S1D15705*****: When setting the display start line to one channel
D3
0
D2
D1
D0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
COM0
COM1
COM2
COM3
0
0
0
Page 0
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COMS
0
0
0
0
0
1
1
0
Page 1
Page 2
0
0
0
1
1
0
1
0
Page 3
Page 4
Start
0
0
1
1
0
1
1
0
Page 5
Page 6
0
1
1
0
1
0
1
0
Page 7
Page 8
The 65th line
is accessed
independently
of the display
start line address.
Fig. 4-1
22
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Rev. 3.2
S1D15705 Series Technical Manual
Common
output state:
Normal rotation
Page Address
Line
COM
S1D15707*****, S1D15708*****:
Data
Address
Output
D3
0
D2
D1
D0
0
When setting the display start line to one channel
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
COM0
COM1
COM2
COM3
0
0
Page 0
Page 1
Page 2
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COMS
0
0
0
0
0
1
1
0
0
0
0
1
1
0
1
0
Page 3
Page 4
Start Start
0
0
1
1
0
1
1
0
Page 5
Page 6
0
1
1
0
1
0
1
0
Page 7
Page 8
The 33rd of
S1D15707
*****
and the 17th
S1D15708
*****
are accessed
independ-ently of the
display start line
address.
Fig. 4-2
Rev. 3.2
EPSON
23
S1D15705 Series Technical Manual
Display data latch circuit
even when the display data RAM is asynchronously
accessed during liquid crystal display, the access will
not have any adverse effect on the display such as
flickering.
The display data latch circuit is a latch that temporarily
stores the display data output from the display data
RAM to the liquid crystal drive circuit.
The circuit also generates the internal common timing,
liquid crystal alternating current signal (FR), and
synchronous signal (SYNC) from the display clocks.
As shown in Fig. 5 and 6, the FR normally generates the
drive waveforms in the 2-frame alternating current
drive system to the liquid crystal drive circuit. It can
generate n-line reversal alternating current drive
waveforms by setting data (n-1) to the n-line reversal
drive register. If a display quality problem such as
crosstalk occurs, it can be improved by using the n-line
reversal alternating current drive waveforms. Determine
the number of lines (n) to which alternating current is
applied by actually displaying the liquid crystal.
SNYC is a signal that synchronizes the line counter and
common timing generator circuit to the SYNC signal
output side IC. Therefore the SYNC signal becomes a
waveform at a duty ratio of 50% that synchronizes to the
frame synchronization.
Since the Display Normal Rotation/Reversal, Display
ON/OFF, and Display All Lighting ON/OFF commands
control the data in this latch, the data within the display
data RAM is not changed.
Oscillator Circuit
This oscillator circuit is a CR type oscillator and generates
display clocks. The oscillator circuit is valid only when
M/S=HIGH and CLS=HIGH and starts oscillation after
the Built-in Oscillator Circuit ON command is entered.
When CLS=LOW, the oscillation is stopped and the
display clocks are entered from the CL pin.
Display Timing Generator Circuit
This display timing generator circuit generates timing
signals from the display clocks to the line address circuit
and the display latch circuit. It latches the display data
to the display data latch circuit and outputs it to the
segment drive output pin by synchronizing to the display
clocks. The read operation of display data to the liquid
crystal drive circuit is completely independent of the
access to the display data RAM from the MPU. Therefore
When the S1D15705 series is used for the multiple chip
configuration, the slave side needs to supply the display
timing signals (FR, SYNC, CL, and DOF) from the
master side.
Table 5 shows the state of FR, SYNC, CL, or DOF.
Table 5
Operation mode
FR
SYNC
Output
Output
Input
CL
DOF
Output
Output
Input
Master (M/S=HIGH) Built-in oscillator circuit valid (CLS=HIGH) Output
Built-in oscillator circuit invalid (CLS=LOW) Output
Output
Input
Input
Input
Slave (M/S=LOW) Built-in oscillator circuit valid (CLS=HIGH) Input
Built-in oscillator circuit invalid (CLS=LOW) Input
Input
Input
2-frame alternating current drive waveforms
64 65
1
2
3
4
5
6
60 61 62 63 64 65
1
2
3
4
5
6
CL
SYNC
FR
VDD
V1
COM0
V
V
4
5
V
V
DD
1
COM1
V
V
4
5
RAM
DATA
V
V
V
V
DD
2
SEGn
3
5
Fig. 5
24
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Rev. 3.2
S1D15705 Series Technical Manual
n-line reversal alternating current drive waveforms (Example of n=5: when the line reversal
register is set to 4)
64 65
1
2
3
4
5
6
60 61 62 63 64 65
1
2
3
4
5
6
CL
SYNC
FR
V
V
DD
1
COM0
COM1
V
V
4
5
V
V
DD
1
V
V
4
5
RAM
DATA
V
V
V
V
DD
2
SEGn
3
5
Fig. 6
Common Output State Selection Circuit
The S1D15705 series can set the scanning direction of the COM output using the common output state selection
command (see Fig. 6). Therefore the IC assignment restrictions at LCD module assembly are reduced.
Table 6
State
COM scanning direction
S1D15705*****
S1D15707*****
S1D15708*****
Normal rotation
Reversal
COM 0
→
COM 63
COM 0
→
COM 31
COM 0
→
COM 15
COM 63
→
COM 0
COM 31
→
COM 0
COM 15
→
COM 0
Liquid Crystal Drive Circuit
These are a 233-channel (S1D15705
that generate four voltage levels for liquid crystal drive. It outputs the liquid crystal drive voltage that corresponds to
***** and S1D15707*****), a 217-channel (S1D15708*****) multiplexers
the combinations of the display data, COM scanning signal, and FR signal.
Fig. 7 shows examples of the SEG and COM output waveforms.
Rev. 3.2
EPSON
25
S1D15705 Series Technical Manual
COM0
V
V
DD
SS
FR
COM1
COM2
COM3
COM4
V
V
V
DD
1
2
COM5
COM6
COM7
COM0
COM1
COM2
V3
V4
V5
V
V
V
DD
1
2
COM8
V3
V4
V5
COM9
COM10
COM11
COM12
COM13
COM14
COM15
V
V
V
DD
1
2
V3
V4
V5
V
V
V
DD
1
2
SEG0
SEG1
SEG2
V
V
V
3
4
5
V
V
V
DD
1
2
V3
V4
V5
V
V
V
DD
1
2
V3
V4
V5
V5
V4
V3
V
V
V
2
1
COM0–SEG0
DD
–V
1
2
–V
–V3
–V4
–V5
V5
V4
V3
V
V
V
–V
–V
–V
–V
–V
2
1
COM0–SEG1
DD
1
2
3
4
5
Fig. 7
26
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Rev. 3.2
S1D15705 Series Technical Manual
circuit, voltage adjusting circuit, and voltage follower
circuit using the power supply control set command,
respectively.
Therefore, it can also use the partial functions of the
external power supply and built-in power supply
together. Table 7 lists the functions that control 3-bit
data using the power control set command and Table 8
lists the reference combinations.
Power Supply Circuit
This power supply circuit is a low power supply
consumption one that generates the voltage required for
the liquid crystal drive and consists of a boosting circuit,
voltage adjusting circuit, and voltage follower circuit. It
is valid only at master operation.
The power supply circuit ON/OFF controls the boosting
Table 7 Description of controlling bits using the power control set command
State
Item
“1”
“0”
D2 Boosting circuit control bit
ON
OFF
D1 Voltage adjusting circuit (V adjusting circuit) control bit
D0 Voltage follower circuit (V/F circuit) control bit
ON
ON
OFF
OFF
Table 8 Reference combinations
Boosting V adjusting
V/F
External
Boosting
Status of use
D2
D1
D0
circuit
circuit
circuit voltage input system pin
1
2
Built-in power
supply used
1
1
1
O
O
O
VSS2
Used
V adjusting circuit
and V/F circuit only
0
1
1
X
O
O
VOUT, VSS2
OPEN
3
4
V/F circuit only
0
0
0
0
1
0
X
X
X
X
O
X
V5, VSS2
V1 to V5
OPEN
OPEN
External power
supply only
• The boosting system pin indicates the CAP1+, CAP1–, CAP2+, CAP2–, or CAP3– pin.
• Although the combinations other than those listed in the above table are also possible, they cannot be recommended
because they are not actual use methods.
triple-boosted to the negative side and output to the
VOUT pin by connecting the capacitor C1 between
CAP1+↔ and CAP1–, between CAP2+↔ and CAP2–,
and between VSS2↔ and VOUT and strapping both
CAP3– and VOUT pins.
For the double boosting, the VDD ↔ VSS2 potential is
doubly boosted to the negative side and output to the
VOUT pin by connecting the capacitor C1 between
CAP1+↔ and CAP1–, and between VSS2↔, setting
CAP2+ to OPEN, and VOUT and strapping CAP2–,
CAP3–, and VOUT pins.
Boosting circuit
The boosting circuit incorporated in the S1D15705
series enables the quadruple boosting, triple boosting,
and double boosting of the VDD – VSS2 potential.
For the quadruple boosting, the VDD ↔ VSS2 potential
is quadruple-boosted to the negative side and output to
the VOUT pin by connecting the capacitor C1 between
CAP1+↔and CAP1–, between CAP2+↔ and CAP2–,
between CAP1+↔ and CAP3–, and between VSS2↔
and VOUT.
For the triple boosting, the VDD ↔ VSS2 potential is
Fig. 8 shows the relationships of boosting potential.
Rev. 3.2
EPSON
27
S1D15705 Series Technical Manual
V
V
SS2
V
V
SS2
V
V
SS2
+
+
+
+
C1
C1
C1
C1
OUT
OUT
OUT
CAP3–
CAP3–
CAP3–
C1
C1
+
+
CAP1+
CAP1+
CAP1+
+
+
C1
C1
CAP1–
CAP2–
CAP1–
CAP2–
CAP1–
CAP2–
C1
CAP2+
CAP2+
OPEN CAP2+
Quadruple boosting circuit
Triple boosting circuit
Double boosting circuit
V
DD = 0V
V
DD = 0V
SS2 = –5V
V
DD = 0V
V
SS2 = –3V
V
SS2 = –3V
V
V
OUT = 3 x VSS2 = –9V
VOUT = 2 x VSS2 = –10V
V
OUT = 4 x VSS2 = –12V
Quadruple boosting
potential relationship
Triple boosting
potential relationship
Double boosting
potential relationship
Fig. 8
• Set the VSS2” voltage range so that the voltage of the VOUT pin cannot exceed the absolute maximum ratings.
(A) When using the V5 voltage adjusting built-in resistor
The liquid crystal power supply voltage V5 can be
controlled only using the command without an
external resistor and the light and shade of liquid
crystal display be adjusted by using the V5 voltage
adjusting built-in resistor and the electronic control
function.
Voltage adjusting circuit
The boosting voltage generated in VOUT outputs the
liquid crystal drive voltage V5 through the voltage
adjusting circuit.
Since the S1D15705 series incorporates a high-accuracy
constant power supply, 64-step electronic control
function, and V5 voltage adjusting resistor, a high-
accuracy voltage adjusting circuit can eliminate and
save parts.
The V5 voltage can be obtained according to
Expression A-1 within the range of |V5|<|VOUT|.
Rb
V5 = 1+
VEV
Ra
(Expression A-1)
Rb
Ra
α
= 1+
1–
VREG
162
ꢀ
α
VEV = 1−
VREG
(
)
[
]
162
28
EPSON
Rev. 3.2
S1D15705 Series Technical Manual
V
DD
V
EV (Constant voltage source
+ electronic control)
Built-in Ra
Built-in Rb
+
V
5
–
Fig. 9
VREG is a constant voltage source within an IC, and the
Table 10
value at Ta=25°C is constant as listed in Table 9.
D5
0
D4
0
D3
0
D2
0
D1
D0
0
α
0
63
62
61
·
·
·
Table 9
Device
Temperature Unit VREG Unit
gradient
0
0
0
0
0
1
1
0
0
0
0
0
Internal
power supply
–0.05
[%/°C] –2.1
[V]
·
·
·
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
2
1
0
α indicates an electronic control command value. Setting
data in a 6-bit electronic control register enters one state
among 64 states. Table 10 lists the values of α based on
the setup of the electronic control register.
Rb/Ra indicates the V5 voltage adjusting built-in
resistance ratio and can be adjusted into eight steps
using the V5 voltage adjusting built-in resistance ratio
set command. The reference values of the (1+Rb/Ra)
ratio are obtained as listed in Table 11 by setting 3-bit
data in the V5 voltage adjusting built-in resistance ratio
register.
Table 11 (Reference values)
S1D15705*****
S1D15707*****/ S1D15708*****
Register
Device per temperature Device per temperature
gradient [Unit: %/°C]
gradient [Unit: %/°C]
D2
0
D1
0
D0
0
–0.05
4.5
5.0
5.5
6.0
6.5
7.0
7.6
8.1
–0.05
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
It is necessary to take a manufacturing deviation of upto ±7% of the built-in resistance ratio into consideration. When
this is not permissible, supplement external Ra and Rb to ajdust the V5 voltage.
Figs. 10 show the V5 voltage reference values per temperature gradient device based on the values of the V5 voltage
adjusting built-in resistance ratio register and electronic control register at Ta=25°C.
Rev. 3.2
EPSON
29
S1D15705 Series Technical Manual
–18
–17
–16
–15
–14
–13
–12
–11
–10
–9
S1D15705
*****
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
–8
–7
–6
–5
V
5
voltage adjusting
built-in resistance
ratio registers
–4
(D2, D1, and D0)
–3
–2
–1
0
Electric Volume
Resister
Temperature gradient = –0.05%/°C device
Fig. 10-1 S1D15705*****
V5 voltage based on the values of V5 voltage adjusting built-in resistance ratio register and electronic
control register
–18
–17
S1D15707
, S1D15708
*****
*****
–16
–15
–14
–13
–12
–11
–10
–9
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
–8
–7
–6
–5
V
5
voltage adjusting
built-in resistance
ratio registers
–4
(D2, D1, and D0)
–3
–2
–1
0
Electric Volume
Resister
Temperature gradient = –0.05%/°C device
Fig. 10-2 S1D15707*****, S1D15708*****
V5 voltage based on the values of V5 voltage adjusting built-in resistance ratio register and electronic
control register
*S1D15708 should be used in system operating voltage ranges. (V5–VDD = –10V or V5–VDD=less than –
10V)
30
EPSON
Rev. 3.2
S1D15705 Series Technical Manual
<Setting example: S1D15705***** When setting V5 = –9 V at Ta=25°C>
From Fig. 8 and Expression A-1.
Table 12
Register
Description
D5
–
D4
–
D3
–
D2
0
D1
1
D0
0
V5 voltage adjusting
electronic control
0
1
1
0
0
1
In this case, Table 13 lists the V5 voltage variable range and pitch width using the electronic control function.
Table 13
V5
Min.
Typ.
–9.3
67
Max.
Unit
[V]
Variable range
Pitch width
–11.6
to
to
–7.1
[mV]
(B) When using the external resistor (not using the V5
The V5 voltage can be obtained from Expression B-
1 by setting the external resistors Ra’ and Rb’
within the range of |V5| < |VOUT|.
1
voltage adjusting built-in resistor)
The liquid crystal power supply voltage V5 can
also be set by adding the resistors (Ra’ and Rb’)
between VDD and VR and between VR and V5
without the V5 voltage adjusting built-in resistor
(IRS pin=LOW). Also in this case, the liquid crystal
power supply voltage V5 can be controlled using
the command and the light and shade of liquid
crystal display can be adjusted by using the
electronic control function.
Rb'
V5 = 1+
VEV
Ra'
(Expression B-1)
Rb'
Ra'
α
= 1+
1–
VREG
162
ꢀ
VEV = 1−
α
VREG
(
)
[
]
162
VDD
VEV (Constant voltage source
+ electronic control)
Stand-alone Ra'
+
V5
–
VR
Stand-alone Rb
Fig. 11
<Setting example: S1D15705***** When setting V5=–7 V at Ta=25°C>
Set the value of the electronic control register as the
intermediate value (D5, D4, D3, D2, D1, D0) =
(1,0,0,0,0,0). From the foregoing we can establish the
expression:
Also, suppose the current applied to Ra’ and Rb’ is 5µA.
(Expression B-2)
It follows that
Ra' +Rb' = 1.4MΩ
Therefore from Expressions B-2 and B-3, we have
α
= 31
Rb'
= 3.12
Ra'
VREG = –2.1V
Ra' = 340kΩ
From Expression B-1, it follows that
Rb' = 1060kΩ
Rb'
Ra'
Rb'
Ra'
α
V = 1+
1−
VREG
5
(Expression B-2)
In this case, Table 14 lists the V5 voltage variable range
and pitch width using the electronic control function.
162
31
−7V = 1+
1−
−2.1
)
(
162
Rev. 3.2
EPSON
31
S1D15705 Series Technical Manual
Table 14
V5
Min.
Typ.
Max.
Unit
[V]
Variable range
Pitch width
–8.6
to
–7.0
to
–5.3
52
[mV]
(C) When using the external resistor (not using the V5
The V5 voltage can be obtained from the following
expression C-1 by setting the external resistors R1,
R2 (variable resistors), and R3 within the range of
|V5| < |VOUT| and finely adjusting R2 (∆R2).
R3 + R2 − ∆R2
2
voltage adjusting built-in resistor)
In the use of the above-mentioned external resistor,
the liquid crystal power supply voltage V5 can also
be set by adding the resistors to finely adjust Ra’
and Rb’. Also in this case, the liquid crystal power
supply voltage V5 can be controlled using the
command and the light and shade of liquid crystal
display can be adjusted by using the electronic
control function.
V5 = 1+
VEV
R1 + ∆R2
R3 + R2 − ∆R2
R1 + ∆R2
α
= 1+
1–
VREG
162
ꢀ
VEV = 1−
α
VREG
(
)
[
]
(Expression C-1)
162
V
DD
VEV (Constant voltage source
+ electronic control)
Ra'
Stand-alone R1
+
V5
∆R2
Stand-alone R2
–
VR
Rb'
Stand-alone R3
Fig. 12
<Setting example: S1D15705***** When setting V5=–5 to –9 V at Ta=25°C>
Set the value of the electronic control register as the
intermediate value (D5, D4, D3, D2, D1, D0) =
(1,0,0,0,0,0). From the foregoing we can establish the
expression:
When ∆R2=R2, to obtain V5=-5V, it follows that
R3
31
−5V = 1 +
1 −
−2.1
(
)
R + R2
162
1
(Expression C-3)
α
= 31
VREG = −2.1V
Also, suppose the current applied between VDD and V5
When ∆R2=0Ω, to obtain V5=–9 V from Expression C-
1, it follows that
is 5µA.
R + R2 + R3 = 1.4MΩ
1
(Expression C-4)
It follows that
Therefore from Expressions C-2, C-3, and C-4, we have
R3 + R2
31
−9V = 1 +
1 −
−2.1
(
)
R
162
1
(Expression C-2)
R
= 264kΩ
1
R2 = 211kΩ
R3 = 925kΩ
32
EPSON
Rev. 3.2
S1D15705 Series Technical Manual
In this case, Table 6-15 lists the V5 voltage variable range and pitch width using the electronic control function.
Table 15
V5
Min.
Typ.
–7.0
53
Max.
Unit
[V]
Variable range
Pitch width
–8.7
to
to
–5.3
[mV]
• When using the V5 voltage adjusting built-in resistor or electronic control function, the state where at least the voltage
adjusting circuit and voltage follower circuit are operated together needs to be set using the power control set
command. Also when the boosting circuit is OFF, the voltage needs to be applied from VOUT.
• The VR pin is valid only when the V5 voltage adjusting built-in resistor (IRS pin=LOW). Set the VR pin to OPEN
when using the V5 voltage adjusting built-in resistor (IRS pin=HIGH).
• Since the VR pin has high input impedance, noise must be taken into consideration such as for short and shielded lines.
may be deteriorated in large load liquid crystal or
panels. In this case, the display quality can be improved
by setting HPM pin=LOW (high power mode). Whether
to use the power supply circuit in this mode should need
the display confirmation by actual equipment.
Besides, if the improvement is insufficient even for the
high power mode setting, the crystal liquid drive power
needs to be supplied externally.
Liquid crystal voltage generator circuit
The V5 voltage is resistor-split within an IC and generates
the V1, V2, V3, and V4 potentials required for the liquid
crystal drive.
Further, the V1, V2, V3, and V4 potentials are impedance-
converted by the voltage follower and supplied to the
liquid crystal drive circuit.
Using the bias set command allows you to select a
desired bias ratio from 1/9 or 1/7 for the
Command sequence when the built-in power
supply is turned off
S1D15705***** and 1/6 or 1/5 for the S1D15707*****
and S1D15708***** .
To turn off the built-in power supply, set it in the power
save state and then turn off the power supply according
to the command sequence shown in Fig. 13 (procedure).
High power mode
The power supply circuit incorporated in the S1D15705
series has the ultra-low power consumption (normal
mode: HPM=HIGH). Therefore the display quality
Procedure
Description
Command address
D7 D6 D5 D4 D3 D2 D1 D0
(Command, state)
Step1
Step2
Power save
1
0
1
0
1
0
0
0
1
Power save command
Turning off the built
-in power supply
(Both stand-by and
sleep can be useal)
Fig. 13
Rev. 3.2
EPSON
33
S1D15705 Series Technical Manual
Reference circuit examples
1 Built-in power supply used
(1) When using the V
5
voltage adjusting built-in resistor
(2) When not using the V
5 voltage adjusting built-in resistor
(Example of VSS2=VSS, quadruple boosting)
(Example of VSS2=VSS, quadruple boosting)
V
V
DD
SS
VDD
IRS M/S
IRS M/S
V
V
SS2
V
V
SS2
C
1
C
1
OUT
OUT
V
V
SS
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
C
C
1
1
C
C
1
1
C1
C1
R3
R2
R1
V
V
5
V
V
5
R
R
V
DD
DD
V
V
V
V
V
V
DD
1
V
V
V
V
V
V
DD
1
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
2
2
3
3
4
4
5
5
2 Only the voltage adjusting circuit and V/F circuit used
(1) When using the V
5
voltage adjusting built-in resistor
(2) When not using the V5 voltage adjusting built-in resistor
V
DD
VDD
IRS M/S
IRS M/S
V
SS
V
V
SS
OUT
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
V
V
V
V
SS
V
V
SS
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
External
Power
Supply
External
Power
Supply
OUT
R3
R2
R1
5
V
V
5
R
R
V
DD
DD
V
V
V
V
V
V
DD
1
V
V
V
V
V
V
DD
1
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
2
2
3
3
4
4
5
5
34
EPSON
Rev. 3.2
S1D15705 Series Technical Manual
3 Only the V/F circuit used
4 Only the external power supply used
Depending on all external power supplies
V
DD
VSS
VDD
IRS M/S
IRS M/S
V
V
SS
OUT
V
V
SS
OUT
V
SS
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
External
Power
Supply
CAP3–
CAP1+
CAP1–
CAP2+
CAP2–
V
5
V
V
5
VR
R
V
DD
VDD
V
V
V
V
V
V
DD
V
V
V
V
V
V
DD
1
C2
C2
C2
C2
C2
1
2
2
External
Power
Supply
3
3
4
4
5
5
Common reference setting example
At V5=–8 to –12 V variable
Item Setting value Unit
C1
C2
1.0 to 4.7
0.01 to 1.0
µF
µF
Fig. 14
*1 Since the VR pin has high input impedance, it uses short and shielded wires.
*2 C1 and C2 are determined according to the size of the LCD panel. Set a value so that the liquid crystal drive voltage
can be stable.
[Setting example] • Turn on the V adjusting circuit and the V/F circuit and apply external voltage.
• Display LCD heavy load patterns like lateral stripes and determine C2 so that the liquid crystal
drive voltages (V1 to V5) can be stable.
• Then turn on all built-in power supplies and determine C1.
*3 Capacity is connected in order to stabilize voltage between VDD and VSS power supplies.
Rev. 3.2
EPSON
35
S1D15705 Series Technical Manual
*4 When the built-in V/F circuit is used to drive an LCD panel with heavy alternating or direct current load, we
recommend that external resistance be connected in order to stabilize V/F outputs, or electric potentials, V1, V2,
V3 and V4.
Exemplary connection diagram 1 for external resistance
Exemplary connection diagram 2 for external resistance
VDD
VDD
VDD
VDD
R4
R4
V1
V2
V3
V1
V2
V3
C2
C2
C2
C2
C2
C2
R4
R4
V
4
5
V
4
5
C
2
2
C
2
2
R4
R4
V
V
C
C
Adjust resistance value R4 to the optimal level by
checking driving waveform displayed on the LCD.
Reference setting: R4 = 0.1 to 1.0 [MΩ]
Fig. 15
*5 Precautions when installing the COG
the resistance of ITO wiring is being inserted in
series with the switching transistor, thus dominating
the boosting ability.
Consequently, the boosting ability will be hindered
as a result and pay sufficient attention to the wiring
to respective boosting capacitors.
When installing the COG, it is necessary to duly consider
the fact that there exists a resistance of the ITO wiring
occurring between the driver chip and the externally
connected parts (such as capacitors and resistors). By the
influence of this resistance, non-conformity may occur
with the indications on the liquid crystal display.
Therefore, when installing the COG design the module
paying sufficient considerations to the following three
points.
1. Suppress the resistance occurring between the driver
chip pin to the externally connected parts as much as
possible.
2. Suppress the resistance connecting to the power
supply pin of the driver chip.
2. Connection of the smoothing capacitors for the
liquid crystal drive
The smoothing capacitors for the liquid crystal
driving potentials (V1. V2, V3 and V4) are
indispensable for liquid crystal drives not only for
the purpose of mere stabilization of the voltage
levels. If the ITO wiring resistance which occurs
pursuant to installation of the COG is supplemented
to these smoothing capacitors, the liquid crystal
driving potentials become unstable to cause non-
conformity with the indications of the liquid crystal
display. Therefore, when using the COG module,
we definitely recommend to connect reinforcing
resistors externally.
3. Make various COG module samples with different
ITO sheet resistance to select the module with the
sheet resistance with sufficient operation margin.
Also, as for this driver IC, pay sufficient attention to the
following points when connecting to external parts for
the characteristics of the circuit.
1. Connection to the boosting capacitors The boosting
capacitors (the capacitors connecting to respective
CAP pins and capacitor being inserted between
VOUT and VSS2) of this IC are being switched over
by use of the transistor with very low ON-resistance
of about 10Ω. However, when installing the COG,
Reference value of the resistance is 100kΩ to 1MΩ.
Meanwhile, because of the existence of these
reinforcing resistors, current consumption will
increase.
Indicated below is an exemplary connection diagram of
external resistors.
Please make sufficient evaluation work for the display
statuses with any connection tests.
36
EPSON
Rev. 3.2
S1D15705 Series Technical Manual
Exemplary connection diagram 1.
Exemplary connection diagram 2.
VDD
V
DD
VDD
V
DD
R4 R4
V1
V
V
V
1
2
3
C2
C2
C2
C2
R4
V2
C2
V3
C2
R4
V4
V
V
4
5
C2
C
2
2
R4 R4
V5
C2
C
On the other hand, when using the reset command, only
the items 11 to 20 of the above-mentioned initial setting
are executed.
Reset Circuit
When the RES input is set to the LOW level, this LSI
enters each of the initial setting states
1. Display OFF
When the power is turned on, the initialization using the
RES pin is required. After the initialization using the
RES pin, each input pin needs to be controlled normally.
Besides, when the MPU control signal has high
impedance, overcurrent may be applied to an IC. After
turning on the power, take action so that the input pin
cannot have high impedance.
The S1D15705 Series discharge electric charges of V5
and VOUT at RES pin is set to the LOW level. If external
power supplies for driving LCD are used, do not input
external power while the RES pin is set to the LOW
level to prevent short-circuiting between the external
power supplies and VDD.
2. Display Normal Rotation
3. ADC Select: Normal rotation (ADC command
D0=0)
4. Power Control Register: (D2,D1,D0)=(0,0,0)
5. Register Data Clear within Serial Interface
6. LCD Power Supply Bias Ratio:
S1D15705: 1/9 bias
S1D15707/S1D15708: 1/6 bias
7. n-Line Alternating Current Reversal Drive Reset
8. Sleeve mode cancel (standby mode is not canceled)
9. Display All Lighting OFF: (Display All Lighting
ON/OFF command D0=LOW)
10. Built-in Oscillator Circuit stopped
11. Static Indicator OFF
Static Indicator Register: (D1,D2)=(0,0)
12. Read Modify Write OFF
13. Display start line set to the first line
14. Column address set to address 0
15. Page address set to page 0
16. Common Output State Normal rotation
17. V5 Voltage Adjusting Built-in Resistance Ratio
Register: (D2,D1,D0)=(0,0,0)
18. Electronic Control Register Set Mode Reset
Electronic Control Register* (D5, D4, D3, D2,
D1, D0) = (1,0,0,0,0,0)
19. n-Line Alternating Current Reversal Register: (D3,
D2, D1, D0) = (0, 0, 0, 0)
20. Test Mode Reset
Rev. 3.2
EPSON
37
S1D15705 Series Technical Manual
7. COMMAND
The S1D15705 series identifies data bus signals according to the combinations of A0, RD(E), and WR(R/W). Since the
interpretation and execution of commands are performed only by the internal timing independently of external clocks,
the S1D15705 performs high-speed processing that does not require busy check normally.
The 80 series MPU interface starts commands by inputting low pulses to the RD pin at read and to the WR pin at write
operation. The 68 series MPU interface enters the read state when HIGH is input to the R/W pin. It enters the write state
when LOW is input to the same pin. It starts commands by inputting high pulses to the E pin (for the timing, see the
Timing Characteristics of Chapter 10). Therefore the 68 series MPU interface differs from the 80 series MPU interface
in that RD(E) is set to “1 (H)” at status read and display data read in the Command Description and Command Table.
The command description is given below by taking the 80 series MPU interface as an example.
When selecting the serial interface, enter sequential data from D7.
Command description
(1) Display ON/OFF
This command specifies display ON/OFF.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Setting
0
1
0
1
0
1
0
1
1
1
1
0
Display ON
Display OFF
For display OFF, the segment and common drivers output the VDD level.
(2) Display Start Line Set
This command specifies the display start line address of the display data RAM shown in Fig. 4. The display area is
displayed for 65 lines for the S1D15705
*****, 33 lines for the S1D15707*****and 17 lines for the S1D15708*****
from the specified line address to the line address increment direction. When this command is used to dynamically
change the line address, the vertical smooth scroll and page change are enabled. For details, see the Line address circuit
of “Function Description”.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Line address
0
1
0
0
1
0
0
0
0
0
0
0
0
0
↓
0
0
0
0
0
1
0
1
0
0
1
2
↓
1
1
1
1
1
1
1
1
1
1
0
1
62
63
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(3) Page Address Set
This command specifies the page address that corresponds to the low address when accessing the display data RAM
shown in Fig. 4 from the MPU side. The display data RAM can access desired bits when the page address and column
address are specified. Even when the page address is changed, the display state will not be changed. For details, see the
Page address circuit of “Function Description”.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Page address
0
1
0
1
0
1
1
0
0
0
0
0
0
↓
0
0
1
0
1
0
0
1
2
↓
0
1
1
0
1
0
1
0
7
8
(4) Column Address Set
This command specifies the column address of the display data RAM shown in Fig. 4. The column address is set
(basically successively) by dividing it into high-order four bits and low-order four bits. Since the column address is
automatically incremented by 1 whenever the display data RAM is accessed. The MPU can successively read/write the
display data. The column address stops the increment at C7H. In this case, the page address is not changed successively.
For details, see the Column address circuit of “Function Description”.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
High-order bit →
Low-order bit →
0
1
0
0
0
0
1
0
A7 A6 A5 A4
A3 A2 A1 A0
A7 A6 A5 A4 A3 A2 A1 A0 Column address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
2
↓
↓
↓
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
1
166
167
↓
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
1
198
199
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(5) Status Read
E R/W
A0 RD WR
D7
D6
D5
D4
D3 D2 D1 D0
0
0
1
BUSY ADC ON/OFF RESET
0
0
0
0
BUSY
ADC
When BUSY=1, indicates an internal operation being done or reset.
The command cannot be accepted until BUSY=0 is reached. However, if the cycle time is
satisfied, the command needs not be checked.
Indicates the correspondence relationship between the column address and segment driver.
0: Reversal (column address 199–n ↔ SEG n)
1: Normal rotation (column address n ↔ SEG n)
(Reverses the polarity of ADC command.)
ON/OFF ON/OFF: Specifies display ON/OFF
0: Display ON
1: Display OFF
(Reverses the polarity of display ON/OFF command.)
RESET Indicates the RES signal or that initial setting is being done using the reset command.
0: Operating state
1: Resetting
(6) Display Data Write
This command writes 8-bit data to the specified address of the display data RAM. Since the column address is
automatically incremented by 1 after the data is written, the MPU can successively write the display data.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
1
1
0
Write data
(7) Display Data Read
This command reads the 8-bit data in the specified address of the display data RAM. Since the column address is
automatically incremented by 1 after the data is written, the MPU can successively read the data consisting of multiple
words.
Besides, immediately after the column address is set, dummy read is required one time. For details, see the description
of the Display data RAM and internal register access of “Function Description”.
When using the serial interface, the display cannot be read.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
Read data
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(8) ADC Select (Segment Driver Direction Select)
This command can reverse the correspondence relationship between the column address of the display RAM data shown
in Fig. 4 and the segment driver output. Therefore the order of the segment driver output pin can be reversed using the
command. After the display data is written and read, the column address is incremented by 1 according to the column
address of Fig. 4. For details, see the Column address circuit of “Function Description”.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Setting
0
1
0
1
0
1
0
0
0
0
0
1
Clockwise (normal rotation)
Counterclockwise (reversal)
(9) Display Normal Rotation/Reversal
This command can reversal display lighting and non-lighting without overwriting the contents of display data RAM.
In this case, the contents of display data RAM are held.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Setting
0
1
0
1
0
1
0
0
1
1
0
LCD on potential (normal rotation)
RAM data HIGH
1
LCD on potential (reversal)
RAM data LOW
(10) Display All Lighting ON/OFF
This command can forcedly make all display set in the lighting state irrespective of the contents of display data RAM.
In this case, the contents of display data RAM are held.
This command has priority over the display normal rotation/reversal command.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Setting
Normal display state
Display all lighting
0
1
0
1
0
1
0
0
1
0
0
1
(11) LCD Bias Set
This command selects the bias ratio of the voltage required for liquid crystal drive. The command is valid when the V/
F circuit of the power supply circuit is operated.
E R/W
Selected state
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
S
S1D15705*****
1D15707***** / S1D15708*****
0
1
0
1
0
1
0
0
0
1
0
1
1/9 bias
1/6 bias
1/7 bias
1/5 bias
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(12) Read Modify Write
This command is used together with the end command. Once this command is entered, the column address can be
incremented by 1 only using the display data write command instead of being changed using the display read command.
This state is held until the end command is entered. When the end command is entered, the column address returns to
the address when the read modify write command is entered. This function can reduce the load of the MPU when
repeatedly changing data for a specific display area such as a blinking cursor.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
0
0
0
0
* The commands other than Display Data Read/Write can be used even in Read Modify Write mode. However, the
column address set command cannot be used.
• Sequence for cursor display
Page Address Set
Column Address Set
Read Modify Write
Dummy Read
Data Read
Data processing
Data Write
No
Is the change terminated?
Yes
End
Fig. 16
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(13) End
This command resets the Read Modify Write mode and returns the column address to the mode initial address.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
1
1
1
0
Return
Column address
N
N+1
N+2
N+3
• • •
N+m
N
End
Read Modify Write Mode Set
Fig. 17
(14) Reset
This command initializes Display Start Line, Column Address, Page Address, Common Output State, V5 Voltage
Adjusting Built-in Resistance Ratio, Electronic Control, and Static Indicator and resets the Read Modify Write mode
and Test mode. This will not have any effect on the display data RAM. For details, see the Reset of “ Function
Description”.
Reset operation is performed after the reset command is entered.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
0
0
1
0
The initialization when the power is applied is performed using the reset signal to the RES pin. The reset command
cannot be substituted for the signal.
(15) Common Output State Selection
This command can select the scanning direction of the COM output pin. For details, see the Common Output State
Selection Circuit of “Function Description”.
E R/W
Selected state
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
S1D15705***** S1D15707***** S1D15708*****
Normal rotation COM0 → COM63 COM0 → COM31 C OM0 → COM15
0
1
0
1
1
0
0
0
1
*
*
*
Reversal
COM63 → COM0 COM31 → COM0 COM15→ COM0
*: Invalid bit
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(16) Power Control Set
This command sets the function of the power supply circuit. For details, see the Power Supply Circuit of “Function
Description”.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Selected state
0
1
0
0
0
1
0
1
0
1
Boosting circuit: OFF
Boosting circuit: ON
0
1
V adjusting circuit: OFF
V adjusting circuit: ON
0
1
V/F circuit: OFF
V/F circuit: ON
(V/F circuit: Voltage follower circuit, V adjusting circuit: voltage adjusting circuit)
(17) V5 Voltage Adjusting Built-in Resistance Ratio Set
This command sets the V5 voltage adjusting built-in resistance ratio. For details, see the Power Supply Circuit of
“Function Description”.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Rb to Ra ratio
0
1
0
0
0
1
0
0
0
0
0
0
0
1
↓
0
1
0
Small
↓
1
1
1
1
0
1
Large
(18) Electronic Control (2-Byte Command)
This command controls the liquid crystal drive voltage V5 output from the voltage adjusting circuit of the built-in liquid
crystal power supply and can adjust the light and shade of liquid crystal display.
Since this command is a 2-byte command that is used together with the electronic control mode set command and
electronic control register set command, always use both the commands consecutively.
• Electronic Control Mode Set
Entering this command validates the electronic control register set command. Once the electronic control mode is set,
the commands other than the electronic control register set command cannot be used. This state is reset after data is set
in the register using the electronic control register set command.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
0
0
0
0
0
1
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• Electronic Control Register Set
This command is used to set 6-bit data in the electronic volume register to allow the liquid crystal drive voltage V5 to
enter one-state voltage value among 64-state voltage values.
After this command is entered and the electronic control register is set, the electronic control mode is reset.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
| V5 |
0
0
0
1
1
1
0
0
0
*
*
*
*
*
*
0
0
0
0
0
0
0
0
0
↓
0
0
0
0
0
1
0
1
0
Small
↓
0
0
1
1
0
0
*
*
*
*
1
1
1
1
1
1
1
1
1
1
0
1
Large
*: Invalid bit
When not using the electronic control function, set (1,0,0,0,0,0).
• Sequence of the electronic control register set
Electronic Control Mode Set
Electronic Control Register Set
Electronic control mode reset
No
Is the change terminated?
Yes
Fig. 18
(19) Static Indicator (2-Byte Command)
This command controls the indicator display of the static drive system. The static indicator display is controlled only
using this command, and this command is independent of other display control commands.
The static indicator is used to connect the SYNC pin to one of its liquid crystal drive electrodes and the FRS pin to the
other. For the electrodes used for the static indicator, the pattern separated from the electrodes for dynamic drive are
recommended. When this pattern is too adjacent, the deterioration of liquid crystal and electrodes may be caused.
Since the static indicator ON command is a 2-byte command that is used together with the static indicator register set
command, always use both the commands consecutively. (The static indicator OFF command is a 1-byte command.)
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• Static Indicator ON/OFF
Entering the static indicator ON command validates the static indicator register set command. Once the static indicator
ON command is entered, the commands other than the static indicator register set command cannot be used. This state
is reset after the data is set in the register using the static indicator register set command.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Static indicator
0
1
0
1
0
1
0
1
1
0
0
1
OFF
ON
• Static Indicator Register Set
This command sets data in the 2-bit static indicator register and sets the blinking state of the static indicator.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Indicator display state
0
1
0
*
*
*
*
*
*
0
0
0
1
OFF
ON (blinks at an interval of approximately
0.5 second.)
1
1
0
1
ON (blinks at an interval of approximately
one second.)
ON (goes on at all times.)
*: Invalid bit
• Sequence of Static Indicator Register Set
Static Indicator ON
Static Indicator Register Set
(Static indicator
mode reset)
No
Is the change terminated?
Yes
Fig. 19
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(20) Power Save
This command makes the static indicator enter the power save state and can greatly reduce the power consumption. The
power save state consists of the sleep state and stand-by state.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Power save state
0
1
0
1
0
1
0
1
0
0
0
1
Stand-by state
Sleep state
The operating state before the display data and power save activation is held in the sleep and stand-by states, and the
display data RAM can also be accessed from the MPU.
• Sleep State
This command stops all the operations of LCD display systems, and can reduce the power consumption approximate
to the static current when they are not accessed from the MPU. The internal state in the sleep state is as follows:
(1) The oscillator circuit and the LCD power supply circuit are stopped.
(2) All liquid crystal drive circuit is stopped and the segment and common drivers output the VDD level.
• Stand-by State
This command stops the operation of the duty LCD display system and operates only the static drive system for
indicators. Consequently the minimum current consumption required for the static drive is obtained. The internal state
in the stand-by state is as follows:
(1) The LCD power supply circuit is stopped. The oscillator circuit is operated.
(2) The duty drive system liquid crystal drive circuit is stopped and the segment and common drivers output the VDD
level. The static drive system is operated.
* When using external power supplies, it is recommended that the function of the external power supply circuit
should be stopped at power save activation. For example, when providing each level of the liquid crystal drive
voltage using a stand-alone split resistor circuit, it is recommended that the circuit which cuts off the current
applied to the split resistor circuit should be added at power save activation. The S1D15705 series has the liquid
crystal display blanking control pin DOF and is set to LOW at power save activation. The function of the
external power supply circuit can be stopped using the DOF output.
(21) Power Save Reset
This command resets the power save state and returns the state before power save activation.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
0
0
0
1
(22) n-Line Reversal Drive Register Set
This command sets the number of reversal lines of the liquid crystal drive in the register. 2 to 16 lines can be set. For
details, see the Display Timing Generator Circuit of “Function Description”.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Line of reversal lines
0
1
0
0
0
1
1
0
0
0
0
0
0
0
0
1
↓
0
1
0
—
2
3
↓
1
1
1
1
1
1
0
1
15
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(23) n-Line Reversal Drive Reset
This command resets the n-line reversal alternating current drive and returns to the normal 2-frame reversal alternating
current drive system. The value of the n-line reversal alternating current drive register is not changed.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
0
1
0
0
(24) Built-in Oscillator Circuit ON
This command starts the operation of the built-in CR oscillator circuit. This command is valid only for the master
operation (M/S=HIGH) and built-in oscillator circuit valid (CLS=HIGH).
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
1
0
1
0
1
1
(25) NOP
Non-OPeration
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
0
0
0
1
1
(26) Test
IC chip test command. Do not use this command. If the test command is used incorrectly, it can be reset by setting the
RES input to LOW or by using the reset command or NOP.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
1
1
1
*
*
*
*
*: Invalid bit
(Note) Although the S1D15705 series holds the command operating state, it may change the internal state if excessive
foreign noise is entered. Such action that suppresses the generation of noise and prevents the effect of noise
needs to be taken on installation and systems. Besides, to prevent sudden noise, it is recommended that the
operating state should periodically be refreshed.
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Table 16 S1D15705 Series Commands
Command code
Command
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Function
(1) Display ON/OFF
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
0
0
1
0
0
1
0
1
1
1
0
1
LCD display ON/OFF
0: OFF, 1: ON
(2) Display Start Line Set
(3) Page Address Set
(4) Column Address Set
Display start address Sets the display start line
address of the display RAM.
1
1
Page
Address
Sets the page address of
the display RAM.
0
1
High order
Column
address
Low order
Column
Sets the high-order four bits of
the column address of the display
RAM.
Sets the low-order four bits of
the column address of the display
RAM.
High-Order Bit
Column Address Set
Low-Order Bit
0
1
0
0
0
0
0
address
(5) Status Read
0
1
1
0
0
1
0
1
1
0
1
0
Status
0
0
0
0
Reads the status information.
Writes data on the display RAM.
Reads data from the display RAM.
(6) Display Data Read
(7) Display Data Write
(8) ADC Select
Write data
Read data
1
1
0
0
1
0
0
0
1
0
1
0
1
Supports the SEG output of
the display RAM address.
0: normal rotation, 1: Reversal
(9) Display Normal
Rotation/Reversal
0
1
0
1
0
0
0
1
LCD display normal rotation/
reversal
0: normal rotation, 1: Reversal
(10) Display All Lighting
ON/OFF
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
0
1
0
1
Display all lighting
0: normal display, 1: All ON
(11) LCD Bias Set
0
1
Sets the LCD drive voltage bias ratio.
S1D15705***** 0: 1/9, 1: 1/7,
S1D15707***** 0: 1/6, 1: 1/5
Increments the column address.
At write operation: By 1, at read: 0
(12) Read Modify Write
0
1
0
1
1
1
0
0
0
0
0
(13) End
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
1
0
*
1
1
*
0
0
*
Resets Read Modify Write.
Internal resetting
(14) Reset
(15) Common Output State
Selection
Selects the scanning direction of
the COM output.
1
1
0: Normal rotation, 1: Reversal
(16) Power Control Set
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
Operating Selects the state of the built-in
state power supply
(17) V5 Voltage Adjusting Internal
Resistance Ratio Set
0 Resistance Selects the state of the built-in
ratio setting resistance ratio (Rb/Ra).
(18) Electronic Control
Mode Set
0
0
1
1
0
0
1
*
0
*
0
0
0
1
Electronic Control
Register Set
Electronic
control value
Sets the V5 output voltage
in the electronic register.
(19) Static Indicator ON/OFF
0
0
1
1
0
0
1
*
0
*
1
*
0
1
1
0
0
1
0: OFF, 1: ON
Static Indicator
Register Set
*
*
*
State Sets the blinking state.
(20) Power Save
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
Moves to the power save state.
0: Stand-by, 1: Sleep
(21) Power Save Reset
0
0
1
1
0
0
1
0
1
0
1
1
0
1
1
Resets power save.
(22) n-Line Reversal Drive
Register Set
Number of
reversal Line reversal drive lines.
Sets the number of line
(23) n-Line Reversal Drive Reset
0
0
1
1
0
0
1
1
1
0
1
1
0
0
0
1
1
0
0
1
0
1
Resets the line reversal drive.
(24) Built-in Oscillator
Circuit ON
Starts the operation of the built-in
CR oscillator circuit.
(25) NOP
(26) Test
0
0
1
1
0
0
1
1
1
1
1
1
0
1
0
*
0
*
1
*
1
*
Non-Operation command
Do not use the IC chip
test command.
*: Invalid bit
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8. COMMAND SETTING
Instruction Setup: Reference
(1) Initial Setting
Turn on the VDD - VSS power supply in the RES pin=LOW *1
Power supply regulated
Reset the reset state (RES pin=HIGH)
Initial setting state (default) *2
Function setting by command input (set by user)
(21) Power Save Reset *3
(24) Built-in Oscillator Circuit ON *4
(The built-in CR oscillator circuit is used)
Function setting by command input (set by user)
(11) LCD Bias Set *5
(8) ADC Select *6
(15) Common Output State Selection *7
(22) n-Line Reversal Register Set *8
(When the n-line alternating current
reversal drive is used)
Function setting by command input (set by user)
(17) V5 Voltage Adjusting Built-in Resistance
ratio Set *9
(18) Electronic Control *10
Function setting by command input (set by user)
(16) Power Control Set *11
End of initial setting
Notes: Reference items
*1: If external power supplies for driving LCD are used, do not supply voltage on VOUT or V5 pin during
the period when RES = LOW. Instead, input voltage after releasing the reset state.
6. Function Description “Reset Circuit”
*2: The contents of DDRAM are not defined even in the initial setting state after resetting.
6. Function Description Section “Reset Circuit”
*3: 7. Command Description Item (21) Power save reset
*4: 7. Command Description Item (24) Built-in oscillator circuit ON
*5: 7. Command Description Item (11) LCD bias set
*6: 7. Command Description Item (8) ADC select
*7: 7. Command Description Item (15) Common output state selection
*8: 6. Function Description Section “Display Timing Generator Circuit”, 7. Command Description Item (22)
n-Line Reversal Register Set
*9: 6. Function Description Section “Power Supply Circuit” and 7. Command Description Item (17) V5
Voltage Adjusting Built-in Resistance ratio Set
*10: 6. Function Description Section “Power Supply Circuit” and 7. Command Description Item (18)
Electronic Control
*11: 6. Function Description Section “Power Supply Circuit” and 7. Command Description Item (16)
Power Control Set
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S1D15705 Series Technical Manual
(2) Data Display
End of initial setting
Function setting by command input (set by user)
(2) Display Start Line Set *12
(3) Page Address Set *13
(4) Column Address Set *14
Function setting by command input (set by user)
(6) Display Data Write *15
Function setting by command input (set by user)
(1) Display ON/OFF *16
End of data display
Notes: Reference items
*12: 7. Command Description Item (2) Display Start Line Set
*13: 7. Command Description Item (3) Page Address Set
*14: 7. Command Description Item (4) Column Address Set
*15: The contents of DDRAM is not defined after completing initial setting. Enter data in each DDRAM to
be used for display.
7. Command Description Item (6) Display Data Write
*16: Avoid activating the display function with entering space characters as the data if possible.
7. Command Description Item (1) Display ON/OFF
(3) Refresh *17
A desired mode
Set all commands again
Function setting by command
(21) Power Save Reset
(22) NOP
Write in the display data RAM again
Notes: Reference items
*17: It is recommended that the operating modes and display contents be refreshed periodically to prevent
the effect of unexpected noise.
Input (21) Power Save Reset and (22) NOP in order to avoid going into a power save state and IC tip
test state accidentally.
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(4) Power OFF *17
Any desired state
Function setting by command input (set by user)
(20) Power Save *19
Reset state (RES pin=LOW) *20
Set the time interval after the point when reset
state has attained and the point when VDD – VSS
power is shut off (tL) so that electric potentials, V1
through V5, attain values lower than the threshold
voltage displayed on the LCD panel. *21
V
DD – VSS power OFF
Notes: Reference items
*18: This IC is a VDD – VSS power system circuit controlling the LCD driving circuit for the VDD – V5
power system. Shutting of power with voltage remaining in the VDD – V5 power system may cause
uncontrolling voltage to be output from the SEG and COM pins. Follow the Power OFF sequence.
*19: 7. Command Description Item Power Saving
*20: When external power supplies for driving LCD are used, turn all external power supplies off before
entering reset state.
6. Function Description Item Reset Circuit
*21: The reference value for the threshold voltage of the LCD panel is 1 [V].
When the built-in power circuit is used, the discharge time, tH, or the time interval between the point
when the reset state has started and the point when voltage between VDD and V5 becomes 1 [V]
depends on the VDD – VSS power voltage and the capacity C2 connected between V1 – V5 and VDD.
100
80
60
40
20
0
0
0.2
0.4
0.6
0.8
1
Capacity C2 [µF]
Fig. 20
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Set up tL so that the relationship, tL > tH, is maintained. A state of tL < tH may cause faulty display.
t
L
Power OFF
2.4 [V]
Power saving
V
DD
RES
As power (VDD – VSS
is shut off, it becomes
impossible to fix output.
)
SEG
COM
At or under Vth on LCD.
Use 1.0 [V] as a
reference.
V
VDD
V1
2
V
V3
V4
5
t
H
Fig. 21
Take action so that the relationship,
tL > tH, is maintained by measures
such as making the trailing
t
L
Power OFF
characteristic longer.
V
DD
2.4 [V]
RES
As power (VDD – VSS
is shut off, it becomes
unable to fix output.
)
SEG
COM
At or under Vth on LCD.
Use 1.0 [V] as a
reference.
V
VDD
V1
2
V
V3
V4
5
t
H
If command control is disabled when power is OFF, take action so that the relationship, tL > tH, is
maintained by measures such as making the trailing characteristic of power (VDD – VSS) longer.
Fig. 22
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S1D15705 Series Technical Manual
9. ABSOLUTE MAXIMUM RATINGS
Table 17
VSS=0 V unless specified otherwise
Item
Power supply voltage
Symbol
Specification value
Unit
VDD
–0.3
–7.0
–6.0
–4.5
to
to
to
to
+7.0
+0.3
+0.3
+0.3
+0.3
+0.3
V
Power supply voltage (2)
(Based on VDD)
At triple boosting
VSS2
At quadruple boosting
Power supply voltage (3) (Based on VDD)
Power supply voltage (4) (Based on VDD)
Input voltage
V5, VOUT
V1, V2, V3, V4
VIN
–20.0 to
V5
to
–0.3
–0.3
–40
–55
–55
to VDD+0.3
to VDD+0.3
Output voltage
VO
Operating temperature
TOPR
to
to
to
+85
+100
+125
°C
Storage temperature
TCP
TSTR
Bare chip
VCC
VDD
VDD
VSS
GND
VSS2, V1 to
V4
V5, VOUT
System (MPU) side
S1D15705 side
Fig. 23
(Notes) 1. The values of the VSS2, V1 to V5, and VOUT voltages are based on VDD=0 V.
2. The V1, V2, V3, and V4 voltages must always satisfy the condition of VDD≥V1≥V2≥V3≥V4≥V5.
3. The VSS2 and VOUT voltages must always satisfy the condition of VDD≥VSS≥VSS2≥VOUT.
4. When LSI is used exceeding the absolute maximum ratings, the LSI may be damaged permanently.
Besides, it is desirable that the LSI should be used in the electrical characteristics condition for normal
operation. If this condition is exceeded, the LSI may malfunction and have an adverse effect on the
reliability of the LSI.
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10. DC CHARACTERISTICS
Table 18
Unless otherwise specified, VSS=0 V, Ta=–40 to +85°C
Specification value
Applicable
pin
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
S1D15705*03**/S1D15707*03**
Operating voltage (1)
VDD
VDD
2.4
3.6
—
—
3.6
5.5
V
VDD *1
VDD *1
S1D15705*00**/S1D15707*00**
/S1D15708*00**
Operating voltage (2)
Operating voltage (3)
VSS2
(Based on VDD)
–6.0
—
–1.8
VSS2
S1D15705***** (Based on VDD)
S1D15707***** (Based on VDD)
S1D15708***** (Based on VDD)
V5
V5
V5
–18.0
–16.0
–10.0
0.4×V5
V5
—
—
—
—
—
–4.5
–4.5
–4.5
VDD
0.6×V5
V5 *2
V5 *2
V5 *2
V1, V2
V3, V4
V1, V2 (Based on VDD)
V3, V4 (Based on VDD)
High level input voltage
Low level input voltage
VIHC
VILC
0.8×VDD
VSS
—
—
VDD
0.2×VDD
*3
*3
High level output voltage
Low level output voltage
VOHC IOH=–0.5mA
0.8×VDD
VSS
—
—
VDD
0.2×VDD
*4
*4
VOLC
IOL=0.5mA
Input leak current
Output leak current
ILI
ILO
VIN=VDD or VSS
–1.0
–3.0
—
—
1.0
3.0
µA
kΩ
µA
pF
*5
*6
Liquid crystal driver
On resistance
RON
Ta=25°C
(Based on VDD) V5=–8.0V
V5=–14.0V
—
—
2.0
3.2
3.5
5.4
SEGn
COMn *7
Static current consumption ISSQ
Output leak current
—
—
0.01
0.01
5
15
VSS, VSS2
V5
I5Q
V5=–18.0V (Based on VDD)
Ta=25°C, f=1MHz
Ta=25°C
Input pin capacity
CIN
—
5.0
22
8.0
26
Oscillating Built-in
fOSC
18
*8
frequency oscillation
Ta=25°C, S1D15705*****
Ta=25°C, S1D15707*****
Ta=25°C, S1D15708*****
External input
fCL
4.5
5.5
6.5
kHz
CL *8
CL *8
CL *8
2.25
1.13
2.75
1.38
3.25
1.63
Table 19
Specification value
Applicable
pin
Item
Symbol
Condition
Unit
Min.
Typ.
Max.
Input voltage
VSS2
At triple boosting
(Based on VDD)
–6.0
—
–1.8
V
VSS2
VSS2
At quadruple boosting
(Based on VDD)
–4.5
—
–1.8
VSS2
Boosting output voltage VOUT (Based on VDD)
–20.0
–20.0
—
—
—
VOUT
VOUT
Voltage adjusting circuit VOUT (Based on VDD)
operating voltage
–6.0
V/F circuit operating
voltage
V5
V5
—
—
–4.5
–4.5
V5 *9
V5 *9
S1D15705***** (Based on VDD) –18.0
–16.0
S1D15707***** (Based on VDD)
V5
–10.0
—
–4.5
V5 *9
*10
S1D15708***** (Based on VDD)
Reference voltage
VREG0 Ta=25°C,
–0.05%/°C
–2.04
–2.10
–2.16
[*: see Page 61.]
Rev. 3.2
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Dynamic current consumption value (1) During display operation and built-in power supply OFF
Current values dissipated by the whole IC when the external power supply is used
Table 20-1 Display All White
Ta=25°C
Unit Remarks
Specification value
Item
Symbol
Condition
Min.
Typ.
22
22
8
Max.
37
37
14
14
7
IDD
VDD=5.0V, V5–VDD=–11.0V
VDD=3.0V, V5–VDD=–11.0V
VDD=5.0V, V5–VDD=–8.0V
VDD=3.0V, V5–VDD=–8.0V
VDD=5.0V, V5–VDD=–6.0V
—
µA
*11
S1D15705*00**
S1D15705*03**
S1D15707*00**
S1D15707*03**
S1D15708*00**
(1)
—
8
4
Table 20-2 Display Checker Pattern
Ta=25°C
Specification value
Item
Symbol
Condition
Unit Remarks
Min.
Typ.
33
32
14
14
5
Max.
55
54
24
24
9
IDD
VDD=5.0V, V5–VDD=–11.0V
VDD=3.0V, V5–VDD=–11.0V
VDD=5.0V, V5–VDD=–8.0V
VDD=3.0V, V5–VDD=–8.0V
VDD=5.0V, V5–VDD=–6.0V
—
µA
*11
S1D15705*00**
S1D15705*03**
S1D15707*00**
S1D15707*03**
S1D15708*00**
(1)
—
Dynamic current consumption value (2) During display operation and built-in power supply ON
Current values dissipated by the whole IC containing the built-in power supply circuit
Table 21-1 Display Checker Pattern
Ta=25°C
Specification value
Item
Symbol
Condition
Normal mode
Unit Remarks
µA *12
Min.
Typ.
Max.
S1D15705*00**
IDD
(2)
VDD=5.0V,
Triple boosting
—
73
122
V5–VDD=–11.0V High power mode
—
—
216
92
360
154
VDD=3.0V,
Normal mode
S1D15705*03**
S1D15707*00**
S1D15707*03**
S1D15708*00**
Quadruple boosting
V5–VDD=–11.0V High power mode
—
—
272
40
454
67
VDD=5.0V,
Triple boosting
Normal mode
V5–VDD=–8.0V High power mode
—
—
171
51
285
85
VDD=3.0V,
Normal mode
Quadruple boosting
V5–VDD=–8.0V High power mode
—
—
228
28
380
47
VDD=5.0V,
Double boosting
Normal mode
V5–VDD=–6.0V High power mode
—
137
229
[*: see Page 61.]
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S1D15705 Series Technical Manual
Table 21-2 Display Checker Pattern
Ta=25°C
Specification value
Unit Remarks
Item
Symbol
Condition
Normal mode
Min.
Typ.
Max.
S1D15705*00**
IDD
(2)
VDD=5.0V,
Triple boosting
—
97
162
µA
*12
V5–VDD=–11.0V High power mode
—
—
254
130
424
217
VDD=3.0V,
Normal mode
S1D15705*03**
S1D15707*00**
S1D15707*03**
S1D15708*00**
Quadruple boosting
V5–VDD=–11.0V High power mode
—
—
308
54
514
90
VDD=5.0V,
Triple boosting
Normal mode
V5–VDD=–8.0V High power mode
—
—
185
71
309
119
VDD=3.0V,
Normal mode
Quadruple boosting
V5–VDD=–8.0V High power mode
—
—
248
35
414
59
VDD=3.0V,
Double boosting
Normal mode
V5–VDD=–6.0V High power mode
—
144
240
Current consumption at power save VSS=0 V and VDD=3.0 V ±10% (S1D15705*03**, S1D15707*03**)
5.0V ± 10% (S1D15705*00**, S1D15707*00**,
S1D15708*00**)
Table 22
Item
Ta=25°C
Specification value
Symbol
Condition
Unit Remarks
Min.
Typ.
0.01
4
Max.
Sleep state
IDDS1
IDDS2
Ta=25°C
Ta=25°C
—
5
8
µA
Stand-by state
—
[*: see Page 61.]
Rev. 3.2
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57
S1D15705 Series Technical Manual
[Reference data 1]
• Dynamic current consumption (1) External power supply used and LCD being displayed
Condition: Built-in power supply OFF
40
30
20
10
0
External power supply used
S1D15705: V5 – VDD = –11.0 V
S1D15707: V5 – VDD = –8.0 V
S1D15708: V5 – VDD = –6.0 V
Display pattern: All white/checker
Ta = 25°C
S1D15705/
Checker
S1D15705*03**/ S1D15705*00**/
S1D15707*03** S1D15707*00**
S1D15705/
All white
S1D15707/
Checker
Remarks: *11
S1D15707/
All white
S1D15708/Checker
S1D15708/All white
0
2
3.6 4
DD [V]
6
8
V
Fig. 24
[Reference data 2]
• Dynamic current consumption (2) Built-in power supply used and LCD being displayed
250
Condition: Built-in power supply ON
Normal mode
Quadruple boosting
S1D15705: V5 – VDD = –11.0 V
Triple boosting
S1D15707: V5 – VDD = –8.0 V
Double boosting
S1D15708: V5 – VDD = –6.0 V
Display pattern: All white/checker
Ta = 25°C
S1D15705*03**/ S1D15705*00**/
S1D15707*03** S1D15707*00**
200
150
100
50
S1D15705/Checker
S1D15705/All white
S1D15707/Checker
S1D15707/All white
S1D15708/Checker
S1D15708/All white
Remarks: *12
0
0
2
3.6 4
DD [V]
6
8
V
Fig. 25
[*: see page 61.]
58
EPSON
Rev. 3.2
S1D15705 Series Technical Manual
[Reference data 3]
• Dynamic current consumption (3) During access
Indicates the current consumption when the checker
pattern is always written at fCYC.
Only IDD (1) when not accessed
Condition: Built-in power supply OFF and external
power supply used
10
S1D15705*00**
S1D15705*03**
S1D15707*00**
S1D15707*03**
S1D15705:
V5 – VDD = –11.0 V
S1D15707:
S1D15708*00**
1
V5 – VDD = –11.0 V
S1D15705*03**/S1D15707*03**:
VDD – VSS = 3.0 V
S1D15705*00**/S1D15707*00**
0.1
/S1D15708*00**:
VDD – VSS = 5.0 V
Ta = 25°C
[*: see page 61.]
0.01
0.001
0.01
0.1
1
10
f
CYC [MHz]
Fig. 26
Rev. 3.2
EPSON
59
S1D15705 Series Technical Manual
[Reference data 4]
VSS and V5 system operating voltage
ranges
Remarks: *2
–20
–18
–20
–15
–10
–5
–16
S1D15705*00**
S1D15705*03**
–15
S1D15707*03**
S1D15707*00**
–10
–5
0
Operation
Area
Operation
Area
–9.6
–4.5
–9.6
–4.5
2.4
3.6
4
5.5
2.4
3.6
4
5.5
0
0
0
2
6
8
2
6
8
V
DD [V]
VDD [V]
–20
–15
–10
–5
[*: see page 61.]
S1D15708*00**
Operation
Area
–4.5
3.6
4
5.5
0
0
2
6
8
V
DD [V]
Fig. 27
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S1D15705 Series Technical Manual
Relationships between the oscillating frequency fOSC, display clock frequency fCL, and liquid
crystal frame frequency fFR
Table 23
fFR
Item
fCL
Normal duty drive n-line reverse drive
When built-in oscillator
circuit used
When built-in oscillator
circuit not used
When built-in oscillator
circuit used
When built-in oscillator
circuit not used
fOSC
4
fOSC
4.65
fCL
65
fOSC
8.33
fCL
33
fOSC
4.n
fCL
n
fOSC
8.n
fCL
n
S1D15705*****
S1D15707*****
S1D15708*****
External input (fCL)
fOSC
8
External input (fCL)
When built-in oscillator
circuit used
fOSC
16
fOSC
16.17
fOSC
16.n
When built-in oscillator
circuit not used
External input (fCL)
fCL
17
fCL
n
(fFR shows the alternating current cycle (frame cycle) of liquid crystal. The signal of FR terminal becomes twice as a
frame cycle.)
[Reference items marked by *]
*1 The wide operating voltage range is not warranted. However, when there is a sudden voltage change
during MPU access, it cannot be warranted.
*2 For the VDD and V5 operating voltage ranges, see Fig. 27. These ranges are applied when using the
external power supply.
*3 A0, D0 to D5, D6 (SCL), D7 (SI), RD (E), WR (R/W), CS1, CS2, CLS, CL, FR, M/S, C86, P/S, DOF,
RES, IRS and HPM pins
*4 D0 to D7, FR, FRS, DOF and CL pins
*5 A0, RD (E), WR (R/W), CS1, CS2, CLS, M/S, C86, P/S, RES, IRS and HPM pins
*6 Applied when D0 to D5, D6 (SCL), D7 (SI), CL, FR, and DOF pins are in the high impedance state
*7 Resistance value when the 0.1 V voltage is applied between the output pin SEGn or COMn and power
supply pins (V1, V2, V3, and V4). Specified within the range of operating voltage (3)
RON = 0.1 V/∆I (∆I indicates the current applied when 0.1 V is applied between the power ON.)
*8 For the relationship between the oscillating frequency and frame frequency, see Table 23. The
specification value of the external input item is a recommended value.
*9 The V5 voltage adjusting circuit is adjusted within the voltage follower operating voltage range.
*10 Built-in reference voltage source of the V5 voltage adjusting circuit.
*11 and *12 Indicate the current dissipated by a single IC at built-in oscillator circuit used, 1/9 bias
(S1D15705
*****), 1/6 bias (S1D15707*****/S1D15708*****), and display ON.
Does not include the current due to the LCD panel capacity and wireing capacity.
Applicable only when there is no access from the MPU.
*12 When the V5 voltage adjusting built-in resistor is used
Rev. 3.2
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Timing Characteristics
System bus read/write characteristics 1 (80 series MPU)
A0
t
AW8
t
AH8
CS1
(CS2="1")
t
CYC8
*1
t
CCLR, tCCLW
WR, RD
t
CCHR
,
t
CCHW
CS1
(CS2="1")
*2
t
f
t
r
WR, RD
t
DS8
t
DH8
D0 to D7
(Write)
t
ACC8
t
OH8
D0 to D7
(Read)
[S1D15705*00**, S1D15707*00**, S1D15708*00**: VDD=4.5V to 5.5V, Ta=–40 to +85°C]
Specification value
Item
Signal Symbol
Condition
Unit
Min.
Max.
Address hold time
Address setup time
A0
tAH8
tAW8
0
0
—
—
ns
System cycle time
tCYC8
250
—
Control LOW pulse width (Write)
WR
tCCLW
tCCLR
tCCHW
tCCHR
30
70
30
30
—
—
—
—
Control LOW pulse width (Read) RD
Control HIGH pulse width (Write WR
Control HIGH pulse width (Read) RD
)
Data setup time
Data hold time
D0 to D7
tDS8
tDH8
30
10
—
—
RD access time
Output disable time
tACC8
tOH8
CL=100pF
—
5
70
50
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Rev. 3.2
S1D15705 Series Technical Manual
[S1D15705*00**, S1D15707*00**, S1D15708*00**: VDD=3.6V to 4.5V, Ta=–40 to +85°C]
Specification value
Item
Signal Symbol
Condition
Unit
Min.
Max.
Address hold time
Address setup time
A0
tAH8
tAW8
0
0
—
—
ns
System cycle time
tCYC8
300
—
Control LOW pulse width (Write
Control LOW pulse width (Read
Control HIGH pulse width (Write)
)
WR
RD
WR
tCCLW
tCCLR
tCCHW
tCCHR
60
120
60
—
—
—
—
)
Control HIGH pulse width (Read) RD
60
Data setup time
Data hold time
D0 to D7
tDS8
tDH8
40
15
—
—
RD access time
Output disable time
tACC8
tOH8
CL=100pF
—
10
280
100
[S1D15705*03**, S1D15707*03**: VDD=2.4V to3.6V, Ta=–40 to +85°C]
Specification value
Item
Signal Symbol
Condition
Unit
Min.
Max.
Address hold time
Address setup time
A0
tAH8
tAW8
0
0
—
—
ns
System cycle time
tCYC8
800
—
Control LOW pulse width (Write
Control LOW pulse width (Read
Control HIGH pulse width (Write)
Control HIGH pulse width (Read) RD
)
)
WR
RD
WR
tCCLW
tCCLR
tCCHW
tCCHR
120
240
120
120
—
—
—
—
Data setup time
Data hold time
D0 to D7
tDS8
tDH8
80
30
—
—
RD access time
Output disable time
tACC8
tOH8
CL=100pF
—
10
280
200
*1 This is in the case of making the access by WR and RD, setting the CS1=LOW.
*2 This is in the case of making the access by CS1, setting the WR, RD=LOW.
*3 The rise and fall times (tr and tf) of the input signal are specified for less than 15 ns. When using the system cycle
time at high speed, they are specified for (tr+tf) ≤ (tCYC8–tCCLW–tCCHW) or (tr+tf) ≤ (tCYC8–tCCLR–tCCHR).
*4 All timings are specified based on the 20 and 80% of VDD.
*5 tCCLW and tCCLR are specified for the overlap period when CS1 is at LOW (CS2= HIGH) level and WR, RD are
at the LOW level.
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System bus read/write characteristics 2 (68 series MPU)
A0
R/W
t
AW6
t
AH6
CS1
(CS2="1")
t
CYC6
*1
t
EWHR, tEWHW
E
t
EWLR, tEWLW
CS1
(CS2="1")
t
r
t
f
*2
E
t
DS6
t
DH6
D0 to D7
(Write)
t
ACC6
t
OH6
D0 to D7
(Read)
[S1D15705*00**, S1D15707*00**, S1D15708*00**: VDD=4.5V to 5.5V, Ta=–40 to +85°C]
Specification value
Item
Signal
Symbol
Condition
Unit
Min.
Max.
Address hold time
Address setup time
A0
tAH6
tAW6
0
0
—
—
ns
System cycle time
tCYC6
250
—
Data setup time
Data hold time
D0 to D7
tDS6
tDH6
30
10
—
—
Access time
Output disable time
tACC6
tOH6
CL=100pF
—
5
70
50
Enable HIGH pulse width Read
Write
E
E
tEWHR
tEWHW
70
30
—
—
Enable LOW pulse width Read
Write
tEWLR
tEWLW
30
30
—
—
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S1D15705 Series Technical Manual
[S1D15705*00**, S1D15707*00**, S1D15708*00**: VDD=3.6V to 4.5V, Ta=–40 to +85°C]
Specification value
Item
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
Signal
A0
Symbol
tAH6
tAW6
tCYC6
tDS6
tDH6
tACC6
tOH6
tEWHR
tEWHW
tEWLR
tEWLW
Condition
Min.
0
0
Max.
—
—
—
—
Unit
ns
300
40
15
—
10
120
60
60
60
D0 to D7
—
Access time
CL=100pF
140
100
—
—
—
Output disable time
Enable HIGH pulse width Read
Write
Enable LOW pulse width Read
Write
E
E
—
[S1D15705*03**, S1D15707*03**: VDD=2.4V to 3.6V, Ta=–40 to +85°C]
Specification value
Item
Signal
Symbol
Condition
Unit
Min.
0
Max.
—
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
A0
tAH6
tAW6
tCYC6
tDS6
ns
0
—
800
80
—
—
D0 to D7
tDH6
30
—
Access time
tACC6
tOH6
tEWHR
tEWHW
tEWLR
tEWLW
CL=100pF
—
10
240
120
120
120
280
200
—
—
—
Output disable time
Enable HIGH pulse width Read
Write
Enable LOW pulse width Read
Write
E
E
—
*1 This is in the case of making the access by E, setting the CS1=LOW.
*2 This is in the case of making the access by CS1, setting the E=HIGH.
*3 The rise and fall times (tr and tf) of the input signal are specified for less than 15 ns. When using the system cycle
time at high speed, they are specified for (tr+tf) ≤ (tCYC6–tEWLW–tEWHW) or (tr+tf) ≤ (tCYC6–tEWLR–tEWHR).
*4 All timings are specified based on the 20 and 80% of VDD.
*5 tEWLW and tEWLR are specified for the overlap period when CS1 is at LOW (CS2= HIGH) level and E is at the
HIGH level.
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Serial interface
t
CSS
t
CSH
CS1
(CS2="1")
t
SAS
t
SAH
A0
t
SCYC
t
SLW
SCL
t
SHW
t
f
t
r
t
SDS
t
SDH
SI
[S1D15705*00**, S1D15707*00**, S1D15708*00**: VDD=4.5V to 5.5V, Ta=–40 to +85°C]
Specification value
Item
Signal
Symbol
Condition
Unit
Min.
200
75
Max.
—
—
Serial clock cycle
SCL HIGH pulse width
SCL LOW pulse width
Address setup time
Address hold time
Data setup time
SCL
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
ns
75
—
A0
SI
50
—
100
50
—
—
Data hold time
CS-SCL time
50
—
CS
100
100
—
—
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S1D15705 Series Technical Manual
[S1D15705*00**, S1D15707*00**, S1D15708*00**: VDD=3.6V to 4.5V, Ta=–40 to +85°C]
Specification value
Item
Signal
Symbol
Condition
Unit
Min.
250
100
100
150
150
100
100
150
150
Max.
—
—
—
—
—
—
—
—
Serial clock cycle
SCL HIGH pulse width
SCL LOW pulse width
Address setup time
Address hold time
Data setup time
SCL
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
ns
A0
SI
Data hold time
CS-SCL time
CS
—
[S1D15705*03**, S1D15707*03**: VDD=2.4V to 3.6V, Ta=–40 to +85°C]
Specification value
Item
Signal
Symbol
Condition
Unit
Min.
400
150
150
250
250
150
150
250
250
Max.
—
—
—
—
—
—
—
—
Serial clock cycle
SCL HIGH pulse width
SCL LOW pulse width
Address setup time
Address hold time
Data setup time
SCL
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
ns
A0
SI
Data hold time
CS-SCL time
CS
—
*1 The rise and fall times (tr and tf) of the input signal are specified for less than 15 ns.
*2 All timings are specified based on the 20 and 80% of VDD.
Rev. 3.2
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S1D15705 Series Technical Manual
Display control output timing
CL
(OUT)
t
DFR
FR
t
DSNC
SYNC
[S1D15705*00**, S1D15707*00**, S1D15708*00**: VDD=4.5V to 5.5V, Ta=–40 to +85°C]
Specification value
Item
Signal
Symbol
Condition
Unit
Min.
—
Typ.
10
Max.
40
FR delay time
FR
tDFR
CL=50pF
CL=50pF
ns
ns
SYNC delay time SYNC
tDSNC
—
10
40
[S1D15705*00**, S1D15707*00**, S1D15708*00**: VDD=3.6V to 4.5V, Ta=–40 to +85°C]
Specification value
Item
Signal
Symbol
tDFR
Condition
CL=50pF
CL=50pF
Min.
—
Typ.
20
Max.
80
Unit
ns
FR delay time
FR
SYNC delay time SYNC
tDSNC
—
20
80
ns
[S1D15705*03**, S1D15707*03**: VDD=2.4V to 3.6V, Ta=–40 to +85°C]
Specification value
Item
Signal
Symbol
tDFR
Condition
CL=50pF
CL=50pF
Min.
—
Typ.
50
Max.
200
Unit
ns
FR delay time
FR
SYNC delay time SYNC
tDSNC
—
50
200
ns
*1 Valid only when the master mode is selected.
*2 All timings are specified based on the 20 and 80% of VDD.
*3 Pay attention not to cause delays of the timing signals CL, FR and SYNC to the salve side by wiring resistance, etc.,
while master/slave operations are in progress. If these delays occur, indication failures such as flickering may occur.
68
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Rev. 3.2
S1D15705 Series Technical Manual
Reset input timing
t
RW
RES
t
R
Internal state
Resetting
Completion of reset
[S1D15705*00**, S1D15707*00**, S1D15708*00**: VDD=4.5V to 5.5V, Ta=–40 to +85°C]
Specification value
Item
Signal Symbol
Condition
Min.
—
Typ.
—
Max.
0.5
Unit
Reset time
tR
µs
Reset LOW pulse width
RES
tRW
0.5
—
—
[S1D15705*00**, S1D15707*00**, S1D15708*00**: VDD=3.6V to 4.5V, Ta=–40 to +85°C]
Specification value
Item
Signal Symbol
Condition
Min.
—
Typ.
—
Max.
1
Unit
Reset time
tR
µs
Reset LOW pulse width
RES
tRW
1
—
—
[S1D15705*03**, S1D15707*03**: VDD=2.4V to 3.6V, Ta=–40 to +85°C]
Specification value
Item
Signal Symbol
Condition
Min.
—
Typ.
—
Max.
1.5
Unit
Reset time
tR
µs
Reset LOW pulse width
RES
tRW
1.5
—
—
*1 All timings are specified based on the 20 and 80% of VDD.
Rev. 3.2
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S1D15705 Series Technical Manual
11. MICROPROCESSOR (MPU) INTERFACE: REFERENCE
The S1D15705 series can directly be connected to the 80 system MPU and 68 series MUP. It can also be operated with
a fewer signal lines by using the serial interface.
The S1D15705 series is used for the multiple chip configuration to expand the display area. In this case, it can select
the ICs that are accessed individually using the Chip Select signal.
After the initialization using the RES pin, the respective input pins of the S1D15705 series need to be controlled
normally.
80 series MPU
VDD
V
CC
VDD
C86
P/S
A0
A0
A1 to A7
IORQ
CS1
CS2
Decoder
RESET
D0 to D7
RD
D0 to D7
RD
WR
RES
WR
RES
GND
VSS
VSS
68 series MPU
VDD
V
CC
V
DD
C86
P/S
A0
A0
A1 to A15
VMA
CS1
CS2
Decoder
RESET
D0 to D7
E
D0 to D7
E
R/W
R/W
RES
RES
GND
V
SS
VSS
Serial interface
V
CC
VDD
C86
A0
A0
VDD or VSS
CS1
CS2
A1 to A7
Decoder
RESET
Port 1
Port 2
RES
SI
SCL
RES
P/S
GND
V
SS
V
SS
70
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Rev. 3.2
S1D15705 Series Technical Manual
12. CONNECTION BETWEEN LCD DRIVERS: REFERENCE
The S1D15705 series is used for the multiple chip configuration to easily expand the liquid crystal display area. Use
the same device (S1D15705*****/S1D15705*****, S1D15707*****/S1D15707***** or S1D15708*****/
S1D15708*****) for the master/slave.
S1D15705 (master) ↔ S1D15705 (slave)
VDD
M/S
M/S
FR
FR
SYNC
CL
SYNC
CL
DOF
DOF
Output
Input
VSS
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S1D15705 Series Technical Manual
13. LCD PANEL WIRING: REFERENCE
The S1D15705 series is used for the multiple chip configuration to easily expand the liquid crystal display area. Use
the same device (S1D15705*****/S1D15705*****, S1D15707*****/S1D15707***** or S1D15708*****/
S1D15708*****) for the multiple chip configuration.
1-chip configuration
168 x 65 Dots
COM
SEG
COM
S1D15705
Master
2-chip configuration
336 x 65 Dots
COM
SEG
SEG
COM
S1D15705 Series
Master
S1D15705 Series
Slave
72
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Rev. 3.2
S1D15705 Series Technical Manual
14. TCP PIN LAYOUT
Reference
FRS
FR
CL
SYNC
DOF
SYNC
CS1
CS2
RES
A0
COM S
COM 63
•
•
WR,R/W
RD, E
D0
•
•
D1
•
D2
COM 33
D3
D4
COM 32
D5
SEG 167
D6, SCL
D7, SI
SEG 166
V
DD
SS
SS2
OUT
•
V
V
•
V
CAP3-
CAP1+
CAP1-
CAP2-
CAP2+
VRS
•
•
•
SEG 1
VDD
SEG 0
V1
V2
V3
V4
V5
COM S
COM 0
•
VR
•
V
DD
M/S
CLS
C86
P/S
•
•
•
HPM
IRS
COM 30
COM 31
Note) This TCP pin layout does not specify the TCP dimensions.
Rev. 3.2
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S1D15705 Series Technical Manual
15. TCP DIMENSIONS
t B a r
k i n g a r e a ) P ( M o l d , M a r
74
EPSON
Rev. 3.2
S1D15705 Series Technical Manual
16. TEMPERATURE SENSOR CIRCUIT
S1D15705*10** incorporates a temperatujre sensor circuit with a 11.4mV/°C (typ.) temperature gradient carrying
analog voltage output pins. The S1D15705*10** makes it possible to provide LCD indications with optimum contrast
throughout a wide temperature range without need for use of supplementary parts by inputting electronic volume control
registration value equivalent signals corresponding to the outputs of the temperature sensor through the MPU to control
the LCD drive voltage V5.
For LCD drive voltage controls of higher precision, we recommend you to constitute a system which can absorb
deviations of the output voltage by, such as, feeding back sampled output voltages under a certain temperature
environment to the MPU to let it memorize as the reference voltages.
Regarding the specifications of other items than the temperature sensor circuit, such as of the absolute maximum ratings,
DC characteristics, AC characteristics, etc., refer to the specifications for S1D15705*00**.
Pin Definitions
Temperature sensor circuit related pins are allocated to TEST1, 2, 3 and 4 and the pin names are TEST1, SVS, VSEN,
SEN and SENSEL in the given sequence. The temperature sensor should be used under the pin statuses indicated in
the Table below. When the temperature sensor is not being used, fix respective pins to HIGH.
Number
of pins
Pin names
I/O
Pin definitions
SVS
Power
supply
This is the power supply pin for the temperature sensor. Apply
prescribed operating voltage between the VDD.
1
VSEN
SEN
O
O
I
This is the analog voltage output pin for the temperature sensor.
Monitor the output voltage between the VDD.
1
1
1
Consider to keep this pin open in order not to apply the load
capacitance of wires, etc.
SENSEL
Fix this pin to HIGH.
Electric Characteristics
Items
Specifications
Applicable
pins
Codes
Conditions
Units
Min. Typ. Max.
Operating voltage
Output voltage
SVS
(On the basis of VDD) –5.5 –5.0 –4.5
V
V
SVS
VSEN
(On the basis of VDD) –4.35 –3.62 –2.89
Ta = 40°C
VSEN
(On the basis of VDD) –3.48 –2.88 –2.28
Ta = 25°C
(On the basis of VDD) –2.92 –2.20 –1.47
Ta = 85°C
Output voltage
VGRA
*1
9.4 11.4 13.4 mV/°C
VSEN
temperature gradient
Output voltage linearity
∆VL
*2
*3
–1.5
100
—
—
—
40
1.5
—
%
mS
µA
VSEN
VSEN
SVS
Output voltage setup time tSEN
Operating current
ISEN
Ta = 25°C
150
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S1D15705 Series Technical Manual
[* Notes]
*1: Represents the gradient of the approximate line of the Typ. output voltages.
*2: Represents the maximum deviation between the output voltage curve and the approximate line.
Assuming that the difference of output voltages at –40°C and at 80°C as ∆VSEN, assuming that the difference
between the approximate line and the output voltage values as ∆DIFF and assuming that the maximum value
thereof as ∆DIFF (MAX), the output voltages linearity ∆VL can be calculated by use of the following equation.
∆DIFF (MAX)
∆VL = ———————— × 100
∆VSEN
∆VDIFF
∆VSEN
∆VDIFF
Output voltage
= VSEN(–40°C)–VSEN(85°C)
Approximate line
The ∆VDIFF which becomes the
maximum point under all the
temperature levels is to be
deemed as the ∆VDIFF (MAX).
∆VDIFF
–50
–25
0
25
50
75
100
Temperature Ta [°C]
*3: Represents the queuing time after the supply voltage SVS is applied to the SVS pin until the output voltage is
stabilized and monitoring thereof becomes feasible. Be sure to sample the output voltage after the prescribed
queuing time has elapsed.
Output voltage characteristics
0
–1
Min.
–2
Typ.
Max.
–3
–4
–5
–50
–25
0
25
50
75
100
Temperature Ta [°C]
76
EPSON
Rev. 3.2
S1D15705 Series Technical Manual
Output Pin Load
Maintain the load capacity CL for the VSEN output pin VSEN at 100pF or less and keep the load resistance RL for the
VSEN output pin VSEN at 1MΩ or more.
In order to obtain accurate output voltage values, be careful not to insert a current flowing channel between the VSS.
V
DD
V
DD
CL
RL
V
SEN
V
SEN
Rev. 3.2
EPSON
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S1D15705 Series Technical Manual
17. CAUTIONS
Cautions must be exercised on the following points when using this Development Specification:
1. This Development Specification is subject to change for engineering improvement.
2. This Development Specification does not guarantee execution of the industrial proprietary rights or other rights, or
grant a license. Examples of applications described in This Development Specification are intended for your
understanding of the Product. We are not responsible for any circuit problem or the like arising from the use of them.
3. Reproduction or copy of any part or whole of this Development Specification without permission of our company,
or use thereof for other business purposes is strictly prohibited.
For the use of the semi-conductor,cautions must be exercised on the following points:
[Cautions against Light]
The semiconductor will be subject to changes in characteristics when light is applied. If this IC is exposed to light,
operation error may occur. To protect the IC against light, the following points should be noted regarding the substrate
or product where this IC is mounted:
(1) Designing and mounting must be provided to get a structure which ensures a sufficient resistance of the IC to
light in practical use.
(2) In the inspection process, environmental configuration must be provided to ensure a sufficient resistance of the
IC to light.
(3) Means must be taken to ensure resistance to light on all the surfaces, backs and sides of the IC
78
EPSON
Rev. 3.2
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Document Code: 404948101
First Issue February, 2004
Printed October 2005 in JAPAN
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