S1D15E06D00A [SEIKO]
LIQUID CRYSTAL DISPLAY DRIVER, UUC412, DIE-412;
| 型号： | S1D15E06D00A |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC412, DIE-412 驱动 |
| 文件： | 总85页 (文件大小：773K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MF1393-04
S1D15E05 Series
Rev. 1.3
“Seiko Epson is neither licensed nor authorized to license its customers under one or more patents held by
Motif Corporation to use this integrated circuit in the manufacture of liquid crystal display modules. Such
license, however, may be obtained directly from MOTIF by writing to: Motif, Inc., c/o In Focus Systems, Inc.,
27700A SW Parkway Avenue, Wilsonville, OR 97070-9215, Attention: Vice President Corporate
Development.”
SEIKO EPSON CORPORATION 2002
Rev. 1.3
Contents
1. DESCRIPTION .................................................................................................................................................. 1
2. FEATURES........................................................................................................................................................ 1
3. BLOCK DIAGRAM ............................................................................................................................................. 2
4. PIN ASSIGNMENT ............................................................................................................................................ 4
5. PIN DESCRIPTION ......................................................................................................................................... 11
6. FUNCTIONAL DESCRIPTION ........................................................................................................................ 16
7. COMMAND ...................................................................................................................................................... 34
8. ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 57
9. DC CHARACTERISTICS................................................................................................................................. 59
10. TIMING CHARACTERISTICS ......................................................................................................................... 68
11. MPU INTERFACE (Reference example) ......................................................................................................... 76
12. CONNECTION BETWEEN LCD DRIVERS (Reference example) .................................................................. 77
13. LCD PANEL WIRING (Reference example) .................................................................................................... 78
14. S1D15E05T00A TCP PIN LAYOUT ............................................................................................................. 79
*
15. TCP DIMENSIONS (Reference example) ....................................................................................................... 80
16. CAUTIONS ...................................................................................................................................................... 82
– i –
Rev. 1.3
S1D15E05 Series
1. DESCRIPTION
2. FEATURES
The S1D15E05 series is a single chip MLS driver for dot
matrix liquid crystal displays which can be directly
connected to the microcomputer bus. It accepts the 8-
bit parallel or serial display data from the microcomputer
to store the data in the on-chip display data RAM, and
issues liquid crystal drive signals independently of the
microcomputer.
• Direct RAM data display by display data RAM
• 4 gray-scale display
(Normally white in normal display mode)
RAM bit data (high order and low order)
(1,1) : gray-scale 3, black
(1,0) : gray-scale 2
(0,1) : gray-scale 1
The S1D15E05 series provides both 4 gray-scale display
and binary display. It incorporates a display data RAM
(132 × 160 × 2 bits). In the case of 4 gray-scale display,
2 bits of the on-chip RAM respond to one-dot pixels,
while in the case of binary display, 1 bit of the on-chip
RAM respond to one-dot pixels.
(0,0) : gray-scale 0, white
• Binary display
(Normally white display is in normal mode)
RAM bit data
“1” : On and black
“0” : Off and white
The S1D15E05 series features 132 common output
circuits and 160 segment output circuits. A single chip
provides a display of 10 characters by 8 lines with 132
× 160 dots (16 × 16 dots) and display of 13 characters by
11 lines by the 12 × 12 dot-character font.
Display data RAM read/write operations do not require
operation clock from outside, thereby ensuring operation
with the minimum current consumption. Furthermore,
it incorporates a LCD-drive power supply characterized
by low power consumption and a CR oscillator circuit
for display clock; therefore, the display system of a
handy and high-performance instrument can be realized
by use of the minimum current consumption and
minimum chip configuration.
• RAM capacity
132 × 160 × 2 = 42,240 bits
• Liquid crystal drive circuit
132 common outputs and 160 segment outputs
• High-speed 8-bit MPU interface (directly connectable
to the MPUs of both 80/68 series) /serial interface
possible
• A variety of command functions
Area scroll display, partial display, n-line reversal,
display data RAM address control, contrast control,
display ON/OFF, display normal/reverse rotation,
display all lighting ON/OFF, liquid crystal drive
power supply circuit control, display clock built-in
oscillator circuit control
• Lower power MLS drive technology
Built-in high precision voltage regulation function
• High precision CR oscillator circuit incorporated
• Very low power consumption
• Power supply
Logic power supply: VDD – VSS = 1.7 to 3.6 V
Liquid crystal drive power supply: V2 – VSS = 3.4 V
to 14.0 V (S1D15E05), V3 – VSS = 3.4 to 14.0 V
(S1D15E06)
• Wide operation temperature range: –40 to 85°C
• CMOS process
• Shipping form : Bare chips, TCP
• Light and radiation proof measures are not taken in
designing.
Series specifications
Product name
Bias
Duty (Max.) Form of shipping Chip thickness
S1D15E05D00B
S1D15E05D00E
S1D15E05T00A
1/4
1/4
1/4
1/7
1/7
1/7
1/100
1/100
1/100
1/132
1/132
1/132
Bare chip
Bare chip
TCP
Bare chip
Bare chip
TCP
0.400mm
0.625mm
–
0.400mm
0.625mm
–
*
*
*
S1D15E06D00B
*
S1D15E06D00E
S1D15E06T00A
*
*
Rev. 1.3
EPSON
1
S1D15E05 Series
3. BLOCK DIAGRAM
3.1 S1D15E05D00B
*
• • • • • • • • • • • • • • • • • • • •
• • • • • • • • • • • • • • • • •
VDD
VSS
V2
V
1
SEG Drivers
COM Drivers
VC
MV1
MV2
(VSS)
Decode circuit
CAP1+
CAP1–
CAP2+
CAP2–
Display data latch circuit
FR
CA
F1
VOUT
CAP3+
CAP3–
CAP4+
CAP4–
CPP+
Display data RAM
160 x 132 x 2
F2
CL
DOF
M/S
CPP–
CPM+
CPM–
Column address
CLS
Bus holder
Command decoder
Status
MPU Interface
2
EPSON
Rev. 1.3
S1D15E05 Series
3.2 S1D15E06D00B
*
V
DD
SS
V
V
3
V
V
2
1
V
C
SEG Drivers
COM Drivers
MV
MV
1
2
MV3 (VSS)
Decode circuit
Display data latch circuit
CAP1+
CAP1–
CAP2+
CAP2–
FR
CA
F1
Display data RAM
160 x 132 x 2
V
OUT
F2
CAP3+
CAP3–
CAP4+
CAP4–
CL
DOF
M/S
Column address
CLS
Bus holder
Command decoder
Status
MPU Interface
Rev. 1.3
EPSON
3
S1D15E05 Series
4. PIN ASSIGNMENT
4.1 Chip Assignment
98
1
99
412
345
D15E5D0B
Die No.
S1D15E05 Series
(0, 0)
166
167
344
* Die No. is D15E6D1B for S1D15E06D00B .
*
Size
Unit
Item
X
Y
Chip size
Chip thickness
Bump pitch
10.26
×
3.98
mm
mm
µm
0.4/0.625
50 (Min.)
Bump size PAD No.1 to 98
70
116
61
×
×
×
×
92
33
61
116
µm
µm
µm
µm
PAD No.99 to 166, 345 to 412
PAD No.167 to 175, 336 to 344
PAD No.176 to 335
33
Bump height
22.5 (Typ.)
µm
4.2 Alignment mark
Alignment coordinate
1(–4761.4, 1830.0) µm
2( 4926.0, –1819.1) µm
Mark size
b
a
a = 80 µm
b = 20 µm
4
EPSON
Rev. 1.3
S1D15E05 Series
4.3 Pad Center Coordinates
4.3.1 S1D15E05D00B
*
Unit: µm
PAD
No.
1
2
3
4
5
6
7
Pin
Name
NC
PAD
No.
51
Pin
Name
D4
PAD
No.
Pin
Name
X
Y
X
Y
X
Y
4494 1830
4402
–170 1830
–262
101 COM64 –4958 1575
NC
52
D5
102 COM63
103 COM62
104 COM61
105 COM60
106 COM59
107 COM58
108 COM57
109 COM56
110 COM55
111 COM54
112 COM53
113 COM52
114 COM51
115 COM50
116 COM49
117 COM48
118 COM47
119 COM46
120 COM45
121 COM44
122 COM43
123 COM42
124 COM41
125 COM40
126 COM39
127 COM38
128 COM37
129 COM36
130 COM35
131 COM34
132 COM33
133 COM32
134 COM31
135 COM30
136 COM29
137 COM28
138 COM27
139 COM26
140 COM25
141 COM24
142 COM23
143 COM22
144 COM21
145 COM20
146 COM19
147 COM18
148 COM17
149 COM16
150 COM15
1525
1475
1425
1375
1325
1275
1225
1175
1125
1075
1025
975
925
875
825
775
725
675
625
575
525
475
425
375
325
275
225
175
125
75
25
–25
TEST0 4310
TEST1 4218
TEST2 4126
TEST3 4034
TEST4 3942
TEST5 3850
53 D6, SCL –354
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
D7, SI
VSS
VSS
VSS
VDD
VDD
VDD
VOUT
VOUT
CAP1+ –1274
CAP1+ –1366
CAP1– –1458
CAP1– –1550
CAP2– –1642
CAP2– –1734
CAP2+ –1826
CAP2+ –1918
CAP3+ –2010
CAP3+ –2102
CAP3– –2194
CAP3– –2286
CAP4– –2378
CAP4– –2470
CAP4+ –2562
CAP4+ –2654
–446
–538
–630
–722
–814
–906
–998
–1090
–1182
8
9
VSS
3742
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
TEST6 3634
TEST7 3542
TEST8 3450
TEST9 3358
TEST10 3266
TEST11 3174
TEST12 3082
TEST13 2990
TEST14 2898
TEST15 2806
TEST16 2714
TEST17 2622
TEST18 2530
VSS
FR
CL
DOF
F1
2422
2314
2222
2130
2038
1946
1854
1762
1670
1578
1486
1394
F2
CA
V2
V2
V2
V2
V1
V1
VC
VC
–2746
–2838
–2930
–3022
–3114
–3206
–3298
–3390
–3482
–3574
–3666
–3758
–3850
–3942
VSS
TEST
CS1
RES
A0
–75
35 WR, R/W 1302
–125
–175
–225
–275
–325
–375
–425
–475
–525
–575
–625
–675
–725
–775
–825
–875
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
RD, E
CS2
VDD
M/S
VSS
CLS
VDD
C86
VSS
P/S
VDD
D0
1210
1118
1026
934
842
750
658
566
474
382
290
198
106
14
MV1
MV1
MV2
MV2
MV2
MV2
CPP+ –4034
CPP– –4126
CPM+ –4218
CPM– –4310
NC
NC
NC
–4402
–4494
–4958 1675
D1
D2
D3
–78
100 COM65
1625
Rev. 1.3
EPSON
5
S1D15E05 Series
Unit: µm
PAD
No.
Pin
Name
PAD
No.
Pin
Name
PAD
No.
Pin
Name
X
Y
X
Y
X
Y
151 COM14 –4958 –925
201 SEG25 –2725 –1818
202 SEG26 –2675
203 SEG27 –2625
204 SEG28 –2575
205 SEG29 –2525
206 SEG30 –2475
207 SEG31 –2425
208 SEG32 –2375
209 SEG33 –2325
210 SEG34 –2275
211 SEG35 –2225
212 SEG36 –2175
213 SEG37 –2125
214 SEG38 –2075
215 SEG39 –2025
216 SEG40 –1975
217 SEG41 –1925
218 SEG42 –1875
219 SEG43 –1825
220 SEG44 –1775
221 SEG45 –1725
222 SEG46 –1675
223 SEG47 –1625
224 SEG48 –1575
225 SEG49 –1525
226 SEG50 –1475
227 SEG51 –1425
228 SEG52 –1375
229 SEG53 –1325
230 SEG54 –1275
231 SEG55 –1225
232 SEG56 –1175
233 SEG57 –1125
234 SEG58 –1075
235 SEG59 –1025
236 SEG60 –975
237 SEG61 –925
238 SEG62 –875
239 SEG63 –825
240 SEG64 –775
241 SEG65 –725
242 SEG66 –675
243 SEG67 –625
244 SEG68 –575
245 SEG69 –525
246 SEG70 –475
247 SEG71 –425
248 SEG72 –375
249 SEG73 –325
250 SEG74 –275
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
SEG75 –225 –1818
SEG76 –175
SEG77 –125
152 COM13
153 COM12
154 COM11
155 COM10
–975
–1025
–1075
–1125
–1175
–1225
–1275
–1325
–1375
–1425
–1475
–1525
–1575
–1625
–1675
–4704 –1846
–4621
–4539
–4456
–4374
–4291
–4209
–4126
–4044
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
–75
–25
25
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
NC
NC
NC
NC
NC
NC
NC
NC
NC
75
125
175
225
275
325
375
425
475
525
575
625
675
725
775
825
875
925
975
NC
SEG0 –3975 –1818
SEG1 –3925
SEG2 –3875
SEG3 –3825
SEG4 –3775
SEG5 –3725
SEG6 –3675
SEG7 –3625
SEG8 –3575
SEG9 –3525
276 SEG100 1025
277 SEG101 1075
278 SEG102 1125
279 SEG103 1175
280 SEG104 1225
281 SEG105 1275
282 SEG106 1325
283 SEG107 1375
284 SEG108 1425
285 SEG109 1475
286 SEG110 1525
287 SEG111 1575
288 SEG112 1625
289 SEG113 1675
290 SEG114 1725
291 SEG115 1775
292 SEG116 1825
293 SEG117 1875
294 SEG118 1925
295 SEG119 1975
296 SEG120 2025
297 SEG121 2075
298 SEG122 2125
299 SEG123 2175
300 SEG124 2225
186 SEG10 –3475
187 SEG11 –3425
188 SEG12 –3375
189 SEG13 –3325
190 SEG14 –3275
191 SEG15 –3225
192 SEG16 –3175
193 SEG17 –3125
194 SEG18 –3075
195 SEG19 –3025
196 SEG20 –2975
197 SEG21 –2925
198 SEG22 –2875
199 SEG23 –2825
200 SEG24 –2775
6
EPSON
Rev. 1.3
S1D15E05 Series
Unit: µm
PAD
No.
Pin
Name
PAD
No.
Pin
Name
PAD
No.
Pin
Name
X
Y
X
Y
X
Y
301 SEG125 2275 –1818
302 SEG126 2325
303 SEG127 2375
304 SEG128 2425
305 SEG129 2475
306 SEG130 2525
307 SEG131 2575
308 SEG132 2625
309 SEG133 2675
310 SEG134 2725
311 SEG135 2775
312 SEG136 2825
313 SEG137 2875
314 SEG138 2925
315 SEG139 2975
316 SEG140 3025
317 SEG141 3075
318 SEG142 3125
319 SEG143 3175
320 SEG144 3225
321 SEG145 3275
322 SEG146 3325
323 SEG147 3375
324 SEG148 3425
325 SEG149 3475
326 SEG150 3525
327 SEG151 3575
328 SEG152 3625
329 SEG153 3675
330 SEG154 3725
331 SEG155 3775
332 SEG156 3825
333 SEG157 3875
334 SEG158 3925
335 SEG159 3975
351 COM71 4958 –1375
401 COM121 4958 1125
352 COM72
353 COM73
354 COM74
355 COM75
356 COM76
357 COM77
358 COM78
359 COM79
360 COM80
361 COM81
362 COM82
363 COM83
364 COM84
365 COM85
366 COM86
367 COM87
368 COM88
369 COM89
370 COM90
371 COM91
372 COM92
373 COM93
374 COM94
375 COM95
376 COM96
377 COM97
378 COM98
379 COM99
380 COM100
381 COM101
382 COM102
383 COM103
384 COM104
385 COM105
386 COM106
387 COM107
388 COM108
389 COM109
390 COM110
391 COM111
392 COM112
393 COM113
394 COM114
395 COM115
396 COM116
397 COM117
398 COM118
399 COM119
400 COM120
–1325
–1275
–1225
–1175
–1125
–1075
–1025
–975
–925
–875
–825
–775
–725
–675
–625
–575
–525
–475
–425
–375
–325
–275
–225
–175
–125
–75
–25
25
75
125
175
225
275
325
375
425
475
525
575
625
675
725
402 COM122
403 COM123
404 COM124
405 COM125
406 COM126
407 COM127
408 COM128
409 COM129
410 COM130
411 COM131
1175
1225
1275
1325
1375
1425
1475
1525
1575
1625
1675
412
NC
336
337
338
339
340
341
342
343
344
345
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
4044 –1846
4126
4209
4291
4374
4456
4539
4621
4704
775
825
875
925
975
1025
1075
4958 –1675
–1625
–1575
–1525
–1475
–1425
346 COM66
347 COM67
348 COM68
349 COM69
350 COM70
Rev. 1.3
EPSON
7
S1D15E05 Series
4.3.2 S1D15E06D00B
*
Unit: µm
PAD
No.
1
2
3
4
5
6
7
Pin
Name
NC
PAD
No.
51
Pin
Name
D4
PAD
No.
Pin
Name
X
Y
X
Y
X
Y
4494 1830
4402
–170 1830
–262
101 COM64 –4958 1575
NC
52
D5
102 COM63
103 COM62
104 COM61
105 COM60
106 COM59
107 COM58
108 COM57
109 COM56
110 COM55
111 COM54
112 COM53
113 COM52
114 COM51
115 COM50
116 COM49
117 COM48
118 COM47
119 COM46
120 COM45
121 COM44
122 COM43
123 COM42
124 COM41
125 COM40
126 COM39
127 COM38
128 COM37
129 COM36
130 COM35
131 COM34
132 COM33
133 COM32
134 COM31
135 COM30
136 COM29
137 COM28
138 COM27
139 COM26
140 COM25
141 COM24
142 COM23
143 COM22
144 COM21
145 COM20
146 COM19
147 COM18
148 COM17
149 COM16
150 COM15
1525
1475
1425
1375
1325
1275
1225
1175
1125
1075
1025
975
925
875
825
775
725
675
625
575
525
475
425
375
325
275
225
175
125
75
25
–25
TEST0 4310
TEST1 4218
TEST2 4126
TEST3 4034
TEST4 3942
TEST5 3850
53 D6, SCL –354
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
D7, SI
VSS
VSS
VSS
VDD
VDD
VDD
VOUT
VOUT
CAP1+ –1274
CAP1+ –1366
CAP1– –1458
CAP1– –1550
CAP2– –1642
CAP2– –1734
CAP2+ –1826
CAP2+ –1918
CAP3+ –2010
CAP3+ –2102
CAP3– –2194
CAP3– –2286
CAP4– –2378
CAP4– –2470
CAP4+ –2562
CAP4+ –2654
–446
–538
–630
–722
–814
–906
–998
–1090
–1182
8
9
VSS
3742
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
TEST6 3634
TEST7 3542
TEST8 3450
TEST9 3358
TEST10 3266
TEST11 3174
TEST12 3082
TEST13 2990
TEST14 2898
TEST15 2806
TEST16 2714
TEST17 2622
TEST18 2530
VSS
FR
CL
DOF
F1
2422
2314
2222
2130
2038
1946
1854
1762
1670
1578
1486
1394
F2
CA
V3
V3
V2
V2
V1
V1
VC
VC
–2746
–2838
–2930
–3022
–3114
–3206
–3298
–3390
–3482
–3574
–3666
–3758
–3850
–3942
VSS
TEST
CS1
RES
A0
–75
35 WR, R/W 1302
–125
–175
–225
–275
–325
–375
–425
–475
–525
–575
–625
–675
–725
–775
–825
–875
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
RD, E
CS2
VDD
M/S
VSS
CLS
VDD
C86
VSS
P/S
VDD
D0
1210
1118
1026
934
842
750
658
566
474
382
290
198
106
14
MV1
MV1
MV2
MV2
MV3
MV3
CPP+ –4034
CPP– –4126
CPM+ –4218
CPM– –4310
NC
NC
NC
–4402
–4494
–4958 1675
D1
D2
D3
–78
100 COM65
1625
8
EPSON
Rev. 1.3
S1D15E05 Series
Unit: µm
PAD
No.
Pin
Name
PAD
No.
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
Pin
Name
PAD
No.
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
Pin
Name
SEG75 –225 –1818
SEG76 –175
SEG77 –125
X
Y
X
Y
X
Y
151 COM14 –4958 –925
SEG25 –2725 –1818
SEG26 –2675
SEG27 –2625
SEG28 –2575
SEG29 –2525
SEG30 –2475
SEG31 –2425
SEG32 –2375
SEG33 –2325
SEG34 –2275
SEG35 –2225
SEG36 –2175
SEG37 –2125
SEG38 –2075
SEG39 –2025
SEG40 –1975
SEG41 –1925
SEG42 –1875
SEG43 –1825
SEG44 –1775
SEG45 –1725
SEG46 –1675
SEG47 –1625
SEG48 –1575
SEG49 –1525
SEG50 –1475
SEG51 –1425
SEG52 –1375
SEG53 –1325
SEG54 –1275
SEG55 –1225
SEG56 –1175
SEG57 –1125
SEG58 –1075
SEG59 –1025
SEG60 –975
SEG61 –925
SEG62 –875
SEG63 –825
SEG64 –775
SEG65 –725
SEG66 –675
SEG67 –625
SEG68 –575
SEG69 –525
SEG70 –475
SEG71 –425
SEG72 –375
SEG73 –325
SEG74 –275
152 COM13
153 COM12
154 COM11
155 COM10
–975
–1025
–1075
–1125
–1175
–1225
–1275
–1325
–1375
–1425
–1475
–1525
–1575
–1625
–1675
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
–75
–25
25
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
NC
NC
NC
NC
NC
NC
NC
NC
NC
75
125
175
225
275
325
375
425
475
525
575
625
675
725
775
825
875
925
975
–4704 –1846
–4621
–4539
–4456
–4374
–4291
–4209
–4126
–4044
NC
SEG0 –3975 –1818
SEG1 –3925
SEG2 –3875
SEG3 –3825
SEG4 –3775
SEG5 –3725
SEG6 –3675
SEG7 –3625
SEG8 –3575
SEG9 –3525
276 SEG100 1025
277 SEG101 1075
278 SEG102 1125
279 SEG103 1175
280 SEG104 1225
281 SEG105 1275
282 SEG106 1325
283 SEG107 1375
284 SEG108 1425
285 SEG109 1475
286 SEG110 1525
287 SEG111 1575
288 SEG112 1625
289 SEG113 1675
290 SEG114 1725
291 SEG115 1775
292 SEG116 1825
293 SEG117 1875
294 SEG118 1925
295 SEG119 1975
296 SEG120 2025
297 SEG121 2075
298 SEG122 2125
299 SEG123 2175
300 SEG124 2225
186 SEG10 –3475
187 SEG11 –3425
188 SEG12 –3375
189 SEG13 –3325
190 SEG14 –3275
191 SEG15 –3225
192 SEG16 –3175
193 SEG17 –3125
194 SEG18 –3075
195 SEG19 –3025
196 SEG20 –2975
197 SEG21 –2925
198 SEG22 –2875
199 SEG23 –2825
200 SEG24 –2775
Rev. 1.3
EPSON
9
S1D15E05 Series
Unit: µm
PAD
No.
Pin
Name
PAD
No.
Pin
Name
PAD
No.
Pin
Name
X
Y
X
Y
X
Y
301 SEG125 2275 –1818
302 SEG126 2325
303 SEG127 2375
304 SEG128 2425
305 SEG129 2475
306 SEG130 2525
307 SEG131 2575
308 SEG132 2625
309 SEG133 2675
310 SEG134 2725
311 SEG135 2775
312 SEG136 2825
313 SEG137 2875
314 SEG138 2925
315 SEG139 2975
316 SEG140 3025
317 SEG141 3075
318 SEG142 3125
319 SEG143 3175
320 SEG144 3225
321 SEG145 3275
322 SEG146 3325
323 SEG147 3375
324 SEG148 3425
325 SEG149 3475
326 SEG150 3525
327 SEG151 3575
328 SEG152 3625
329 SEG153 3675
330 SEG154 3725
331 SEG155 3775
332 SEG156 3825
333 SEG157 3875
334 SEG158 3925
335 SEG159 3975
351 COM71 4958 –1375
401 COM121 4958 1125
352 COM72
353 COM73
354 COM74
355 COM75
356 COM76
357 COM77
358 COM78
359 COM79
360 COM80
361 COM81
362 COM82
363 COM83
364 COM84
365 COM85
366 COM86
367 COM87
368 COM88
369 COM89
370 COM90
371 COM91
372 COM92
373 COM93
374 COM94
375 COM95
376 COM96
377 COM97
378 COM98
379 COM99
380 COM100
381 COM101
382 COM102
383 COM103
384 COM104
385 COM105
386 COM106
387 COM107
388 COM108
389 COM109
390 COM110
391 COM111
392 COM112
393 COM113
394 COM114
395 COM115
396 COM116
397 COM117
398 COM118
399 COM119
400 COM120
–1325
–1275
–1225
–1175
–1125
–1075
–1025
–975
–925
–875
–825
–775
–725
–675
–625
–575
–525
–475
–425
–375
–325
–275
–225
–175
–125
–75
–25
25
75
125
175
225
275
325
375
425
475
525
575
625
675
725
402 COM122
403 COM123
404 COM124
405 COM125
406 COM126
407 COM127
408 COM128
409 COM129
410 COM130
411 COM131
1175
1225
1275
1325
1375
1425
1475
1525
1575
1625
1675
412
NC
336
337
338
339
340
341
342
343
344
345
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
4044 –1846
4126
4209
4291
4374
4456
4539
4621
4704
775
825
875
925
975
1025
1075
4958 –1675
–1625
–1575
–1525
–1475
–1425
346 COM66
347 COM67
348 COM68
349 COM69
350 COM70
10
EPSON
Rev. 1.3
S1D15E05 Series
5. PIN DESCRIPTION
5.1 Power Pin
5.1.1 S1D15E05D00B
*
Number of
pins
Pin name
I/O
Description
VDD
Power Connect to MPU power pin VCC.
supply
6
VSS
Power Connect to system GND.
supply It connected to MV2 inside.
8
V2, V1, VC Power A liquid crystal drive multi-level power supply. The voltages
MV1, MV2 supply determined by the liquid crystal cell are impedance-converted
14
(V2, MV2,
4 each,
V1, MV1,
2 each)
(=VSS)
by resistive divider and operational amplifier for application.
The following order must be maintained:
V2 ≥ V1 ≥ VC ≥ MV1 ≥ MV2 (=VSS)
Master operation: When power supply is turned on, the following
voltage is applied to each pin by the built-in power supply circuit.
MV2 is connected to VSS inside the IC chip.
V1
VC
MV1
3/4 • V2
2/4 • V2
1/4 • V2
5.1.2 S1D15E06D00B
*
Number of
pins
Pin name
I/O
Description
VDD
Power Connect to system MPU power supply pin VCC.
supply
6
VSS
Power Connect to the system GND.
supply MV3 is short circuited with MV3 inside the IC chip.
8
V3, V2, V1, Power A liquid crystal drive multi-level power supply. The voltages
14
(2 each)
VC, MV1,
MV2, MV3,
(=VSS)
supply determined by the liquid crystal cell are impedance-converted by
resistive divider and operational amplifier for application.
The following order must be maintained:
V3 ≥ V2 ≥ V1 ≥ VC ≥ MV1 ≥ MV2 ≥ MV3 (=VSS)
Master operation: When power supply is turned on, the following
voltage is applied to each pin by the built-in power supply circuit.
MV3 is connected to with VSS inside the IC chip.
V2
V1
VC
MV1
MV2
11/14 • V3
9/14 • V3
7/14 • V3
5/14 • V3
3/14 • V3
Rev. 1.3
EPSON
11
S1D15E05 Series
5.2 LCD Power Supply Circuit Pin
5.2.1 S1D15E05D00B
*
Number of
pins
Pin name
I/O
Description
CAP1+
O
Pin connected to the positive side of the step-up capacitor.
2
2
2
2
2
2
2
2
2
1
1
1
1
Connect the capacitor between this pin and CAP1– pin.
CAP1–
CAP2+
CAP2–
VOUT
O
O
O
O
O
O
O
O
O
O
O
O
Pin connected to the negative side of the step-up capacitor.
Connect the capacitor between this pin and CAP1+ pin.
Pin connected to the positive side of the step-up capacitor.
Connect the capacitor between this pin and CAP2– pin.
Pin connected to the negative side of the step-up capacitor.
Connect the capacitor between this pin and CAP2+ pin.
Output pin for step-up.
Connect the capacitor between this pin and VDD.
Pin connected to the positive side of the step-up capacitor.
Connect the capacitor between this pin and CAP3– pin.
Pin connected to the negative side of the step-up capacitor.
Connect the capacitor between this pin and CAP3+ pin.
Pin connected to the positive side of the step-up capacitor.
Connect the capacitor between this pin and CAP4– pin.
Pin connected to the negative side of the step-up capacitor.
Connect the capacitor between this pin and CAP4+ pin.
Pin connected to the positive side of the step-down capacitor.
Connect the capacitor between this pin and CPP– pin.
Pin connected to the negative side of the step-down capacitor.
Connect the capacitor between this pin and CPP+ pin.
Pin connected to the positive side of the step-down capacitor.
Connect the capacitor between this pin and CMP– pin.
Pin connected to the negative side of the step-down capacitor.
Connect the capacitor between this pin and CMP+ pin.
CAP3+
CAP3–
CAP4+
CAP4–
CPP+
CPP–
CPM+
CPM–
5.2.2 S1D15E06D00B
*
Number of
pins
Pin name
I/O
Description
CAP1+
O
Pin connected to the positive side of the step-up capacitor.
2
2
2
2
2
2
2
2
2
Connect the capacitor between this pin and CAP1– pin.
CAP1–
CAP2+
CAP2–
VOUT
O
O
O
O
O
O
O
O
Pin connected to the negative side of the step-up capacitor.
Connect the capacitor between this pin and CAP1+ pin.
Pin connected to the positive side of the step-up capacitor.
Connect the capacitor between this pin and CAP2– pin.
Pin connected to the negative side of the step-up capacitor.
Connect the capacitor between this pin and CAP2+ pin.
Output pin for step-up.
Connect the capacitor between this pin and VDD.
Pin connected to the positive side of the step-up capacitor.
Connect the capacitor between this pin and CAP3– pin.
Pin connected to the negative side of the step-up capacitor.
Connect the capacitor between this pin and CAP3+ pin.
Pin connected to the positive side of the step-up capacitor.
Connect the capacitor between this pin and CAP4– pin.
Pin connected to the negative side of the step-up capacitor.
Connect the capacitor between this pin and CAP4+ pin.
CAP3+
CAP3–
CAP4+
CAP4–
CPP+
CPP–
CPM+
CPM–
O
O
O
O
Keep it open.
Keep it open.
Keep it open.
Keep it open.
1
1
1
1
12
EPSON
Rev. 1.3
S1D15E05 Series
5.3 System Bus Connection Pin
Number of
pins
Pin name
I/O
Description
D7 to D0
I/O
Connects to the 8-bit or 16-bit MPU data bus via the 8-bit
bi-directional data bus.
8
(SI)
(SCL)
When the serial interface is selected (P/S = LOW), D7 serves as the
serial data input (SI) and D6 serves as the serial clock input (SCL),
In this case, D0 through D5 go to a high impedance state. When the
Chip select is inactive, D0 through D7 go to a high impedance state.
A0
I
Normally, the least significant bit MPU address bus is connected
to distinguish between data and command.
1
A0 = HIGH : indicates that D0 to D7 are display data or command parameters.
A0 = LOW : indicates that D0 to D7 are control commands.
RES
I
I
I
When the RES is LOW, initialization is achieved.
Resetting operation is done on the level of the RES signal.
1
2
1
CS1
CS2
A chip select signal. When CS1 = LOW and CS2 = HIGH, signals
are active, and data/command input/output are enabled.
RD
(E)
• When the 80 series MPU is connected.
A pin for connection of the RD signal of the 80 series MPU.
When this signal is LOW, the data bus of the S1D15E05 series
is in the output state.
• When the 68 series MPU is connected.
Serves as a 68 series MPU enable clock input pin.
WR
(R/W)
I
• When the 80 series MPU is connected.
A pin for connection of the WR signal of the 80 series MPU.
Signals on the data bus are latched at the leading edge of the
WR signal.
1
• Serves as a read/write control signal input pin when the 68 series
MPU is connected.
R/W = HIGH : Read
R/W = LOW : Write
C86
P/S
I
I
A MPU interface switching pin.
1
1
C86 = HIGH : 68 series MPU interface
C86 = LOW : 80 series MPU interface
Parallel data input/serial data input select pin
P/S = HIGH : Parallel data input
P/S = LOW : Serial data input
The following Table shows the summary:
P/S Data/Command
Data
Read/Write Serial clock
HIGH
LOW
A0
A0
D0 to D7
SI (D7)
RD, WR
Write only
SCL (D6)
When P/S = LOW, D0 to D5 are high impedance.
D0 to D5 can be HIGH, LOW or open.
RD(E) and WR(R/W) are locked to HIGH or LOW.
The serial data input does not allow the RAM display data to be read.
Rev. 1.3
EPSON
13
S1D15E05 Series
Number of
pins
Pin name
I/O
Description
CLS
I
A pin used to select Enable/Disable state of the built-in oscillator
circuit for display clock.
1
CLS = HIGH : Built-in oscillator circuit Enabled
CLS = LOW : Built-in oscillator circuit Disabled (External input)
When CLS is LOW, display clock is input from the CL pin. When
the S1D15E05 series is used in the master/slave mode, each CLS
pins must be set to the same level.
Display clock
Built-in oscillator circuit used
External input
Master
HIGH
LOW
Slave
HIGH
LOW
M/S
I
A pin used to select the master/slave operation for S1D15E05 series.
Liquid crystal display system is synchronized when the master
operation outputs the timing signal required for liquid crystal
display, while the slave operation inputs the timing signal required
for liquid crystal display.
1
M/S = HIGH : Master operation
M/S = LOW : Slave operation
The following Table shows the relation in conformance to the M/S and CLS:
Oscillation
circuit
Power
circuit
FR, DOF,
F1, F2, CA
M/S CLS
CL
HIGH
HIGH
Enabled
Disabled
Enabled
Enabled
Output
Input
Output
Output
LOW
HIGH Disabled
Disabled
Disabled
Input
Input
Input
Input
LOW
LOW
Disabled
The slave power supply circuit can also operate, but do not use it.
CL
I/O
Display clock input/output pin.
The following Table shows the relation in conformance to the M/S and CLS state:
1
M/S CLS
CL
HIGH Output
HIGH
LOW
LOW
Input
HIGH
LOW
Input
Input
When you want to use the S1D15E05 series in the master/slave
mode, connect each CL pin.
FR
I/O
I/O
I/O
A liquid crystal alternating current input/output pin.
M/S = HIGH : Output
M/S = LOW : Input
When you want to use the S1D15E05 series in the master/slave
mode, connect each FR pin.
1
F1, F2,
CA
A liquid crystal sync signal input/output pin.
M/S = HIGH : Output
M/S = LOW : Input
When you want to use the S1D15E05 series in the master/slave
mode, connect each F1, F2 and CA pins.
3
(1 each)
DOF
A liquid crystal blanking control pin.
M/S = HIGH : Output
1
M/S = LOW : Input
When you want to use the S1D15E05 series in the master/slave
mode, connect each DOF pin.
14
EPSON
Rev. 1.3
S1D15E05 Series
5.4 Liquid crystal drive pin
5.4.1 S1D15E05D00B
*
Number of
pins
Pin name
I/O
Description
SEG0 to
SEG159
O
Liquid crystal segment drive output pins. One of the V2, V1, VC,
MV1, and MV2 (VSS) levels is selected by a combination of the
display RAM content and FR/F1/F2 signals.
160
COM0 to
COM131
O
Liquid crystal common drive output pins. One of the V2, VC,
MV2 (VSS) levels is selected by a combination of the scan data
and FR/F1/F2 signals.
132
5.4.2 S1D15E6D00B
*
Number of
pins
Pin name
I/O
Description
SEG0 to
SEG159
O
Liquid crystal segment drive output pins. One of the V2, V1, VC,
MV1, and MV2 levels is selected by a combination of the display
RAM content and FR/F1/F2 signals.
160
COM0 to
COM131
O
Liquid crystal common drive output pins. One of the V3, VC,
MV3 (VSS) levels is selected by a combination of the scan data
and FR/F1/F2 signals.
132
5.5 Test pins
Number of
pins
Pin name
I/O
Description
TEST,
I
IC chip test pins. Lock them to LOW.
5
TEST2 to 5
TEST0, 1,
6 to 18
I/O
IC chip test pins. Open them and make sure that the capacity is not
consumed by wiring, etc.
15
Rev. 1.3
EPSON
15
S1D15E05 Series
6. FUNCTIONAL DESCRIPTION
6.1 MPU Interface
6.1.1 Selection of Interface Type
S1D15E05 series allows data to be sent via the 8-bit bi-directional data buses (D7 to D0) or serial data input (SI). By
setting the polarity of the P/S pin to HIGH or LOW, you can select either 8-bit parallel data input or serial data input,
as shown in Table 6.1.
Table 6.1
P/S
CS1
CS2
CS2
CS2
A0
A0
A0
RD
RD
—
WR
WR
—
C86
C86
—
D7
D7
SI
D6
D6
D5 to D0
D5 to D0
(HZ)
HIGH : Parallel input CS1
LOW : Serial input CS1
SCL
—: Fixed to HIGH or LOW HZ: High impedance state
6.1.2 parallel interface
When the parallel interface is selected (P/S = HIGH), direction connection to the MPU bus of either 80 series MPU or
68 series MPU is performed by setting the 86 pin to either HIGH or LOW, as shown in Table 6.2.
Table 6.2
P/S
CS1
CS1
CS1
CS2
CS2
CS2
A0
A0
A0
RD
E
WR
R/W
WR
D7 to D0
D7 to D0
D7 to D0
HIGH : 68 series MPU bus
LOW : 80 series MPU bus
RD
The data bus signals are identified by a combination of A0, RD (E), and WR (R/W) signals as shown in Table 6.3.
Table 6.3
Common 68 series
80 series
WR
Function
A0
1
R/W
RD
0
1
0
1
1
0
0
Display data read, status read
Display data write, command parameter write
Command write
1
1
0
1
6.1.3 Serial interface
When the serial interface is selected (P/S =LOW), the chip is active (CS1 = LOW, CS2 = HIGH), and reception of serial
data input (SI) and serial clock input (SCL) is enabled. Serial interface comprises a 8-bit shift register and 3-bit counter.
The serial data are latched by the rising edge of serial clock signals in the order of D7, D6, .... and D0 starting from the
serial data input pin. On the rising edge of 8th serial clock signal, they are converted into 8-bit parallel data to be
processed.
Whether serial data input is a display data or command is identified by A0 input. A0 = HIGH indicates display data,
while A0 = LOW shows command data. The A0 input is read and identified at every 8 × n-th rising edge of the serial
clock after the chip has turned active.
Fig. 6.1 shows the serial interface signal chart.
16
EPSON
Rev. 1.3
S1D15E05 Series
CS1
CS2
SI
D7
1
D6
2
D5
3
D4
4
D3
5
D2
6
D1
7
D0 D7
D6
10
D5
D4
D3
13
D2
14
SCL
8
9
11
12
A0
Fig. 6.1
* When the chip is inactive, the counter is reset to the initials state.
* Reading is not performed in the case of serial interface.
* For the SCL signal, a sufficient care must be taken against terminal reflection of the wiring and external noise.
Recommend to use an actual equipment to verify the operation.
processing via the bus holder accompanying the internal
data bus.
For example, when data is written to the display data
RAM by the MPU, the data is once held by the bus
holder. It is written to the display data RAM before the
next data write cycle comes.
On the other hand, when the MPU reads the content of
the display data RAM, it is read in the first data read
cycle (dummy), and the data is held in the bus holder.
Then it is read onto on the system bus from the bus
holder in the next data read cycle. Restrictions are
imposed on the display data RAM read sequence. When
the address has been set, specified address data is not
output to the Read command immediately after that.
The specified address data is output in the second data
reading. This must be carefully noted. Therefore, one
dummy read operation is mandatory subsequent to
address setting or write cycle. Fig. 6.2 illustrates this
relationship.
6.1.4 Chip Selection
The S1D15E05 series has two chip select pins; CS1 and
CS2. MPU interface or serial interface is enabled only
when CS1 = LOW and CS2 = HIGH.
When the chip select pin is inactive, D0 to D5 are in the
state of high impedance, while A0, RD and WR inputs
are disabled. When serial interface is selected, the shift
register and counter are reset.
6.1.5 Access to display data RAM and
internal register
Access to S1D15E05 series viewed from the MPU side
is enabled only if the cycle time requirements are kept.
This does not required waiting time; hence, high-speed
data transfer is allowed.
Furthermore, at the time of data transfer with the MPU,
S1D15E05 series provides a kind of inter-LSI pipe line
Rev. 1.3
EPSON
17
S1D15E05 Series
Write
A0
WR
Latch
DATA
White
N
N+1
N+2
Command
N
N+1
N+2
BUS Holder
Write Signal
Read
A0
WR
RD
DATA
Read
Dumy
n
n+1
Command
Read Signal
Column Address
Preset N
Read command code
Increment N+1
n
N+2
Bus Holder
n+1
n+2
Dummy Read
Data Read
Data Read
Fig. 6.2
RAM bit data (high order and low order)
6.2 Display data RAM
6.2.1 Display Data RAM
(1,1) : gray-scale 3
Black (when display is in
normal mode)
This is a RAM to store the display dot data, and comprises
132 × 160 × 2 bits. Access to the desired bit is enabled
by specifying the page address and column address.
When the 4 gray-scale is selected by the Display Mode
command, display data input for gray-scale display are
processed as a two-bit pair. Combination is as follows:
(1,0) : gray-scale 2
(0,1) : gray-scale 1
(0,0) : gray-scale 0
White (when display is in
normal mode)
When binary display is selected by the Display Mode
command, the RAM 1 bit built in the one-dot pixel
responds to it. When the RAM bit data is “1”, the
display is black. If it is “0”, the display is given in white.
RAM bit data
(MSB, LSB) = (D1,D0), (D3,D2), (DS,D4), (D7,D6)
When the RAM bit data is gray-scale 1 and 2, gray-scale
display is realized according to the parameter of the
Gray-scale Pattern Set command.
“1” : Light On
Black (when display is in
normal mode)
“0” : Light Off
White (when display is in
normal mode)
18
EPSON
Rev. 1.3
S1D15E05 Series
Display data D7 to D0 from the MPU correspond to
LCD common direction, as shown in Fig. 6.3 and 6.4.
Therefore, less restrictions when multi-chip usage.
Furthermore, read/write operations from the MPU to
the RAM are carried out via the input/output buffer.
The read operation from Display data RAM is designed
as an independent operation. Accordingly, even if the
MPU accesses the RAM asynchronously during LCD
display, no adverse effect is given to display.
(D1,D0) (0,0) (1,1) (1,1)
(D3,D2) (1,1) (0,0) (0,0)
(D5,D4) (0,0) (1,0) (0,1)
(D7,D6) (0,0) (0,0) (0,0)
(0,0)
(0,0)
(0,0)
(0,0)
COM0
COM1
COM2
COM3
Display data RAM
LCD
Fig. 6.3 4 gray-scale
D0 0 1 1 1
D1 1 0 0 0
D2 0 0 0 0
D3 0 1 1 1
D4 1 0 0 0
0
COM0
COM1
COM2
COM3
COM4
0
0
0
0
Display data RAM
LCD
Fig. 6.4 Binary
or read operation.
6.2.2 Gray-scale display
When the column direction is selected for address
increment, the column address is increased by +1 for
every write or read operation. After the column address
has accessed up to 9FH, the page address is incremented
by +1 and the column address shifts to 0H.
When the page direction is selected for address
increment, the page address is increased with the column
address locked in position. When the page address has
accessed up to 32H, the column address is incremented
by +1, and the page address goes to 0H.
Whichever direction is selected for address increment,
the page address goes back to 0H and the column
address to 0H after access up to the column address 9FH
of page address 32H.
As shown in Fig. 6.4, relationship between the display
data RAM column address and segment output can be
reversed by the Column Address Set Direction command.
This will reduce restrictions on IC layout during LCD
module assembling.
When the 4 gray-scale is selected by the Display Mode
command, gray-scale is represented by the FRM control
carried out according to the gray-scale data written in
the display data RAM.
Of the 4 gray-scale, 2 gray-scale of halftones (gray-
scale 2 and 1) has its level of contrast specified by the
Gray-scale Set command. Gray-scale can be selected
from 6 levels of contrast.
6.2.3 Page address circuit/column address
circuit
The address of the display data RAM to be accessed is
specified by the Page Address Set command and Column
Address Set command, as shown in Fig. 6.5 and Fig. 6.6.
For Address incremental direction, either the column
direction or page direction can be selected by the Address
Direction command. Whichever direction is chosen,
increment is carried out by positive one (+1) after write
Rev. 1.3
EPSON
19
S1D15E05 Series
Table 6.4
SEG output
SEG0
SEG159
ADC “0”
0(H)→ Column Address →9F(H)
9F(H)← Column Address ←0(H)
(D0)
“1”
dynamic modification of the line address, screen scroll
and page change are enabled.
6.2.4 Line address circuit
The line address circuit specifies the line address
corresponding to COM output when the contents of the
display data RAM is displayed, as shown in Fig. 6.5 and
6.6. Normally, the top line of the display (COM0 output
in the case of normal rotation of the common output
status and COM131 output in the case of reverse rotation)
is specified by the Display Start Line Address Set
command. The display area starts from the specified
display start line address to cover the area corresponding
to the lines specified by the DUTY Set command in the
direction where the line address increments.
6.2.5 Area scroll
The display area can be divided into the display area
fixed in the COM direction and scrollable area by the
area scroll command. The scroll area is set by a scroll
mode, scroll start line address (AS), scroll end address
(AE), and scroll display line count (AL) as parameters
for the area scroll command. Display start line address
(DL) in the scroll area can be specified by the display
start line address set command.
If the display start line address set command is used for
Fixed area
Scrollable
Fixed area
Scrollable
Scrollable
Scrollable
Fixed area
Fixed area
Mode 3
Mode 0
Mode 1
Mode 2
Scroll mode
00H
Upper fixed area
Number of line : AS
AS-1
DL
Scroll area
Number of line : AL
AE+1
Lower fixed area
Number of line
Final line address
middle of reading the scroll area, the line address to be
read next will be 00H. When all the AL lines have been
read, the address to be read next will be AE + 1. When
reading is completed up to the final line address, the
control goes back to the line address DL, and parameter
AS is disabled. DL can be specified in the range from
00H to AE.
6.2.5.1 Mode 0 (full screen scroll)
This mode releases the area scroll. Parameters AS, AE
and AL are disabled,
6.2.5.2 Mode 1 (Upper scroll )
Reading starts from the line address DL to read AL lines
as a scroll area. If the line address AE is read in the
20
EPSON
Rev. 1.3
S1D15E05 Series
6.2.5.3 Mode 2 (lower scroll)
6.2.6 Display data latch circuit
Reading starts from line address 00H to reach the line
address AS-1 in the continuous reading mode. Upon
completion of reading of line address AS-1, the line
address moves to the DL to read the area corresponding
to AL lines from the line address DL as a scroll area. If
the final line address is read in the middle of reading the
scroll area, the line address to be read next will be AS.
When all AL lines have been read, the control goes back
to the line address 00H, and parameter AE is disabled.
DL can be specified in the range from AS to the final line
address.
The display data latch circuit is a latch to temporarily
latch the display data output from then display data
RAM to the liquid crystal drive circuit. Display normal/
reverse, display ON/OFF, and display all lighting ON/
OFF commands control the data in this latch, without
the data in the display data RAM being controlled.
6.2.7 Partial display
Partial display of the screen is provided by the partial
display ON/OFF command. The partial area (display
start line, number of display lines) are set by the partial
display set command.
The display start line of the parameter shows the line
assigned in the COM direction of the liquid crystal
screen. It is different from the line address given in Fig.
6.5 and 6.6.
6.2.5.4 Mode 3 (Center scroll)
Reading starts from line address 00H to reach the line
address AS-1 in the continuous reading mode.
Upon completion of reading of line address AS-1, the
line address moves to the DL to read the area
corresponding to AL lines from the line address DL as
a scroll area. If the final line address is read in the
middle of reading the scroll area, the line address to be
read next will be AS. When all AL lines have been read,
the line address will be AE+1. When up to the final line
address has been read, the control goes back to the line
address 00H, DL can be specified in the range from AS
to AE.
Example: When the point is set at 1 (COM4 to 7) by the
Duty Reset command, the display line is
assigned as shown below. If the display start
line 4 and display line count 3 are specified
by the partial display set command, the display
area is COM8 to COM10.
Display line
LCD panel
0
1
2
3
4
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
5
6
7
8
9
10
Rev. 1.3
EPSON
21
S1D15E05 Series
Common
Output state:
Normal rotation
4 gray-scale display
COM
Line
Page Address
Data
Address
Output
D5
0
D1 D0
D4 D3
D2
When the display start line is set to 11H
COM0
COM1
COM2
COM3
COM4
COM4
COM6
COM7
00H
01H
02H
03H
04H
05H
06H
07H
D1,D0
D3,D2
D5,D4
D7,D6
0
0
0
0
0
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
D1,D0
D3,D2
D5,D4
D7,D6
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
D1,D0
D3,D2
D5,D4
D7,D6
COM8
COM9
08H
09H
0AH
0BH
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
D1,D0
D3,D2
D5,D4
D7,D6
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
D1,D0
D3,D2
D5,D4
D7,D6
D1,D0
D3,D2
D5,D4
D7,D6
Start
7CH
7DH
7EH
7FH
D1,D0
D3,D2
D5,D4
D7,D6
COM124
COM125
COM126
COM127
COM128
COM129
COM130
COM131
Page 31
Page 32
1
0
1
0
0
1
1
0
1
0
1
0
80H
81H
82H
83H
D1,D0
D3,D2
D5,D4
D7,D6
Fig. 6.5 4 gray-scale
22
EPSON
Rev. 1.3
S1D15E05 Series
Binary display
Common
output state:
Normal mode
Page Address
Line
Address
COM
Output
Data
When the display start line is set to 0CH
D5 D4 D3 D2 D1 D0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
0
79H
7AH
7BH
7CH
7DH
7EH
7FH
80H
81H
82H
83H
84H
85H
86H
87H
88H
89H
8AH
8BH
8CH
8DH
8EH
8FH
90H
91H
92H
93H
94H
95H
96H
F9H
FAH
FBH
FCH
FDH
FEH
FFH
100H
101H
102H
103H
104H
105H
106H
107H
COM0
COM1
COM2
COM3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
Page 0
Page 1
Page 2
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
Start
0
0
0
0
0
0
0
1
1
0
1
0
Page 3
Page 4
0
0
0
0
0
1
1
1
0
1
1
1
Page 5
COM121
COM122
COM123
COM124
COM125
COM126
COM127
COM128
COM129
COM130
COM131
Page 15
0
0
1
1
0
0
0
0
0
0
0
1
Page 16
Page 17
Page 18
Page 31
0
0
1
1
0
1
0
1
1
1
0
1
Page 32
1
0
0
0
0
0
Fig. 6.6 Binary display
Rev. 1.3
EPSON
23
S1D15E05 Series
flicker.
6.3 Oscillator circuit
Furthermore, the display clock generates internal
common timing, liquid crystal alternating signal(FR),
field start signal (CA) and drive pattern signal (Fl and
F2).
The FR normally generates 2-frame alternating drive
system drive waveform to the liquid crystal drive
circuit. The n-line reverse alternating drive waveform
is generated for each 4 × (a+1) line by setting data on the
n-line reverse drive register. When there is a display
quality problem including crosstalk,the problem may
be solved using the n-line reverse alternating drive.
Execute liquid crystal display to determine the number
of lines “n” for alternation.
A display clock is generated by the CR oscillator. The
oscillator circuit is enabled only when M/S = HIGH and
CLS = HIGH. Oscillation starts after input of the built-
in oscillator circuit ON command input.
When CLS = LOW, oscillation stops, and display clock
is input from the CL pin.
6.4 Display timing generation circuit
Timing signals are generated from the display clock to
the line address circuit and display data latch circuit.
Synchronized with display clock, display data is latched
in display data latch circuit, and is output to the segment
drive output pin. Reading of the display data into the
LCD drive circuit is completely independent of access
from the MPU to the display data RAM. Accordingly,
asynchronous access to the display data RAM during
LCD display does not give any adverse effect; like as
When you want to use the S1D15E05 series in multi-
chip configuration, supply display timing signal (FR,
CA, F1, F2, CL, DOF) to the slave side from the master
side. Table 6.5 shows the statuses of FR, CA, F1, F2,
CL, DOF.
Table 6.5
Operating mode
CL
FR, CA, F1, F2, DOF
Master (M/S = HIGH) Built-in oscillator circuit enabled (CLS = HIGH) Output
Built-in oscillator circuit disabled (CLS = LOW) Input
Output
Output
Slave (M/S = LOW) Built-in oscillator circuit enabled (CLS = HIGH) Input
Built-in oscillator circuit disabled (CLS = LOW) Input
Input
Input
6.5 Liquid crystal drive circuit
6.5.1 SEG Drivers
6.5.2 COM Drivers
6.5.2.1 S1D15E05D00B
*
This is a COM output circuit. It selects three values of
V2, VC and MV2(VSS) using the driver control signal
determined by the decoder, and output them.
6.5.1.1 S1D15E05D00B
*
SEG output circuit selects five values of V2, V1, VC,
MV1 and MV2(VSS) using the driver control signal
determined by the decoder, and outputs them.
6.5.2.2 S1D15E06D00B
*
This is a COM output circuit. It selects three values of
V3, VC and MV3(VSS) using the driver control signal
determined by the decoder, and output them.
SED15E series allows the COM output scanning
direction to be set by the common output status select
command. (See Table 6.6). This will reduce restrictions
on IC layout during LCD module assembling.
6.5.1.2 S1D15E06D00B
*
This is a SEG output circuit. It selects the five values of
V2, V1, VC, MV1 and MV2 using the driver control
signal determined by the decoder, and output them.
Table 6.6
Status
Direction of COM scanning
Normal
COM 0
→
→
COM 131
COM 0
Reverse COM 131
24
EPSON
Rev. 1.3
S1D15E05 Series
control of step-up circuit, voltage regulating circuit and
liquid crystal drive potential generating circuit. This
allows a combined use of the external power supply and
part of built-in power supply functions. Table 6.7
shows functions controlled by the 5-bit data of the
control set command, and Table 6.8 shows reference
combinations. The power supply circuit is enabled only
during master operation.
6.6 Power supply circuit
This is a power supply circuit to generate voltage
required for liquid crystal drive, and is characterized by
a low power consumption. It consists of a step-up
circuit, voltage regulating circuit and liquid crystal
drive voltage generating circuit, and is enabled only
during master operation. The power supply circuit uses
the power control set command to provide an on/off
Table 6.7 Control by 5-bit data of the control set command
Item
State
“1”
Triple Double Single
“0”
–
D4 Step-cut circuit scaling factor select bit 1
–
1
1
–
–
–
1
0
–
–
–
0
1
–
–
–
D3 Step-cut circuit scaling factor select bit 2
–
–
D2 Step-cut circuit control bit
ON
ON
ON
OFF
OFF
OFF
D1 Voltage regulator circuit (VC regulator circuit) control bit
D0 LCD driving potential generating circuit (LCDV circuit) control bit
Table 6.8 Reference combination
Circuits used
D4 D3 D2 D1 D0 Step-up VC regulator
LCDV
circuit
Eternal input
power supply
circuit
circuit
1Use of all built-in
power supplies
Triple step-up
Double step-up
VOUT = VDD
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
“1”
“1”
“1”
“1”
“1”
“1”
“1”
“1”
“1”
–
–
–
×
2VC regulating circuit and
0
0
0
1
1
“0”
“1”
“1”
VOUT
LCDV circuit only
×
×
×
×
3LCDV circuit only
0
0
0
0
0
0
0
0
1
0
“0”
“0”
“0”
“0”
“1”
VC
×
×
4-1 External power supply
only (S1D15E05D00B )
“0”
“0”
V2, V1, VC, MV1
*
×
×
4-2 External power supply
only (S1D15E06D00B )
0
0
0
0
0
“0”
“0”
V3, V2, V1, VC,
MV1, MV2
*
* Any combinations other than the above are not available.
*100ms or more should be kept from VC regulator circuit ON to LCDV circuit ON.
Rev. 1.3
EPSON
25
S1D15E05 Series
6.6.1 Step-up circuit
2When used by switching between the double step-up
and VOUT = VDD using a command:
Capacitors C1 are connected between CAP1+
<-> CAP1 and between VDD <-> VOUT for use.
3Only VOUT = VDD is used.
VDD-VSS potential can be triple and double step-up by
the step-up circuit built in the S1D15E05 series. The
status of VOUT = VDD can be selected by stopping the
operation of the triple and double step-up circuit using
the command
VDD pin and VOUT pin are connected for use.
1When used by switching between the triple, double
step-up and VOUT = VDD using a command:
Capacitors C1 are connected between CAP1+
<-> CAP1, between CAP2+ <-> CAP2 and
between VDD <-> VOUT for use.
VDD
VDD
VDD
C1
C1
+
+
+
+
V
OUT
V
OUT
V
OUT
CAP1+
CAP1+
OPEN
OPEN
OPEN
CAP1+
CAP1–
CAP2–
CAP2+
C1
C1
C1
CAP1–
CAP2–
CAP1–
CAP2–
CAP2+
OPEN
+
OPEN
CAP2+
1Triple, double step-up or
2Double step-up or
3VOUT = VDD (without step-up)
VOUT = VDD
VOUT = VDD
Fig.6.7 shows the potential relationship for boosting.
VOUT = 3 x VDD
VOUT = 2 x VDD
= 6V
= 6V
VOUT = VDD
= 3.6V
VDD = 3V
VDD = 2V
VSS = 0V
VSS = 0V
VSS = 0V
Triple step-up potential relationship Double step-up potential relationship
VOUT = VDD potential relationship
Fig. 6.7
* Set the VDD voltage range so that the VOUT pin voltage does not exceed the absolute maximum rating.
26
EPSON
Rev. 1.3
S1D15E05 Series
only by the command without adding any external parts.
The variable range of the VC voltage is from about 1.6
to 7.0 [V]. When the internal step-up is used, or VOUT
is input for use, the VOUT potential should be, in
principle, the voltage 20% or more higher than the
maximum voltage of the VC to be used, giving
consideration to temperature characteristics.
6.6.2 Voltage Regulating Circuit
VOUT generated from the step-up circuit or VOUT input
from the outside produces liquid crystal drive voltage
VC via the voltage regulating circuit. The voltage
regulating circuit is controlled by liquid crystal drive
voltage change command and electronic volume.
The S1D15E05 series has a high precision constant
voltage source, and incorporates 4-step liquid crystal
drive voltage change command and 128-step electronic
volume functions. This makes it possible to provide a
high precision liquid crystal drive voltage regulation
Example: When VC output is 7 [V], VOUT ≥ 8.4 [V]
(three times 2.8 [V], etc.)
When VC output is 4 [V], VOUT ≥ 4.8 [V]
(two times 2.4 [V], three times 1.8 [V])
• Electronic volume
α of Table 6.9 indicates an electronic volume command
value. It takes one of 128 states when the data is set in
the 7-bit electronic volume register.
Table 6.9 shows the value of α by setting the data in the
electronic volume register.
Table 6.9
D6
D5
D4
D3
D2
D1
D0
α
Voltage VC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
2
Small
↑
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
125
126
127
↓
Large
• Liquid crystal drive voltage selection
The liquid drive voltage range can be selected from 3
states by the liquid crystal drive voltage select command
using the two-bit crystal drive voltage select command
register.
Table 6.10
D1
0
D0
0
VC voltage output range
1.77V to 3.50V
1
0
2.53V to 5.00V
1
1
3.54V to 7.00V
Rev. 1.3
EPSON
27
S1D15E05 Series
Equation A-1 represents VC logical values. For the output voltage of VC, a manufacturing dispersion of up to ± 3%
should be taken into account.
Equation A-1
Unit [V]
Electronic
LCD voltage selection
VR
D1
0
D0
0
D1
1
D0
0
D1
1
D0
1
α
VC (Max.) = 3.50V
1.77 + 0.0195 × α
VC (Max.) = 5.00V
2.53 + 0.028 × α
VC (Max.) = 7.00V
3.54 + 0.039 × α
0 to 31
32 to 63
64 to 95
96 to 127
2.39 + 0.0156 × (α –32)
2.89 + 0.0117 × (α –64)
3.26 + 0.0078 × (α –96)
3.42 + 0.0223 × (α–32)
4.12 + 0.0167 × (α–64)
4.65 + 0.0112 × (α–96)
4.78 + 0.0313 × (α–32)
5.77 + 0.0234 × (α–64)
6.52 + 0.0156 × (α–96)
7
6
5
4
VC
3
2
1
0
32
64
96
127
Value of electronic volume α
Figure 6.8
28
EPSON
Rev. 1.3
S1D15E05 Series
6.6.3 Liquid crystal drive voltage generation
circuit
6.6.3.2 S1D15E06D00B
*
Voltage VC is stepped up in the IC to generate potential
V3. Furthermore, voltages V3 and VC are converted by
resistive divider to produce V2, V1, MV1 and MV2
voltages. V2, V2, MV1 and MV2 voltages are impedance-
converted by the voltage follower, and is supplied to the
liquid crystal drive circuit.
6.6.3.1 S1D15E05D00B
*
The voltage VC is stepped up and down in the IC, and
generates voltage V2, V1 and MV1 required for liquid
crystal drive.
Voltage V2 is output at the value double of the VC,
voltage V1 at the value intermediate between V2 and
VC, and potential MV1 at the value intermediate between
VC and MV2(VSS).
V2
V1
VC
MV1
MV2
11/14 • V3
9/14 • V3
7/14 • V3
5/14 • V3
3/14 • V3
V1
VC
MV1
3/4 • V2
2/4 • V2
1/4 • V2
Rev. 1.3
EPSON
29
S1D15E05 Series
An example of circuit around the power supply circuit
(S1D15E05D00B )
*
2
1Use of all built-in power supplies
When used by switching between the triple, double
step-up and VOUT = VDD using a command: (12 C’s)
When used by switching between the double step-up
and VOUT = VDD using a command: (11 C’s)
+
+
CAP1+
CAP1–
CAP1+
CAP1–
C1
C1
CAP2–
CAP2+
CAP2–
CAP2+
C1
+
+
+
V
V
OUT
DD
V
V
OUT
DD
C1
C1
+
+
V
V
DD
VDD
C1
C1
SS
VSS
+
+
CAP3+
CAP3–
CAP4–
CAP4+
CAP3+
CAP3–
CAP4–
CAP4+
C1
C1
C1
C1
+
+
+
+
CPP+
CPP–
CPM+
CPM–
CPP+
CPP–
CPM+
CPM–
C2
C2
C2
C2
+
+
+
+
+
+
+
+
+
+
V
V
V
MV
MV
2
1
C
V
V
V
MV
MV
2
1
C
C3 × 4
C3 × 4
1
2
1
2
(VSS
)
(VSS)
Only VOUT = VDD is used (9 C’s)
2VC regulating circuit and LCDV circuit
VOUT external output (10 C’s)
CAP1+
CAP1–
CAP2–
CAP2+
CAP1+
CAP1–
CAP2–
CAP2+
V
OUT
V
V
OUT
DD
V
V
OUT
DD
+
+
V
V
DD
SS
V
V
DD
SS
C1
C1
+
+
CAP3+
CAP3–
CAP4–
CAP4+
CAP3+
CAP3–
CAP4–
CAP4+
C1
C1
C1
C1
+
+
+
+
CPP+
CPP–
CPM+
CPM–
CPP+
CPP–
CPM+
CPM–
C2
C2
C2
C2
+
+
+
+
+
+
+
+
+
+
V
V
V
MV
MV
2
1
C
V
V
V
MV
MV
2
1
C
C3 × 4
C3 × 4
1
2
1
2
(VSS
)
(VSS)
30
EPSON
Rev. 1.3
S1D15E05 Series
3LCDV circuit only
4External power supply only
VC external input (9 C’s)
external input (1 C)
CAP1+
CAP1+
CAP1–
CAP2–
CAP2+
CAP1–
CAP2–
CAP2+
V
V
OUT
DD
V
V
OUT
DD
+
+
V
V
DD
SS
V
V
DD
C1
C1
SS
+
CAP3+
CAP3–
CAP4–
CAP4+
CAP3+
CAP3–
CAP4–
CAP4+
C1
C1
+
+
CPP+
CPP–
CPM+
CPM–
CPP+
CPP–
CPM+
CPM–
C2
C2
+
+
+
V
V
V
MV
MV
2
1
C
V
V
V
MV
MV
2
1
C
External
Power
Supply
C3 × 4
V
C
+
+
1
2
1
2
(VSS
)
(VSS)
An example of circuit around the power supply circuit
(S1D15E06 D00B )
1Use of all built-in power supplies
*
When used by switching between the double step-up
and VOUT = VDD: (11 C’s)
When used by switching between the triple, double
step-up and VOUT = VDD: (12 C’s)
+
+
CAP1+
CAP1–
CAP1+
CAP1–
C1
C1
CAP2–
CAP2+
CAP2–
CAP2+
C1
+
+
+
V
V
OUT
DD
V
V
OUT
DD
C1
C1
+
+
V
V
DD
SS
V
V
DD
SS
C1
C1
+
+
+
+
CAP3+
CAP3–
CAP4–
CAP4+
CAP3+
CAP3–
CAP4–
CAP4+
C1
C1
C1
C1
CPP+
CPP–
CPM+
CPM–
CPP+
CPP–
CPM+
CPM–
+
+
+
+
+
+
+
+
+
+
+
+
V
V
V
V
MV
MV
MV
3
2
1
C
V
V
V
V
MV
MV
MV
3
2
1
C
C3 × 6
C3 × 6
1
2
3
1
2
3
(VSS
)
(VSS)
Rev. 1.3
EPSON
31
S1D15E05 Series
Only VOUT = VDD is used: (9 C’s)
2VC regulating circuit and LCDV circuit
VOUT external input (10 C’s)
CAP1+
CAP1–
CAP2–
CAP2+
CAP1+
CAP1–
CAP2–
CAP2+
V
OUT
V
V
OUT
DD
V
V
OUT
DD
+
+
V
V
DD
SS
V
V
DD
SS
C1
C1
+
+
+
+
CAP3+
CAP3–
CAP4–
CAP4+
CAP3+
CAP3–
CAP4–
CAP4+
C1
C1
C1
C1
CPP+
CPP–
CPM+
CPM–
CPP+
CPP–
CPM+
CPM–
+
+
+
+
+
+
+
+
+
+
+
+
V
V
V
V
MV
MV
MV
3
2
1
C
V
V
V
V
MV
MV
MV
3
2
1
C
C3 × 6
C3 × 6
1
2
3
1
2
3
(VSS
)
(VSS)
4External power supply only
3LCDV circuit only
external input (1 C)
VC external input (9 C’s)
CAP1+
CAP1–
CAP2–
CAP2+
CAP1+
CAP1–
CAP2–
CAP2+
V
V
OUT
DD
V
V
OUT
DD
+
+
V
V
DD
SS
V
V
DD
C1
C1
SS
+
CAP3+
CAP3–
CAP4–
CAP4+
CAP3+
CAP3–
CAP4–
CAP4+
C1
C1
+
CPP+
CPP–
CPM+
CPM–
CPP+
CPP–
CPM+
CPM–
+
+
+
V
V
V
V
MV
MV
MV
3
2
1
C
V
V
V
V
MV
MV
MV
3
2
1
C
External
Power
Supply
C3 × 6
V
C
+
+
+
1
2
3
1
2
3
(VSS
)
(VSS)
32
EPSON
Rev. 1.3
S1D15E05 Series
Examples of common reference settings
The optimum values for above-mentioned Cl, C2 and
C3 vary according to the LCD panel to drive. Use the
above-mentioned values as references. Actually verify
the display of a pattern with big load to make a decision.
Item
C1
Settings
1.0 to 4.7
0.47 to 1.0
0.47 to 1.0
Unit
µF
C2
C3
17. Partial display : OFF
6.6.4 Temperature gradient select circuit
18. Partial display start line : (D7, D6, D5, D4, D3, D2,
D1, D0) = (0, 0, 0, 0, 0, 0, 0)
Number of partial display lines : (D7, D6, D5, D4,
D3, D2, D1, D0) = (0, 0, 0, 0, 0, 0, 0)
19. Read modify write : OFF
20. Built-in oscillation circuit : stop
21. Oscillation frequency register : (D3, D2, D1,D0) =
(0, 0, 0, 0) (120 kHz)
22. Power control register : (D4, D3, D2, D1, D0) = (0,
0, 0, 0, 0)
23. Clock frequency for step-up/step-down
Step-up : (D2, D1, D0) = (1, 0, 1)
Step-down : (D6, D5, D4) = (1, 0, 1)
24. Liquid crystal drive voltage selection register :
(D1,D0) = (0, 0)
This is a circuit to select the temperature gradient
characteristics of the liquid crystal drive power supply
voltage. Temperature gradient characteristics can be
selected from eight states by the Temperature Gradient
command. Selection of temperature gradient
characteristics conforming to the temperature
characteristics of the liquid crystal to be used makes it
possible to configure a system without providing an
external element for temperature characteristics
compensation.
6.7 Reset circuit
When the RES input becomes LOW, this LSI is set to the
initialized state.
The following shows the initially set state:
25. Electronic volume register : (D6, D5, D4, D3, D2,
D1, D0) = (0, 0, 0, 0, 0, 0, 0)
1. Display : OFF
2. Display OFF mode : VSS output
3. Display : normal mode
26. Discharge : ON (only for when RES = LOW)
27. Power save : OFF
28. Temperature gradient resistor : (D2, D1, D0) = (0,
0, 0) (–0.06/°C)
4. Display all lighting : OFF
5. Common output status : normal
6. Display start line : Set to 1st line
7. Page address : Set to 0 page
8. Column address : Set to 0 address
9. Display data input direction : Column direction
10. Column address direction : forward
11. n-line a.c. reverse drive : OFF (reverse drive for
each frame)
29. Register data in the serial interface : Clear
When the Reset command is used, only the above-
mentioned inilialized items 7, 8 and 19 are executed.
When power is turned on, initialization by the RES pin
is necessary. After initialization by the RES pin, each
input pin must be controlled correctly.
12. n-line reverse drive register : (D4, D3, D2, D1, D0)
= (0, 1, 1, 0, 0)
Furthermore, when control signals from the MPU have
a high impedance, the excessive current may flow to the
IC.
After VDD is applied, measures should be taken to
ensure that the input pin does not have a high impedance.
The S1D15E05 series discharges the electric charge of
VOUT and liquid crystal drive voltage (V2, V1, VC,
MV1) at the level of RES pin = LOW(V3, V2, V1,VC,
13. Display mode : 4 gray-scale display
14. Gray-scale pattern register : (D7, D6, D5, D4, D3,
D2, D1, D0) = ( , 1, 0, 1, , 0, 1, 0)
*
*
15. Area scroll :
Scroll mode : (D1, D0) = (0, 0)
Scroll start address : (D7, D6, D5, D4, D3, D2, D1,
D0) = (0, 0, 0, 0, 0, 0, 0, 0)
Scroll terminating address : (D7, D6, D5, D4, D3,
D2, D1, D0) = (0, 0, 0, 0, 0, 0, 0, 0)
MV1,MV2 as for S1D15E06D00B ). When liquid
*
crystal drive external power supply is used, external
power supply should not be supplied during the period
of RES = LOW to prevent external power supply and
VDD from being short circuited.
Number of display lines : (D7, D6, D5, D4, D3, D2,
D1, D0) = (0, 0, 0, 0, 0, 0, 0, 0)
16. DUTY register : (D5, D4, D3, D2, D1, D0) = (1, 0,
0, 0, 0, 0) (1/132 duty)
Start spot (block) register : (D5, D4, D3, D2, D1,
D0) = (0, 0, 0, 0, 0) (COM0)
Rev. 1.3
EPSON
33
S1D15E05 Series
7. COMMAND
The S1D15E05 series identifies data bus signals by a combination of A0, RD(E) and WR(R/W). Interpretation and
execution of the command are executed by the internal timing alone which is independent of the external clock. This
allows high-speed processing.
The 80 series MPU interface allows the command to be started by entering the low pulse in the RD pin during reading
and by entering the low pulse in the WR pin during writing.
The 68 series MPU interface allows a read state to occur by entering HIGH in the R/W pin, and permits a write state
to occur by entering LOW. It also allows the command to be started by entering the high pulse in the pin E. (For timing,
see the description of “10. Timing characteristics”).
Accordingly, the 68 series MPU interface is different from 80 series MPU interface in that RD(E) is “1(H)” in the case
of display data/read shown in the Command Description and Command Table. The following describes the commands,
based on the example of the 80 series MPU interface:
When the serial interface is selected, enter data sequentially starting from D7.
Command Description
(1) Display ON/OFF
This command sets the display ON/OFF.
When display OFF is specified, segment and common drivers outputs the level selected by the display OFF Mode Select
command.
E
RD
R/W
WR
A0
D7
D6
D5
D4
D3
D2
D1
D0 Output level
0
1
0
1
0
1
0
1
1
1
0
1
Display OFF
Display ON
(2) Display OFF Mode Select
This command is used to set the output level of the segment and common driver when the display is off.
* When D0 = 0 is selected in the case of S1D15E06D00B , the MV2 and common driver VSS level is output by segment
*
driver when display is off. Select D0 = 1 to use the S1D15E06D00B .
*
E
RD
R/W
WR
A0
D7
D6
D5
D4
D3
D2
D1
D0 Output level
0
1
0
1
0
1
1
1
1
1
0
1
VSS
VC
(3) Display Normal/Reverse
This command allows the display ON/OFF state to be reversed, without having to rewrite the contents of the display
data RAM. In this case, contents of the display data RAM are maintained.
E
RD
R/W
WR
A0
D7
D6
D5
D4
D3
D2
D1
D0
Setting
0
1
0
1
0
1
0
0
1
1
0
RAM data = HIGH
LCD ON Voltage
(normal)
1
RAM data = LOW
LCD ON Voltage
(reverse)
34
EPSON
Rev. 1.3
S1D15E05 Series
(4) Display All Lighting ON/OFF
This command forces all the displays to be turned on independently of the contents of the display data RAM. In this
case, the contents of the display data RAM are maintained. Fully white display can also be made by a combination of
the Display Reverse command.
E
RD
R/W
WR
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
Setting
0
1
0
1
0
1
0
0
1
0
Normal display status
Display all lighting
1
(5) Common Output Status Select
This command allows the scanning direction of the COM output pin to be selected. For details, see the description of
“6.5.2 COM Drivers” in the Function Description.
E
RD
R/W
A0
WR D7 D6 D5 D4 D3 D2 D1 D0
Selected state
0
1
0
1
1
0
0
0
1
0
0
1
Normal
COM0 → COM131
COM131 → COM0
Reverse
(6) Display Start Line set (Parameter: 1 byte (4 gray-scale) and 2 bytes (binary))
The parameter following this command specifies the display start line address of the display data RAM shown in Fig.
6.5 and 6.6. When the Display Mode command is used to select 4 gray-scale display, a 1-byte parameter must be entered.
When the binary display is selected, a 2-byte parameter must be entered.
The display area is indicated in the direction where line address numbers are incremented, starting from the specified
line address. If a dynamic change of the line address is made by this command, smooth scrolling in the longitudinal
direction and page breaking are enabled. For details, see the description of “6.2.4 Line address circuit” in the Function
Description.
E
RD
R/W
WR
A0
0
D7
1
D6
0
D5
0
D4
0
D3
1
D2
0
D1
1
D0
1
1
1
0
0
0
0
Mode setting
1
P7
*
P6
*
P5
*
P4
*
P3
*
P2
*
P1
*
P0 Register setting 1
P8 Register setting 2
1
(only binary display required)
*: denote invalid bits.
Rev. 1.3
EPSON
35
S1D15E05 Series
• Display Start Line Set command parameter
(i) When the display mode is a 4 gray-scale mode:
The one-byte parameter is used to specify the address.
Line
address
P7
0
P6
0
P5
0
P4
0
P3
0
P2
0
P1
0
P0
0
00H
01H
02H
↓
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
↓
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
82H
83H
Set to the line address 00H at the time of resetting.
(ii) When the display mode is binary:
To specify the address, continuous 2-byte data is necessary. The first byte D0 is LSB, and the second byte D0 is MLB.
P7
P6
P5
P4
P3
P2
P1
P0
P8
Line
address
1st byte
2nd byte
0
*
0
*
0
*
0
*
0
*
0
*
0
*
0
0
00H
01H
02H
0
*
0
*
0
*
0
*
0
*
0
*
0
*
1
0
0
*
0
*
0
*
0
*
0
*
0
*
1
*
0
0
↓
↓
0
*
0
*
0
*
0
*
0
*
1
*
1
*
0
1
106H
0
*
0
*
0
*
0
*
0
*
1
*
1
*
1
1
107H
Set to line address 000H at the time of resetting. *: denote invalid bits.
• Line address setting sequence
Set Line Address Mode
One byte for 4 gray-scale
Two bytes for binary display
Set Line Address Register
Reset Line Address Mode
No
Change Completed?
Yes
Fig. 7.1
36
EPSON
Rev. 1.3
S1D15E05 Series
(7) Page Address Set
This command specifies the page address corresponding to row address when MPU access to the display data RAM
shown in Fig. 6.5 and 6.6. For details, see the description of “6.2.2 Page address circuit” in the Function Description.
E
RD
R/W
WR
A0
0
D7
1
D6
0
D5
1
D4
1
D3
0
D2
0
D1
0
D0
Page address
1
1
0
0
1
Command
1
*
*
P5
P4
P3
P2
P1
P0 Page address setting
*: denote invalid bits.
P5
0
P4
0
P3
0
P2
0
P1
0
P0
0
Page address
0
1
0
0
0
0
0
1
↓
↓
0
1
1
0
1
0
1
0
1
0
1
0
31
32
(8) Column Address Set
This command sets the display data RAM column address given in Fig. 6.5 and 6.6. For details, see the description of
“6.2.3 Column address circuit” in the Function Description.
E
RD
R/W
WR
A0
0
D7
0
D6
0
D5
0
D4
1
D3
0
D2
0
D1
1
D0
1
1
1
0
0
1
P7
P6
P5
P4
P3
P2
P1
P0
Column
address
P7
0
P6
0
P5
0
P4
0
P3
0
P2
0
P1
0
P0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
2
↓
↓
1
1
0
0
0
0
0
1
0
1
0
1
1
1
0
1
158
159
(9) Display Data Write
This command allows the 8-bit data to be written to the address specified by the display data RAM. After writing,
column address or page address is automatically incremented +1 by the Display Data Input Direction Select command.
This enables the MPU to write the display data continuously.
E
RD
R/W
WR
A0
0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
0
0
0
0
1
1
1
0
1
1
Write Data
Rev. 1.3
EPSON
37
S1D15E05 Series
(10) Display Data Read
This command allows the 8-bit data to be read from the address specified by the display data RAM. After reading,
column address or page address is automatically incremented +1 by the Display Data Input Direction select command.
This enables the MPU to read multiple word data continuously.
It should be noted that one dummy reading is essential immediately after the column address or page address has been
set. For details, see the description of “6.1.5 Access to display data RAM and internal register” in the Function
Description. When the serial interface is used, display data cannot be read.
E
RD
R/W
WR
A0
0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
1
0
0
0
1
1
1
0
0
1
Read Data
(11) Display Data Input Direction Select
This command sets the direction where the display RAM address number is automatically incremented. For details,
see the description of “6.2.3 Column address circuit” in the Function Description.
E
RD
R/W
WR
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
Direction
Column
Page
0
1
0
1
0
0
0
0
1
0
1
(12) Column Address Set Direction
This command can reverse the relationship between the display RAM data column address and segment driver output
shown in Fig. 6.5 and 6.6. So you can reverse the sequence of segment driver output pins using this command. When
the display data is written or read, the column address is incremented by (+1) according to the column address given
in Fig. 6.4 and 6.5. For details, see the description of “6.2.3 Column address circuit” in the Function Description.
E
RD
R/W
WR
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
Setting
Normal
Reverse
0
1
0
1
0
1
0
0
0
0
1
(13) n-line Inversion Drive Register Set
This command sets the liquid crystal alternating drive reverse line count in the register to start line reverse driving
operation. The line count to be set is 4 to 128 (32 states for each 4 lines. For details, see the description of “6.4 Display
timing generation circuit” in the Function Description.
E
RD
R/W
WR
A0
0
D7
0
D6
0
D5
1
D4
1
D3
0
D2
1
D1
1
D0 Reverse line count
Command
1
1
0
0
0
1
*
*
*
P4
P3
P2
P1
P0 Reverse line count
*: denote invalid bits.
P4
0
P3
0
P2
0
P1
0
P0 Reverse line count
0
1
4 (1 × 4)
8 (2 × 4)
↓
0
0
0
0
↓
1
1
1
1
1
1
1
1
0
1
124 (31 × 4)
128 (32 × 4)
38
EPSON
Rev. 1.3
S1D15E05 Series
(14) N-line ON/OFF
This command provides ON/OFF control of N-line inverting drive.
E
RD
R/W
WR
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
N-line
0
1
0
1
1
1
0
0
1
0
OFF
ON
1
(15) Display Mode
This command sets the display mode. 4 gray-scale and binary display each have a different RAM configuration.
For details, see the description of “6.2.1 Display Data RAM” in the Function Description.
E
RD
R/W
WR
A0
0
D7
0
D6
1
D5
1
D4
0
D3
0
D2
1
D1
1
D0
0
Display mode
Command
1
1
0
0
1
*
*
*
*
*
*
P1
P0
Display mode
*: denote invalid bits.
P1
0
P0
0
Display mode
4gray-scale
0
1
Binary value
Set to 4 gray-scale (D1, D0) = (0, 0) at the time of resetting.
(16) Gray-scale Pattern Set
This command sets the level of gray-scale.
E
RD
R/W
WR
A0
0
D7
0
D6
0
D5
1
D4
1
D3
1
D2
0
D1
0
D0 Gray-scale pattern
1
1
0
0
1
Command
1
*
P6
P5
P4
*
P2
P1
P0
Selection of
gray-scale level
* (P6, P5, P4) : Selects the level of gray-scale bit (1, 0)
* (P2, P1, P0) : Selects the level of gray-scale bit (0, 1)
Gray-scale bit (1, 0)
Gray-scale bit (0, 1)
P6
0
P5
0
P4
1
P2
–
P1
–
P0 Level of gray-scale
–
–
–
–
–
–
White
0
1
0
–
–
↓
↓
–
1
1
0
–
–
–
–
Black
P6
–
P5
–
P4
–
P2
0
P1
0
P0 Level of gray-scale
–
–
–
–
1
0
White
–
–
–
0
1
↓
↓
–
–
–
–
–
1
1
0
Black
Rev. 1.3
EPSON
39
S1D15E05 Series
(17) Area Scroll Set
This command sets the area scroll. When the binary display is selected by the Display Mode Set command, the scroll
end line address becomes a two-byte parameter.
14 gray-scale display
E
RD
R/W
WR
A0
0
D7
0
D6
0
D5
0
D4
1
D3
0
D2
0
D1
D0
Area scroll
Command
1
1
1
1
1
0
0
0
0
0
0
0
1
*
*
*
*
*
*
P11 P10
Scroll mode
1
P27 P26 P25 P24 P23 P22 P21 P20
P37 P36 P35 P34 P33 P32 P31 P30
P47 P46 P45 P44 P43 P42 P41 P40
Scroll start line address
Scroll end line address
Scroll display line count
1
1
*: denote invalid bits.
P11 P10
Scroll mode
0 (full screen)
1 (Upper)
0
0
1
1
0
1
0
1
2 (Lower)
3 (Central)
P27 P26 P25 P24 P23 P22 P21 P20 Scroll start line address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
↓
1
1
0
1
00H
01H
↓
1
1
0
0
0
0
0
0
0
0
0
0
0
1
82H
83H
P37 P36 P35 P34 P33 P32 P31 P30 Scroll end line address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
↓
1
1
0
1
00H
01H
↓
1
1
0
0
0
0
0
0
0
0
0
0
0
1
82H
83H
P47 P46 P45 P44 P43 P42 P41 P40 Scroll display line count
0
0
0
0
0
0
0
0
0
0
0
0
0
1
↓
1
0
1
0
1
2
↓
1
1
0
0
0
0
0
0
0
0
0
1
1
0
131
132
40
EPSON
Rev. 1.3
S1D15E05 Series
2Binary display
E
RD
R/W
WR
A0
0
D7
0
D6
0
D5
0
D4
1
D3
0
D2
0
D1
D0
Area scroll
Command
1
1
1
1
1
1
0
0
0
1
0
*
*
*
*
*
*
P11 P10
Scroll mode
1
0
P27 P26 P25 P24 P23 P22 P21 P20
P37 P36 P35 P34 P33 P32 P31 P30
Scroll start line address
Scroll end line address
1
0
1
0
*
*
*
*
*
*
*
P38
1
0
P47 P46 P45 P44 P43 P42 P41 P40
Scroll display line count
*: denote invalid bits.
• Specifications on the parameters for scroll mode, scroll start line address and scroll display line count are the same
as those on 4 gray-scale display.
P37 P36 P35 P34 P33 P32 P31 P30 Scroll end line address
P38
Binary value
1st byte
2nd byte
0
*
0
*
0
*
0
*
0
*
0
*
0
*
0
0
00H
0
*
0
*
0
*
0
*
0
*
0
*
0
*
1
0
01H
↓
↓
0
*
0
*
0
*
0
*
0
*
1
*
1
*
0
1
106H
0
*
0
*
0
*
0
*
0
*
1
*
1
*
1
1
107H
(18) Duty Set Command
Liquid crystal drive at a lower power consumption is ensured by using this command to change the duty. Use of this
command also allows display at a desired position on the panel (continuous COM pins on a 4-line basis).
This command is used with a pair of the duty set parameter and start point (block) parameter, so be sure to set both
parameters so that one of them will immediately follow the other.
E
RD
R/W
WR
A0
0
D7
0
D6
1
D5
D4
D3
D2
D1
D0
Selected state
Duty set command
Duty set
1
1
1
0
0
0
1
0
1
1
0
1
1
*
*
P15 P14 P13 P12 P11 P10
P25 P24 P23 P22 P21 P20
1
*
*
Start point set
*: denote invalid bits.
• Duty set
Duty can be set in the range from 1/4 duty to 1/132 duty by 4 steps.
Set to 1/132 duty after resetting.
P15 P14 P13 P12 P11 P10
Duty set
1/4 duty set
1/8 duty set
1/12 duty set
1/16 duty set
↓
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
↓
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1/128 duty set
1/132 duty set
Rev. 1.3
EPSON
41
S1D15E05 Series
• Start point (block) register set parameter
Use this parameter to set 6-bit data in the start point (block) register. Then one of 33 start point blocks will be determined.
* Use the Display Start Line Set command (6) for display scroll. Do not use this command for display scroll.
P25 P24 P23 P22 P21 P20
Start piont setting
0 (COM0 to 3)
1 (COM4 to 7)
2 (COM8 to 11)
↓
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
↓
0
1
1
0
1
0
1
0
1
0
1
0
31 (COM124 to 127)
32 (COM128 to 131)
Set to 0 block (D7 to D0: ***00000) at the time of resetting
* Voltage optimum to liquid crystal drive is changed when the duty is changed. Use the electronic volume and set the
voltage to get the optimum display.
• Duty command setup example
1. Duty 1/88 When 1 (COM4 to COM7) is specified as the start point (block)
Display area COM4 to COM91
2. Duty 1/68 When 26 (COM104 to COM107) is specified as the start point (block)
Display area COM104 to COM131 and COM0 to COM39
* If the COM pin is not shared by the master and slave in the master/slave 2-chip operation (for vertical drive such as
SEG132, COM80+COM80), the same duty must be used on the master and slave. Otherwise, display contrast will
be different on the master and slave. When you want to disable display on either the master and slave, use the display
OFF Mode Select command to set the side you want to disable, so that VC level is output.
(19) Partial Display ON/OFF
The LCD partial display is turned on or off by this command.
E
RD
R/W
WR
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
Partial display
0
1
0
1
0
0
1
0
1
1
OFF
ON
1
(20) Partial Display Set
This command sets the LCD partial display area. Duty is placed in the state selected by the Duty Set command. When
partial display is switched by this command, liquid crystal drive voltage need not be changed. For details, see the
description of “6.2.7 Partial Display” in the Function Description.
E
RD
R/W
WR
A0
0
D7
D6
D5
D4
D3
D2
D1
D0
Partial display
Command
1
1
1
0
0
0
0
0
1
1
0
0
1
0
1
P17 P16 P15 P14 P13 P12 P11 P10
P27 P26 P25 P24 P23 P22 P21 P20
Display start line
Display line count
1
P17 P16 P15 P14 P13 P12 P11 P10
Display start line
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
↓
1
1
0
1
0
0
1
2
↓
1
1
0
0
0
0
0
0
0
0
0
0
0
1
131
132
42
EPSON
Rev. 1.3
S1D15E05 Series
P17 P16 P15 P14 P13 P12 P11 P10
Display start line
0
0
0
0
0
0
0
0
0
0
0
0
0
1
↓
1
0
1
2
↓
1
1
0
0
0
0
0
0
0
0
0
1
1
0
1
0
131
132
* The result of display start line added to display line count exceeding 132 should be disregarded.
(21) Read Modify Write
This command is paired with end command for use. If this command is entered, the column address is not changed by
the Display Data Read command. It can be incremented +1 by the Display Data Read command alone. This state s
retained until the End command is input. If the End command is input, the column address goes back to the address
when the Read Modify Write command is input. This function reduces the MPU loads when changing the data repeated
in the specific display area such as blinking cursor.
E
RD
R/W
WR
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
0
0
0
0
* A command other than display data Read/Write command can be used in the Read Modify Write mode. However,
you cannot use the column address set command.
• Sequence for cursor display
Page Address Set
Column Address Set
Read Modify Write
Dummy Read
Data Read
Data Manipulation
Data Write
No
Change Completed?
Yes
End
Fig. 7.2
Rev. 1.3
EPSON
43
S1D15E05 Series
(22) End
This command releases the read modify write mode and gets column address back to the initial address of the mode.
E
RD
R/W
WR
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
1
1
1
0
Return
Column address
N
N+1
N+2
N+3
• • •
N+m
N
End
Set read-modify-write mode
Fig. 7.3
(23) Built-in Oscillator Circuit ON/OFF
This command starts the built-in oscillator circuit operation. It is enabled only in the master operation mode (M/S =
HIGH) when built-in oscillator circuit is valid (CLS = HIGH).
When the built-in power supply is used, the Oscillator Circuit ON command must be executed before the Power Control
Set command. (See the description of “(16) power control command”). If the built-in oscillator circuit is turned off
when the built-in power supply is used, display failure may occur.
E
RD
R/W
WR
Built-in oscillator
circuit
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
1
0
1
0
1
0
1
OFF
ON
1
44
EPSON
Rev. 1.3
S1D15E05 Series
(24) Built-in Oscillator Circuit Frequency Select
This command sets the built-in oscillator circuit frequency. The frequency can be selected whether the built-in oscillator
circuit is turned on or off.
E
RD
R/W
WR
A0
0
D7
0
D6
1
D5
0
D4
1
D3
1
D2
1
D1
1
D0
fOSC kHz
fCL kHz
1
1
0
0
1
Command
Command
1
*
*
*
*
P3
P2
P1
P0 Oscillation CL frequency
frequency
Oscillation CL frequency
frequency
fOSC kHz
fCL kHz
P3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
P2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
P1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
P0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
120.0
100.0
88.0
fOSC 120.0
fOSC 100.0
fOSC 88.0
76.0
fOSC 76.0
120.0
100.0
88.0
fOSC/2 = 60.0
fOSC/2 = 50.0
fOSC/2 = 44.0
fOSC/2 = 38.0
fOSC/4 = 30.0
fOSC/4 = 25.0
fOSC/4 = 22.0
fOSC/4 = 19.0
fOSC/8 = 15.0
fOSC/8 = 12.5
fOSC/8 = 11.0
fOSC/8 = 9.5
76.0
120.0
100.0
88.0
76.0
120.0
100.0
88.0
76.0
(D7 to D0: ****0000) is set after resetting.
* The above-mentioned value is a Typ. value at 25°C. There is a tolerance of ±12% at 25°C.
Rev. 1.3
EPSON
45
S1D15E05 Series
(25) Power Control Set
This command sets the built-in power supply circuit function. For details, see the description of “6.7 Power supply
circuit” in the Function Description.
E
RD
R/W
WR
A0
0
D7
0
D6
0
D5
1
D4
0
D3
0
D2
1
D1
0
D0
1
Selected state
Command
1
1
0
0
1
0
0
0
P4
P3
P2
P1
P0
Register set
P4
1
P3
1
P2
P1
P0
Selected state
Triple step-up
Double step-up
VOUT = VDD
1
0
0
1
0
1
Step-up: OFF
Step-up: ON
VC: OFF
0
1
VC: ON
0
1
LCD voltage: OFF
LCD voltage: ON
S1D15E05D00B : (LCD voltage: V2, V1, MV1)
*
S1D15E06D00B : (LCD voltage: V3, V2, V1, MV1, MV2)
*
An internal clock is required to operate the built-in power supply circuit. During the operation of the built-in power
supply circuit, be sure that the internal clock is present inside.
If the built-in oscillator circuit is used, execute the built-in oscillator circuit ON command before the power control
set command. If an external oscillator circuit is used, operate the external oscillator circuit before the power control
set command.
If the internal clock is cut off during the operation of the built-in power supply circuit, display failure may occur. To
avoid this, do not cut it off.
In the slave operation mode, only the parameters (D7 to D0 : ***00000) can be used with the power control set
command. Do not use any other parameter.
100ms or more should be kept from VC regulator circuit ON to LCDV circuit ON.
Built-in oscillator ON
External oscillator input
Power Control Set
1. Step-up circuit ON
2. V regulator circuit ON
3. LCDV circuit ON*
C
A built-in oscillator used
An external oscillator used
Fig. 7.4
46
EPSON
Rev. 1.3
S1D15E05 Series
(26) Step-up CK Frequency Select
This command selects the step-up CK and step-down CK frequencies.
E
RD
R/W
WR
A0
0
D7
0
D6
1
D5
0
D4
0
D3
0
D2
0
D1
0
D0
1
1
1
0
0
Command
1
*
P6
P5
P4
*
P2
P1
P0
Register
*: denote invalid bits.
(fosc/32) is set after resetting.
Step-up CK
P6
–
P5
–
P4
–
P2
0
P1
1
P0
1
Step-up CK
fOSC/8
–
–
–
–
–
–
–
–
–
1
0
0
fOSC/16
–
–
–
1
0
1
fOSC/32
↓
1
1
0
fOSC/64
–
–
–
–
–
1
1
1
fOSC/128
It should not use the following. (P2, P1, P0) = (0, 0, 0) , (0, 0, 1) , (0, 1, 0)
Step-down CK
*
–
–
–
P6
0
P5
1
P4 *000 P2
P1
–
P0
–
Step-down CK
fOSC/8
1
0
1
0
1
–
–
–
–
–
–
1
0
–
–
fOSC/16
1
0
–
–
fOSC/32
1
1
↓
fOSC/64
–
1
1
–
–
–
–
fOSC/128
It should not use the following. (P6, P5, P4) = (0, 0, 0) , (0, 0, 1) , (0, 1, 0)
* For S1D15E06D00B , the step-down CK register is disabled.
*
(27) Liquid Crystal Drive Voltage Select
The liquid crystal drive voltage range issued from the liquid crystal drive voltage regulating circuit is selected from 3
states by this command.
E
RD
R/W
WR
VC voltage
output range
A0
0
D7
0
D6
0
D5
1
D4
0
D3
1
D2
0
D1
1
D0
1
1
1
0
0
Command
Register
1
*
*
*
*
*
*
P1
P0
*: denote invalid bits.
VC voltage
output range
P1
0
P0
0
1.77 to 3.50 V
2.53 to 5.00 V
3.54 to 7.00 V
1
0
1
1
VC voltage output range, 1.77 to 3.50V, (D1, D0) = (0, 0) is set after resetting.
Rev. 1.3
EPSON
47
S1D15E05 Series
(28) Electronic Volume
This command controls liquid crystal drive voltage VC issued from the built-in liquid crystal power supply voltage
regulating circuit, and adjusts the liquid crystal display density. For details, see the description of “6.6.2 Voltage
Regulating Circuit” in the Function Description.
E
RD
R/W
WR
A0
0
D7
1
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
1
1
1
0
0
Command
Register
1
*
P6
P5
P4
P3
P2
P1
P0
*: denote invalid bits.
• Electronic Volume Register Set
When a 7-bit data to the electronic volume register is set by this command, liquid crystal drive voltage VC assumes one
state out of voltage values in 128 states.
After this command is input, and the electronic volume register is set, the electronic volume mode is reset.
P6
0
P5
0
P4
0
P3
0
P2
0
P1
0
P0
0
VC
Smaller
0
0
0
0
0
0
1
0
0
0
0
0
1
0
↓
↓
1
1
1
1
1
1
1
1
1
1
1
1
0
1
Larger
*: denote invalid bits.
• Electronic volume register set sequence
Set Electronic Volume Mode
Set Electronic Volume Register
Reset Electronic Volume Mode
Change Completed?
No
Yes
Fig. 7.5
48
EPSON
Rev. 1.3
S1D15E05 Series
(29) Discharge ON/OFF
This command discharges the capacitors connected to the power supply circuit. This command is used when the system
power of this IC (S1D15E05 series) is turned off, and the duty is changed. See the description of (3) Power Supply OFF
and (4) Changing the Duty in the Instruction Setup: Reference.
E
RD
R/W
WR
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
Setting
0
1
0
1
1
1
0
1
0
1
Discharge OFF
Discharge ON
1
* If this command is executed when the external power supply is used, a large current may flow to damage the IC. If
external power supply is used to drive liquid crystal, be sure to turn off the external power supply before executing
this command.
(30) Power Saving
This command establishes the power save mode, thereby ensuring a substantial reduction of current consumption.
E
RD
R/W
WR
A0
D7
D6
D5
D4
D3
D2
D1
D0 Power save mode
0
1
0
1
0
1
0
1
0
0
0
1
OFF
ON
In the power save mode, display data and operation before power saving are maintained. Access to the display data
RAM from the MPU is also possible. The current consumption is reduced to the value close to static current if all
operations of the LCD display system are stopped and there is no access from the MPU.
In the power save mode, the following occurs:
Stop of oscillator circuit
Stop of LCD power supply circuit
Stop of all liquid crystal drive circuit (VSS level output is issued as the segment and common driver output).
The power save OFF command releases the power save mode. The system goes back to the state before the power save
mode.
* When the external power supply is used, it is recommended to stop the external power supply circuit function when
the power save mode is started. For example, when each level of the liquid crystal drive voltage is given from the
external resistive divider circuit, it is recommended to add a circuit to cut off the current flowing to the resistive
divider circuit when power save function is started. The S1D15E05 series has a liquid crystal display blanking
control control pin DOF, and the level goes LOW when power save function is started. You can use the DOF output
to stop the external power supply circuit function.
Rev. 1.3
EPSON
49
S1D15E05 Series
(31) Temperature Gradient Set
The 3-bit data of this command is used to set the temperature gradient characteristics of the liquid crystal drive voltage
output from the built-in power supply circuit from eight states to one state. The temperature gradient of the liquid crystal
drive voltage can be set according to the liquid crystal temperature gradient to be used. This eliminates the need of a
temperature characteristics regulating circuit to be installed outside this IC (S1D15E05 series).
E
RD
R/W
WR
Temperature
gradient [%/°C]
A0
0
D7
0
D6
1
D5
0
D4
0
D3
1
D2
1
D1
1
D0
0
1
1
0
0
Command
Register
1
*
*
*
*
*
P2
P1
P0
*: denote invalid bits.
Temperature
gradient [%/°C]
P2
0
P1
0
P0
0
–0.06
–0.08
–0.10
–0.11
–0.13
–0.15
–0.17
–0.18
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
(D7 to D0: *****000) is set after resetting. *: denote invalid bits.
(32) Status Read
This command reads out the temperature gradient select bit set on the register.
E
RD
R/W
WR
Temperature
gradient [%/°C]
A0
0
D7
1
D6
0
D5
0
D4
0
D3
1
D2
1
D1
1
D0
0
1
0
0
1
Command
Register
1
*
*
*
*
*
P2
P1
P0
*: denote invalid bits.
Temperature
gradient [%/°C]
P2
0
P1
0
P0
0
–0.06
–0.08
–0.10
–0.11
–0.13
–0.15
–0.17
–0.18
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
50
EPSON
Rev. 1.3
S1D15E05 Series
(33) Reset
This command resets the column address, page address, read modify write mode and test mode without giving adverse
effect to the display data RAM. For details, see the description of “6.8 Reset” in Function Description. Resetting is
carried out after the reset command has been input.
E
RD
R/W
WR
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
0
0
1
0
Initialization upon application of power supply is carried out by the reset signal to the RES pin. The reset command
cannot be used for this purpose.
(34) NOP
This is a Non-Operation command.
E
RD
R/W
WR
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
0
0
1
1
Note: S1D15E05 series maintains the operation status due to the command. However, when exposed to excessive
external noise, internal status may be changed. This makes it necessary to take some measures which reduces
noise generation in terms of installation or system configuration, or which protects the system against adverse
effect of noise. To cope with sudden noise, it is recommended to refresh the operation status on a periodic basis.
Rev. 1.3
EPSON
51
S1D15E05 Series
Table 7.1 Table of commands in SED15E0 series
Command code
Command
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Function
(1) Display ON/OFF
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
0
1
1
1
1
0
0
0
1
0
0
0
0
1
1
0
0
0
1
1
1
1
1
1
0
1
1
1
0
0
1
0
1
0
1
0
1
0
1
LCD display ON/OFF control.
0: OFF, 1: ON
Output level when the display is OFF and in
(2) Display OFF Mode
Select
(3) Display Normal
/Reverse
(4) Display All Lighting
ON/OFF
(5) Common Output
Status Select
the power save mode
0: VSS, 1: VC
LCD display normal/reverse
0: Normal, 1: Reverse
Display All Lighting
0: Normal display, 1: All ON
Selects COM output scan direction.
0: Normal, 1: Reverse
Sets display start line.
When the display mode is binary,
the parameter consists of two bytes.
0
1
0
(6) Display Start Line Set
0
1
1
1
1
1
0
0
0
1
Display start line address
*
*
*
*
*
*
*
↓
(7) Page Address Set
(8) Column Address Set
(9) Display Data Write
(10) Display Data Read
0
1
0
1
*
0
*
0
1
1
0
0
0
1
Sets the display RAM page address.
Page address
1
0
1
0
1
0
1
0
1
1
1
1
1
0
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
1
0
Sets the display RAM column
address.
Writes data to the display RAM.
Column Address Set
0
0
0
0
0
1
1
1
1
1
0
Writes data
0
Reads data
0
1
1
Reads data to the display RAM.
(11) Display Data Input
Direction Select
(12) Column Address Set
Direction
0
0
0
1
0
1
Display RAM data input direction
0: Column direction 1: Page direction
Compatible with display RAM
address SEG output
0
1
0
1
0
0
0: Normal 1: Reverse
(13) N-line inversion Drive
Register Set
0
1
1
1
0
0
0
*
0
*
1
*
1
0
1
1
0
Line invert drive.
Sets the line count.
Invert line count
(14) N-line ON/OFF
0
1
0
1
1
1
0
0
1
0
0
1
Resets the line invert drive.
0: N-line OFF 1: N-line ON
(15) Display Mode
0
1
0
1
1
1
1
1
0
0
0
0
0
*
0
1
*
0
1
*
1
0
*
1
0
*
1
1
*
0
1
0
00: 4 gray-scale, 01: binary
Mode
0
(16) Gray-scale Pattern Set
1
Selects the contrast of gray-scale
bit (1,0) (0,1).
Gray-scale pattern
(17) Area Scroll
Scroll Mode
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
*
0
*
0
*
1
*
0
*
0
*
0
0
Mode
When the display mode is binary,
the end address consists of
two bytes.
Scroll Start address
Scroll End address
Display page count
Start address
End address
Display page count
(18) Duty Set Command
Duty Set
0
1
0
0
*
*
1
*
*
1
0
1
1
0
1
Duty count
Static spot (block)
Static spot (block) set
(19) Partial Display
ON/OFF
(20) Partial Display Set
Display Start line
Display Line count
(21) Read Modify Write
0
0
1
1
0
0
1
0
0
1
0
1
1
0
1
Partial display ON/OFF
0: OFF, 1: ON
0
0
1
1
0
0
1
0
0
0
Start line
Line count
1
0
1
0
1
1
0
0
0
0
Increments the column address.
Increments +1 in the write mode.
Does not increment in the read mode.
Resets read modify write functions.
Built-in oscillator circuit operation
0: OFF, 1: ON
(22) End
(23) Built-in Oscillator
Circuit ON/OFF
0
0
1
1
0
0
1
1
1
0
1
1
0
0
1
1
1
0
1
1
0
1
(24) Built-in Oscillator
Circuit Frequency Select
0
1
1
1
0
0
0
*
1
*
0
*
1
*
1
1
1
1
Frequency
(25) Power Control Set
0
1
1
1
0
0
0
*
0
*
1
0
0
1
0
1
Selects built-in power supply
Operation state operation state.
52
EPSON
Rev. 1.3
S1D15E05 Series
Command code
Command
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Function
(26) Step-up CK
Frequency Select
0
1
1
1
0
0
0
*
1
0
0
0
0
0
1
Frequency
(27) Liquid Crystal Drive
Voltage Select
0
1
1
1
0
0
0
*
0
*
1
*
0
*
1
*
0
*
1
1
VC range
(28) Electronic Volume
Mode Set
Electronic Volume
Register Set
(29) Discharge ON/OFF
0
1
0
1
1
1
0
0
0
1
*
1
0
0
0
0
0
0
1
Electronic volume
VC output voltage is set to the
electronic volume register. 128 states
Discharges Power supply circuit
connection capacitor.
0: OFF (normal), 1: ON
1
1
0
1
0
1
0
1
(30) Power Save ON/OFF
(31) Temperature
Gradient Select
0
0
1
1
1
1
0
0
0
1
0
*
0
1
*
1
0
*
0
0
*
1
1
*
0
1
0
1
0
0
Power Save 0: OFF, 1: ON
Sets to 8 steps.
Temperature gradient
(32) Stator Read
0
1
1
0
0
1
1
*
0
*
0
*
0
*
1
1
1
0
Issues the temperature gradient
*Temperature gradient select bit.
(33) Reset
0
1
0
1
1
1
0
0
0
1
0
Resets the column, page and
address registers.Resets the read
modify write function.
(34) NOP
0
1
0
1
1
1
0
0
0
1
1
Non-operation command
Rev. 1.3
EPSON
53
S1D15E05 Series
Instruction Setup Example (Reference)
(1) Initial setup
VDD - VSS power turns on when RES terminal = LOW.
Stable power supply
*1
Release the reset state. (RES terminal = HIGH)
Function setup by command entry (set by users)
(12) Column address set direction
(5) Common output status select
(3) Display normal/reverse
(4) Display all lighting ON/OFF
(18) Set the duty
(2) Display OFF mode select
(27) LCD voltage select
(28) Electronic volume
(31) Temperature gradient set
(When the n-line invert drive is not used)
Function setup by command entry (set by users)
(13) n-line invert drive register set
(14) n-line ON/OFF
(When the external oscillator circuit is used)
Enter the external clock
Function setup by command entry (set by users)
(24) Built-in oscillator circuit frequency select
(23) Built-in oscillator circuit ON/OFF
(When the external LCD power supply circuit is used)
External LCD power supply entry
Function setup by command entry (set by users)
(25) Power control set
1. Step-up circuit ON
2. VC regulator circuit ON
3. LCDV circuit ON*2
Initialization completed
Note: *1 DDRAM contents are not determined even in the initialized state after resetting. See “6.7 Reset Circuit”
in the “6. Function Description”.
*2 100ms or more should be kept from VC regulator circuit ON to LCDV circuit ON.
* Numerals in the command parenthesis correspond to the numerals of the items in Command Description.
54
EPSON
Rev. 1.3
S1D15E05 Series
(2) Data display
End of initialization
Function setup by command entry (set by users)
(6) Display start line set
(7) Page address set
(8) Column address set
Function setup by command entry (set by users)
(9) Display data write
Function setup by command entry (set by users)
(1) Display ON/OFF command
End of data display
Note:
* DDRAM contents are not determined after end of initialization. Write data to all the DDRAM used for
display. See “9. Display data write” in the “7. Command Description”.
(3) Power OFF
A desired state
Function setup by command entry (set by users)
(30) Power save ON
(When an external LCD power supply circuit is used)
External LCD power supply OFF
(When the built-in power supply circuit is used)
Function setup by command entry (set by users)
(29) Discharge ON/OFF
Reset state (RES terminal = LOW)
Set the time (t
DD-VSS power supply liquid crystal drive potential (MV
that it is longer than the time (t ) where it is reduced below the
threshold value of the LCD panel.
L
) between entry into the reset state and turning off of
V
1
,V ,V ,V ) so
C
1
2
H
V
DD - VSS power supply OFF
Note:
* This IC controls the circuit of the liquid crystal drive power supply system using the VDD-VSS power supply
circuit. If the VDD-VSS power supply is cut off with voltage remaining in the liquid crystal drive power
supply system, voltage not controlled will be issued from the SEG and COM pins, and this may result in
display failure. To avoid this, follow the above-mentioned power off sequence.
Rev. 1.3
EPSON
55
S1D15E05 Series
(4) How to change the duty
A desired state
Function setup by command entry (set by users)
(1) Displya OFF
Function setup by command entry (set by users)
(30) Power save ON
Function setup by command entry (set by users)
(29) Discharge ON
Function setup by command entry (set by users)
(28) Electronic volume
Secure an interval of
30ms or more between
discharge ON to
(24) Built-in oscillator circuit frequency select
(18) Duty set
When the n-line reversing command is used :
(13) n-line reverse drive register set
discharge OFF .
Function setup by command entry (set by users)
(29) Discharge OFF
Function setup by command entry (set by users)
(30) Power save OFF
End of duty change
Note:
* Execution of the above sequence causes display to be turned off temporarily (for the time from Power
Saving command ON to Power Saving command OFF plus 200 ms (frame frequency 60Hz) upon switching
of the duty. Temporary display failure may occur if Duty Change command is executed during liquid
crystal display without executing the above-mentioned setup example. Follow the setup example when the
duty is changed as discussed above.
(5) Refresh
It is recommended that the operating modes and display contents be refreshed periodically to prevent the effect of
unexpected noise.
Refresh sequence
NOP command
Set all commands to the ready state
(Including default state setting.)
Refreshing of DRAM
56
EPSON
Rev. 1.3
S1D15E05 Series
8. ABSOLUTE MAXIMUM RATINGS
8.1 S1D15E05D00B
Table 8.1
*
VSS = 0V unless otherwise specified.
Item
Power voltage (1)
Symbol
Specified value
–0.3 to +4.0
–0.3 to +17.0
–0.3 to V2
Unit
VDD
V2, VOUT
V1, VC, MV1
VIN
V
Power voltage (2)
Power voltage (3)
Input voltage
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–40 to +85
Output voltage
VO
Operating temperature
Storage temperature
TOPR
°C
TCP
TSTR
–55 to +100
–55 to +125
bare chip
V2
VOUT
VC
V1, MV1
V
CC
V
DD
SS
GND
V
System (MPU) side
S1D15E05 side
Fig. 8.1
Notes: 1. Voltages V2, V1, VC, MV1 and MV2 (VSS) must always meet the conditions of V2≥V1≥VC≥MV1≥MV2
(VSS).
2. Voltage VOUT must always meet the conditions of VOUT≥VDD and VOUT≥VC.
3. If the LSI has been used in excess of the absolute maximum rating, it may be subjected to permanent
breakdown. So in the normal operation, the LSI is preferred to be used under the condition of electrical
characteristics. If this condition is not met, LSI operation error may occur and LSI reliability may be
deteriorated.
Rev. 1.3
EPSON
57
S1D15E05 Series
8.2 S1D15E06D00B
Table 8.2
*
VSS = 0V unless otherwise specified.
Item
Power voltage (1)
Power voltage (2)
Power voltage (3)
Input voltage
Symbol
Specified value
–0.3 to +4.0
–0.3 to +17.0
–0.3 to V3
Unit
VDD
V
V3, VOUT
V2, V1, VC, MV1, MV2
VIN
VO
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–40 to +85
Output voltage
Operating temperature
Storage temperature
TOPR
TSTR
°C
TCP
–55 to +100
–55 to +125
bare chip
V
3
V
OUT
V
C
V2, V1,MV1,MV2
V
CC
V
V
DD
SS
GND
System (MPU) side
S1D15E06 side
Fig. 8.2
Notes: 1. Voltages V3, V2, V1, VC, MV1, MV2 and MV3 (VSS) must always meet the conditions of
V3≥V2≥V1≥VC≥MV1≥MV2≥MV3 (VSS).
2. Voltage VOUT must always meet the conditions of VOUT≥VDD and VOUT≥VC.
3. If the LSI has been used in excess of the absolute maximum rating, it may be subjected to permanent
breakdown. So in the normal operation, the LSI is preferred to be used under the condition of electrical
characteristics. If this condition is not met, LSI operation error may occur and LSI reliability may be
deteriorated.
58
EPSON
Rev. 1.3
S1D15E05 Series
9. DC CHARACTERISTICS
VSS = 0V, VDD = 2.7V ± 10% and Ta = –40 to +85°C unless otherwise specified.
Table 9.1
Specified value
Applicable
Item
Symbol
Conditions
Unit
pin
Min.
Typ.
—
Max.
Working voltage (1) Operation enabled VDD
Working voltage (2) Operation recommended VOUT
1.7
3.6
V
VDD *1
VOUT
VDD
—
14.0
Working voltage (3) Operation enabled
Operation enabled
V2
VC
V1
Applicable to
S1D15E05
3.4
1.7
VC
—
—
—
—
14.4
7.2
V2
V2 *2
VC
V1
Operation enabled
Operation enabled MV1
VSS
VC
MV1
Working voltage (4) Operation enabled
V3
VC
V2
V1
Applicable to
S1D15E06
3.4
1.7
VC
VC
VSS
VSS
—
—
—
—
—
—
14.4
7.2
V3
V3
VC
V3 *3
VC
V2
V1
MV1
MV2
Operation enabled
Operation enabled
Operation enabled
Operation enabled MV1
Operation enabled MV2
VC
High-level input voltage
Low-level input voltage
VIHC VDD=1.8V to 3.3V
VILC
0.8×VDD
VSS
—
—
VDD
0.2×VDD
*4
*4
High-level output voltage
Low-level output voltage
VOHC VDD=1.8V
I
OH=–0.25mA 0.8×VDD
—
—
VDD
0.2×VDD
*5
*5
VOLC
to 3.3V
IOL=0.25mA
VSS
Input leak current
Output leak current
ILI
ILO
VIN=VDD or VSS
–1.0
–3.0
—
—
1.0
3.0
µA
kΩ
kΩ
µA
µA
*6
*7
LCD driver ON resistance (1)
(S1D15E05)
RON
RON
Ta=25°C V2=7.2V
—
—
1.5
3.0
2.3
4.6
SEGn
COMn *8
V2=4.8V
LCD driver ON resistance (2)
(S1D15E06)
Ta=25°C V3=7.2V
—
—
1.5
3.0
2.3
4.6
SEGn
COMn *8
V3=4.8V
Static current consumption (1)
(S1D15E05)
IDDQ Ta=25°C VDD=3.3V
I2Q V2=10.0V
—
—
0.2
1.0
5.0
5.0
VDD
V2
Static current consumption (2)
(S1D15E06)
IDDQ Ta=25°C VDD=3.3V
I3Q
—
—
0.2
1.0
5.0
5.0
VDD
V3
V3=14.0V
Input pin capacity
CIN
Ta=25°C, f=1MHz
—
20
25
pF
Oscillation
frequency
Built-in oscillation
fOSC Ta=25°C
Max. frequency
110
120
130
kHz
*9
[* See the description on P.67.]
Rev. 1.3
EPSON
59
S1D15E05 Series
Table 9.2
Specified value
Applicable
pin
Item
Symbol
Conditions
Unit
Min.
Typ.
Max.
Input voltage
VDD
VDD
Double step-up
Triple step-up
1.7
1.7
—
—
3.6
3.6
V
VDD
Boosted output voltage
VOUT
VC
—
—
—
14.0
7.0
VOUT
Working voltage for voltage
control circuit
1.8
VC *10
Dynamic current consumption (1): Built-in power is turned on during display.
Ta=25°C
This is the current consumed by the entire IC including the built-in power supply.
Display mode in 4 gray-scale at fFR = 80Hz
Table 9.3.1 Display entirely in white (S1D15E05)
Code: ISS (1)
DUTY
1/100 DUTY 1/64
VDD Boosting V2 Voltage
Unit Remarks
µA *11
Typ.
36
Max.
60
Typ.
Max.
57
1.8V
2.7V
3.6V
Double
Triple
6V
8V
6V
8V
6V
8V
34
50
35
40
40
50
52
86
84
Double
46
76
58
51
85
67
None
50
83
68
Double
61
101
84
Table 9.3.2 Display entirely in white (S1D15E06)
Code: ISS (1)
1/132 DUTY 1/100 DUTY
VDD Boosting V3 Voltage
Unit Remarks
Typ.
68
Max.
112
134
121
154
Typ.
67
Max.
111
117
104
137
2.7V
Triple
10V
12V
10V
12V
µA
*11
81
71
3.6V
Double
Triple
73
63
93
83
[* See the description on P.67.]
60
EPSON
Rev. 1.3
S1D15E05 Series
Display mode in 4 gray-scale at fFR = 80Hz
Table 9.4.1 Display: Heavy load display (S1D15E05D00B )
*12 Code: ISS (1)
*
1/100 DUTY 1/64
DUTY
VDD Boosting V2 Voltage
Unit Remarks
µA *11
Typ.
101
160
122
142
92
Max. Typ.
Max.
114
194
154
177
117
150
1.8V
2.7V
3.6V
Double
Triple
6V
8V
6V
8V
6V
8V
167
265
202
235
154
235
68
116
93
Double
107
70
None
Double
142
90
Table 9.4.2 Display: Heavy load display (S1D15E06D00B )
Code: ISS (1)
*
1/132 DUTY 1/100 DUTY
VDD Boosting V3 Voltage
Unit Remarks
Typ.
241
373
189
380
Max.
400
619
313
630
Typ.
187
313
146
314
Max.
310
519
242
521
2.7V
3.6V
Triple
10V
12V
10V
12V
µA
*11
Double
Triple
Display mode in binary at fFR = 60Hz
Table 9.5.1 Display entirely in white (S1D15E05) Code: ISS (1)
1/100 DUTY 1/64
DUTY
Max.
42
VDD Boosting V2 Voltage
Unit Remarks
µA *11
Typ.
26
Max. Typ.
1.8V
2.7V
3.6V
Double
Triple
6V
8V
6V
8V
6V
8V
43
66
51
58
54
68
25
38
29
33
26
40
40
47
48
55
44
67
Double
31
35
None
32
Double
41
Table 9.5.2 Display entirely in white (S1D15E06) Code: ISS (1)
1/132 DUTY 1/100 DUTY
VDD Boosting V3 Voltage
Unit Remarks
Typ.
65
Max.
108
120
95
Typ.
50
Max.
83
2.7V
3.6V
Triple
10V
12V
10V
12V
µA
*11
72
56
93
Double
Triple
57
44
73
82
136
63
104
[* See the description on P.67.]
Rev. 1.3
EPSON
61
S1D15E05 Series
Display mode in binary at fFR = 60Hz
Table 9.6.1 Display Heavy load display (S1D15E05) Code: ISS (1)
1/100 DUTY 1/64
DUTY
Max.
87
VDD Boosting V2 Voltage
Unit Remarks
µA *11
Typ.
58
Max. Typ.
1.8V
2.7V
3.6V
Double
Triple
6V
8V
6V
8V
6V
8V
96
52
93
52
63
46
78
102
68
170
112
136
100
152
155
86
Double
82
104
77
None
60
Double
92
130
Table 9.6.2 Display Heavy load display (S1D15E06) Code: ISS (1)
1/132 DUTY 1/100 DUTY
VDD Boosting V3 Voltage
Unit Remarks
Typ.
188
313
150
322
Max.
312
520
249
534
Typ.
135
226
108
232
Max.
224
300
143
308
2.7V
3.6V
Triple
10V
12V
10V
12V
µA *11
Double
Triple
Current consumption under power saving mode: VSS = 0V, VDD = 3.3V, Ta = 25°C
Table 9.7.1 (S1D15E05)
Specified value
Min. Typ. Max.
Item
Symbol
Condition
Condition
Unit Remarks
Sleep state
IDDS1
—
0.2
5
µA
Table 9.7.2 (S1D15E06)
Specified value
Min. Typ. Max.
Item
Symbol
Unit Remarks
Sleep state
IDDS1
—
0.2
5
µA
[* See the description on P.67.]
62
EPSON
Rev. 1.3
S1D15E05 Series
[Reference Data 1]
• Dynamic current consumption (1)-1 during LCD display when internal power is used (S1D15E05)
Conditions:
Built-in power supply “ON”
1/100DUTY
fFR = 80Hz
Indication pattern: Totally white / Checker
Ta = 25°C
Remarks: *11
Fig. 9.1
• Dynamic current consumption (1)-2 during LCD display when internal power is used (S1D15E06)
Conditions:
Built-in power supply “ON”
1/132DUTY
fFR = 80Hz
Triple boosting
4 gray-scale
Display mode :
Indication pattern: Totally white / Checker
Ta = 25°C
Remarks: *11
Fig. 9.2
[* See the description on P.67.]
Rev. 1.3
EPSON
63
S1D15E05 Series
[Reference Data 2]
• Dynamic current consumption (2)-1 during LCD display when internal power is used (S1D15E05)
Conditions:
VDD = 2.7V
Built-in power supply “ON”
Double boosting
fFR = 80Hz
Display mode :
4 gray-scale
Indication pattern: Totally white / Checker
Ta = 25°C
Remarks: *11
Fig. 9.3
• Dynamic current consumption (2)-2 during LCD display when internal power is used (S1D15E06)
Conditions:
VDD = 2.7V
Built-in power supply “ON”
Triple boosting
fFR = 80Hz
Display mode :
4 gray-scale
Indication pattern : Totally white / Checker
Ta = 25°C
Remarks: *11
Fig. 9.4
[* See the description on P.67.]
64
EPSON
Rev. 1.3
S1D15E05 Series
[Reference Data 3]
• Dynamic current consumption (3)-1 during access
(S1D15E05)
Indicates the current consumption when the checker
pattern is always written by fCYC. When not
accessed, only ISS(1) remains.
10
1
Conditions: Built-in voltage used
Double boosting
V2= 8.0V, VDD = 2.7V
Ta = 25°C
fFR=80Hz 1/100 Duty
0.1
0.01
0.001
0.01
0.1
1
10
f
CYC [MHz]
Fig. 9.5
• Dynamic current consumption (3)-2 during access
(S1D15E06)
Indicates the current consumption when the checker
pattern is always written by fCYC. When not
accessed, only ISS(1) remains.
10
1
Conditions: Built-in voltage used
Triple boosting
V3= 12.0V, VDD = 2.7V
Ta = 25°C
fFR=80Hz 1/132 Duty
0.1
0.01
0.001
0.01
0.1
1
10
f
CYC [MHz]
Fig. 9.6
Rev. 1.3
EPSON
65
S1D15E05 Series
[Reference Data 4]
• VDD and V2 system operating voltage range
(S1D15E05)
14.0
Remarks: *2
10.5
Operating range
7.0
3.5
3.4
0
1.7
3.6
0
1
2
3
4
VDD [V]
Fig. 9.7
• VDD and V3 system operating voltage range
(S1D15E06)
14.0
Remarks: *3
10.5
Operating range
7.0
3.5
3.4
0
1.7
3.6
0
1
2
3
4
VDD [V]
Fig. 9.8
[* See the description on P.67.]
66
EPSON
Rev. 1.3
S1D15E05 Series
• Relationship between oscillation frequency fOSC, display clock frequency fCL and liquid crystal frame fFR
Table 9.8
Item
fCL
Display mode
fFR
Built-in oscillator
circuit used
See p. 31
Binary display
4 gray-scale
(fCL × DUTY)/4
(fCL × DUTY)/8
Built-in oscillator circuit
not used
External input (fCL)
Binary display
4 gray-scale
(fCL × DUTY)/4
(fCL × DUTY)/8
(fFR indicates the cycle of rewriting one screen; it does not indicate FR signal cycle.)
[Asterisked references]
*1.
*2.
Does not guarantee if there is an abrupt voltage variation during MPU access.
For VDD and V2 system operating voltage range, see Fig. 9.5.
Applicable when the external power supply is used.
*3.
*4.
For VDD and V3 system operating voltage range, see Fig. 9.6.
Applicable when the external power supply is used.
A0, D0 to D5, D6(SCL), D7(SI), RD(E), WR(R/W), CS1, CS2, CLS, CL, FR, F1, F2, CA, M/S, C86, P/S, DOF,
RES and TEST pins
*5.
*6.
*7.
*8.
D0 to D7, FR, DOF, CL, F1, F2 and CA pins
A0, RD(E), WR(R/W), CS1, CS2, CLS, M/S, C86, P/S, RES and TEST pins
Applicable when D0 to D5, D6(SCL), D7(S1), CL, FR, DOF, F1, F2 and CA pins have a high impedance.
Indicates the resistance when 0.1V voltage is applied between the output pin SEGn or COMn and each power
supply (V2, V1, VC, MV1, MV2).
RON =0.1V/∆I (where ∆I denotes current when 0.1V is applied when power is on).
For the relationship between oscillation frequency and frame frequency, see Table 9.6. The standard values of
the external input item are recommended ones.
*9.
*10. The VC voltage regulating circuit should be adjusted within the electronic volume operation range.
*11. Indicates the current consumed by a single IC when display is on. Use the electronic volume for voltage
regulation. Also use the internal oscillator circuit. The current due to LCD panel capacity and wiring capacity
is not included. Applicable when there is access from the MPU.
*12. Heavy load indicates the load where the maximum current is consumed as a display pattern.
Rev. 1.3
EPSON
67
S1D15E05 Series
10. TIMING CHARACTERISTICS
(1) System path read/write characteristics 1 (80 system MPU)
A0
t
AW8
t
AH8
CS1
(CS2=“1”)
t
CYC8
*1
t
CCLR, tCCLW
WR, RD
t
CCHR, tCCHW
CS1
(CS2=“1”)
t
f
t
r
*2
WR, RD
t
DS8
t
DH8
D0 to D7
(Write)
t
ACC8
t
OH8
D0 to D7
(Read)
Fig. 10.1
Table 10.1.1
[VDD = 3.0V to 3.6V, Ta = –40 to +85°C]
Specified value
Parameter
Signal Symbol
Condition
Unit
Min.
Max.
Address hold time
Address setup time
A0
tAH8
tAW8
0
0
—
—
ns
System write cycle time
System read cycle time
WR
RD
tWCYC8
tRCYC8
200
300
—
—
Control LOW-pulse width (Write)
WR
RD
WR
RD
tCCLW
tCCLR
tCCHW
tCCHR
60
100
60
—
—
—
—
Control LOW-pulse width (Read)
Control HIGH-pulse width (Write)
Control HIGH-pulse width (Read)
100
Data setup time
Data hold time
D0 to D7
tDS8
tDH8
20
10
—
—
RD access time
Output disable time
tACC8
tOH8
CL=100pF
—
10
80
80
68
EPSON
Rev. 1.3
S1D15E05 Series
Table 10.1.2
[VDD = 2.4V to 3.0V, Ta = –40 to +85°C]
Specified value
Parameter
Signal Symbol
Condition
Unit
Min.
Max.
Address hold time
Address setup time
A0
tAH8
tAW8
0
0
—
—
ns
System write cycle time
System read cycle time
WR
RD
tWCYC8
tRCYC8
300
400
—
—
Control LOW-pulse width (Write)
Control LOW-pulse width (Read)
Control HIGH-pulse width (Write)
Control HIGH-pulse width (Read)
WR
RD
WR
RD
tCCLW
tCCLR
tCCHW
tCCHR
80
200
80
—
—
—
—
200
Data setup time
Data hold time
D0 to D7
tDS8
tDH8
30
15
—
—
RD access time
Output disable time
tACC8
tOH8
CL=100pF
—
10
120
120
Table 10.1.3
Parameter
[VDD = 1.7V to 2.4V, Ta = –40 to +85°C]
Specified value
Signal Symbol
Condition
Unit
Min.
Max.
Address hold time
Address setup time
A0
tAH8
tAW8
0
0
—
—
ns
System write cycle time
System read cycle time
WR
RD
tWCYC8
tRCYC8
400
600
—
—
Control LOW-pulse width (Write)
Control LOW-pulse width (Read)
Control HIGH-pulse width (Write)
Control HIGH-pulse width (Read)
WR
RD
WR
RD
tCCLW
tCCLR
tCCHW
tCCHR
100
250
140
250
—
—
—
—
Data setup time
Data hold time
D0 to D7
tDS8
tDH8
40
20
—
—
RD access time
Output disable time
tACC8
tOH8
CL=100pF
—
10
200
200
*1. This is in case of making the access by WR and RD, setting the CS1 = LOW.
*2. This is in case of making the access by CS1, setting the WR, RD = LOW.
*3. Input signal rise and fall time (tr, tf) must not exceed 15 ns. When the system cycle time is used at a high speed,
it is specified by (tr + tf) ≤ (tCYC8 – tCCLW – tCCHW) or (tr + tf) ≤ (tCYC8 – tCCLR – tCCHR).
*4. Timing is entirely specified with reference to 20% or 80% of VDD.
*5. tCCLW and tCCLR are specified in terms of the overlapped period when CS1 is at LOW (CS2 = HIGH) level and
WR and RD are at LOW level.
Rev. 1.3
EPSON
69
S1D15E05 Series
(2) System path read/write characteristics 2 (68 system MPU)
A0
R/W
tAW6
tAH6
CS1
(CS2=“1”)
tCYC6
*1
tEWHR, tEWHW
E
tEWLR, tEWLW
CS1
(CS2=“1”)
*2
tf
tr
E
tDS6
tDH6
D0 to D7
(Write)
tACC6
tOH6
D0 to D7
(Read)
Fig. 10.2
Table 10.2.1
[VDD = 3.0V to 3.6V, Ta = –40 to +85°C]
Specified value
Parameter
Signal Symbol
Condition
Unit
Min.
Max.
Address hold time
Address setup time
A0
E
tAH6
tAW6
tWCYC6
tRCYC6
0
0
—
—
ns
System write cycle time
System read cycle time
200
300
—
—
Data setup time
Data hold time
D0 to D7
tDS6
tDH6
20
10
—
—
Access time
Output disable time
tACC6
tOH6
CL=100pF
—
10
80
80
Enable HIGH-pulse width Read
Write
E
E
tEWHR
tEWHW
tEWLR
tEWLW
100
60
—
—
Enable LOW-pulse width Read
Write
100
60
—
—
70
EPSON
Rev. 1.3
S1D15E05 Series
Table 10.2.2
[VDD = 2.4V to 3.0V, Ta = –40 to +85°C]
Specified value
Parameter
Signal Symbol
Condition
Unit
Min.
Max.
Address hold time
Address setup time
A0
E
tAH6
tAW6
tWCYC6
tRCYC6
0
0
—
—
ns
System write cycle time
System read cycle time
300
400
—
—
Data setup time
Data hold time
D0 to D7
tDS6
tDH6
30
15
—
—
Access time
Output disable time
tACC6
tOH6
CL=100pF
—
10
120
120
Enable HIGH-pulse width Read
Write
E
E
tEWHR
tEWHW
tEWLR
tEWLW
150
80
—
—
Enable LOW-pulse width Read
Write
150
80
—
—
Table 10.2.3
Parameter
[VDD = 1.7V to 2.4V, Ta = –40 to +85°C]
Specified value
Signal Symbol
Condition
Unit
Min.
Max.
Address hold time
Address setup time
A0
E
tAH6
tAW6
tWCYC6
tRCYC6
0
0
—
—
ns
System write cycle time
System read cycle time
400
600
—
—
Data setup time
Data hold time
D0 to D7
tDS6
tDH6
40
20
—
—
Access time
Output disable time
tACC6
tOH6
CL=100pF
—
10
200
200
Enable HIGH-pulse width Read
Write
E
E
tEWHR
tEWHW
250
100
—
—
Enable LOW-pulse width Read
Write
tEWLR
250
140
—
—
tEWLW
*1 This is in case of making the access by E, setting the CS1 = LOW.
*2 This is in case of making the access by CS1, setting the E = HIGH.
*3 The rise time and the fall time (tr & tf) of the input signals should be set to 15ns or less. When it is necessary to
use the system cycle time at high speed, the rise time and the fall time should be so set to conform
to (tr+tf) ≤ (tCVC6-tEWLW-tEWHW) or (tr+tf) ≤ (tCYC6-tEWLR-tEWHR).
*4 All the timing should basically be set to 20% and 80% of the “VDD”.
*5 tEWLW, tEWLR should be set to the overlapping zone where the CS1 is on the LOW level (CS2 = HIGH level) and
where the E is on the HIGH level.
Rev. 1.3
EPSON
71
S1D15E05 Series
(3) Serial interface
CS1
tCSS
tCSH
(CS2=“1”)
tSAS
tSAH
A0
tSCYC
tSLW
SCL
tSHW
tf
tr
tSDS
tSDH
SI
Figure 10.3
Table 10.3.1
[VDD = 3.0V to 3.6V, Ta = –40 to +85°C]
Specified value
Parameter
Signal Symbol
Condition
Unit
Min.
Max.
Serial clock period
SCL HIGH pulse width
SCL LOW pulse width
SCL
tSCYC
tSHW
tSLW
100
40
40
—
—
—
ns
Address setup time
Address hold time
A0
SI
tSAS
tSAH
tSDS
tSDH
80
80
—
—
Data setup time
Data hold time
20
20
—
—
CS-SCL time
CS
tCSS
tCSH
80
150
—
—
72
EPSON
Rev. 1.3
S1D15E05 Series
Table 10.3.2
[VDD = 2.4V to 3.0V, Ta = –40 to +85°C]
Specified value
Parameter
Signal Symbol
Condition
Unit
Min.
Max.
Serial clock period
SCL HIGH pulse width
SCL LOW pulse width
SCL
tSCYC
tSHW
tSLW
125
50
50
—
—
—
ns
Address setup time
Address hold time
A0
SI
tSAS
tSAH
tSDS
tSDH
100
100
—
—
Data setup time
Data hold time
30
30
—
—
CS-SCL time
CS
tCSS
tCSH
100
200
—
—
Table 10.3.3
Parameter
[VDD = 1.7V to 2.4V, Ta = –40 to +85°C]
Specified value
Signal Symbol
Condition
Unit
Min.
Max.
Serial clock period
SCL HIGH pulse width
SCL LOW pulse width
SCL
tSCYC
tSHW
tSLW
154
60
60
—
—
—
ns
Address setup time
Address hold time
A0
SI
tSAS
tSAH
tSDS
tSDH
120
140
—
—
Data setup time
Data hold time
40
40
—
—
CS-SCL time
CS
tCSS
tCSH
120
350
—
—
*1. Input signal rise and fall time (tr, tf) must not exceed 15 ns.
*2. Timing is entirely specified with reference to 20% or 80% of VDD.
Rev. 1.3
EPSON
73
S1D15E05 Series
(4) Display control output timing
CL
(OUT)
t
DFR
FR
F1, F2
CA
t
DF1,F2
t
DCA
Fig. 10.4
Table 10.4.1
Parameter
[VDD = 3.0V to 3.6V, Ta = –40 to +85°C]
Specified value
Unit
Signal Symbol
Condition
Min.
—
Typ.
125
125
125
Max.
312
312
312
FR delay time
F1, F2 delay time
CA delay time
FR
F1, F2 tDF1, tF2
CA tDCA
tDFR
CL = 50pF
ns
ns
ns
—
—
Table 10.4.2
Parameter
[VDD = 2.3V to 2.8V, Ta = –40 to +85°C]
Specified value
Unit
Signal Symbol
Condition
Min.
—
Typ.
150
150
150
Max.
360
360
360
FR delay time
F1, F2 delay time
CA delay time
FR
F1, F2 tDF1, tF2
CA tDCA
tDFR
CL = 50pF
ns
ns
ns
—
—
Table 10.4.3
Parameter
[VDD = 1.8V to 2.3V, Ta = –40 to +85°C]
Specified value
Unit
Signal Symbol
Condition
Min.
—
Typ.
225
225
225
Max.
514
514
514
FR delay time
F1, F2 delay time
CA delay time
FR
F1, F2 tDF1, tF2
CA tDCA
tDFR
CL = 50pF
ns
ns
ns
—
—
*1. Valid only in master operation
*2. Timing is entirely specified with reference to 20% or 80% of VDD.
74
EPSON
Rev. 1.3
S1D15E05 Series
(5) Reset input timing
t
RW
RES
t
R
Internal state
During resetting
Fig. 10.5
End of resetting
Table 10.5.1
Parameter
[VDD = 3.0V to 3.6V, Ta = –40 to +85°C]
Specified value
Unit
Signal Symbol
Condition
Min.
Typ.
Max.
Reset time
tR
—
—
0.5
µs
Reset LOW pulse width
RES
tRW
0.5
—
—
Table 10.5.2
Parameter
[VDD = 2.4V to 3.0V, Ta = –40 to +85°C]
Specified value
Unit
Signal Symbol
Condition
Min.
Typ.
Max.
Reset time
tR
—
—
1.0
µs
Reset LOW pulse width
RES
tRW
1.0
—
—
Table 10.5.3
Parameter
[VDD = 1.7V to 2.4V, Ta = –40 to +85°C]
Specified value
Unit
Signal Symbol
Condition
Min.
Typ.
Max.
Reset time
tR
—
—
1.5
µs
Reset LOW pulse width
RES
tRW
1.5
—
—
*1. Timing is entirely specified with reference to 20% or 80% of VDD.
Rev. 1.3
EPSON
75
S1D15E05 Series
11. MPU INTERFACE (Reference Example)
The S1D15E05 series can be connected to the 80 series MPU and 68 series MPU. Use of a serial interface allows
operation with a smaller number of signal lines.
You can expand the display area using the S1D15E05 series as a multi-chip. In this case, the IC to be accesses can be
selected individually by the chip select signal. After initialization by the RES pin, each input terminal of the S1D15E05
series must be placed under normal control.
(1) 80 series MPU
VDD
V
CC
VDD
C86
P/S
A0
A0
A1 to A7
IORQ
CS1
CS2
Decoder
RESET
D0 to D7
RD
D0 to D7
RD
WR
RES
WR
RES
GND
VSS
V
SS
Fig. 11.1
(2) 68 series MPU
VDD
V
CC
VDD
C86
P/S
A0
A0
A1 to A15
VMA
CS1
CS2
Decoder
RESET
D0 to D7
E
D0 to D7
E
R/W
R/W
RES
RES
GND
V
SS
V
SS
Fig. 11.2
(3) Serial interface
Fig. 11.3
V
DD
VCC
VDD
C86
A0
A0
VDD or VSS
CS1
CS2
A1 to A7
Decoder
RESET
Port 1
Port 2
RES
SI
SCL
RES
P/S
GND
V
SS
VSS
76
EPSON
Rev. 1.3
S1D15E05 Series
12. CONNECTION BETWEEN LCD DRIVERS (Reference example)
You can easily expand the liquid crystal display area using the S1D15E05 series as a multi-chip. In this case, use the
same model (S1D15E05*****/S1D15E05*****) or (S1D15E06*****/S1D15E06*****) as the master and
slave systems.
S1D15E05 (Master)
S1D15E05 (Slave)
V
DD
V
SS
V
DD
M/S
M/S
CL
FR
DOF
F1
CL
FR
DOF
F1
F2
F2
CA
CA
CLS
CLS
V
V
2
1
V
V
V
2
1
C
V
C
MV
(VSS) MV
1
2
MV
MV
1
2
(VSS
)
Fig. 12 Master/slave connection example (S1D15E05)
Rev. 1.3
EPSON
77
S1D15E05 Series
13. LCD PANEL WIRING (Reference example)
You can easily expand the liquid crystal display area using the S1D15E05 series as a multi-chip. In the case of multi-
chip configuration, use the same models.
(1) Single chip configuration example
160 x 132 Dots
COM
SEG
COM
S1D15E06
Master
Fig. 13.1 Single chip configuration example (S1D15E06)
(2) Double chip configuration example
320 x 132 Dots
COM
SEG
SEG
COM
S1D15E06 Series
Master
S1D15E06 Series
Slave
Fig. 13.2 Double chip configuration example (S1D15E06)
78
EPSON
Rev. 1.3
S1D15E05 Series
14. S1D15E05T00A TCP PIN LAYOUT
*
Note: This does not specify the TCP outside shape.
Reference
COM131
COM130
VSS
FR
CL
COM129
COM128
DOF
F1
F2
•
•
•
•
•
CA
TEST
CS1
RES
A0
WR, R/W
RD, E
CS2
M/S
COM 67
COM 66
CLS
C86
P/S
SEG 159
SEG 158
D0
D1
D2
D3
D4
D5
•
•
•
•
•
•
D6, SCL
D7, SI
V
SS
DD
OUT
V
V
SEG 1
CAP1+
CAP1–
CAP2–
CAP2+
CAP3+
CAP3–
CAP4–
CAP4+
SEG 0
COM 0
COM 1
COM 2
COM 3
V
2
•
•
•
•
•
V1
VC
MV1
(VSS)MV
2
CPP+
CPP–
CPM+
CPM–
COM 64
COM 65
Rev. 1.3
EPSON
79
S1D15E05 Series
15. TCP DIMENSIONS (Reference example)
80
EPSON
Rev. 1.3
S1D15E05 Series
Rev. 1.3
EPSON
81
S1D15E05 Series
16. CAUTIONS
Cautions must be exercised on the following points when using this Development Specification:
1. This Development Specification is subject to change for engineering improvement.
2. This Development Specification does not guarantee execution of the industrial proprietary rights or other rights, or
grant a license. Examples of applications described in This Development Specification are intended for your
understanding of the Product. We are not responsible for any circuit problem or the like arising from the use of them.
3. Reproduction or copy of any part or whole of this Development Specification without permission of our company,
or use thereof for other business purposes is strictly prohibited.
For the use of the semi-conductor,cautions must be exercised on the following points:
[Cautions against Light]
The semiconductor will be subject to changes in characteristics when light is applied. If this IC is exposed to light,
operation error may occur. To protect the IC against light, the following points should be noted regarding the substrate
or product where this IC is mounted:
(1) Designing and mounting must be provided to get a structure which ensures a sufficient resistance of the IC to
light in practical use.
(2) In the inspection process, environmental configuration must be provided to ensure a sufficient resistance of the
IC to light.
(3) Means must be taken to ensure resistance to light on all the surfaces, backs and sides of the IC
82
EPSON
Rev. 1.3
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