S1F81100F5R1000 [SEIKO]
SWITCHING REGULATOR, 1200kHz SWITCHING FREQ-MAX, QCC48, QFN-48;
| 型号： | S1F81100F5R1000 |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | SWITCHING REGULATOR, 1200kHz SWITCHING FREQ-MAX, QCC48, QFN-48 开关 |
| 文件： | 总55页 (文件大小：919K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MF1531 03
Power Supply IC
S1F81100F0R/S1F81100F5R
Technical Manual
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written
permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material
or due to its application or use in any product or circuit and, further, there is no representation that this material
is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to
any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty
that anything made in accordance with this material will be free from any patent or copyright infringement of a
third party. This material or portions thereof may contain technology or the subject relating to strategic
products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export
license from the Ministry of International Trade and Industry or other approval from anther government agency.
©SEIKO EPSON CORPORATION 2003, All rights reserved.
Intel is registered trademark of Intel Corporation.
XScale is trademark of Intel Corporation.
All other product names mentioned herein are trademarks and/or registered trademarks of their respective
companies.
Configuration of product number
zDEVICES
S1
F
81100
F
00A0
00
Packing specifications
00: Besides tape & reel
0A: TCP BL 2 directions
0B: Tape & reel Back
0C: TCP BR 2 directions
0D: TCP BT 2 directions
0E: TCP BD 2 directions
0F: Tape & reel FRONT
0G: TCP BT 4 directions
0H: TCP BD 4 directions
0J: TCP SL 2 directions
0K: TCP SR 2 directions
0L: Tape & reel LEFT
0M:TCP ST 2 directions
0N: TCP SD 2 directions
0P: TCP ST 4 directions
0Q: TCP SD 4 directions
0R: Tape & reel RIGHT
99: Specs not fixed
Specifications
Shape
(F : QFP)
Model number
Model name
(F : Power Supply)
Product classification
(S1:Semiconductors)
CONTENTS
1. DESCRIPTION....................................................................................................................................1
1.1 Features .....................................................................................................................................1
1.2 Block Diagram............................................................................................................................2
1.3 Package Dimensions and Pin Assignment................................................................................4
1.4 Pin Description...........................................................................................................................6
2. INPUT VOLTAGE AND INITIAL RESET............................................................................................8
2.1 Input Voltage ..............................................................................................................................8
2.1.1 Main Battery <VIN>.......................................................................................................8
2.1.2 Sub-Battery <VBAK> .....................................................................................................8
2.1.3 Constant Voltage for Internal Circuits <VD1>...............................................................8
2.1.4 Reference Voltage for Internal Circuits <VREF>...........................................................9
2.1.5 Voltage for External Interface Pins <BATT_VCC>........................................................9
2.2 Initial Reset............................................................................................................................... 11
2.2.1 Reset Input Pin <XRST>............................................................................................ 11
2.2.2 Reset Output Pin <nRESET> .................................................................................... 11
2.3 Test Pin <XTEST0>.................................................................................................................. 11
3. REGULATOR AND OPERATION ....................................................................................................12
3.1 CH-1 (VCC1) Output Voltage.....................................................................................................13
3.1.1 Main Regulator (PWM Controller)..............................................................................13
3.1.2 Soft Start Function .....................................................................................................14
3.1.3 Output Voltage Setting Function ................................................................................14
3.1.4 Power Good Function ................................................................................................16
3.1.5 CH-1’s (VCC1) Output Voltage Protection Function....................................................16
3.2 CH-2 (VCC2) Output Voltage.....................................................................................................17
3.2.1 Main Regulator (PWM Controller)..............................................................................17
3.2.2 Sub-Regulator (Backup Regulator)............................................................................18
3.2.3 Soft Start Function .....................................................................................................18
3.2.4 Short-Circuit Proof Function.......................................................................................18
3.2.5 Power Good Function ................................................................................................18
3.3 CH-3 (VCC3) Output Voltage.....................................................................................................19
3.3.1 Main Regulator (PWM Controller)..............................................................................19
3.3.2 Sub-Regulator (Backup Regulator)............................................................................19
3.3.3 Soft Start Function .....................................................................................................20
3.3.4 Short-Circuit Proof Function.......................................................................................20
3.3.5 Power Good Function ................................................................................................20
3.4 CH-4 (VCC4) Output Voltage.....................................................................................................21
3.4.1 Main Regulator (Series Regulator) ............................................................................21
3.5 Output Timing of Regulator on Initial Startup...........................................................................22
4. OPERATION MODES.......................................................................................................................23
4.1 Description of Each Operation Mode.......................................................................................23
4.2 Sleep Mode..............................................................................................................................23
4.3 Ultra-Power-Saving Mode........................................................................................................24
5. AUXILIARY FUNCTIONS AND OPERATIONS...............................................................................25
5.1 External Voltage Determining Function ...................................................................................25
5.2 Output Voltage Determining Function......................................................................................26
5.3 Input Voltage Determining Function.........................................................................................27
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6. BASIC EXTERNAL CONNECTION DIAGRAMS............................................................................28
7. ELECTRICAL CHARACTERISTICS ...............................................................................................30
8. PACKAGE ........................................................................................................................................43
9. TERMINAL EQUIVALENT CIRCUIT................................................................................................45
APPENDIX SELECTION OF PWM CONTROLLER’S EXTERNAL COMPONENTS........................47
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S1F81100F0R/S1F81100F5R Technical Manual
1. DESCRIPTION
The S1F81100F0R/S1F81100F5R is a power IC for the system equipped with a 4-channel regulator. Batteries
such as lithium ion batteries are used to generate each output voltage via external devices. The 4-channel
regulator consisting of PWM controller with 3 channels and series regulator with 1 channel are independent of
each other and can be controlled separately.
In addition, it is equipped with the input voltage detecting function, output voltage detecting function, external
voltage detecting function, etc.
Moreover, this series exhibits power saving performance by effectively using the normal, Sleep and
ultra-energy-saving modes provided as operation mode according to the situation.
The S1F81100F0R/S1F81100F5R is also equipped with an I/O pin dedicated for interface to Intel’s
PXA250/210 (XScaleTM) processor, and is most suitable for use as a power supply unit for mobile devices such
as PDAs equipped with an XScaleTM and smart-phone.
Product number
Shipping forms
S1F81100F0R 000
QFP12-48 Package
QFN7-48 Package
*
S1F81100F5R 000
*
Note: The above is replaced with a serial number depending on the option.
*
z Product List
The following optional products (including those under development) are currently prepared for the
S1F81100F0R/S1F81100F5R.
Table 1.1 Product List
Mask Option
[No.2]
CH-3
2.5V
Model
Package
[No.1]
CH-2
3.3V
3.3V
[others]
* S1F81100F0R1000
* S1F81100F5R1000
* Under development
QFP12-48
QFN7-48
2.5V
1.1 Features
The features of the S1F81100F0R/S1F81100F5R include the following:
zInput voltage:
zRegulator:
VIN
4 channels
3.3V to 5.5V
CH-1 (VCC1): PWM controller
High-speed synchronized rectification type PWM controller
(Connected to an external component to configure a switching regulator.)
Features include the High-speed response circuit using the current/voltage returning system, shorting
proofing circuit, more compact external parts thanks to the High-speed clock.
Output voltage
Output current
1.5/1.4/1.3/1.2/1.1/1.0/0.9V
Select one value from above by pin settings for the P03 pin through P01 pin.
Accuracy: within ±5%
Sleep mode
OFF
Operating mode
Max.: 500mA
CH-2 (VCC2): PWM controller
High-speed synchronized rectification type PWM controller
(Connected to an external component to configure a switching regulator.)
Features include a fast response circuit using a current/voltage returning system, a short-circuit-proof circuit,
more compact external components thanks to a fast clock, and a sub-regulator.
Output voltage
3.3V
Accuracy: within ±5%
Output current
Sleep mode
Operating mode
Max.: 10mA (Sub regulator operation)
Max.: 1A
Rev.2.4
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S1F81100F0R/S1F81100F5R Technical Manual
CH-3 (VCC3): PWM controller
High-speed synchronized rectification type PWM controller
(Connected to an external component to configure a switching regulator.)
Features include a fast response circuit using a current/voltage returning system, a short-circuit-proof circuit,
more compact external components thanks to a fast clock, and a sub-regulator.
Output voltage
2.5V
Accuracy: within ±5%
Output current
Sleep mode
Operating mode
Max.: 10mA (Sub regulator operation)
Max.: 1A
CH-4 (VCC4): Series regulator
Low power consumption type series regulator
Output voltage
Output current
1.5/1.4/1.3/1.2/1.1/1.0/0.9V…Same voltage as in CH-1 setting
Sleep time OFF
Operating time 5mA
Typ.: 0.7µA(@VIN=4.0V)
Normal time 2mA(Typ.)
zShutdown current:
zCurrent consumption:
Sleep time
zOutput voltage detecting function: 1 channel (nVCC_FLT)
The output of power good circuit will be LOW if one of CH1 to CH3
100µA(Typ.)
output is out of defined value.
zInput voltage detecting function:
1 channel (nBAT_FLT)
The LOW output is applied if the detected input voltage fails to comply
with the specs.
zExternal voltage detecting function: 1 channel (nVCK_FLT)
Monitoring the external voltage, LOW output will be made when the
external voltage drops below 0.7V.
1 channel (XRST(I),nRESET(O))
1 channel (PWR_EN)
zResetting function:
zSleep function:
1.2 Block Diagram
The following is a block diagram of the S1F81100F0R/S1F81100F5R.
[****]
[****]
[****]
****
: Input Power Terminal
: Backup Power Terminal
: GND Terminal
: VIN Level I/O Terminal
: VCC1 Level I/O Terminal
: VCC2 Level I/O Terminal
: VCC3 Level I/O Terminal
: VCC4 Level I/O Terminal
: BATT_VCC Level I/O Terminal
: Analog Terminal
****
****
****
****
****
****
Fig.1.2.1 Notation of Pin Voltage Levels in Fig.1.2.2.
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S1F81100F0R/S1F81100F5R Technical Manual
S1F81100F0R/S1F81100F5R
[VIN]
[VIN1]
VCC1
[VSS]
CH-1
FB1M
SW1OH
SW1OL
SSCAP1
[VSS1]
PWM cont.
Power-Good
Soft start
Err. Dtct.
etc.
OSC
AD_EN
P03
[VIN2]
VCC2
P02
CH-2
P01
PWM cont.
Series Reg.
Power-Good
Soft start
Err. Dtct.
etc.
FB2M
SW2OH
SW2OL
SSCAP2
[VSS2]
XRST
Reset
Cont.
nRESET
VIN
nBAT_FLT
nVCC_FLT
PWR_EN
Dtct.
VOUT
[VIN3]
VCC3
Dtct.
CH-3
Sleep
Cont.
PWM cont.
Series Reg.
Power-Good
Soft start
Err. Dtct.
etc.
FB3M
SW3OH
SW3OL
SSCAP3
[VSS3]
Ext.
Power
Dtct.
VCK
WUP
Int. Power
Reg.
VD1
VCC4
FB4
Ref. Power
Reg.
VREF
CH-4
XSDWN
XTEST0
BATT_VCC
[VBAK]
Test
Cont.
Backup
Switch
Fig.1.2.2 Block Diagram
Rev.2.4
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S1F81100F0R/S1F81100F5R Technical Manual
1.3 Package Dimensions and Pin Assignment
[QFP12-48]
9±0.4
7±0.1
36
25
37
24
INDEX
48
13
1
12
+0.1
0.5
0.18
-0.05
0.125±0.05
0°
10°
0.5±0.2
1
Unit: mm
Fig.1.3.1 QFP12-48 Package Diagram
Table 1.3.1 QFP12-48 Pin Assignment Table
Pin#
1
2
3
4
5
6
7
8
Pin#
13
14
15
16
17
18
19
Pin#
25
26
Pin#
37 XPOR(N.C.)
Pin name
FB3M
SW3OL
VSS3
VCC1
VIN1
SW1OH
FB1M
SW1OL
VSS1
Pin name
FB4
VCC4
VIN
XRST
XTEST0
XSDWN
XC1TRG
Pin name
VD1
VBAK
Pin name
38
P02
P03
27 BATT_VCC 39
28 PWR_EN 40
29 nVCK_FLT 41
VCC2
VIN2
30
nRESET
42
SW2OH
FB2M
SW2OL
VSS2
31 nBAT_FLT 43
20 TCLK(N.C.) 32 nVCC_FLT 44
21 CLKIN(N.C.) 33 P00(N.C.) 45
9
10
11
12
22
23
24
VSS
VCK
VREF
34
P01
46
VCC3
VIN3
SW3OH
SSCAP3
SSCAP2
SSCAP1
35 SCL(N.C.) 47
36 SDA(N.C.) 48
4
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Rev.2.4
S1F81100F0R/S1F81100F5R Technical Manual
[QFN7-48]
7
6.75
0.42+−
0.18
0.18
13
24
12
25
1
36
48
37
0.5
Fig.1.3.2 QFN7-48 Package Diagram
Table 1.3.2 QFN7-48 Pin Assignment Table
Pin#
1
2
3
4
5
6
7
8
Pin#
13
14
15
16
17
18
19
Pin#
25
26
Pin#
37 XPOR(N.C.)
Pin name
FB3M
SW3OL
VSS3
VCC1
VIN1
SW1OH
FB1M
SW1OL
VSS1
Pin name
FB4
VCC4
VIN
XRST
XTEST0
XSDWN
XC1TRG
Pin name
VD1
VBAK
Pin name
38
P02
P03
27 BATT_VCC 39
28 PWR_EN 40
29 nVCK_FLT 41
VCC2
VIN2
30
nRESET
42
SW2OH
FB2M
SW2OL
VSS2
31 nBAT_FLT 43
20 TCLK(N.C.) 32 nVCC_FLT 44
21 CLKIN(N.C.) 33 P00(N.C.) 45
9
10
11
12
SSCAP3
SSCAP2
SSCAP1
22
23
24
VSS
VCK
VREF
34
P01
46
VCC3
VIN3
SW3OH
35 SCL(N.C.) 47
36 SDA(N.C.) 48
Rev.2.4
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S1F81100F0R/S1F81100F5R Technical Manual
1.4 Pin Description
Table 1.4.1(a) Pin Descriptions
[Power supply/controlling pins]
Pin name
VIN
I/O
Level
Function
Voltage (+) input pin
Voltage (-) input pin
VSS
Interface power input pin (short-circuits to the VCC2 outside
the IC)
VBAK
VD1
Internal constant voltage output pin
VREF
Reference voltage output pin
Interface power input pin (short-circuits to the VCC2 outside
the IC)
BATT_VCC
nVCC_FLT
nBAT_FLT
nRESET
PWR_EN
XRST
O
O
O
I
BATT_VCC
BATT_VCC
BATT_VCC
BATT_VCC
VIN
Output voltage detection result output pin
Input voltage detection result output pin
System reset signal output pin
Sleep state setting input pin
Resetting input pin
I
XTEST0
XSDWN
XC1TRG
P01 to 03
VCK
I
I
I
VIN
Testing input pin
VIN
Ultra-power-saving mode setting input pin
CH-1 output voltage changing triggering input pin
CH-1 output voltage setting pin
External reference voltage (+) input pin
External voltage detection result output pin
VIN
I/O
VCC2
nVCK_FLT
O
BATT_VCC
[CH-1 Related Pins]
Pin name
VIN1
I/O
Function
Voltage (+) input pin
SW1OH
SW1OL
SSCAP1
FB1M
VCC1
VSS1
O
O
P-ch power MOS transistor drive signal output pin
N-ch power MOS transistor drive signal output pin
CH-1 soft start setting pin
Output current feedback input pin
Output voltage feedback input pin
Voltage (-) input pin
I
I
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Rev.2.4
S1F81100F0R/S1F81100F5R Technical Manual
Table 1.4.1(b) Pin Description
[CH-2 Related Pins]
Function
Pin name
VIN2
I/O
Voltage (+) input pin
SW2OH
SW2OL
SSCAP2
FB2M
VCC2
VSS2
O
O
P-ch power MOS transistor drive signal output pin
N-ch power MOS transistor drive signal output pin
CH-2 soft start setting pin
Output current feedback input pin
Output voltage feedback input pin [sub-regulator output pin]
Voltage (-) input pin
I
I
[CH-3 Related Pins]
Function
Voltage (+) input pin
Pin name
VIN3
I/O
SW3OH
SW3OL
SSCAP3
FB3M
VCC3
VSS3
O
O
P-ch power MOS transistor drive signal output pin
N-ch power MOS transistor drive signal output pin
CH-3 soft start setting pin
Output current feedback input pin
Output voltage feedback input pin [sub-regulator output pin]
Voltage (-) input pin
I
I
[CH-4 Related Pins]
Function
VCC4 voltage output pin
Feedback input pin
Pin name
VCC4
I/O
O
I
FB4
Notes: The following pins are dedicated to test use. Always indicate as N.C. when using.
Operation without the indication of N.C. cannot be guaranteed.
XPOR, TCLK, P00, SCL, SDA, CLKIN
Rev.2.4
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S1F81100F0R/S1F81100F5R Technical Manual
2. INPUT VOLTAGE AND INITIAL RESET
This chapter describes the input voltage specifications and the initial reset specifications of the
S1F81100F0R/S1F81100F5R.
2.1 Input Voltage
By using its main battery, the S1F81100F0R/S1F81100F5R generates internal constant voltage VD1 and internal
reference voltage VREF, which are necessary for its operation. The external interface’s I/O voltage BATT_VCC
and VBAK pins must short-circuit to the VCC2 outside the S1F81100F0R/S1F81100F5R.
The detailed specifications are described as follows.
V
V
V
V
IN
V
D1
IN1
IN2
IN3
Regulator
Other
Peripheral
Circuits
(oscillation,I2C,
digital circuit
etc.)
VD1
Main
Battery
CH-1
CH-2
CH-3
CH-4
VSS1
VSS2
VSS3
VSS
VCC1
VCC2
VCC3
VCC4
BATT_VCC
VBAK
Fig.2.1.1 Power Supply System Block Diagram
2.1.1 Main Battery <VIN>
The input voltage range of the S1F81100F0R/S1F81100F5R’s main battery is as follows:
3.3 to 5.5V
The S1F81100F0R/S1F81100F5R is activated if a single power supply with the voltage of the above range is
provided between VIN and VSS and generates 4-channel output voltage as well as constant voltage VD1 for the
internal circuits.
2.1.2 Sub-Battery <VBAK>
Short-circuit the S1F81100F0R/S1F81100F5R VBAK pin to the VCC2 externally.
2.1.3 Constant Voltage for Internal Circuits <VD1>
Since the S1F81100F0R/S1F81100F5R generates constant voltage for the internal circuit VD1 by using its main
battery, it is not required to input any external voltage.
To stabilize the voltage, connect the external capacitor 0.1µF to the VD1 pin.
Notes: Driving an external load by using an internal constant voltage VD1 is strictly prohibited.
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S1F81100F0R/S1F81100F5R Technical Manual
2.1.4 Reference Voltage for Internal Circuits <VREF>
The S1F81100F0R/S1F81100F5R generates reference voltage for the internal circuit VREF by using its main
battery. The S1F81100F0R/S1F81100F5R internally generates VREF voltage, and uses it as a reference voltage
for internal circuits such as the PWM controller. Accordingly, it is not required to input any external voltage.
To stabilize output voltage, connect the external capacitor 0.1µF to the VREF pin.
The VREF voltage potential is the same as the VIN while LOW-level voltage is input to the XRST pin.
Notes: Driving an external load by using an internal reference voltage VREF is strictly prohibited.
2.1.5 Voltage for External Interface Pins <BATT_VCC>
The S1F81100F0R/S1F81100F5R is equipped with the following external interface pins that interface with any
external processors.
nVCC_FLT
nBAT_FLT
PWR_EN
WUP
(Output) Output voltage level detection pin
(Output) Input voltage level detection pin
(Input) Sleep state setting pin
(Output) Sleep state status output pin
(Output) Reset output pin
nRESET
Short-circuit the power supply BATT_VCC to drive the above interface pins to the VCC2 outside the
S1F81100F0R/S1F81100F5R.
Fig.2.1.5.2 shows the external connection diagram.
Rev.2.4
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S1F81100F0R/S1F81100F5R Technical Manual
CH-2
Regulator
VCC2
V
BAK
BATT_VCC
nVCC_FLT
nBAT_FLT
PWR_EN
WUP
S1F81100
nRESET
Fig.2.1.5.1 The Internal Configuration of BATT_VCC Pin
CH-2
Regulator
V
CC2
BAK
V
IN
V
VIN1
VIN2
VIN3
BATT_VCC
nVCC_FLT
nBAT_FLT
PWR_EN
WUP
V
SS
VSS1
V
SS2
V
SS3
S1F81100
nRESET
Fig.2.1.5.2 External Connection Diagram for the BATT_VCC and the VBAK pins
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S1F81100F0R/S1F81100F5R Technical Manual
2.2 Initial Reset
The S1F81100F0R/S1F81100F5R requires initial reset to initialize its circuits. The following is the initial reset
factor:
(1) External initial reset via the XRST pin.
Initial reset initializes the internal circuit of the IC. To initialize the circuits, be sure to perform one of these
actions.
During the initial reset period, the LOW level signal is output from the nRESET pin.
Fig.2.2.1 shows the initial reset circuit diagram.
XRST
nRESET
Counter
Circuit
Power Good
Circuit
Input Voltage
Detection
Circuit
Fig.2.2.1 Initial Reset Circuit Diagram
2.2.1 Reset Input Pin <XRST>
Initial reset can be performed by externally setting the reset (XRST) input pin to LOW level (VSS). After this,
the internal circuits stay in the initial reset state until outputs of all the four channels are activated.
Keep the XRST pin at LOW level for a period of 50µs or longer so that initial resetting can be performed.
Notes: While the LOW level is input to the XRST pin, VREF voltage must be set to the same voltage as VIN.
2.2.2 Reset Output Pin <nRESET>
The S1F81100F0R/S1F81100F5R can output a reset signal to external devices via the nRESET pin.
The nRESET signal starts outputting the LOW level signal as soon as the S1F81100F0R/S1F81100F5R unit has
entered the initial reset state, and keeps the LOW level (initial reset state) until all output voltages of the four
channels are activated. When all the output voltages are activated and the input level of the XRST pin attains
the HIGH level (VIN level), the output level of the reset output signal nRESET becomes HIGH (BATT_VCC,
VCC2 level).
After the input voltage is turned ON, the nRESET signal maintains the LOW level for around 60 ms after all
four channels are activated.
2.3 Test Pin <XTEST0>
This pin is used for testing ICs before shipping. In normal operation, XTEST0 should be connected to VIN.
Rev.2.4
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S1F81100F0R/S1F81100F5R Technical Manual
3. REGULATOR AND OPERATION
The S1F81100F0R/S1F81100F5R has a regulator with 4 channels (CH-1, CH-2, CH-3, and CH-4) that are
optimized for Intel’s PXA250/210 processors.
As a main regulator, CH-1, CH-2, and CH-3 are mounted with PWM controllers. The PWM controllers can
output stable voltage by configuring a switching regulator that connects the external power MOS transistor and
coil, etc. In addition, each channel is equipped with a series regulator, which acts as a sub (backup) regulator.
To control the system’s current consumption, the sub regulator can be operated independently (light load mode)
depending on the loading condition.
CH-4 is a series regulator and can independently output voltage.
This chapter describes in detail each regulator.
CH-1 (VCC1)
CORE power (VCC) for PXA250/210
Select 1 value from 1.5/1.4/1.3/1.2/1.1/1.0/0.9V: Select one value among the P03 pin through the P01 pin.
Main regulator: PWM controller
Sleep mode: OFF, Operating load: 500mA (Max.), Maximum conversion efficiency: about 80%.
CH-2 (VCC2)
Peripheral power (VCCQ) for PXA250/210
3.3V: Select 1 value from mask options.
Main regulator: PWM controller
Sleep mode: OFF, Operating load: 1A (Max.), Maximum conversion efficiency: about 90%.
Sub-regulator: series regulator
CH-3 (VCC3)
Memory power (VCCN) for PXA250/210
2.5V: Select 1 value from mask options.
Main regulator: PWM controller
Sleep mode: OFF, Operating load: 1A (Max.), Maximum conversion efficiency: about 90%.
Sub-regulator: series regulator
CH-4 (VCC4)
PLL power (PLL_VCC) for PXA250/210
1.5/1.4/1.3/1.2/1.1/1.0/0.9V (Output value same with the VCC1 set value)
Series regulator
Sleep mode: OFF, Operating load: 5mA (Max.)
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3.1 CH-1 (VCC1) Output Voltage
This section describes CH-1, a variable output type PWM controller. Fig.3.1.1 shows CH-1’s internal and
external configurations.
S1F81100F0R/S1F81100F5R
V
CC1
IN1
Power
Good
Mask Option
V
Sub-regulator
(backup)
SW1OTHP1
-
-
+
CL1
Error
AMP
CMP.
FB1M
SW1OL
PWM
Waveform
Drive Circuit
TN1
SD1
CC1
V
SS1
PG1
POFF1
LMD1
Power
Manager
Output
Voltage
Control
Circuit
VS1n
SSCAP1
CS1
Soft Start
Fig.3.1.1 CH-1 Regulator Configuration
3.1.1 Main Regulator (PWM Controller)
The main regulator of CH-1 is a variable output type PWM controller. External components can be connected
to it to form a switching regulator to allow constant voltage to be generated and output from input voltage VIN
(VIN1) and internal constant voltage VD1.
[Configuration of CH-1 Switching Regulator]
Synchronized rectification type switching regulator.
Clock
Approximately 1 MHz (when the internal oscillator circuit is used)
Required external components: P-ch power MOS transistor
TP1
TN1
SD1
CL1
N-ch power MOS transistor
Schottky diode
Coil: 10µH
Stabilizing capacitor (100µF) CC1
Capacitor for soft start CS1
The output values are variable and by external pin settings for the P03 through P01, the output voltage value can
be selected and preset.
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3.1.2 Soft Start Function
With a capacitor connected to the SSCAP1 pin, CH-1 provides a soft start function that adjusts the power’s rise
time when it is turned on. The soft start time expiration triggers CH-1’s voltage output. Fig.3.1.2.1 shows
the relation between the soft start time and the soft start capacitor capacity (CS1). When using the CH1’s
voltage output as a core power supply for the PXA250/210 (XScaleTM) processor, its core voltage must rise
within 10 ms after the PWR_EN input enters the HIGH voltage level.
Hence, it is recommended to set the capacitor capacity to 0.01µF or less.
(Typ.)
CSn [µF]
Fig.3.1.2.1 The Relation between the Soft Start Time and the Soft Start Capacitor Capacity (CS1)
3.1.3 Output Voltage Setting Function
The output voltage of the CH-1 can be selected from seven different values by pin settings for the P03 pin
through P01 pin. It is possible to make optimum output voltage setting fitting to the operation of the driving
device while an application is in operation.
Also, as the timing for changing the output voltage, there are two choices of trigger inputs to the XC1TRG pin
and shifting into the “Sleep” mode.
zPin setting and output voltage
As mentioned above, it is possible to preset the output voltage value of the CH-1 by pin settings for the P03 pin
through P01 pin. Table 3.1.3.1 indicates the correlation table between pin settings and the output voltage.
Table 3.1.3.1 Correlation table between pin settings and the output voltage.
P03
1
P02
1
P01
1
VCC1 [V]
(Setting prohibited)
1
1
0
1.5
1.4
1.3
1.2
1.1
1.0
0.9
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
The status after the input voltage rises and after the initial reset signal is input through the XRST pin, the
voltage will be 1.2V regardless of the pin setting.
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zOutput voltage changing timing
As the timing for changing the output voltage, there are two choices of LOW level inputs to the XC1TRG pin
and shifting into the “Sleep” mode/returning (LOW pulse input to the PWR_EN pin).
(1) LOW level input to the XC1TRG pin
When LOW level input is made to the XC1TRG pin after changing the pin settings for the P03 pin through
P01 pin, the output voltage of the CH-1 will be of the new voltage value of the new voltage setting.
During the period when the LOW level input is being maintained, the pin settings for the P03 pin through
P01 pin will be passed through. In other words, if the pin settings for the P03 pin through P01 pin are
changed during the period while the XC1TRG pin is being maintained at the LOW level, the output value
of the CH-1 will change by the timing.
When the input to the XC1TRG pin is set to the HIGH level, the pin settings for the P03 pin through P01
pin will be latched at the timing and the output voltage of the CH-1 will be maintained at the same value.
Note: The XC1TRG pin is being pulled up to the VIN level internally. Therefore, when connecting to
some other device, make a careful connection like connecting to an open drain output.
Fig.3.1.3.1 shows the timing chart.
(2) Shifting into the “Sleep” mode/returning (LOW pulse input to the PWR_EN pin)
When shifting into the “Sleep” mode/cancelling is made, after the cancellation, the output voltage of the
CH-1 will be changed. At the timing when the input to the PWR_EN pin is set to the HIGH level, the pin
settings for the P03 pin through P01 pin will be latched.
Fig.3.1.3.1 shows the timing chart.
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XC1TRG LOW level signal
A
B
C
D
P03-P01
XC1TRG
XC1TRG LOW-level
C
(Output)
(VSS)
A
B
V
CC1
During XC1TRG keep LOW level, P03-P01 settings will through and
can control V output power.
CC1
After XC1TRG change to HIGH level, P03-P01 settings are latched
at the rising edge. And V
output power keep the same level.
CC1
PWR_EN HIGH-edge
A
B
P03-P01
PWR_EN
(Output)
A
B
V
CC1
(VSS)
Cancel the Sleep mode.
CC1 output power change to new value
at the same time.
V
Enter to Sleep mode.
Simulutaneously, V
power will down.
CC1
Fig.3.1.3.1 CH-1 output voltage changing timing chart
3.1.4 Power Good Function
CH-1 has a Power Good function. The Power Good function refers to a function that monitors the output
voltage value inside the S1F81100F0R/S1F81100F5R unit and determines if it is normal or not. If a state
approximately 10% or more below the typical output voltage exceeds approximately 10ms, it is determined to
be “abnormal output.”
The result of the Power Good judgement can be monitored by output level of nVCC_FLT pin.
See section 5.2 for details of the nVCC_FLT pin.
3.1.5 CH-1’s (VCC1) Output Voltage Protection Function
CH-1’s output incorporates an output protection function. This function terminates CH-1’s switching regulator
circuit operation when an output voltage 10% lower than specified continues for 110 ms or more. The output
voltage drop detection circuit also works as CH-1’s power good detection circuit.
Output protection detection time: 110 ± 20 [ms]
The circuit can be restored from the short-circuit protection mode by inputting from the reset pin (XRST).
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3.2 CH-2 (VCC2) Output Voltage
This section describes CH-2, a PWM controller. Fig.3.2.1 shows CH-2’s internal and external configurations.
S1F81100F0R/S1F81100F5R
V
V
CC2
IN2
Power
Good
Sub-regulator
(backup)
TP2
SW2OH
-
-
+
CL2
Error
AMP
CMP.
FB2M
SW2OL
PWM
Waveform
Drive Circuit
TN2
SD2
CC2
V
SS2
PG2
POFF2
LMD2
Power
Manager
SSCAP2
Soft Start
CS2
Fig.3.2.1 CH-2 Regulator Configuration
3.2.1 Main Regulator (PWM Controller)
The main regulator of CH-2 is a PWM controller. External components can be connected to it to form a
switching regulator to allow a constant voltage to be generated and output from input voltage VIN (VIN2) and
internal constant voltage VD1.
[Configuration of CH-2 Switching Regulator]
Synchronized rectification type switching regulator.
Clock
Approximately 1 MHz (when the internal oscillator circuit is used)
Required external components: P-ch power MOS transistor
TP2
TN2
SD2
CL2
N-ch power MOS transistor
Schottky diode
Coil: 10µH
Stabilizing capacitor (100µF) CC2
Capacitor for soft start
CS2
The output value is fixed to 3.3V.
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3.2.2 Sub-Regulator (Backup Regulator)
CH-2 has a series regulator which serves as its sub-regulator.
For output value, a value approximately 0.1V lower than the value set of the main regulator is outputted.
3.2.3 Soft Start Function
With a capacitor connected to the SSCAP2 pin, CH-2 provides a soft start function that adjusts the rise time of
the power when it is turned on. This function effectively works to prevent a system malfunction that may
occur due to rush current when the power is activated. Fig.3.2.3.1 shows the relation between the soft start
time and the soft start capacitor capacity (CS2).
(Typ.)
CSn [µF]
Fig.3.2.3.1 The Relation between the Soft Start Time and the Soft Start Capacitor Capacity (CS2)
3.2.4 Short-Circuit Proof Function
The S1F81100F0R/S1F81100F5R’s CH-2 output incorporates an output protection function. It terminates
CH-2’s switching regulator circuit operation when an output voltage lower than specified continues for 110 ms
or more. The circuit can be restored from the short-circuit proof mode by inputting from the reset pin (XRST).
Output reduction detection CH-2 output set value
3.3V
Output reduction detected value
2.3V ± 0.2V
Output proof detection time 110 ± 20 [ms]
Notes: Take short-circuit proof countermeasures other than above to increase the security of the application.
3.2.5 Power Good Function
CH-2 has a Power Good function. The Power Good function refers to a function that monitors the output
voltage value inside the S1F81100F0R/S1F81100F5R unit and determines if it is normal or not. If a state
approximately 10% or more below the typical output voltage exceeds approximately 10ms, it is determined to
be “abnormal output.”
The result of the Power Good judgement can be monitored by output level of nVCC_FLT pin.
See section 5.2 for details of the nVCC_FLT pin.
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3.3 CH-3 (VCC3) Output Voltage
This section describes CH-3, a PWM controller. Fig.3.3.1 shows CH-3’s internal and external configurations.
S1F81100F0R/S1F81100F5R
V
CC3
IN3
Power
Good
V
Sub-regulator
(backup)
TP3
SW3OH
-
-
+
CL3
Error
AMP
CMP.
FB3M
SW3OL
PWM
Waveform
Drive Circuit
TN3
SD3
CC3
VSS3
PG3
POFF3
LMD3
Power
Manager
SSCAP3
Soft Start
CS3
Fig.3.3.1 CH-3 Regulator Configuration
3.3.1 Main Regulator (PWM Controller)
The main regulator of CH-3 is a PWM controller. External components can be connected to it to form a
switching regulator to allow a constant voltage to be generated and output from input voltage VIN (VIN3) and
internal constant voltage VD1.
[Configuration of CH-3 Switching Regulator]
Synchronized rectification type switching regulator.
Clock
Approximately 1 MHz (when the internal oscillator circuit is used)
Required external components: P-ch power MOS transistor
TP3
TN3
SD3
CL3
N-ch power MOS transistor
Schottky diode
Coil: 10µH
Stabilizing capacitor (100µF) CC3
Capacitor for soft start CS3
The output value is fixed to 2.5V.
3.3.2 Sub-Regulator (Backup Regulator)
CH-3 has a series regulator which serves as its sub-regulator.
For output value, a value approximately 0.1V lower than the value set of the main regulator is outputted.
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3.3.3 Soft Start Function
With a capacitor connected to the SSCAP3 pin, CH-3 provides a soft start function that adjusts the rise time of
the power when it is turned on. This function effectively works to prevent a system malfunction that may occur
due to rush current when the power is activated. Fig.3.3.3.1 shows the relation between the soft start time and
the soft start capacitor capacity (CS3).
(Typ.)
CSn [µF]
Fig.3.3.3.1 The Relation between the Soft Start Time and the Soft Start Capacitor Capacity (CS3)
3.3.4 Short-Circuit Proof Function
The S1F81100F0R/S1F81100F5R’s CH-3 output incorporates a short-circuit proof function. It terminates
CH-3’s switching regulator circuit operation when an output voltage lower than specified continues for 110 ms
or more. The circuit can be restored from the short-circuit proof mode by inputting from the reset pin (XRST).
Output reduction detection CH-2 output set value
2.5V
Output reduction detected value
1.9V ± 0.2V
Output proof detection time 110 ± 20 [ms]
Notes: Take short-circuit proof countermeasures other than above to increase the security of the application.
3.3.5 Power Good Function
CH-3 has a Power Good function. The Power Good function refers to a function that monitors the output
voltage value inside the S1F81100F0R/S1F81100F5R unit and determines if it is normal or not. If a state
approximately 10% or more below the typical output voltage exceeds approximately 10ms, it is determined to
be “abnormal output.”
The result of the Power Good judgement can be monitored by output level of nVCC_FLT pin.
See section 5.2 for details of the nVCC_FLT pin.
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3.4 CH-4 (VCC4) Output Voltage
This section describes CH-4, a series regulator. Fig.3.4.1 shows CH-4’s internal and external configurations.
S1F81100F0R/S1F81100F5R
FB4
VCC4
Power
Manager
POFF4
Fig.3.4.1 CH-4 Regulator Configuration
3.4.1 Main Regulator (Series Regulator)
CH-4 is a push/pull type series regulator that generates constant voltage via CH-3’s output voltage VCC2.
Short-circuit the VCC4 and FB4 pins outside the IC and use after mounting the following required components.
The following lists the required components.
Required external components: Capacitor
22µF
CH-4 output voltage value is the same with the voltage value set in CH-1.
CH-4 output is turned off in the following conditions:
(1) When CH-3 is turned off
(2) When set to Sleep mode (depends on the mask options).
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3.5 Output Timing of Regulator on Initial Startup
Describes about the regulator output after the initial startup (input voltage power-on).
CH-2 and CH-3 are the first ones to rise after input voltage (VIN) power-on.
After the Power Good function of each CH has determined that their output values are within the “specified
range” for CH-2 and CH-3, CH-1 and CH-4 voltages start to rise.
Subsequently, if the Power Good function determines that the output value is within the “specified range” for
CH-1 (CH-4 does not have a Power Good function), the output voltage determining function considers the
voltage to be “normal output voltage.”
Then, set the output level of nVCC_FLT pin to HIGH.
Then, after about 60ms, cancel the initial resetting state in the inside of the IC. At the same time, set the output
level of nRESET pin to HIGH and instruct reset cancellation to the external processor, etc.
See section 5.2 for output voltage determining function.
See section 2.2 for initial reset.
Fig.3.5.1 shows a timing chart illustrating the initial startup.
VIN
VCC2/VCC3
70ms
VCC1/VCC4
5ms
nVCC_FLT
[Digital]
less than 1µs
nRESET
[Digital]
60ms
Ú The values in the diagram are all typical values for approximation.
Fig.3.5.1 Initial Startup Timing
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4. OPERATION MODES
The S1F81100F0R/S1F81100F5R provides the following operation modes (operation statuses).
(1) Normal mode
(2) Sleep mode
(3) Ultra-Power-Saving mode
The Normal mode refers to a state in which the IC operates normally.
Regarding the modes as per the above Items (2) and (3), setting to each mode can be executed by controls from
the outside of the IC. Because each of these two modes ensures power saving as compared to the Normal mode,
it is possible to develop LOW-power consumption type products by efficiently set a mode when the application
is operating.
This chapter describes the Sleep and Ultra-Power-Saving modes in detail.
4.1 Description of Each Operation Mode
The S1F81100F0R/S1F81100F5R enters the Sleep mode when the PWR_EN pin is set to LOW during
operation.
The S1F81100F0R/S1F81100F5R enters the Ultra-Power-Saving mode when the input level of the XSDWN pin
is set to LOW.
In these modes, a part or all of the voltage outputs and IC’s internal circuits can be turned OFF. Thus, using
the mode appropriate for each individual situation allows the S1F81100F0R/S1F81100F5R to deliver power
saving performance.
Table 4.1.1 shows the ON/OFF states of the internal circuits in each mode.
Table 4.1.1 Regulator Operations in Each Mode
Normal
mode
ON
Ultra-Power-
Saving mode
OFF
Sleep mode
CH-1 Main
CH-2 Main
Sub
PWM
controller
PWM
controller
Series
regulator
PWM
controller
Series
regulator
OFF
ON
ON
ON
ON
ON
ON
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
CH-3 Main
Sub
OFF
ON
CH-4 Main
Series
regulator
OFF
ON
Others
(analog/logic)
4.2 Sleep Mode
This section describes how to transition to and cancel the Sleep mode.
zTransitioning to Sleep Mode
To transition to the Sleep mode input level of the PWR_EN pin to LOW.
When the S1F81100F0R/S1F81100F5R enters the Sleep mode,
CH-1: Voltage output is turned OFF.
CH-2: The main regulator is turned OFF.
CH-3: The main regulator is turned OFF.
CH-4: Voltage output is turned OFF.
In the sleep mode, since CH-1/CH-4 will be turned OFF and as the sub-regulator only of the CH-2/CH-3 will
operate, the current consumption of the system can be reduced. Therefore, setting the unit to enter the Sleep
mode via application software when VCC1 voltage is no longer required contributes to higher efficiency of the
unit as the current consumption of the entire system is reduced.
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zCanceling Sleep Mode
To cancel the Sleep mode, set the input level of the PWR_EN pin to HIGH.
When the Sleep mode is canceled, the S1F81100F0R/S1F81100F5R is restored to the same state as it was
before a transition to the Sleep mode.
4.3 Ultra-Power-Saving Mode
The S1F81100F0R/S1F81100F5R provides an Ultra-Power-Saving mode. This mode stops the functions of the
entire IC functionality to minimize power consumption. The current consumption in this mode is on the order of
a few microamperes. This mode is useful for shipping the product or for maintaining applications what are not
to be used for a long period of time.
To set the Ultra-Power-Saving mode, set the input level of the XSDWN pin to LOW. Maintaining the input
level at LOW allows the S1F81100F0R/S1F81100F5R to stay in the Ultra-Power-Saving mode.
To recover from the Ultra-Power-Saving mode, follow the procedures below.
(1) Set the input level of the XRST pin to LOW.
(2) Set the input level of the XSDWN pin to HIGH.
(3) Set the input level of the XRST pin to HIGH.
Setting the XSDWN pin back to HIGH with the XRST pin held HIGH, the IC’s internal circuitry becomes
unstable. Thus, this input state should not be used.
Fig.4.3.1 shows a timing chart when transitioning to and canceling the Ultra-Power-Saving mode.
XSDWN
[Digital]
･･･
･･･
･･･
･･･
XRST
[Digital]
Ultra-
Power-
Saving
mode
Unstable
state
Ultra-Power-Saving
mode
Normal
mode
Normal mode
Reset
Reset
Fig.4.3.1 Timing for Transitioning and Canceling the Ultra-Power-Saving Mode
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5. AUXILIARY FUNCTIONS AND OPERATIONS
The S1F81100F0R/S1F81100F5R has the following auxiliary functions.
1. External voltage determining function
2. Output voltage determining function
3. Input voltage determining function
The following provides detailed descriptions of these functions.
5.1 External Voltage Determining Function
The S1F81100F0R and S1F81100F5R are equipped with the external voltage determining function by which the
external voltage can be compared with the internal reference voltage and the comparison result can be output
through the pins.
This function compares the voltage input into the VCK pin with the reference voltage (0.7V) occurring internally.
The comparison result will then be output through the nVCK_FLT pin.
The output levels of the nVCK_FLT pin will be:
When the VCK input voltage is HIGH: HIGH level
When the VCK input voltage is LOW: LOW level
In the meantime, the voltage level of the nVCK_FLT pin will be BATT_VCC.
Fig.5.1.1 shows the configuration diagram of the external voltage determining function and an external
connection example.
S1F81100F0R/S1F81100F5R
VCK
Vcheck
R
TRM
RDIV
+
-
nVCK_FLT
0.7V
Fig.5.1.1 Configuration diagram of the external voltage determining function and an external
connection example.
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S1F81100F0R/S1F81100F5R Technical Manual
5.2 Output Voltage Determining Function
The S1F81100F0R/S1F81100F5R has an output voltage determining function. This function exposes the
reversed value of the output level of the nVCC_FLT pin to the external devices when at least one of the
regulators’ Power Good circuits for CH-1 to CH-3 is determined to be “outside the specified range” during its
operation.
For the nVCC_FLT pins, the output level will be as follows:
If the voltage is normal:
If the voltage is abnormal:
HIGH level
LOW level
For the nVCC_FLT pins, the voltage level will be BATT_VCC.
For determining the output voltages of the respective regulators, see sections 3.1.5, 3.2.5, and 3.3.5.
With this function, external components can detect the output level of this pin so that the application can be set
to the Sleep mode, etc. as required.
Fig.5.2.1 shows a block diagram of the output voltage determining function.
S1F81100F0R/S1F81100F5R
PG1
PG2
Power Good
(CH-1)
nVCC_FLT
Power Good
(CH-2)
Power Good
(CH-3)
PG3
Fig.5.2.1 Output Determining Function Block Diagram
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5.3 Input Voltage Determining Function
The S1F81100F0R/S1F81100F5R has an input voltage determining function. This function internally
determines on the IC the voltage input to the VIN pin and exposes the reversed value of the output level of the
nBAT_FLT pin to the external devices when the input value is determined to be “outside the specified range.”
For the nBAT_FLT pins, the output level will be as follows:
If the voltage is normal:
If the voltage is abnormal:
HIGH level
LOW level
For the nBAT_FLT pins, the voltage level will be BATT_VCC.
With this function, external components can detect the output level of this pin so that the application can be set
to the Sleep mode, etc. as required.
Fig.5.3.1 shows a block diagram of the input voltage determining function.
S1F81100F0R/S1F81100F5R
nBAT_FLT
Input voltage
determining circuit
Fig.5.3.1 Input Voltage Detecting Function Block Diagram
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6. BASIC EXTERNAL CONNECTION DIAGRAMS
VCC
VCCQ
VCCN
PLL_VCC
*
1
1
CH-1
CH-2
CH-3
*
*1
PWR_EN
nVCC_FLT
nBAT_FLT
PWR_EN
nVCC_FAULT
nBAT_FAULT
FB4
VCC4
CC4
R
nRESET
nRESET
5
F
0
0
1
1
8
F
1
S
/
R
0
F
0
0
1
1
SSCAP1
SSCAP2
SSCAP3
CS3 CS2 CS1
BATT_VCC
VBAK
8
GP(n)
GP(n)
GP(n)
GP(n)
P03
P02
P01
XC1TRG
F
1
S
VIN
XSDWN
XTEST0
GP(n)
nVCK_FLT
VCK
VD1
VREF
BAT1 CP1
+
Vcheck
R
TRM
DIV
CR1 CD1
R
VSS
XRST
Ext. Reset
Controller
[For *1 in figure, see Fig.6.2.]
Fig.6.1 Basic External Connection Diagram (1)
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V
CCn
For CH-n
(n=1 to 3)
V
INn
TPn
TNn
SWnOH
FBnM
CLn
V
CCn
+
CCn +
SWnOL
CP0n
SDn
V
SSn
Fig.6.2 Basic External Connection Diagram (2)
Table 6.1 External Component List (for reference)
Symbol
CL1 to 3
TP1 to 3
TN1 to 3
SD1 to 3
CC1 to 3
CC4
Components
Choke-type coil
P-ch power MOS transistor
N-ch power MOS transistor
Schottky diode
Capacitor
Parameter
10µH
Comment
*1
*2
*3
*4
*5
100µF
22µF
Capacitor
CS1
CS2 to 3
CD1
Capacitor
Capacitor
Capacitor
0.0068µF
0.01µF
0.1µF
CR1
Capacitor
0.1µF
CP1
Capacitor
100µF
47µF
CP01 to 03 Capacitor
(Recommended Components)
*1 SUMIDA/CR43-100(@Imax=500mA), SUMIDA/CR54-100(@Imax=1A)
*2 SANYO/CPH6315, HITACHI/HAT1043M
*3 SANYO/CPH6415, HITACHI/HAT2053M
*4 HITACHI/HRW0702A(@Imax=500mA), SANYO/SBS004, TOSHIBA/CMS06(@Imax=1A)
*5 NEC-TOKIN/ESVB20J107M
Rev.2.4
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29
S1F81100F0R/S1F81100F5R Technical Manual
7. ELECTRICAL CHARACTERISTICS
zAbsolute maximum ratings
Parameter
Input voltage (1)
Input voltage (2)
Input voltage (3)
Allowable total output
current
Symbol
VIN
Applicable
Rating
Unit
V
V
VIN
*1
*2
-0.5 to +7.0
-0.5 to +4.5
-0.5 to +7.0
VI2
VI3
V
10
mA
ΣIVIN
Operating temperature
Storage temperature
Topr
Tstg
-40 to +85
-65 to +150
°C
°C
Soldering
temperature/time
Tsol
260°C, 10s
Allowable package loss
PD
250
mW
*1: VD1
*2: All pins except for input voltages (1) and (2).
zRecommended operating range
Parameter
Symbol
Condition
Min.
3.3
Typ.
Max. Unit
5.5
V
Input voltage
range
VIN,VIN1,VIN2,
VIN3
3.3V output is selected for either
CH-2 or CH-3.
30
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S1F81100F0R/S1F81100F5R Technical Manual
zRegulator characteristics
[CH-1 characteristics]
(Conditions applied unless otherwise specified)
VIN=VIN1=VIN2=VIN3=4V, VSS=VSS1=VSS2=VSS3=0V, VBAK=3V,
VCC2=3.3V, VCC3=2.5V, CS1=0.01µF, IOUT1=100mA, Ta=25°C
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
ÕNormal operation (main and sub regulators)
Output voltage
VCC1
VCC1=0.9V
VCC1=1.0V
VCC1=1.1V
VCC1=1.2V
VCC1=1.3V
VCC1=1.4V
VCC1=1.5V
0.86
0.95
1.05
1.14
1.24
1.33
1.43
15
0.90
1.00
1.10
1.20
1.30
1.40
1.50
40
0.95
1.05
1.16
1.26
1.37
1.47
1.58
65
V
IS1H
VSW1On=0.9･VIN1
mA
Output current with
SW1OH and SW1OL
pins held HIGH
IS1LH
VSW1OH=0.1･VIN1
VSW1OL=0.1･VIN1
-90
-55
-65
-45
2.5
5
-40
-35
5.0
15
mA
mA
Output current with
SW1OH pin held LOW
IS1LL
Output current with
SW1OL pin held LOW
Input stability
Load stability
dVCC1-input
dVCC1-load
dVCC1/dTa･VCC1
VPG1
2.8V<VIN1<5.5V, IOUT1=100mA
VCC1=1.5V
10µA<IOUT1<500mA
VCC1=1.5V
IOUT1=100mA, -40°C<Ta<+85°C
VCC1=1.5V
VCC1=0.9V
VCC1=1.0V
VCC1=1.1V
VCC1=1.2V
VCC1=1.3V
mV
mV
Output voltage
temperature coefficient
-500
-430
ppm/°C
V
Power Good detection
voltage
0.77
0.85
0.94
1.02
1.11
1.19
1.28
0.81
0.90
0.99
1.08
1.17
1.26
1.35
80
0.86
0.95
1.05
1.14
1.24
1.33
1.43
VCC1=1.4V
VCC1=1.5V
VCC1=1.5V
IOUT1=500mA
Maximum conversion
efficiency
EFF1
%
Rev.2.4
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31
S1F81100F0R/S1F81100F5R Technical Manual
[CH-2 characteristics]
(Conditions applied unless otherwise specified)
VIN=VIN1=VIN2=VIN3=4V, VSS=VSS1=VSS2=VSS3=0V, VBAK=3V,
VCC1=1.5V, VCC3=2.5V, CS2=0.1µF, IOUT2=100mA, Ta=25°C
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Õ Normal operation (main and sub regulators)
Output voltage
VCC2
IS2H
3.14
15
3.30
40
3.47
65
V
mA
VSW2On=0.9･VIN2
Output current with
SW2OH and SW2OL
pins held HIGH
IS2LH
VSW2OH=0.1･VIN2
-90
-55
-65
-45
40
-40
-35
100
30
mA
mA
mV
Output current with
SW2OH pin held LOW
IS2LL
VSW2OL=0.1･VIN2
Output current with
SW2OL pin held LOW
Input stability
Load stability
dVCC2-input
3.4<VIN2<5.5V,IOUT2=300mA
dVCC2-load
10µA<IOUT2<1A
10
mV
Output voltage
temperature coefficient
Maximum duty ratio
Short circuit detection
voltage
dVCC2/dTa･VCC2
IOUT2=100mA, -40°C<Ta<+85°C
-500
100
-430
ppm/°C
MaxDuty2
VSHRT2
%
V
0.3
1
Short circuit detection
time
Power Good detection
voltage
Maximum conversion
efficiency
TSHRT2
VPG2
ms
V
2.81
3.04
2.97
90
3.14
EFF2
IOUT2=600mA
%
Õ Sub-regulators only
Output voltage
Input stability
Load stability
Output voltage
VCC2L
3.20
7
12
3.37
12
35
V
mV
mV
dVCC2L-input
dVCC2L-load
dVCC2/dTa･VCC2
3.3V<VIN2<5.5V, IOUT2=2mA
10µA<IOUT2<10mA
IOUT2=2mA, -40°C<Ta<+85°C
-500
14
-430
ppm/°C
temperature coefficient
Overload detection
current
30
mA
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Rev.2.4
S1F81100F0R/S1F81100F5R Technical Manual
[CH-3 characteristics]
(Conditions applied unless otherwise specified)
VIN=VIN1=VIN2=VIN3=4V, VSS=VSS1=VSS2=VSS3=0V, VBAK=3V,
VCC1=1.5V, VCC2=3.3V, CS3=0.1µF, IOUT3=100mA, Ta=25°C
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Õ Normal operation (main and sub regulators)
Output voltage
VCC3
IS3H
2.38
15
2.50
40
2.63
65
V
mA
VSW3On=0.9･VIN3
Output current with
SW3OH and SW3OL
pins held HIGH
IS3LH
IS3LL
VSW3OH=0.1･VIN3
VSW3OL=0.1･VIN3
-90
-55
-65
-45
-40
-35
mA
mA
Output current with
SW3OH pin held LOW
Output current with
SW3OL pin held LOW
Input stability
Load stability
dVCC3-input
dVCC3-load
3.4V<VIN3<5.5V, IOUT3=300mA
10µA<IOUT3<1A
40
10
100
30
mV
mV
Output voltage
temperature coefficient
Maximum duty ratio
Short circuit detection
voltage
dVCC3/dTa･VCC3
IOUT3=100mA, -40°C<Ta<+85°C
-500
100
-430
ppm/°C
MaxDuty3
VSHRT3
%
V
0.3
1
Short circuit detection
time
TSHRT3
VPG3
ms
V
Power Good detection
voltage
Maximum conversion
efficiency
2.13
2.28
2.25
90
2.38
EFF3
IOUT3=600mA
%
Õ Sub-regulators only
Output voltage
Input stability
Load stability
Output voltage
VCC3L
2.40
7
12
2.53
12
35
V
mV
mV
dVCC3L-input
dVCC3L-load
dVCC3/dTa･VCC3
3.3V<VIN3<5.5V, IOUT3=2mA
10µA<IOUT3<10mA
IOUT3=2mA, -40°C<Ta<+85°C
-500
14
-430
ppm/°C
temperature coefficient
Overload detection
current
30
mA
Rev.2.4
EPSON
33
S1F81100F0R/S1F81100F5R Technical Manual
[CH-4 characteristics]
(Conditions applied unless otherwise specified)
VIN=VIN1=VIN2=VIN3=4V, VSS=VSS1=VSS2=VSS3=0V, VBAK=3V,
VCC1=1.5V, VCC2=3.3V, VCC3=2.5V, IOUT4=2mA, Ta=25°C
Parameter
Output voltage
Symbol
Condition
Min.
0.86
0.95
1.05
1.14
1.24
1.33
1.43
Typ.
0.90
1.00
1.10
1.20
1.30
1.40
1.50
12
Max.
0.95
1.05
1.16
1.26
1.37
1.47
1.58
22
Unit
V
VCC4
VCC4=0.9V
VCC4=1.0V
VCC4=1.1V
VCC4=1.2V
VCC4=1.3V
VCC4=1.4V
VCC4=1.5V
Input stability
Load stability
dVCC4-input
VCC3=2.5V, IOUT4=2mA
VCC4=1.5V
mV
mV
dVCC4-load
10µA<IOUT4<5mA
VCC4=1.5V
1
5
Output voltage
temperature coefficient
dVCC4/dTa･VCC4
IOUT4=2mA, -40°C<Ta<+85°C
VCC4=1.5V
-500
-430
ppm/°C
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S1F81100F0R/S1F81100F5R Technical Manual
zMiscellaneous characteristics
[I/O characteristics]
(Conditions applied unless otherwise specified)
VIN=VIN1=VIN2=VIN3=4V, VSS=VSS1=VSS2=VSS3=0V, VBAK=3V, VCC2=3.3V,
VBAT=VCC2, BATT_VCC=VCC2, Ta=25°C
Parameter
HIGH-level input voltage
Symbol
VIH1
VIH2
VIH4
VIH5
VIH6
VIL1
VIL2
VIL4
VIL5
VIL6
IIH1
IIH2
IIH4
IIH5
IIH61
IIH62
IIL1
IIL2
IIL4
Pin name
PWR_EN
P00,P01,P03
XC1TRG
XRST
XSDWN
PWR_EN
P00,P01,P03
XC1TRG
XRST
XSDWN
PWR_EN
P00,P01,P03
XC1TRG
XRST
Condition
Min.
0.8･VBAT
0.8･VCC2
0.8･VIN
0.9･VIN
0.9･VIN
0
0
0
0
0
-0.5
-0.5
-0.5
-0.5
-0.5
-4
Typ.
Max.
VBAT
VCC2
VIN
VIN
VIN
0.2･VBAT
0.2･VCC2
Unit
V
V
V
V
V
V
V
V
LOW-level input voltage
HIGH -level input current
0.2･VIN
0.1･VIN
0.1･VIN
V
V
VIH1=VBAT
0
0
0
0
0
-1
10
10
16
16
1.2
3
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
VIH2=VCC2
VIH4=VIN
VIH5=VIN
VIH6=VIN
VIH6=0.8･VIN
VIL1=VSS
VIL2=VSS
VIL4=VSS
VIL5=VSS
VIL6=VSS
XSDWN
XSDWN
PWR_EN
P00,P01,P03
XC1TRG
XRST
-2.5
7.5
7.5
12
12
0.7
2
LOW -level input current
5
5
8
8
0.2
1
IIL5
IIL6
IOH1
XSDWN
HIGH -level output
current
nVCKFLT,nVCC_FLT, VOH1=0.9･VBAT
nBAT_FLT,nRESET
IOH2
IOL1
P01,P02,P03
nVCKFLT,nVCC_FLT, VOL1=0.1･VBAT
nBAT_FLT,nRESET
VOH2=0.9･VCC2
1
-4
2
-2.5
3
-1
mA
mA
LOW -level output
current
IOL2
P01,P02,P03
VOL2=0.1･VCC2
-4
-2.5
-1
mA
Rev.2.4
EPSON
35
S1F81100F0R/S1F81100F5R Technical Manual
[Current consumption characteristics]
(Conditions applied unless otherwise specified)
VIN=VIN1=VIN2=VIN3=4V, VSS=VSS1=VSS2=VSS3=0V, VBAK=3V,
VCC1=VCC4=1.5V, VCC2=3.3V, VCC3=2.5V, Ta=25°C
Parameter
In Normal mode
Symbol
Condition
IOUT1=1µA, IOUT2=1µA
IOUT3=1µA, IOUT4=1µA
IOUTB=1µA
Min.
Typ.
2
Max.
Unit
mA
Iexe
3
CH-1,2,3: Main regulator turned ON
IOUT2=1µA, IOUT3=1µA
IOUTB=1µA
CH-2,3: Main regulator turned ON
IOUT2=1µA, IOUT3=1µA
IOUTB=1µA
In Sleep mode (1)
In Sleep mode (2)
In Deep Sleep mode
Isleep1
Isleep2
Ids
1.4
100
50
2
mA
µA
µA
130
70
CH-2,3: Main regulator turned OFF
IOUTB=1µA
[Miscellaneous characteristics]
(Conditions applied unless otherwise specified)
VIN=VIN1=VIN2=VIN3=4V, VSS=VSS1=VSS2=VSS3=0V, VBAK=3V,
VCC1=VCC4=1.5V, VCC2=3.3V, VCC3=2.5V, VD1=2.2V, Ta=25°C
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Input voltage abnormal
detection voltage
Built-in oscillator circuit
frequency response
Input frequency
VSVD
fOSH
fCLK
2.65
2.80
2.95
V
0.8
0.8
1
1
1.2
1.2
MHz
MHz
zNOTES
x Use of the S1F81100F0R/S1F81100F5R under conditions beyond the absolute maximum rating may cause
malfunction or permanent damage to it. Although the S1F81100F0R/S1F81100F5R may temporarily operate
as intended, such use can significantly impair the reliability.
x The characteristics are not guaranteed if the S1F81100F0R/S1F81100F5R is used outside the recommended
operating range.
x Radiation-resistant design has not been provided for this chip.
x Although the S1F81100F0R/S1F81100F5R is inherently short circuit proof, we recommend that you provide
an overcurrent protection to enhance application safety.
36
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S1F81100F0R/S1F81100F5R Technical Manual
˜Examples of Main Characteristics (typical values)
– Current consumption vs. input voltage (Iexe) (Isleep1) (Isleep2) (Ids) (Istop)
S1F81100S0R/S1F81100S5R
S1F81100S0R/S1F81100S5R
(mA)
(mA)
VIN (V)
VIN (V)
S1F81100S0R/S1F81100S5R
S1F81100S0R/S1F81100S5R
(
m
A)
(mA)
VIN (V)
VIN (V)
S1F81100S0R/S1F81100S5R
(mA)
VIN (V)
Rev.2.4
EPSON
37
S1F81100F0R/S1F81100F5R Technical Manual
x Output voltage vs. input voltage (Light-Load mode)
(CH-2/CH-3: For 2.5V output)
CH2 input stability (LDO) @ sample No.1
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VIN (V)
(CH-2/CH-3: For 3.3V output)
CH3 input stability (LDO) @ sample No.8
4.00
3.80
3.60
3.40
3.20
3.00
2.80
2.60
2.40
2.20
2.00
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VIN (V)
38
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S1F81100F0R/S1F81100F5R Technical Manual
(CH-1/CH-4: For 1.1V output)
CH4 input stability (LDO) @ sample No.1
2.000
1.800
1.600
1.400
1.200
1.000
0.800
0.600
0.400
0.200
0.000
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VCC3 (V)
Rev.2.4
EPSON
39
S1F81100F0R/S1F81100F5R Technical Manual
˜Examples of Transient Response Characteristics (typical values)
– Output voltage rising waveform
(CH-1: For 1.1V output)
CH 1 starting waveform 100mA load
Ch1 cycle
No cycle
Ch1 frequency
No cycle
– Load fluctuation
(CH-1: For 1.1V output)
Load response
Load response
250mA load --> No load
No load --> 300mA load
Ch1 cycle
No cycle
Ch 1 cycle
Low resolution
Ch 1 frequency
Ch1 frequency
No cycle
Low resolution
No load
No load
IL=300mA
IL=250mA
(CH-2: For 2.5V output)
Load reponse
300mA load --> No load
Load response
No load --> 300mA load
Ch1 frequency
Ch1 frequency
Low resolution
Insufficient
amplitute
No load
IL=300mA
No load
IL=300mA
40
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S1F81100F0R/S1F81100F5R Technical Manual
zReference Data (typical values)
x Conversion efficiency vs. output current
(CH-1: Maximum conversion efficiency vs. setting voltage dependency)
S1F81100 VCC1 efficiency v.s. Iload
100
90
80
70
60
50
40
30
20
10
0
at VCC1=0.8V
at VCC1=1.2V
at VCC1=1.5V
0
100
200
300
400
500
600
700
Iload [mA]
[Measured Condition]
VIN=3.6V, VSS=0V, Ta=25°C
P-ch Power MOS (TP1): SANYO/CPH6315
N-ch Power MOS (TN1): SANYO/CPH6415
Schottky Diode (SD1): SANYO/SBS004
Coil (CL1): SUMIDA/CR43-100
Capacitor (CC1): NEC-TOKIN/ESVB20J107M
Rev.2.4
EPSON
41
S1F81100F0R/S1F81100F5R Technical Manual
x Conversion efficiency vs. output current
(CH-2 and CH-3: Conversion efficiency vs. load current)
S1F81100 VCCn efficiency v.s. Iload
100
90
80
70
60
50
40
30
20
10
0
at VCCn=3.3V
at VCCn=2.5V
0
200
400
600
800
1000
1200
Iload [mA]
[Measured Condition]
VIN=3.6V, VSS=0V, Ta=25°C
P-ch Power MOS (TPn): SANYO/CPH6315
N-ch Power MOS (TNn): SANYO/CPH6415
Schottky Diode (SDn): SANYO/SBS004
Coil (CLn): SUMIDA/CR54-100
Capacitor (CCn): NEC-TOKIN/ESVB20J107M
Note: n=2,3
42
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Rev.2.4
S1F81100F0R/S1F81100F5R Technical Manual
8. PACKAGE
<QFP12-48>
9±0.4
7±0.1
36
25
37
24
INDEX
48
13
1
12
+0.1
0.5
0.18
-0.05
0.125±0.05
0°
10°
0.5±0.2
1
Fig.8.1 QFP12-48 Package
Rev.2.4
EPSON
43
S1F81100F0R/S1F81100F5R Technical Manual
<QFN7-48>
7
6.75
0.18
0.18
0.42+−
13
24
12
25
1
36
48
37
0.5
Fig.8.2 QFN7-48 Package
44
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Rev.2.4
S1F81100F0R/S1F81100F5R Technical Manual
9. TERMINAL EQUIVALENT CIRCUIT
S1F81100 I/O Terminal equivalent Circuit [Input]
BATT_VCC BATT_VCC
(PAD)
(PAD)
(PAD)
PWR_EN
VCC2
VCC2
P01, P02, P03
VIN
VIN
XRST, XC1TRG
XTEST0, XSDWN
Fig.9.1(a) Terminal Equivalent Circuit [Input]
Rev.2.4
EPSON
45
S1F81100F0R/S1F81100F5R Technical Manual
S1F81100 I/O Terminal equivalent Circuit [Output]
BATT_VCC (VCC2)
(PAD)
nBAT_FLT, nVCC_FLT
nVCK_FLT, nRESET
Fig.9.1(b) Terminal Equivalent Circuit [Output]
46
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S1F81100F0R/S1F81100F5R Technical Manual
APPENDIX SELECTION OF PWM CONTROLLER’S EXTERNAL
COMPONENTS
This section provides information regarding the selection of external components for the PWM controller to
configure the switching regulators with respect to the CH-1, CH-2 and CH-3 in the
S1F81100F0R/S1F81100F5R. Please use the information in this section as a basis of component selection.
Note: For details of the specifications of the recommended components listed below, see their documents.
zInput capacitors (CP01, CP02, CP03)
The key selection criteria for the input capacitors is their allowable ripple current values included in their
specification values.
First, the maximum load current on your application should be determined before selecting a capacitor with an
allowable ripple current specification value that is at least equal to or greater than the determined maximum
load current.
zPower MOS transistors (TP1, TP2, TP3, TN1, TN2, TN3)
Select Power MOS transistors that have low on-resistance and small gate capacity for both P- and N-channels.
Higher on-resistance means greater power loss in the power MOS transistors when the switching regulator in
operation, which can impair conversion efficiency. The greater the gate capacity, the higher the charge and
discharge power when the switching regulator in operation, which can also impair conversion efficiency.
zSchottky diodes (SD1, SD2, SD3)
Select a Schottkey diode that has forward current capability equal to or greater than the maximum load current
value on your application or has a low forward voltage.
zCoils (inductors) (CL1, CL2, CL3)
Select a coil with a low dc-resistance and a large rated current.
Larger dc-resistance means greater power loss in the inductors when the switching regulator in operation, which
can impair conversion efficiency.
To prevent the inductors from being saturated, it is required to select a rated current that is far greater than the
current value to use. If an inductor saturates, the ripple current increased, which may cause the outputs to
become unstable. We, therefore, recommend that you select the rated current approximately twice the load
current value on the application.
The recommended inductance is 10 µH.
zRegulator output capacitors (CC1, CC2, CC3)
For a regulator output capacitor, an aluminum or tantalum capacitor of approximately 100µF.
Due to the internal circuit configurations, use of a low ESR capacitor may not ensure that the
S1F81100F0R/S1F81100F5R provides normal voltage outputs. We, therefore, recommend that you select a
capacitor that has approximately 200 mΩ of ESR. (To solve such output anomalies, an improved component is
under development)
zExamples of Component Selection
Type
Maker
SANYO
HITACHI
SANYO
Model Number
CPH6315
HAT1043M
CPH6415
P-ch
power MOS transistor
P-ch
power MOS transistor
HITACHI
HITACHI
SANYO
HAT2053M
HRW0702A
SBS004
Schottky diode
TOSHIBA
SUMIDA
CMS06
Inductor
CR43-100
CR54-100
CR75-100
ESV20J107M
Regulator output capacitor
NEC TOKIN
Rev.2.4
EPSON
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S1F81100F0R/S1F81100F5R
Technical Manual
SEIKO EPSON CORPORATION
ELECTRONIC DEVICES MARKETING DIVISION
EPSON Electronic Devices Website
http://www.epsondevice.com/
First issue September, 2002
H
Printed March, 2003 in Japan
A
相关型号：
S1FLB-M-08
DIODE 0.7 A, 100 V, SILICON, SIGNAL DIODE, DO-219AB, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, SMF, 2 PIN, Signal Diode
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