SED1222DGA [SEIKO]
Dot Matrix LCD Driver, 16 X 60 Dots, CMOS, 7.70 X 2.77 MM, 0.625 MM HEIGHT, ALUMINUM PAD, DIE-125;
| 型号： | SED1222DGA |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | Dot Matrix LCD Driver, 16 X 60 Dots, CMOS, 7.70 X 2.77 MM, 0.625 MM HEIGHT, ALUMINUM PAD, DIE-125 CD |
| 文件： | 总11页 (文件大小：295K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PF834-03
SED1220 Series
Dot Matrix LCD Controller Driver
●12 chara x 3 line (5 x 8 dot)
●Built-in Character Generator ROM and RAM
●Built-in Power Supply Circuit for LCD
■OVERVIEW
SED1220 is a dot matrix LCD controller/driver for character display. Using 4bits data, 8bits data or serial data being
provided from the micro computer, it displays up to 24 characters, 4 user defined characters and up to 120 symbols.
Up to 256 types of built-in character generator ROMs are prepared. Each character font is consisted of 5 × 8 dots.
It also contains the RAM for displaying 4 user defined characters each font consisting of 5 × 8 dots. It is symbol
register allows character display with high degree of freedom. This handy equipment can be operated with
minimum power consumption with its low power consumption design, standby and sleeping mode.
■FEATURES
● Built-in data display RAM – 36 characters + 4 user defined characters + 120 symbols.
● CG ROM (For up to 256 characters), CG RAM (for 4 characters) and symbol register (for 120 symbols).
● No. of display digit and lines
< In normal mode >
(1) (12 digits + 4 segments for signal) × 3 lines + 120 symbols + 5 static symbols (SED1220D✽✽)
(2) (12 digits + 4 segments for signal) × 2 lines + 120 symbols + 5 static symbols (SED1221D✽✽)
(3) 12 digits × 2 lines + 120 symbols + 5 static symbols (SED1222D✽A)
(4) 12 digits × 2 lines + 120 symbols + 10 static symbols (SED122AD✽B)
< In standby mode >
(1) 5 static symbols
(2) 5 static symbols
● Built-in CR oscillation circuit (C and R contained)
● Accepts external clock input
● High-speed MPU interface
Affords interface with both 68/80 system MPUs
Affords interface through 4 bits and 8 bits
● Affords serial interface
● Character font consists of 5 × 8 dots
● Duty ratio
(1) 1/26
(2) 1/18
● Simplified command setting
● Built-in power circuit for driving liquid crystal
Power amplifier circuit, power regulation circuit and voltage followers × 4
● Built-in electronic volume function
● Low power consumption
80 µA max.
(In normal operation, including operating current of the power supply).
TBD µA max. (In standby mode for displaying static icon).
TBD µA max. (In sleeping mode when display is turned off).
● Power supply
VDD - VSS
VDD - V5
–2.4 V to –3.6 V
–4.0 V to –6.0 V
● Temperature range for wide range operation
Ta = –30 to 85°C
● CMOS process
● Shipping style
Chip (Al pad product)
Chip (Au bump product)
TCP
SED1222D✽A
SED122✽D✽B
SED122✽T✽✽
● This unit does not employ radiation protection design
1
SED1220 Series
■ BLOCK DIAGRAM
LCD power circuit
Oscillator
Timing generatinon circuit
Refresh address counter
DD RAM
symbol
register
CG ROM
CG RAM
Address counter
Input buffer
MPU interface
2
SED1220 Series
■ CHIP SPECIFICATION (SED1220D✽✽, SED1221D✽✽, SED122AD✽✽)
146
74
73
147
63
62
56
55
165
54
1
:DUMMY PAD
:PAD
SED122✽D
**
↑
Digits prepared for CGROM pattern changes
Chip size:
Pad pitch:
7.70 × 2.77 mm
100 µm (Minimum)
Chip thickness (for reference): 625 ± 25 µm (SED122✽D✽A)
(SED122✽D✽B)
1) A1 pad specifications
Pad size on Y side:
Pad size on X side:
2) Au bump specifications
Bump size on Y side:
75 µm × 135 µm
135 µm × 75 µm
69 µm × 129 µm
129 µm × 69 µm
22.5 µm ± 5.5 µm
Bump size on X side:
Bump height (for reference)
<Fuse Pines>
1) Al pad. pad size
2) Au bump
86 µm × 75 µm
80 µm × 69 µm
Bump size
3
SED1220 Series
SED1222D✽✽
108
52
• • • • • • • • • • •
109
51
Y
41
40
X
Top View
34
33
125
• • • • • • • • • • •
• • •
• • •
1
11 12
27 28
32
: PAD
SED1222D
**
↑
Digits prepared for CGROM pattern changes
Chip size:
Pad pitch:
7.70 × 2.77 mm
124 µm (Min.)
Chip thickness (for reference): 625 ± 50 µm (SED1222D A)
*
1) A1 pad specifications
Pad size on Y side:
Pad size on X side:
90 µm × 96 µm
96 µm × 90 µm (PAD. NO 1–11, 28–32, 52–108)
175 µm × 135 µm (PAD. NO 12–27)
<Fuse Pines>
1) Al pad. pad size
86 µm × 75 µm
4
SED1220 Series
■ ABSOLUTE MAXIMUM RATINGS
Item
Power supply voltage (1)
Power supply voltage (2)
Power supply voltage (3)
Input voltage
Symbol
VSS
Standard value
Unit
V
–6.0 to +0.3
–6.0 to +0.3
V5 to +0.3
V5, Vout
V1, V2, V3, V4
VIN
V
V
VSS–0.3 to +0.3
VSS–0.3 to +0.3
–30 to +85
V
Output voltage
VO
V
Operating temperature
Topr
°C
TCP
–55 to +100
–65 to +125
Storage temperature
Tstr
°C
Bare chip
(VCC) VDD
(GND) VSS
V
V
DD
5
Notes: 1. All the voltage values are based on VDD = 0 V.
2. For voltages of V1, V2, V3 and V4, keep the condition of VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 and VDD ≥ VSS
≥ V5 ≥ VOUT at all times.
3. If the LSI is used exceeding the absolute maximum ratings, it may lead to permanent destruction.
In ordinary operation, it is desirable to use the LSI in the condition of electrical characteristics. If the LSI
is used out of this condition, it may cause a malfunction of the LSI and have a bad effect on the reliability
of the LSI.
5
SED1220 Series
■ DC CHARACTERISTICS
(VDD = 0 V, VSS = –3.6 V to –2.4 V, Ta = –30 to 85°C unless otherwise specified.)
Item
Recommended
Symbol
Condition
min
–3.6
typ
–3.0
max
–2.4
Unit
V
Applicable pin
VSS
Power
supply
operation
voltage (1)
Operatable
Data retain
voltage
VSS
–5.5
–5.5
–3.0
–2.4
–2.0
*1
Power
supply
Recommended
operation
–6.0
–4.0
V
V5
V5
voltage (2)
Operatable
Operatable
Operatable
–6.5
0.6×V5
VDD
0.2×VSS
VSS
–4.0
VDD
0.4×V5
VDD
0.8×VSS
1.0
*2
V1, V2
V3, V4
VIHC
VILC
ILI
V
V
V
V
µA
KΩ
V1, V2
V3, V4
*3
*3
*3
High-level input voltage
Low-level input voltage
Input leakage current
LC driver ON resistance
VIN = VDD or VSS
–1.0
RON
Ta=25°C
∆V=0.1V
V5=–7.0V
20
40
COM,SEG
*4
Static current consumption
IDDQ
Display State
Sleep state
0.1
5.0
80
5
µA
µA
µA
VDD
VDD *5
VDD
Dynamic current
consumption
IDD
V
5
= –6 V without load
Oscillation OFF,
Power OFF
Access state fcyc=200KHz
500
8.0
µA
pF
VDD *6
*3
Input pin capacity
Frame frequency
CIN
Ta=25°C f=1MHz
5.0
fFR
fck
fck
Ta=25°C VSS=–3.0V
Display of 2 lines
Display of 3 lines
70
100
23.4
33.8
130
Hz
KHz
KHz
*10
*10 *11
*10 *11
External clock frequency
Reset time
Reset pulse width
Reset start time
tR
tRW
tRES
1.0
10
50
µs
µs
ns
*7
*8
*8
Dynamic system
Input voltage
Amplified voltage
output voltage
Voltage follower
operating voltage
Reference voltage
VS1
VOUT
–2.1
–2.0
V
V
*9
VOUT
When voltage is doubled
–6.0
–6.0
V5
–3.5
V
V
VREG
Ta = 25°C
*1: A wide operating voltage range is guaranteed but an
abrupt voltage variation in the access status of the MPU
is not guaranteed.
*4: This is a resistance value when a voltage of 0.1 V is applied
between output pin SEGn, SEGSn, COMn or COMSn, and
each power pin (V1, V2, V3 or V4). It is specified in the range
of operating voltage (2).
*2: When the voltage is Tripled, care must be paid to supply
the voltage VSS so that operating voltage of VOUT and V5
may not be exceeded.
RON = 0.1 V / ∆I
(∆I: Current flowing when 0.1 V is
applied between the power and output)
*3: D0 to D5, D6 (SCL), D7 (SI), A0, RES, CS WR (E), P/
S, IF
6
SED1220 Series
*9: When operating the boosting circuit, the power supply
VSS must be used within the input voltage range.
*5: Character “
” display. This is applicable to the
case where no access is made from the MPU and the
built-in power circuit and oscillating circuit are in operation.
*10:The fOSC frequency of the oscillator circuit for internal
circuit drive may differ from the fBST boosting clock on
some models. The following provides the relationship
between the fOSC frequency, fBST boosting clock, and fFR
frame frequency.
*6: Current consumption when data is always written by fcyc.
The current consumption in the access state is almost
proportional to the access frequency (fcyc).
When no access is made, only IDD (I) occurs.
fOSC = (No. of digits) × (1/Duty) × fFR
fBST = (1/2) × (1/No. of digits) × fOSC
*7: tR (reset time) indicates the internal circuit reset completion
time from the edge of the RES signal. Accordingly, the
SED1220 usually enters the operating state after tR.
*11:When operations are performed using the external clock
instead of the buit-in oscillation circuit, following waveforms
must be entered.
*8: Specifies the minimum pulse width of the RES signal. It
is reset when a signal having the pulse width greater than
tRW is entered.
•
•
Duty = (th/tOSC) × 100 = 70-80%
fOSC = 1/tOSC
V
V
DD
t
OSC
t, h
Power Supply
–2.4 V
SS
t
RES
V
V
DD
SS
RES
t
RW
tR
All signal timings are based on 20% and 80% of VSSS signals.
7
SED1220 Series
SED122✽DA
*
Lower 4 Bit of Code
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
8
SED1220 Series
SED122✽DB
*
Lower 4 Bit of Code
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
9
SED1220 Series
SED122✽DG
*
Lower 4 Bit of Code
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
SED1220 Series
NOTICE:
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson
reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any
inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material
is applicable to products requiring high level reliability, such as, medical products. Morever, no license to any intellectual property rights is granted
by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any
patent or copyright infringement of a third party. This material or portions thereof may contain techonology or the subject relating to strategic
products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry
of International Trade and Industry or other approval from another government agency.
©
Seiko Epson Corporation 1996 All right reserved.
ELECTRONIC DEVICE MARKETING DEPARTMENT
IC Marketing & Engineering Group
421-8 Hino, Hino-shi, Tokyo 191, JAPAN
Phone: 0425-87-5816
FAX: 0425-87-5624
International Marketing Department I (Europe, U.S.A.)
421-8 Hino, Hino-shi, Tokyo 191, JAPAN
Phone: 0425-87-5812
FAX: 0425-87-5564
International Marketing Department II (Asia)
421-8 Hino, Hino-shi, Tokyo 191, JAPAN
H
Phone: 0425-87-5814
FAX: 0425-87-5110
Issue Nov. 1996, printed in Japan
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