SED1278F0E [SEIKO]
16X40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, PQFP80, 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-80;
| 型号： | SED1278F0E |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | 16X40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, PQFP80, 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-80 CD |
| 文件： | 总39页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SED1278
OVERVIEW
FEATURES
The SED1278 is a dedicated character display controller/
driver which, when used with the SED1181F or the
SED1681 segment drivres, is able to display up to 80
characters under 4- or 8-bit MPU control.
The internal character generator (CG) ROM has an
extended 240, 5×10 pixel, character set, plus CGRAM
space for an additional eight user definable 5×8 pixel
characters. These memory features combined with the
rich set of control instructions offer the potential for a
highly flexible character display system.
• Interface for 4- and 8-bit MPUs
• Display RAM – 80 bytes (80 characters)
• Character generator ROM – 240 characters
– 5×8 pixel font
• Character genrator RAM – 64 bytes
– 5×8 pixel font, 8 characters.
– 5×10 pixel font, 4 characters.
• Number of characters used
No. of
characters used
Duty SED1278F SED1181FLA
The SED1278 features a guaranteed minimum LCD
drive voltage of 3 V making it suitable for use with low
voltage LCD panels.
One-line 1/8,
display 1/11
1
0
6
0
3
8 columns
× 1 line
80 columns
× 1 line
Two-line 1/16
display
1
8 columns
× 2 lines
40 columns
× 2 lines
• Powerful display control instructions
• LCD driver outputs
– 40 segment driver outputs
– 16 common driver outputs
• Low LCD drive voltage – 3 V minimum (VDD–V5)
• Dual-frame AC drive
• On-chip power-on reset
• On-chip RC oscillator
• Single 5 V operation
• Chip (SED1278D) and 80-pin QFP (SED1278F)
packages
(Compatible with HD 44780 and HD 66780 by Hitachi
Limited)
The SED1278 is equivalent to the HD 44780 and HD
66780 by Hitachi Limited. Before use, make sure that
there is no problem for practical use. It should be
noted that this is not intended to guarantee enforcement
of industrial property and other rights, or to grant
license for the use of this product.
EPSON
9–1
SED1278
BLOCK DIAGRAM
OSC1
OSC2
Instruction Decoder
Instruction Register
Cursor/ Printer Control
Oscillation
Circuit
Address
Counter ACC
Refresh Address Counter
7
DB 0
to
DB 7
XSCL
LP
FR
7
M P X
Timing Generator
Daia Register
Shift Register 16 Bits
Display Data RAM
DDRAM
80 Bytes
E
R/W
RS
Common Driving
Output Circuit
8
M P X
COM 1 to
COM 16
SEG 1 to
SEG 40
Character Generator
RAM
Character Generator
RAM
(CGROM)
5 x 10 x 240 Bits
V
V
V
V
V
V
V
SS
DC
1
(CGRAM)
64 Bits
Segment Driving
Output Circuit
5
5
2
Latch Circuit
40 Bits
40 Bits
M P X
5
3
4
Parallel/Serial
Data Converter
Shift Register
DO
5
PACKAGE OUTLINE
64
41
40
65
25
80
1
24
9–2
EPSON
SED1278
24
1
25
80
SED1278D
40
65
41
64
PINOUT
Pin
Pin
Pin
Pin
Number
Name
Number
Name
SEG2
Number
41
Name
DB2
Number
61
Name
COM15
COM16
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
1
2
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SEG1
GND
OSC1
OSC2
V1
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
DB3
62
3
DB4
63
4
DB5
64
5
DB6
65
6
DB7
66
7
V2
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
67
8
V3
68
9
V4
69
10
11
12
13
14
15
16
17
18
19
20
V5
70
LP
71
XSCL
VDD
FR
72
73
74
SEG8
DO
75
SEG7
RS
76
SEG6
R/W
E
77
SEG5
78
SEG4
DB0
DB1
79
SEG3
80
EPSON
9–3
SED1278
PIN DESCRIPTION
MPU Interface
DB0 to DB7 TTL level data input/output lines, for
connection to the system MPU data bus.
RS
Register select signal input. Selects
between the data and instruction registers
during CPU access.
RS = 0: Instruction register access cycle
RS = 1: Data register access cycle
This input selects between SED1278
register read and write cycles.
R/W = 0: Register write cycle
R/W = 1: Register read cycle
R/W
E
Read/write execute signal input.
TABLE 1 The Function of the E Signal
Operation
Instruction write cycle
RS
0
R/W
E
1
1
0
1
0
1
Busy flag read cycle
Address counter read cycle
0
DDRAM or CGRAM data write cycle
DDRAM or CGRAM data read cycle
1
1
LCD Panel Interface
External Segment Driver Interface
COM1 to COM16 Common driver outputs to the
LP
Data latch pulse output for an external
X-driver.
Data shift clock output for an external
X-driver.
LCD AC-drive waveform for an external
X-driver.
Display data output for an external X-driver.
LCD panel.
SEG1 to SEG40 Segment driver outputs to the LCD
panel.
XSCL
FR
OSC1
If the internal RC oscillator is used
to generate the LCD drive signals,
the feedback resistor, Rf, is
connected to this pin. If an external
clock source is used, the clock is
connected to this pin.
DO
OSC2
If the internal RC oscillator is used
to generate the LCD drive signals,
the feedback resistor, Rf, is
connected to this pin. If an external
clock source is used, this pin is left
open.
9–4
EPSON
SED1278
TERMINAL CONFIGURATION
1. Input terminal configuration (1)
V
DD
Applicable terminal
· E
· OSCI
Internal
VSS
2. Input terminal configuration (2)
With pull-up MOS resistor
V
DD
Applicable terminal
· RS, R/W
Internal
VSS
3. Output terminal configuration
V
DD
Applicable terminal
· OSC2
· XSCL, LP, FR, DO
Internal
VSS
EPSON
9–5
SED1278
4. Input/Output terminal configuration
V
DD
Applicable terminal
· DBO to DB7
Internal
V
SS
INSTRUCTION DESCRIPTION
Instruction Summary
Code
Cycle Time
Instruction
Description
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(max.)
Clears all display data and sets DDRAM
address 0 in the address counter.
Clear Display
Return Home
0
0
0
0
0
0
0
0
0
0
0
1
410 clocks
Set DDRAM address 0 in the address
counter. Also returns any shifted data to
home. The contents of DDRAM remain
unchanged.
0
0
0
0
0
0
1
*
410 clocks
10 clocks
Specifies the direction in which the cursor
moves and whether the display is to be
shifted or not, when data is writen to or read
from memory
Entry Mode Set
Display ON/OFF
0
0
0
0
0
0
0
1
1
I/D
S
Sets all display on/off (D) cursor on/off (C),
and character blinking in the cursor position
(B).
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
D
C
*
B
*
10 clocks
10 clocks
Cursor or
Moves the cursor and shifts the display
without changing the contents of DDRAM.
S/C R/L
Display Shift
Sets the interface data length (IF), number of
characters to be displayed (N), and character
font (F).
System Set
IF
N
F
*
*
10 clocks
Set CGRAM
Address
Set CGRAM addresses, followed by
transfer of CGRAM data.
0
0
0
0
0
1
ACG
ADD
10 clocks
10 clocks
Set DDRAM
Address
Sets DDRAM address, followed by
transfer of DDRAM data.
Reads the busy flag (BF) which indicates
internal operation and the contents of the
address counter.
Read Busy Flag
and Address
0
1
BF
ACC
0
Write Data to
1
1
0
1
Write Data
Read Data
Writes data to DDRAM or CGRAM.
Reads data from DDRAM or CGRAM.
10 clocks
10 clocks
CG or DDRAM
Read Data from
CG or DDRAM
* Don’t care
9–6
EPSON
SED1278
Write Only Instructions
Clear Display
writing the CGRAM always shifts the cursor. Note
that if a two line display is used both lines will be
shifted simultaneously.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
1
01H
Display ON/OFF
RS = 0
This instruction
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1. loads all locations in the display data (DD) RAM
0
0
0
0
1
D
C
B
08H to 0FH
with 20H.
RS = 0
2. clears the contents of the address counter to 0H.
3. sets the display for zero character shift.
4. sets the address counter to point to the DDRAM.
5. , if the cursor is displayed, moves the cursor to the
left most character in the display or, if a two line
display is used, moves the cursor to the leftmost
character in the top line (line 1).
This instruction controls various features of the display.
• The D bit turns the entire display on or off.
• D = 1: Display on
• D = 0: Display off
• The C bit turns the cursor on or off.
• C = 1: Cursor on
• C = 0: Cursor off
• The B bit enables blinking of the character the cursor
6. sets the address counter to increment on each access
of DDRAM or CGRAM.
coincides with.
• B = 1: Blinking on
• B = 0: Blinking off
Cursor Home
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Blinking is achieved by alternating between a normal
and all dark display of a character. The blinking
period is set at 204800 fOSC. For example if fOSC = 250
kHz the cursor will blink with a period of 0.8192
seconds, or about 1.2 Hz.
0
0
0
0
0
0
1
*
02H, 03H
RS = 0
This instruction
1. clears the contents of the address counter to 0H.
2. sets the address counter to point to the DDRAM.
3. sets the display for zero character shift.
4. , if the cursor is displayed, moves the cursor to the
left most character in the display or, if a two line
display is used, the left most character in the top line
(line 1).
Cursor/Display Shift
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
S/C R/L
*
*
10H to 1FH
RS = 0
This instruction shifts the display and/or moves the
cursor, on character to the left or right, regardless of a
DDRAM ready/write.
• The S/C bit selects movement of the cursor or
movement of both the cursor and the display.
• S/C = 1: Shift both cursor and display
• S/C = 0: Shift cursor only
• The R/L bit selects leftward or rightward movement of
the display and/or cursor.
• R/L = 1: Shift one character right
Entry Mode Set
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
1
I/D
S
04H to 07H
RS = 0
• The I/D bit selects the way in which the contents of the
address counter are modified after every access to
DDRAM or CGRAM.
• I/D = 1: The address counter is incremented.
• I/D = 0: The address counter is decremented.
• The S bit enables display shift, instead of cursor shift,
after each write or read to the DDRAM.
• R/L = 0: Shift one character left
System Set
• S = 1: Display shift enabled.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
• S = 0: Cursor shift enabled.
0
0
1
IF
N
F
*
*
20H to 3FH
The direction in which the display is shifted is opposite
in sense to that of the cursor. For example if S = 0 and
I/D = 1 the cursor would shift one character to the right
after an MPU write to DDRAM. However if S = 1 and
I/D = 1, the display would shift one character to the left
and the cursor would maintain its position on the
panel.
The cursor will already be shifted in the direction
selected by I/D during reads of the DDRAM,
irrespective of the value of S. Similarly reading and
RS = 0
This instruction initializes the system, and must be the
first instruction executed after power-on.
• The IF bit selects between an 8-bit or a 4-bit MPU
interface.
• IF = 1: 8-bit MPU interface using DB7 to DB0.
• IF = 0: 4-bit MPU interface using DB7 to DB4.
• The N and F bits select the number of display lines and
the corresponding duty cycle, as listed in table 2.
EPSON
9–7
SED1278
TABLE 2 Combinations of Display Lines and Duty Cycle
Number of
Line
Duty
Ratio
Common Output Non-Selected Common
N
F
Signal
Output Signal
COM9 to COM16
COM12 to COM16
—
0
0
1
0
1
*
1 line
1 line
1/8
1/11
1/16
COM1 to COM8
COM1 to COM11
COM1 to COM16
2 lines
TABLE 3 Valid CGRAM Address Ranges
Set CGRAM Address
Number of Lines Characters
ADR
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
ACR
40H to 7FH
1-line
1st line
2nd line
80
40
40
00H to 4FH
00H to 27H
40H to 67H
RS = 0
2-line
This instruction
1. loads a new 6-bit address into the address counter.
2. sets the address counter to address CGRAM.
Once “Set CGRAM Address” has been executed, the
contents of the address counter will be automatically
modified after every access of CGRAM, as determined
by the “Entry Mode Set” instruction.
Write Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DATA
If the “Set CGRAM Address” instruction is issued by the
system MPU while the display is enabled, and if either
the cursor is on or blink is on, pseudo-cursor or pseudo-
blink appears. To prevent this, turn both the cursor and
display blink off before loading a new CGRAM address.
The active width of the address counter, when it is
addressing CGRAM, is 6-bits so the counter will wrap
around to 00H from 3FH if more than 64 bytes of data are
written to CGRAM.
RS = 1
This instruction writes the data in DB7 to DB0 into either
the CGRAM or the DDRAM. The RAM space (CG or
DD), and the address in that space, that is accessed
depends on whether a “Set CGRAM Address” or a “Set
DDRAM Address” instruction was last executed, and on
the parameters of that instruction.
The contents of the address counter will be automatically
modified after each “Write Data”, as determined by
“Entry Mode Set”. When data is written to the CGRAM,
the DB7, DB6 and DB5 bits are not displayed directly as
characters.
Set DDRAM Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
ADD
RS = 0
80H to CFH … 1 line
80H to A7H line 1 … 2 line
C0H to E7H line 2 … 2 line
This instruction
1. loads a new 7-bit address into the address counter.
2. sets the address counter to point to the DDRAM.
Once the “Set DDRAM Address” instruction has been
executed, the contents of the address counter will be
automatically modified after each access of DDRAM, as
selected by the “Entry Mode Set” instruction.
The SED1278 has only 80 DDRAM locations. The valid
address spaces for various display configurations are
listed in table 3.
9–8
EPSON
SED1278
Read Only Instructions
Read Busy Flag/Address Counter
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Read Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
BF
ACC
DATA
RS = 1
RS = 1
Reading the instruction register yields the current value
of the address counter and the busy flag. This instruction
must be executed prior to any other instructions.
• ACC, the address counter value, will point to a location
in either CGRAM or DDRAM, depending on the type
of “Set RAM Address” instruction last sent.
In “Busy Flag Check” immediately after executing
“RAM Address Set” instruction, a valid address counter
value can be read 5 clock cycles after the busy flag
(BF) goes low.
In “Busy Flag Check” immediately after executing
“Write Data” instruction, a valid address counter
value can be ready as soon as BF goes low.
• The BF bit shows the status of the busy flag.
• BF = 1: SED1278 busy.
This instruction reads data from either CGRAM or
DDRAM, depending on the type of “Set RAM Address”
instructions last sent. The address in that space depends
on the “Set RAM Address” instructions parameters.
Immediately before executing “Read Data”, “Set
CGRAM Address” or “Set DDRAM Address” must be
executed.
The contents of the address counter are modified after
each “Read Data”, as determined by “Entry Mode Set”.
Display shift is not executed, independently of “Entry
Mode Set”.
• BF = 0: SED1278 ready for next instruction.
EPSON
9–9
SED1278
SPECIFICATIONS
Absolute Maximum Ratings
Parameter
Supply voltage (1)
Symbol
VDD
Rating
–3 to +7.0
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–20 to +75
–65 to +150
260, 10
Unit
V
Supply voltage (2)*
Input voltage
V1 to V5
VIN
V
V
Operating temperature
Storage temperature
Soldering temperature × time**
Power dissipation
Topr
°C
Tstg
°C
Tsol
°C, s
mW
PD
300
Notes: 1. VDD > V1 > V2 > V3 > V4 > V5 > VSS
2. A flat package product can become less resistant to moisture if exposed to extreme temperatures. When
mounting this package on a printed circuit board, use a soldering technique which avoids excessive
thermal loading of the package resin.
3. All voltages assume VSS = 0 V.
DC Characteristics
(VDD = 5.0 V ± 10%, VSS = 0 V, Ta = –20 to +75°C)
Rating
Parameter
Symbol
Condition
Unit Applicable Pins
min
2.0
typ
—
—
—
—
—
—
max
VDD
0.8
VDD
1.0
—
“H” level input voltage (1) (TTL)
“L” level input voltage (1) (TTL)
“H” level input voltage (2) (CMOS)
“L” level input voltage (2) (CMOS)
“H” level output voltage (1) (TTL)
“L” level output voltage (1) (TTL)
VIH1
VIL1
V
V
V
V
V
V
DB0 to DB7, RS,
R/W, E
VSS
VIH2
VIL2
VDD–1.0
VSS
OSC1
VOH1
VOL1
–IOH = 0.205 mA
2.4
DB0 to DB7
IOL = 1.6 mA
—
0.4
“H” level output voltage (2)
(CMOS)
VOH2
VOL2
–IOH = 0.04 mA
0.9VDD
—
—
—
—
V
V
XSCL, LP, DO
“L” level output voltage (2)
(CMOS)
IOL = 0.04 mA
0.1VDD
Driver-on resistor (COM)
Driver-on resistor (SEG)
I/O leakage current
RCOM
RSEG
IIL
| VCOM–Vn | = 0.5 V
| VSEG–Vn | = 0.5 V
VIN = 0 to VDD
—
—
—
2
10
10
1
kΩ COM1 to COM16
2.5
—
kΩ
µA
SEG1 to SEG40
DB0 to CB7, RS,
R/W
Pull-up MOS current
–IP
VDD = 5 V
50
125
250
µA
Rf oscillation, from
Supply current
IOP
external clock
—
0.5
0.8
mA
VDD
VDD = 5 V, fOSC = fCP = 270 kHz
9–10
EPSON
SED1278
AC Characteristics
• MPU write cycle timing (write to SED1278)
V
V
IH1
RS
IL1
t
AH
t
AS
R/W
E
V
IL1
t
WEH
t
AH
t
FE
VIH1
V
IL1
t
DS
t
DH
t
rE
V
V
IH1
IL1
DB0 to DB7
Valid Data
tcycE
(VDD = 5.0 V ± 10%, VSS = 0 V, Ta = –20 to 70°C)
Rating
Parameter
Symbol
Condition
Unit
min
500
220
—
max
—
Enable cycle time
tcycE
tWEH
trE, tfE
tAS
tAH
tDS
ns
ns
ns
ns
ns
ns
ns
Enable “H” level pulsewidth
Enable rise/fall time
RS, R/W setup time
RS, R/W address hold time
Data setup time
—
25
—
40
10
—
60
—
Write data hold time
tDH
10
—
• MPU read cycle timing (read from SED1278)
VIH1
VIL1
RS
tAS
tAH
VIH1
R/W
t
AH
t
WEH
t
fE
VIH1
E
VIL1
t
rE
t
DHR
tRD
VOH1
VOL1
DB0 to DB7
Valid Data
t
cycE
EPSON
9–11
SED1278
(VDD = 5.0 V ± 10%, VSS = 0 V, Ta = –20 to 75°C)
Rating
Parameter
Symbol
Condition
Unit
min
500
220
—
max
—
Enable cycle time
tcycE
tWEH
trE, tfE
tAS
tAH
tRD
ns
ns
ns
ns
ns
ns
ns
Enable “H” level pulsewidth
Enable rise/fall time
—
25
—
RS, R/W setup time
40
RS, R/W address hold time
Read data setup time
Read data hold time
10
—
CL = 100 pF
—
120
—
tDHR
20
• External segment driver signal timing
0.9 VDD
0.9 VDD
LP
t
WCLH
DSLP
t
WCLH
t
0.9 VDD
0.9 VDD
XSCL
0.1 VDD
0.1 VDD
0.1 VDD
t
WCLL
t
DSLP
0.9 VDD
0.1 VDD
0.9 VDD
0.1 VDD
DO
FR
t
OSX
tDHX
0.1 VDD
t
DFR
(VDD = 5.0 V ± 10%, VSS = 0 V, Ta = –20 to 70°C)
Rating
Parameter
Symbol
Condition
Unit
min
max
—
Clock pulsewidth: High level
Clock pulsewidth: Low level
Latch pulse setup time
Data setup time
tWCLH
tWCLL
tDSLP
tOSX
0.8/2fOSC
0.8/2fOSC
0.7/2fOSC
0.7/2fOSC
0.7/2fOSC
–1000
ns
ns
ns
ns
ns
ns
—
—
—
Data hold time
tDHX
—
FR delay
tDFR
1000
9–12
EPSON
SED1278
• Power-on reset timing
4.5V
0.2V
tr
toff
0.1ms ≤ tr ≤ 10ms
toff ≥ 1ms
(Ta = –20 to 75 deg. C)
LCD Drive Voltages
Pin
V1
V2
V3
V4
V5
Duty 1/8 or 1/11
Duty 1/16
4/5 (VDD – V5)
3/5 (VDD – V5)
2/5 (VDD – V5)
1/5 (VDD – V5)
V5
3/4 (VDD – V5)
2/4 (VDD – V5)
2/4 (VDD – V5)
1/4 (VDD – V5)
V5
Mechanical Specifications
SED1278F Package Dimensions
0.992±0.016
(25.2±0.4
)
0.787±0.004
(20.0±0.1
)
64
41
65
40
Index
80
25
0.031±0.006
(0.8±0.15
1
24
0.014±0.004
(0.35±0.1
)
)
0 to 12°
0.102
(2.6)
EPSON
9–13
SED1278
SED1278D Package Dimensions
Chip size:
Chip thickness:
4.50 mm × 3.67 mm
400 µm
Pad size:
Pad pitch:
109 µm × 109 µm
182 µm
24
1
25
80
Y
X
40
65
41
64
9–14
EPSON
SED1278
Pad
Pad
X (µm) Y (µm)
X (µm) Y (µm)
Number Name
Number Name
1
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
GND
OSC1
OSC2
V1
2087
1905
1723
1541
1359
1177
1671
1671
1671
1671
1671
1671
1671
1671
1671
1671
1671
1671
1671
1671
1671
1671
1671
1671
1671
1671
1671
1671
1671
1671
1365
1183
1001
819
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
DB2
–2087 –1671
–1905 –1671
–1723 –1671
–1541 –1671
–1359 –1671
–1177 –1671
–995 –1671
–814 –1671
–633 –1671
–452 –1671
–272 –1671
–91 –1671
91 –1671
2
DB3
3
DB4
4
DB5
5
DB6
6
DB7
7
995
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
8
814
9
633
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
452
272
91
–91
–272
–452
–633
–814
–995
–1177
–1359
–1541
–1723
–1905
–2087
–2087
–2087
–2087
–2087
–2087
–2087
–2087
–2087
–2087
–2087
–2087
–2087
–2087
272 –1671
452 –1671
633 –1671
814 –1671
995 –1671
1177 –1671
1359 –1671
1541 –1671
1723 –1671
1905 –1671
2087 –1671
2087 –1365
2087
–1183
V2
2087 –1001
V3
2087
2087
2087
2087
2087
2087
2087
2087
2087
2087
2087
2087
2087
–819
–637
–455
–273
–91
V4
637
V5
455
LP
273
XSCL
VDD
91
–91
91
FR
–273
–455
–637
–819
273
DO
455
RS
637
R/W
819
E
–2087 –1001
–2087 –1183
–2087 –1365
1001
1183
1365
DB0
DB1
EPSON
9–15
SED1278
OPERATION
The Busy Flag
The SED1278 takes between 10 and 410 clock cycles to
execute instructions. During that period additional
instructions should not be issued. The device is provided
with a busy flag to let the user check the internal state of
the chip. BF should be 0 before another instruction is
issued.
If the busy flag is not checked between instructions the
user must arrange for a guaranteed delay of more than the
instruction execution time, before issuing the next
instruction.
System Initialization
Power-on reset
Although the SED1278 has no external reset input, it will
automatically reset on system power-on. The sequence
starts once VDD < 4.5 V.
While the SED1278 is resetting the busy flag is set to 1.
The reset takes about 3,750 clock cycles. For example if
fOSC = 250 kHz, the reset sequence takes about 30 ms.
Reset places the SED1278 in a state where
• the display is clear.
• the system configuration corresponds to
• IF = 1: 8-bit MPU interface
• N = 0: 1-line display
4-Bit MPU Interface
If a “System Set” instruction is issued with bit 4 set to 0,
then the SED1278 will operate with a 4-bit MPU data bus
interface.
• F = 0: 1/8 duty cycle
• the display configuration corresponds to
• D = 0: Display off
If a 4-bit interface is used, the 8-bit instructions are
written nibble by nibble; the high-order nibble being
written first, followed by the low-order nibble. It is not
necessary to check the busy flag between writing separate
nibbles of individual instructions.
• C = 0: Cursor off
• B = 0: Blink off
• the entry mode is set to
• I/D = 1: Increment
• S = 1: No display shift
Reading the Busy Flag/Address Counter yields the high-
order nibble first, followed by the low-order nibble.
9–16
EPSON
SED1278
Software initialization
Initialization during power-on reset involves several
unstable factors related to power-supply output
fluctuations. For this reason it is strongly recommended
that a software initialization sequence is followed.
• Software Initialization (8-bit MPU bus, fOSC = 250 kHz)
Power-on
30 ms or more
[1]
[2]
[3]
[4]
DB7
0
·
0
·
1
·
1
·
*
·
*
·
*
DB0
*
RS R/W
E
E
E
System set
System set
System set
0
0
4.1 ms or more
DB7
0
·
0
·
1
·
1
·
*
·
*
·
*
DB0
*
RS R/W
0
0
100 µs or more
DB7
0
·
0
·
1
·
1
·
*
·
*
·
*
DB0
*
RS R/W
0
0
40 µs or more
DB7
BF
·
·
·
·
·
·
DB0
RS R/W
E
1
Busy flag
[5]
[6]
[7]
A
CC
0
1
BF=1
BF=0
DB7
0
·
0
·
1
·
1
·
N
·
F
·
*
DB0
*
RS R/W
E
System set
0
0
DB7
BF
·
·
·
·
·
·
DB0
RS R/W
E
1
Busy flag
A
CC
0
1
BF=1
BF=0
EPSON
9–17
SED1278
DB7
0
·
0
·
0
·
0
·
1
·
0
·
0
DB0
0
RS R/W
E
Display
on/off
[8]
[9]
0
0
Display off
DB7
BF
·
·
·
·
·
·
DB0
RS R/W
E
E
Busy flag
A
CC
0
0
BF=1
BF=0
DB7
0
·
0
·
0
·
0
·
0
·
0
·
0
DB0
1
RS R/W
[10]
[11]
Display Clear
0
0
DB7
BF
·
·
·
·
·
·
DB0
RS R/W
E
1
Busy flag
A
CC
0
1
BF=1
BF=0
DB7
0
·
0
·
0
·
0
·
0
·
1
·
I/D
DB0
S
RS R/W
E
Entry Mode
set
[12]
[13]
0
0
DB7
BF
·
·
·
·
·
·
DB0
RS R/W
E
1
Busy flag
ACC
0
1
BF=1
BF=0
Initialize
end
[14]
9–18
EPSON
SED1278
• Software Initialization (4-bit MPU bus, fOSC = 250 kHz)
Power-on
30 ms or more
[1]
[2]
[3]
[4]
[5]
DB7
0
·
0
·
1
DB4
1
RS R/W
E
E
E
E
System set
System set
System set
System set
0
0
4.1 ms or more
DB7
0
·
0
·
1
DB4
1
RS R/W
0
0
100 µs or more
DB7
0
·
0
·
1
DB4
1
RS R/W
0
0
40 µs or more
DB7
0
·
0
·
1
DB4
0
RS R/W
0
0
40 µs or more
DB7
BF
·
·
DB4
RS R/W
E
1
A
CC
(High-order)
(Low-order)
0
1
Busy flag
[6]
[7]
[8]
A
CC
0
1
1
BF=1
BF=0
DB7
0
·
0
·
1
DB4
0
RS R/W
E
(High-order)
(Low-order)
0
0
System set
N
F
*
*
0
0
DB7
BF
·
·
CC
DB4
RS R/W
E
1
A
(High-order)
(Low-order)
0
1
Busy flag
A
CC
0
1
1
BF=1
BF=0
EPSON
9–19
SED1278
DB7
0
·
0
·
0
DB4
0
RS R/W
E
(High-order)
(Low-order)
0
0
Display
on/off
[9]
1
0
0
0
0
0
DB7
BF
·
·
DB4
RS R/W
E
1
A
CC
(High-order)
(Low-order)
0
1
Busy flag
[10]
A
CC
0
1
1
BF=1
BF=0
DB7
0
·
0
·
0
DB4
0
RS R/W
E
(High-order)
(Low-order)
0
0
[11]
Display clear
0
0
0
1
0
0
DB7
BF
·
·
DB4
RS R/W
E
1
A
CC
(High-order)
(Low-order)
0
1
Busy flag
[12]
A
CC
0
1
1
BF=1
BF=0
DB7
0
·
0
·
0
DB4
0
RS R/W
E
(High-order)
(Low-order)
0
0
Entry Mode
set
[13]
0
1
I/D
S
0
0
DB7
BF
·
·
DB4
RS R/W
E
1
A
CC
(High-order)
(Low-order)
0
1
Busy flag
[14]
A
CC
0
1
1
BF=1
BF=0
Initialize
end
[15]
9–20
EPSON
SED1278
THE CHARACTER GENERATOR
Character Generator ROM (CGROM)
Character Generator RAM (CGRAM)
The SED1278 contains a 240 character, masked CGROM.
Each character is 5×10 pixels, for 1/11 duty cycle
compatibility. Refer to Appendix A for available codes
and their corresponding fonts.
Because the CGROM is masked, customers may arrange
to have their own CGROM masks made.
A custom mask allows the user to have
The SED1278 has 64 bytes of CGRAM, allowing the
user to program up to 8 characters.
5×8 pixel font (1/8 or 1/16 duty cycle)
The maximum character height is 8 pixels, however if a
cursor is used row 7 should be all zeros. 8 such characters
are available to the user.
The CGRAM address is made up of the following
components.
• their own character set.
• a character set of up to 256 characters.
• The least significant three bits, a2 to a0, specify the
row number of the character data.
• Bits a5 to a3 are made up of the least significant three
bits of the character code.
• The most significant bit, a7, is ignored.
Figure 1 shows an example 5×8 pixel font.
Please contact the SEIKO EPSON Marketing Department
for further information.
If a custom CGROM is used, two things should be noted.
1. The “Clear Display” instruction relies on the character
whose code is 20H being a blank.
2. If more than 240 ROMed characters are specified,
then the number of CGRAM characters available is
correspondingly reduced. The physical RAM space is
still available, and is available for use as memory,
however it will no longer have an associated character
code.
3. The character ROM implemented in a particular chip
is indicated by a two character suffix attached to the
device number, for example SED1278F0A.
CGRAM data
(Character pattern)
CGRAM address
A5
0
·
·
·
·
A0
0
DB7
·
*
*
*
*
*
*
*
*
·
*
*
*
*
*
*
*
*
·
·
·
·
DB0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
*
*
*
*
*
*
*
*
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
1
0
1
1
0
0
0
0
1
0
0
0
0
0
1
0
Figure 1 A 5×8 Pixel Font
EPSON
9–21
SED1278
5×11 pixel font (1/11 duty cycle)
The maximum character height is 11 pixels, however if
a cursor is used row 10 must be left blank.
The SED1278 requires that, although the maximum
character height is 11 rows, each character is allocated 16
rows (bytes) of address space. The last five bytes are
ignored.
• The least significant 4 bits, a3 to a0, specify the row
number of the character data.
• Bits a5 and a4 correspond to bits 2 and 3, respectively,
of the character code.
• The most significant bit, a7, is ignored.
Figure 2 shows an example 5×11 pixel font.
The CGRAM address is made up of the following
components.
CGRAM address
CGRAM data
A5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
·
·
·
·
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DB7
·
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
·
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
·
0
0
0
0
0
1
0
0
0
0
0
*
·
0
0
0
0
1
1
1
0
0
0
0
*
·
0
0
0
1
0
1
0
1
0
0
0
*
·
0
0
0
0
0
1
0
0
0
0
0
*
DB0
1
1
1
1
1
1
0
0
0
0
0
*
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Figure 2 A 5×11 Pixel Font
9–22
EPSON
SED1278
LCD INTERFACE
LCD Drive Voltages
The SED1278 generates segment and common drive
signals using the voltages supplied to pins V1, V2, V3, V4
and V5. The voltage levels at these pins depend on the
duty cycle of the display. The specifications of these
voltages.
The simplest way of producing these voltages is to use a
resistive dividing network.
Figures 3 and 4 show examples of networks for 1/8, or 1/
11, and 1/16 duty cycles respectively.
SED1278
V
V
V
DD
1
R
R
R
C
C
O
2
VR
C
V
V
3
4
C
R
V
V
5
C
SS
Figure 3 LCD Drive Voltage Network – 1/8 or 1/11 Duty Cycle
SED1278
V
DD
R
R
V
V
1
C
C
O
2
VR
R
R
R
C
V
V
3
4
C
C
V
V
5
C
SS
Figure 4 LCD Drive Voltage Network – 1/16 Duty Cycle
Notes: 1. V5 is set using a potentiometer and (VDD–VSS).
2. The power supply to the SED1278 should be bypassed with a capacitor, CO, of at least 0.1 µF placed as
close to the chip as possible.
EPSON
9–23
SED1278
LCD Drive Signal Waveforms
The segment and common drive waveforms generated
by the SED1278, for various duty cycle ratios, are shown
in figures 5, 6 and 7.
tFR
tFR
....
....
V
V
DD
SS
FR
....
....
....
....
V
V
V
V
DD
COM 1
COM 2
1
4
5
....
....
....
....
V
V
V
V
DD
1
4
5
....
....
....
....
V
V
V
V
DD
1
COM 8
SEG 1
4
5
....
....
....
V
V
V
DD
2
, V3
5
Figure 5 1/8 Duty Cycle Drive Waveforms
t
FR
tFR
....
....
V
V
DD
SS
FR
....
....
....
....
V
V
V
V
DD
1
COM 1
COM 2
4
5
....
....
....
....
V
V
V
V
DD
1
4
5
....
....
....
....
V
V
V
V
DD
1
COM 11
SEG 1
4
5
....
....
....
V
V
V
DD
5, V3
5
Figure 6 1/11 Duty Cycle Drive Waveforms
9–24
EPSON
SED1278
tFR
tFR
....
....
V
V
DD
SS
FR
....
....
....
....
V
V
V
V
DD
1
COM 1
COM 2
4
5
....
....
....
....
V
V
V
V
DD
1
4
5
....
....
....
....
V
V
V
V
DD
1
COM 16
SEG 1
4
5
....
....
....
V
V
V
DD
5, V3
5
Figure 7 1/16 Duty Cycle Drive Waveforms
LCD Interface Configurations
The SED1278 has 16 common and 40 segment drive
outputs, enabling the chip to drive up to 16 characters by
itself. The drive capability can be expanded to 80
characters, by using SED1181FLA external segment
drivers.
• 1 line
• 8 characters
• 5×7 pixels + cursor
• 1/8 duty cycle
• System set: N = 0, F = 0
8 ........
1
No. of
characters
SED1278
· · · · · · · · · · · · ·
COM 1
COM 7
COM 8
LCD panel
SEG 1
· · · · · · · · · · · · ·
SEG 40
EPSON
9–25
SED1278
• 1 line
• 8 characters
• 5×10 pixels + cursor
• 1/11 duty cycle
• System set: N = 0, F = 1
8 ........
No. of
characters
1
SED1278
· · · · · · · · · · · · ·
COM 1
COM 10
COM 11
LCD panel
SEG 1
· · · · · · · · · · · · ·
SEG 40
• 1 line
• 20 characters
• 5×7 pixels + cursor
• 1/8 duty cycle
• System set: N = 0, F = 0
........
SED1278
1
9
20
No. of
characters
8
· · ·
· · · · ·
COM 1
COM 7
COM8
LCD panel
SEG 1
SEG40
DO
NC
· · · · · ·
SEG 0
SEG59
SEG60
to
SEG63
D 0
DO1
SED1181FLA
XSCL
Open
DO0
D 1
LP
FR
XSCL
LP
FR
9–26
EPSON
SED1278
• 1 line
• 80 characters
• 5×7 pixels + cursor
• 1/8 duty cycle
• System set: N = 0, F = 0
1 ........
........
........
9
80
8
No. of
characters
COM 1
COM 7
COM8
LCD panel
SEG 1
SEG40
SEG 0 .......SEG63
SEG 0 .......SEG39
....
DO1
D 0
D 0
DO
Open
DO1
DO0 SED1181FLA
D 1
DO0 SED1181FLA
D 1
XSCL LP
FR
XSCL LP
FR
(1)
(6)
....
....
....
XSCL
LP
FR
• 2 line
• 8 characters
• 5×7 pixels + cursor
• 1/16 duty cycle
• System set: N = 1, F = don’t care
8........No. of
SED1278
1
· · · · · · · · · · · · ·
characters
COM1
1st line
COM7
COM8
COM9
2nd line
COM15
COM16
LCD panel
SEG 1
SEG40
· · · · · · · · · · · · ·
EPSON
9–27
SED1278
• 2 line
• 20 characters
• 5×7 pixels + cursor
• 1/16 duty cycle
• System set: N = 1, F = don’t care
........
1
9
20
No. of
characters
SED1278
COM1
8
· · ·
· · · · ·
1st line
COM7
COM8
COM9
2nd line
COM15
COM16
LCD panel
NC
SEG 1
SEG40
D O
· · · · · ·
· · ·
SEG60 ...SEG63
SEG0
SEG59
· · · · ·
D 0
DO0
D 1
DO1
SED1181FLA
Open
XSCL
LP
FR
XSCL
LP
FR
9–28
EPSON
SED1278
• 2 line
• 40 characters
• 5×7 pixels + cursor
• 16 duty cycle
• System set: N = 1, F = don‘t care
........
40
No. of
characters
· · · ·
· · · · · · · · ·
1
9
SED1278
COM 1
8
1st line
COM 7
COM 8
COM 9
2nd line
COM15
COM16
LCD panel
SEG 1
SEG40
· · · · · · · · ·
NC
SEG 0..SEG31SEG32
SEG 0
SEG63
DO1
· · ·
to
......
D O
D 0
D 0
SEG63
DO1
Open
DO0
D 1
DO0
D 1
LA
SED1181F
SED1181FLA
XSCL LP
FR
XSCL LP
FR
(1)
(3)
XSCL
LP
FR
EPSON
9–29
SED1278
MPU INTERFACE
The SED1278 has selectable 8- or 4-bit MPU interface.
An example of a typical 8-bit MPU interface is shown
figure 8.
Z80
A0
SED1278
RS
G1
A4
A5
A6
A
B
C
G2A
A7
IORQ
G2B
Y0
E
RD
WR
R/W
D0
to
D7
DB0
to
DB7
Figure 8 Interfacing the SED1278 to the Zilog Z80®
9–30
EPSON
SED1278
COMPARISON WITH HD44780 BY HITACHI
Item
HD44780 (Hitachi)
SED1278
Data display RAM
80 bytes
←
Character generator ROM
Character font
192 types
5 × 7: 160 types
5 × 10: 32 types
240 types
5 × 10: 240 types
Character generator RAM
LCD drive output
64 bytes
←
←
16 common driver outputs
40 segment drive outputs
Character font (with cursor)
5 × 8 dots (1/8 and 1/16 duty)
5 × 11 dots (1/1 duty)
←
←
Conversion to duty
1/8, 1/11, 1/16
LCD drive voltage (VDD–V5)
Max. 13.5 V
Min. 4.6 V
Max. 1 VDD
Min. 3 V
LCD drive waveform
E pulse width
Waveform A
(Single frame AC drive)
Waveform D
(Dual frame AC drive)
450 nsec
220 nsec
Timing to change the address
counter subsequent to CGRAM
and DDRAM data writing and
reading
The contents of address counter are
determined 1.5 clock after release of
busy state
The contents of address
counter are determined
immediately after release
of busy state.
(6 microseconds at fOSC = 250 kHz).
No. of instructions
11
←
←
←
←
←
Reset terminal
Not provided
Not provided
Provided
Chip selector terminal
Power-on reset terminal
Extension segment driver
Hitachi HD44100: 40 outputs
SED1181FLA: 64 outputs
Package
80-pin plastic flat package
←
Pin layout
Pin compatible
EPSON
9–31
SED1278
APPENDIX A: CHARACTER CODES AND FONTS
SED1278F0A/SED1278D0A
Higher 4-bit (D4 to D7) of Character Code (Hexadecimal)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
CG
RAM
(1)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
CG
RAM
(2)
CG
RAM
(3)
CG
RAM
(4)
CG
RAM
(5)
CG
RAM
(6)
CG
RAM
(7)
CG
RAM
(8)
CG
RAM
(1)
CG
RAM
(2)
CG
RAM
(3)
CG
RAM
(4)
CG
RAM
(5)
CG
RAM
(6)
CG
RAM
(7)
CG
RAM
(8)
9–32
EPSON
SED1278
SED1278F0B/SED1278D0B
Higher 4-bit (D4 to D7) of Character Code (Hexadecimal)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
CG
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
RAM
(1)
CG
RAM
(2)
CG
RAM
(3)
CG
RAM
(4)
CG
RAM
(5)
CG
RAM
(6)
CG
RAM
(7)
CG
RAM
(8)
CG
RAM
(1)
CG
RAM
(2)
CG
RAM
(3)
CG
RAM
(4)
CG
RAM
(5)
CG
RAM
(6)
CG
RAM
(7)
CG
RAM
(8)
EPSON
9–33
SED1278
SED1278F0C/SED1278D0C
Higher 4-bit (D4 to D7) of Character Code (Hexadecimal)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
CG
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
RAM
(1)
CG
RAM
(2)
CG
RAM
(3)
CG
RAM
(4)
CG
RAM
(5)
CG
RAM
(6)
CG
RAM
(7)
CG
RAM
(8)
CG
RAM
(1)
CG
RAM
(2)
CG
RAM
(3)
CG
RAM
(4)
CG
RAM
(5)
CG
RAM
(6)
CG
RAM
(7)
CG
RAM
(8)
9–34
EPSON
SED1278
SED1278F0E/SED1278D0E
Higher 4-bit (D4 to D7) of Character Code (Hexadecimal)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
CG
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
RAM
(1)
CG
RAM
(2)
CG
RAM
(3)
CG
RAM
(4)
CG
RAM
(5)
CG
RAM
(6)
CG
RAM
(7)
CG
RAM
(8)
CG
RAM
(1)
CG
RAM
(2)
CG
RAM
(3)
CG
RAM
(4)
CG
RAM
(5)
CG
RAM
(6)
CG
RAM
(7)
CG
RAM
(8)
EPSON
9–35
SED1278
SED1278F0G/SED1278D0G
Higher 4-bit (D4 to D7) of Character Code (Hexadecimal)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
CG
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
RAM
(1)
CG
RAM
(2)
CG
RAM
(3)
CG
RAM
(4)
CG
RAM
(5)
CG
RAM
(6)
CG
RAM
(7)
CG
RAM
(8)
CG
RAM
(1)
CG
RAM
(2)
CG
RAM
(3)
CG
RAM
(4)
CG
RAM
(5)
CG
RAM
(6)
CG
RAM
(7)
CG
RAM
(8)
9–36
EPSON
SED1278
SED1278F0H/SED1278D0H
Higher 4-bit (D4 to D7) of Character Code (Hexadecimal)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
CG
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
RAM
(1)
CG
RAM
(2)
CG
RAM
(3)
CG
RAM
(4)
CG
RAM
(5)
CG
RAM
(6)
CG
RAM
(7)
CG
RAM
(8)
CG
RAM
(1)
CG
RAM
(2)
CG
RAM
(3)
CG
RAM
(4)
CG
RAM
(5)
CG
RAM
(6)
CG
RAM
(7)
CG
RAM
(8)
EPSON
9–37
SED1278
APPENDIX B: PIN CONSTRUCTION
Input Pin Type 1
• E
• OSC1
VDD
VSS
Input Pin Type 2
• RS
• R/W
VDD
Pin
VSS
9–38
EPSON
SED1278
Output Pin
• OSC2
• XSCL, LP, FR, DO
V
DD
VSS
I/O Pin
• DB0 to DB7
V
DD
Pin
VSS
EPSON
9–39
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