SED1794T [SEIKO]
LIQUID CRYSTAL DISPLAY DRIVER, UUC, SLIM, TCP;
| 型号： | SED1794T |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC, SLIM, TCP 驱动 接口集成电路 |
| 文件： | 总8页 (文件大小：68K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PF934-01
SED1794D0B
SSCT5F0T0L0CSDeDrriievesr
■ DESCRIPTION
The gate driver LSI SED1794 is designed to drive an active matrix LCD panel.
It enables high-voltage operation, positive and negative output voltages and is compatible with various TFT-LCD
panel driving methods.
By switching the number of outputs between 200 and 192, it is compatible with the XGA/SXGA panel (192 outputs)
and the SVGA panel (200 outputs)
Thanks to its slim TCP shape, it enables a small-architectured LCD module to be realized.
■ FEATURES
● Number of gate driving outputs: 200/192
● Super slim chip: Slim TCP
● Low voltage operation available: 2.7 V (min.)
● Output switching function available (200/192 outputs)
● Gate output voltage VON – VOFF1 amplitude: 40 V (max.)
● Output shift direction-pin selection.
● Output enable function
● Package to be shipped
Au bump chip: SED1794D0B
TCP:
SED1794T
**
● This LSI is not designed to resist radiation or light.
1
SED1794D0B
■ BLOCK DIAGRAM
O1
O200
V
V
OFF1
ON
V
V
OFF1
ON
200-bit gate output circuit
V
V
OFF2
DDH
V
V
OFF2
DDH
200-bit level shifter
V
L
OE
CPV
SHL
200/192-bit bi-directional
shift register
TEST
IPC
MODE
VSS
V
CC
D
D
I
O
2
I
O
1
2
SED1794D0B
■ PAD LAYOUT
y
x
(0.0)
VDDH
VON
VOFF1
V
OFF2 MODE
VDDHL
CPV
OE
VCC
SHL
DIO1 VL
VDDH
VOFF2
TEST
VOFF1
V
ON
VDDH
Chip size:
Pad pitch:
16.00 mm × 1.08 mm
Output pin = 79 µm (min.) *1
Same input pin = 99 µm (min.) *2
Between input pins = 119 µm (min.) *2
Chip thickness: 625 µm (typical)
Au bump specifications: SED1794D0B (reference)
(X direction) (Y direction)
Bump size A:
Bump size B:
Bump size C:
Bump size D:
Bump size E:
50.4 µm × 80.0 µm *1
77.6 µm × 78.4 µm *2
49.6 µm × 56.0 µm *3
50.4 µm × 60.0 µm *4
58.4 µm × 59.2 µm *5
Notes
1. Pad # 81 to 280.
2. Pad # 1 to 18, 20 to 23, 25, 26, 28, 29, 31, 32, 34, 35, 37 to 41, 43, 44, 46 to 53, 55 to 60 and 62 to 75.
3. Pad # 76 to 79 and 282 to 285.
4. Pad # 80 and 281.
5. Pad # 19, 24, 27, 30, 33, 36, 42, 45, 54 and 61.
3
SED1794D0B
■ ABSOLUTE MAXIMUM RATINGS
(VSS = 0V)
Parameter
Supply voltage (1)
Symbol
VCC
Rating
–0.5 to +7.0
Unit
V
Supply voltage (2)
VDDH
–0.5 to +45.0
–0.5 to VDDH +0.5
–23.0 to +0.5
–0.5 to +45.0
V
Supply voltage (3)
VOH
V
Supply voltage (4)
VOFF1, VOFF2
V
Supply voltage (5)
VDDH – VOFF2
VON – VOFF1
V
Input voltage
VIN
IIN
–0.5 to VCC +0.5
±10
V
Input current
mA
mA
°C
Output current
IO
±10
Ambient operating temperature
Storing temperature
Ta
–25 to +85
–55 to +125
Tstg2
°C
Notes
1. All power supplies refer to VSS unless otherwise specified.
2. The LSI may permanently break if used outside the absolute maximum ratings shown above.
3. For voltages VCC, VSS, VDDH, VON, VOFF1 and VOFF2, be sure to keep the condition of “VOFF2 ≤ VOFF1 ≤ VSS ≤ VCC ≤ VDDH”.
4. Turn VCC, VOFF2/VOFF1 and VON/VDDH on in this order and follow the opposite order when turning the power off.
5. Never float VCC while a voltage of 10 V or higher is applied to VDDH – VOFF2 and VON – VOFF1 or allow VCC to go under 2.6
V, otherwise, an overcurrent may flow, disadvantageously affecting the LSI reliability.
V
DDH, VON
V
DDH, VON
V
CC
V
CC
Logic
GND
V
SS
V
OFF1, VOFF2
V
OFF1, VOFF2
■ RECOMMENDED OPERATING CONDITIONS
(VSS = 0 V)
Parameter
Supply voltage (1)
Symbol
VCC
Rating
2.7 to 5.5
Unit
V
Supply voltage (2)
VDDH
VON
10.0 to 40.0
10.0 to 40.0
–21.0 to –2.5
15 to 40.0
V
Supply voltage (3)
V
Supply voltage (4)
Supply voltage (5)
VOFF1, VOFF2
V
VDDH – VOFF2
VON – VOFF1
V
Operating frequency
Notes
fCPV
DC to 400
kHz
1. LSI operation is guaranteed within the recommended operating condition range.
2. Allowing for the power supply impedance in the mounted status, insert a bypass capacitor for noiseproof measures near the
VSS, VOFF1 and VOFF2 pins.
3. Unless swinging the VOFF1 supply voltage, make the electric potential the same as that of VOFF2.
4. When swinging the VOFF1 supply voltage, keep the range within “VOFF2 ≤ VOFF1 ≤ VON – 15 V”. In this case, the guaranteed
output resistance and fall time ratings will differ.
4
SED1794D0B
• Recommended operating voltage range
The recommended operating voltage is based on the combination of the high-dielectric strength logic system
power supply conditions and the logic system power supply conditions (the hatched portion in the figure below
on the right).
0
–2. 5
VOFF2
–10
–9
VDDH
V
V
V
CC
–20
2. 7 to 5. 5V
(0V)
VDDH–VOFF2
–21
26
SS
10
20
30
40
(V)
OFF2
V
DDH–VOFF2
indicates the point where VOFF2
= –21V and VDDH = 19V
■ ELECTRICAL CHARACTERISTICS
● DC Characteristics
Within the recommended operating voltage range when VSS = 0 V and Ta = –25 to 85°C unless otherwise
specified.
Rating
Parameter
Symbol
Condition
Units
Pin used
Min.
VSS
Typ.
—
Max.
0.3 × VCC
VCC
“L” input voltage
“H” input voltage
“L” output voltage
“H” output voltage
Output resistance
VIL
VIH
—
—
V
V
All input pins
All input pins
DIO1, 2
0.7 × VCC
VSS
—
VOL
VOH
RON
IOL = 40 µA
—
VSS + 0.4
VCC
IOH = 40 µA
VCC – 0.4
—
—
DIO1, 2
∆VON
= 1.0 V
VON – VOFF1
= 40 V
0.6
0.9
kΩ
O1 to O200
VON – VOFF1
= 30 V
—
—
0.7
0.9
1.0
1.5
VON – VOFF1
= 15 V
Input leakage current
Input capacity
ILI
—
–1.0
—
—
—
1.0
15
µA
pF
µA
µA
µA
All input pins
All input pins
VCC
CIN
ICC
Ta = 25°C
Current consumption (1)
Current consumption (2)
Current consumption (3)
fCPV = 60 kHz
—
5
10
IDDH
IOFF
—
380
–380
990
–990
VDDH
—
VOFF1, VOFF2
5
SED1794D0B
● AC Characteristics
t
CPV
CPV
t
CPV
CPVH
DH
t
t
DS
t
t
CPVL
DIO
(input)
t
pd3
tpd4
On
t
OR
t
OF
t
pd1
tpd2
DIO
(output)
t
WOE
OE
t
pd6
t
pd5
On
Notes
The input and output signal timings refer to 50% of the signal amplitude.
On output signal tOR and tOF refer to 10% and 90%.
6
SED1794D0B
• Input Timing Characteristics
Within the recommended operating voltage range when VSS = 0 V and Ta = –25 to 85°C unless otherwise
specified.
Parameter
Symbol
tCPV
Condition
Min.
2.5
Max.
—
Unit
µs
CPV cycle
During cascade connection
CPV high-level pulse width
CPV low-level pulse width
Data setup time
tCPVH
tCPVL
tDS
tDH
tWOE
—
—
—
—
—
400
500
100
100
700
—
ns
—
ns
—
ns
Data hold time
—
ns
OE high-level pulse width
—
ns
The logic input rise/fall times (tr and tf) are specified at 30 ns or less.
• Output Timing Characteristics
Within the recommended operating voltage range when VSS = 0 V and Ta = –25 to 85°C unless otherwise
specified.
Parameter
Symbol
tpd1
tpd2
tpd3
tpd4
Condition
Min.
Max.
600
600
550
550
Unit
ns
CPV to DIO output delay time
CL = 20 pF
—
ns
CPV to On output delay time
OE to On output delay time
CL = 220 pF
VDDH = VON = 20 V
VOFF2 = VOFF1 = –20 V
—
—
ns
ns
tpd5
tpd6
CL = 220 pF
VDDH = VON = 20 V
VOFF2 = VOFF1 = –20 V
—
—
550
550
ns
ns
On output rise time
On output fall time
tOR
tOF
CL = 220 pF
VDDH = VON = 20 V
VOFF2 = VOFF1 = –20 V
—
—
600
600
ns
ns
7
SED1794D0B
NOTICE:
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson
reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any
inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material
is applicable to products requiring high level reliability, such as, medical products. Morever, no license to any intellectual property rights is granted
by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any
patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products
under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry of
International Trade and Industry or other approval from another government agency.
IBM is registered trademark of International Business Machines Corporation, U.S.A.
©
Seiko Epson Corporation 1996 All right reserved.
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H
Printed Feb. 1998 in Japan
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