SG-645PHG33.0000MC0 [SEIKO]
IC,CRYSTAL OSCILLATOR,1-CHANNEL,2.5MHZ-33MHZ,HYBRID,DIP,4PIN,PLASTIC;
| 型号： | SG-645PHG33.0000MC0 |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | IC,CRYSTAL OSCILLATOR,1-CHANNEL,2.5MHZ-33MHZ,HYBRID,DIP,4PIN,PLASTIC |
| 文件： | 总2页 (文件大小：60K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Crystal oscillator
SOJ HIGH-FREQUENCY CRYSTAL OSCILLATOR
SG-645 series
Product number (Please refer to P1)
Q3364 5xxxx xxx 00
• Reflowable and high-density mounting-type SMD.
• Operable 3.3 V or 5.0 V.
• Output frequency from 2.5 MHz to 135 MHz.
• Output enable (OE:P type) or Stanby (ST:S Type) function allow more low
current consumption.
Actual size
Specifications
Item
Symbol
Remarks
SG-645PTG
SG-645PHG
2.5000 MHz to 33.0000 MHz
-0.5 V to +7.0 V
4.5 V to 5.5 V
-55 °C to +125 °C
SG-645PCG/SCG
2.7 V to 3.6 V
Output frequency range
fO
Refer to page 31. "Frequency range"
Max. supply voltage
Power source
voltage
Temperature
range
VDD-GND
Operating voltage
V
DD
STG
OPR
Storage temperature
Operating temperature
T
Stored as bare product after unpacking
Refer to page 31. "Frequency range"
-20 °C to +70 °C
T
-40 °C to +85 °C
B : ±50 x 10-6 C : ±100 x 10-6
M : ±100 x 10-6
Frequency stability
∆f/f0
-40 °C to +85 °C
No load condition
OE=GND (P G)
ST=GND (SCG)
25 mA Max.
20 mA Max.
—
12 mA Max.
10 mA Max.
50 µA Max.
Current consumption
Output disable current
Standby current
I
I
I
OP
OE
ST
50 % VDD, CL = 25 pF
1.4 V Level, CL = 25 pF
IOH = -8 mA
CMOS level
—
45 % to 55 %
Duty
tw/t
TTL level
40 % to 60 %
2.4 V Min.
—
—
—
VDD -0.4 V Min.
—
VOH
IOH = -16 mA
IOL = 8 mA
IOL = 16 mA
VDD -0.4 V Min.
Output voltage
—
0.4 V Max.
—
VOL
0.4 V Max.
Output load condition (fan out)
CL
VIH
VIL
25 pF
Output enable
CMOS level
2.0 V Min.
0.8 V Max.
70 % VDD Min.
20 % VDD Max.
OE,ST
OE,ST
disable input voltage
TTL level
CMOS level
Output rise time
TTL level
—
3.4 ns Max.
4.0 ns Max.
20 % to 80 % VDD, CL ≤ 25 pF
0.8 V to 2.0 V CL ≤ 25 pF
0.4 V to 2.4 V CL ≤ 25 pF
80 % to 20 % VDD CL ≤ 25 pF
2.0 V to 0.8 V CL ≤ 25 pF
2.4 V to 0.4 V CL ≤ 25 pF
Time at minimum operating voltage to be 0 s
Ta=+25 °C, VDD = 5.5 V / 3.3 V, First year
t
t
TLH
THL
1.2 ns Max.
2.4 ns Max.
—
1.2 ns Max.
2.4 ns Max.
—
—
—
—
4.0 ns Max.
—
CMOS level
Output fall time
TTL level
3.4 ns Max.
—
—
—
12 ms Max.
±5 x 10-6 Max.
Oscillation start up time
Aging
t
OSC
fa
Three drops on a hard board from 750 mm or
excitation test with 29400 m/s2 x 0.3 ms x 1/2
sine wave in 3 directions
±20 x 10-6
Shock resistance
S.R.
Note: • Unless otherwise stated, characteristics (specifications) shown in the above table are based on the rated operating temperature and voltage condition.
• External by-pass capacitor is recommended.
2.5
3.375
3.579545
3.6864
3.75
3.84
4.0
5.0
6.75
7.5
7.68
8.0
10.0
11.25
12.288
12.5
13.5
15.0
15.36
16.0
20.0
22.5
27.0
30.0
30.72
32.0
2.8125
3.072
3.125
5.625
6.144
6.25
7.15909
7.3728
14.31818
14.7456
14.74945
28.63636
29.4912
29.4989
24.576
25.0
3.6873625
4.096
7.374725
8.192
16.384
32.768
(Unit: mm)
(Unit: mm)
7.1±0.2
# 4
# 3
NO. Pin terminal
1.8
1
2
3
4
OE or ST
GND
OUT
VDD
# 1
# 2
0.4
0 Min.
5.08
(0.75)
(0.75)
Note.
OE Pin (PT, PH, PC, PTW, PHW, PCW)
OE pin - "H" or "open" : Specified frequency output.
OE pin - "L" : Output is high impedance.
5.08
ST pin (PT, PH, PC, PTW, PHW,PCW)
ST pin - "H" or "open" : Specified frequency output.
ST pin - "L" : Output is low level (weak pull-down), oscillation stops.
39
Metal may be exposed on the top or bottom of this product. This won't affect any quality, reliability or electrical spec.
Crystal oscillator
Specifications
Item
Symbol
Remarks
SG-645PTW / STW
SG-645PHW / SHW
SG-645PCW / SCW
Output frequency range
f
O
Refer to page 31. "Frequency range"
32.0001 MHz to 135.0000 MHz
-0.5 V to +7.0 V
4.5 V to 5.5 V
-55 °C to +125 °C
-20 °C to +70 °C
B : ±50 x 10-6
C : ±100 x 10-6
—
Max. supply voltage
Power source
voltage
VDD-GND
Operating voltage
V
DD
STG
OPR
3.0 V to 3.6 V
Storage temperature
Operating temperature
Temperature
range
T
Stored as bare product after unpacking
Refer to page 31. "Frequency range"
T
-40 °C to +85 °C
-20 °C to +70 °C
Frequency stability
∆f/f0
M: ±100 x 10-6
28 mA Max.
-40 °C to +85 °C
No load condition (fo = 135 MHz)
OE=GND (P W), fo = 135 MHz
ST=GND (S W)
Current consumption
Output disable current
Standby Current
I
OP
OE
ST
45 mA Max.
30 mA Max.
I
16 mA Max.
I
50 µA Max.
—
—
40 % to 60 %
45 % to 55 %
—
—
—
—
50 % VDD, CL = Max.
50 % VDD, CL = 25 pF (fo ≤ 66.6667 MHz)
1.4 V, CL = Max.
1.4 V, 5TTL +15 pF (fo ≤ 66.6667 MHz)
50 % VDD, CL = 15pF
Duty
tw/t
40 % to 60 %
45 % to 55 %
—
—
—
—
40 % to 60 %
V
DD -0.4 V
I
OH = -16 mA( TW / HW)
OH = -8 mA( CW)
OL = 16 mA( TW / HW)
OL = 8 mA( CW)
V
OH
V
DD -0.4 V
I
Output voltage
0.4 V
I
VOL
0.4 V
—
—
I
15 pF
—
—
(fo ≤ 135 MHz)
(fo ≤ 90 MHz)
5 TTL + 15 pF
25 pF
—
—
—
—
—
—
—
—
—
(fo ≤ 66.6667 MHz)
(fo ≤ 135 MHz)
(fo ≤ 90 MHz)
(fo ≤ 50 MHz)
(fo ≤ 135 MHz)
Output load
condition (fan out)
CL
15 pF
25 pF
50 pF
—
15 pF
70 % VDD
20 % VDD
3.0 ns
Output enable
disable input voltage
VIH
VIL
2.0 V Max.
0.8 V Max.
OE or ST
—
—
2.0 ns
4.0 ns
—
—
2.0 ns
4.0 ns
4.0 ns
3.0 ns
—
20 % to 80 % VDD CL = Max.
20 % to 80 % VDD CL ≤ 25 pF
0.8 V to 2.0 V CL = Max.
CMOS level
Output rise time
Output fall time
t
t
TLH
THL
—
—
3.0 ns
TTL level
CMOS level
TTL level
—
0.4 V to 2.4 V CL = Max.
4.0 ns
3.0 ns
—
80 % to 20 % VDD CL = Max.
80 % to 20 % VDD CL ≤ 25 pF
2.0 V to 0.8 V CL = Max.
—
—
—
2.4 V to 0.4 V CL = Max.
10 ms Max.
±5 x 10-6 / year Max.
Oscillation start up time
Aging
t
OSC
Ta = +25 °C, VDD = 5.0 V / 3.3 V, First year
fa
Three drops on a hard board from 750 mm or
excitation test with 29400 m/s2 x 0.3 ms x 1/2
sine wave in 3 directions
±20 x 10-6 Max.
Shock resistance
S.R.
40
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