SRM2264L10 [SEIKO]
Standard SRAM, 8KX8, 100ns, CMOS, PDIP28, PLASTIC, DIP-28;
| 型号： | SRM2264L10 |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | Standard SRAM, 8KX8, 100ns, CMOS, PDIP28, PLASTIC, DIP-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总12页 (文件大小：61K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SRM2264L10/12
CMOS 64K-BIT STATIC RAM
● Low Supply Current
● Access Time 100ns/120ns
● 8,192 Words × 8 Bits, Asynchronous
■ DESCRIPTION
The SRM2264L10/12 is an 8,192-word × 8-bit asynchronous, static, random access memory on a
monolithic CMOS chip. Its very low standby power requirement makes it ideal for applications requir-
ing non-volatile storage with back-up batteries. The asynchronous and static nature of the memory
requires no external clock or refreshing circuit. Both the input and output ports are TTL compatible,
and the three-state output allows easy expansion of memory capacity.
■ FEATURES
•
Fast access time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRM2264L10 . . . . . . . . . . . . . . . . . 100ns (Max)
SRM2264L12 . . . . . . . . . . . . . . . . . 120ns (Max)
•
Low supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standby
:
0.5µA (Typ)
Operation : 47mA (Typ) . . . . . . . . . . . . 100ns
45mA (Typ) . . . . . . . . . . . . 120ns
•
•
•
•
•
•
Completely static . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . No clock required
Single power supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ± 10%
TTL compatible inputs and outputs
Three-state output with wired-OR capability
Non-volatile storage with back-up batteries
Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRM2264L10/12 . . . . . . . . . . . DIP-28 pin (plastic)
SRM2264LM10/12 . . . . . . . SOP2-28 pin (plastic)
SRM2264LTM10/12 . . . . TSOP (I)-28 pin (plastic)
■ BLOCK DIAGRAM
A0
A1
A2
A3
A4
7
128
Memory Cell Array
128 x 64 x 8
A5
A6
A7
A8
A9
64 x 8
A10
A11
A12
6
64
Column Gate
CS1
CS2
8
OE
I/O Buffer
WE
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8
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SRM2264L10/12
■ PIN CONFIGURATION
■ PIN DESCRIPTION
A0 to A12
WE
Address Input
Write Enable
NC
A12
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
WE
CS2
A8
A9
A11
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
OE
Output Enable
Chip Select
CS1, CS2
I/O1 to 8
VDD
Data Input/Output
Power Supply (+5V)
Power Supply (0V)
No Connection
VSS
NC
9
10
11
12
13
14
A0
I/O1
I/O2
I/O3
VSS
■ ABSOLUTE MAXIMUM RATINGS
(VSS = 0V)
Parameter
Supply voltage
Symbol
Ratings
–0.5 to 7.0
–0.5 to 7.0
–0.5 to VDD + 0.3
1.0
Unit
V
VDD
VI
Input voltage*
V
Input/Output voltage*
Power dissipation
VI/O
PD
V
W
°C
°C
—
Operating temperature
Storage temperature
Soldering temperature and time
TOPR
TSTG
TSOL
0 to 70
–65 to 150
260°C, 10s (at lead)
*VI, VI/O (Min) = –3V (Pulse width is 50ns)
■ RECOMMENDED DC OPERATING CONDITIONS
(VSS = 0V, Ta = 0 to 70°C)
Parameter
Symbol
VDD
VSS
Min
4.5
Typ
5.0
0
Max
Unit
V
5.5
0
Supply voltage
0
V
VIH
2.2
3.5
0
VDD + 0.3
0.8
V
Input voltage
VIL
–0.3*
V
*
If pulse width is less than 50ns, it is –1.0V
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SRM2264L10/12
■ ELECTRICAL CHARACTERISTICS
DC Electrical Characteristics
●
(VDD = 5V ± 10%, VSS = 0V, Ta = 0 to 70°C)
SRM2264L10
SRM2264L12
Parameter
Symbol
Conditions
Unit
Min Typ* Max Min Typ* Max
Input leakage
current
ILI
VI = 0 to VDD
–1
—
—
—
1
–1
—
—
—
1
µA
mA
µA
IDDS
IDDS1
CS1 = VIH or CS2 = VIL
0.5
0.5
1.0
20
0.5
0.5
1.0
20
Standby supply
current
CS1 = CS2 ≥ VDD – 0.2V
or CS2 ≤ 0.2V
Average operating
current
VI = VIL, VIH
II/O = 0mA, tCYC = Min
IDDA
IDDO
—
—
47
35
82
60
—
—
45
35
80
60
mA
mA
Operating supply
current
VI = VIL, VIH
II/O = 0mA
CS1 = VIH or CS2 = VIL
or WE = VIL or OE = VIH,
VI/O = 0 to VDD
Output leakage
ILO
–1
—
1
–1
—
1
µA
High level output
voltage
VDD
– 0.1
VDD
– 0.1
VOH
VOL
IOH = –1.0mA
IOL = 4.0mA
2.4
—
—
2.4
—
—
V
V
Low level output
voltage
0.2
0.4
0.2
0.4
*
Typical values are measured at Ta = 25°C and VDD = 5.0V
●
Terminal Capacitance
Parameter
(f = 1MHz, Ta = 25°C)
Symbol
CADD
CI
Conditions
VADD = 0V
VI = 0V
Min
Typ
3
Max
Unit
pF
Address capacitance
Input capacitance
I/O capacitance
—
—
—
5
6
7
5
pF
CI/O
VI/O = 0V
6
pF
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SRM2264L10/12
●
AC Electrical Characteristics
Read Cycle
°
(VDD = 5V ± 10%, VSS = 0V, Ta = 0 to 70°C)
SRM2264L10
SRM2264L12
Test
Conditions
Parameter
Symbol
Unit
Min
100
—
—
—
—
10
—
10
—
5
Max
—
Min
120
—
—
—
—
10
—
10
—
5
Max
—
Read cycle time
tRC
tACC
tACS1
tACS2
tOE
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
CS1 access time
100
100
100
50
120
120
120
60
*1
CS2 access time
OE access time
CS1 output set time
CS1 output floating time
CS2 output set time
CS2 output floating time
OE Output set time
OE Output floating time
Output hold time
tCLZ1
tCHZ1
tCLZ2
tCHZ2
tOLZ
—
—
35
40
—
—
*2
*1
35
40
—
—
tOHZ
tOH
—
10
35
—
10
40
—
—
Write Cycle
°
(VDD = 5V ± 10%, VSS = 0V, Ta = 0 to 70°C)
SRM2264L10
SRM2264L12
Test
Conditions
Parameter
Symbol
Unit
Min
100
80
80
80
0
Max
—
—
—
—
—
—
—
—
—
35
—
Min
120
85
85
85
0
Max
—
—
—
—
—
—
—
—
—
40
—
Write cycle time
tWC
tCW1
tCW2
tAW
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip select time 1
Chip select time 2
Address enable time
Address setup time
Write pulse width
tAS
*1
tWP
tWR
tDW
tDH
60
0
70
0
Address hold time
Input data setup time
Input data hold time
WE Output floating
WE Output setup time
50
0
50
0
tWHZ
tOW
—
5
—
5
*3
*
See next page for test condtions.
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SRM2264L10/12
*1 Read/Write Cycle Test Conditions
1. Input pulse level: 0.8V to 2.4V
2. tr = tf = 10ns
3. Input and output timing reference levels: 1.5V
4. Output load ITTL + CL = 100pF
*2 Read Cycle Test Conditions
1. Input pulse level: 0.8V to 2.4V
2. tr = tf = 10ns
Test: tCHZ1, tCHZ2, tOHZ
Both SW1 and SW2 are closed.
Test: tCLZ1, tCLZ2, tOLZ Hi-Z→“H”
3. Test Circuit
SW1 is open, SW2 is closed.
Test: tCLZ1, tCLZ2, tOLZ Hi-Z→“L”
SW1 is closed, SW2 is open.
VDD
Output turn-on turn-off times
To scope
SW1
300Ω
1.5V
1.5V
OE
To output terminal
tOHZ
tOLZ
1.5V
“H”
“L”
“H”
“L”
Hi-Z
1.5V
Hi-Z
0.5V
I/O
1 kΩ
1.5V
1.5V
1.5V
1.5V
CS1
5 pF
tCHZ1
tCLZ1
CS2
I/O
Include scope,
SW2
tCLZ2
1.5V
tCHZ2
test, tool capacity
“H”
“L”
“H”
“L”
Hi-Z
VSS
VSS
1.5V
Hi-Z
0.5V
*3 Write Cycle Test Conditions
1. Input pulse level: 0.8V to 2.2V
2. tr = tf = 10ns
Test: tOW, tWHZ Hi-Z→“H” and “H”→Hi-Z
SW is VDD side
Test: tOW, tWHZ Hi-Z→“L” and “L”→Hi-Z
3. Test Circuit
SW is VSS side
Output turn-on turn-off times
VDD
To scope
300Ω
WE
1.5V
tOW
1.5V
tWHZ
H
L
Hi–Z
Hi–Z
0.1V
0.1V
0.1V
0.1V
I/O
To output terminal
SW
1 kΩ
5 pF
Include scope,
test, tool capacity
VSS
VSS
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SRM2264L10/12
●
Timing Charts
Read Cycle*1
°
tRC
ADDRESS
CS1
tOH
tACC
tACS1
tCHZ1
tCLZ1
CS2
tACS2
tCLZ2
tCHZ2
OE
tOE
tOHZ
tOLZ
Dout
Note: *1. During the read cycle, WE must be “H”.
Write Cycle (1) (CS1 Control)*2
°
tWC
ADDRESS
CS1
tAW
tWR
tCW1
tAS
CS2
WE
Dout
Din
tDW
tDH
Note: *2. During write cycle (1) and (2), the Output Buffer is in high impedance regardless of the OE level.
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SRM2264L10/12
Write Cycle (2) (CS2 Control)*2
°
tWC
ADDRESS
CS1
tAW
tWR
tAS
CS2
tCW2
WE
Dout
tDW
tDH
Din
Note: *2. During write cycle (1) and (2), the Output Buffer is in high impedance regardless of the OE level.
Write Cycle (3) (WE Control)*3
°
tWC
ADDRESS
tAW
tWR
CS1
CS2
WE
tAS
tWP
tWHZ
tOW
Dout
Din
tDW
tDH
Note: *3. During write cycle (3), the Output Buffer is in high impedance if the OE level is “H”.
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SRM2264L10/12
■ DATA RETENTION CHARACTERISTIC WITH LOW VOLTAGE POWER SUPPLY
(Ta = 0 to 70°C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply voltage
VDDR
2.0
—
5.5
V
VDD = 3V
CS1 = CS2 ≥ VDD – 0.2V
or CS2 ≤ 0.2V
Data retention current
IDDR
—
—
10
µA
Chip select data hold time
Operation recovery time
tCDR
tR
0
—
—
—
—
ns
ns
tRC*
*
tRC = Read Cycle time
●
Data Retention Timing (CS1 Control)
Data hold mode
VDD
4.5V
4.5V
V
DDR ≥ 2.0V
tCDR
tR
CS1 ≥ VDD – 0.2V
CS1
2.2V
2.2V
●
Data Retention Timing (CS2 Control)
Data hold mode
VDD
V
DDR ≥ 2.0V
4.5V
4.5V
tCDR
tR
CS2
0.4V
0.4V
CS2 ≤ 0.2V
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SRM2264L10/12
■ FUNCTIONS
●
Truth Table
CS1
CS2
X
OE
—
—
X
WE
—
—
L
A0 to A12
—
Data I/O
Hi-Z
Mode
Unselected
Unselected
Write
IDD
IDDS, IDDS1
IDDS, IDDS1
IDDO
H
—
L
L
—
Hi-Z
H
Stable
Stable
Stable
Input data
Output data
Hi-Z
L
H
L
H
Read
IDDO
L
H
H
H
Output disable
IDDO
X: “H” or “L”
—: “H”, “L”, or “Hi-Z”
●
●
Read Data
Data is able to be read when the address is set while holding CS1=“L”, CS2=“H”, OE=“L” and WE=“H”.
Since Data I/O terminals are high impedance state when OE=“H”, the data bus line can be used for
any other objective, then access time apparently is able to be cut down.
Write Data
There are four ways of writing data into memory (see “Timing Charts”, above):
1. Hold CS2=“H”, WE=“L” set addresses and give “L” pulse to CS1.
2. Hold CS1=“L”, WE=“L” set addresses and give “H” pulse to CS2.
3. Hold CS1=“L”, CS2=“H” set addresses and give “L” pulse to WE.
4. After setting addresses, give “L” pulse to CS1, WE and give “H” pulse to CS2.
Anyway, data on the Data I/O terminals are latched up into the SRM2264L10/12 at the end of the period
that CS1, WE are “L” level, and CS2 is “H” level. As Data I/O terminals are in high impedance state
when any of CS1, OE=“H”, or CS2=“L”, the contention on the data bus can be avoided.
●
Standby Mode
When CS1 is “H” or CS2 is “L” level, the SRM2264L10/12 is in the standby mode which has data re-
taining operation. In this case Data I/O terminals are Hi–Z, and all inputs of addresses, WE. When
CS1 and CS2 level are in the range over VDD – 0.2V, or CS2 level is in the range under 0.2V, in the
SRM2264L10/12 there is almost no current flow except through the high resistance parts of the memory.
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SRM2264L10/12
■ PACKAGE DIMENSIONS
Plastic DIP-28pin
Unit: Inches (mm)
1.472Max
(37.4Max)
0.004
1.445 ±
(36.7 ±
0.1
)
28
15
14
1
0.600
(15.24)
0.059
(1.5 )
0.0010
0.0004
0.010 ±
(0.25 ±
0.03
)
0.01
0.600~0.655
(15.24~16.64)
0.010
0.004
0.100 ±
(2.54 ±
0.018 ±
(0.46 ±
0.25
0.1
)
)
Plastic SOP2-28pin*
Unit: Inches (mm)
0.713 Max
(18.1 Max)
0.004
0.701 ±
(17.8 ±
0.1
)
28
15
1
14
0.370
(9.4)
0.004
0.039
(1.0)
0.050
(1.27)
0.016 ±
(0.4 ±
0.1
)
*
SRM2264LM10/12 has the same electrical characteristics as SRM2264L10/12.
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SRM2264L10/12
■ CHARACTERISTIC CURVES
Normalized IDDA—tcycle
VDD = 5.5V
Normalized IDDA—VDD
Normalized IDDA—Ta
VDD = 5.5V
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
Ta = 25°C
T
cyc = Min
1.2
1.0
0.8
0.6
0.4
0.2
1.1
1.0
0.9
0.8
0.7
Ta = 25°C
cyc = Min
T
0
20
40
60 (°C)
100
200 300 500 700 1,000
3
4
5
6
7
(V)
(ns)
Normalized IDDS1—Ta
Normalized IDDS1—VDD
10
5
IOH—VOH
VDD = 5.5V
CS = VDD – 0.2V
4.0
3.0
(mA)
10
VDD = 4.5V
Ta = 25°C
Ta = 25°C
CS = VDD – 0.2V
2.0
1.0
1.0
0.5
5
0.4
0
1
2
3
4
5
0
3
4
5
6
7
(V)
(V)
0
20
40
60 (°C)
Normalized tACC·tACS—Ta
VDD = 4.5V
Normalized tACC·tACS—VDD
IOL—VOL
(mA)
10
VDD = 4.5V
Ta = 25°C
Ta = 25°C
CL = 100pF
CL = 100pF
1.1
1.2
1.0
0.9
0.8
0.7
1.1
1.0
0.9
0.8
5
0
20
40
60
80 (°C)
0
4
5
6
6
(V)
0.5
1.0 (V)
0
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