SRM2B256SLMX55 [SEIKO]

Standard SRAM, 32KX8, 100ns, CMOS, PDSO28;


型号：	SRM2B256SLMX55
厂家：	SEIKO EPSON CORPORATION
描述：	Standard SRAM, 32KX8, 100ns, CMOS, PDSO28 静态存储器光电二极管内存集成电路
文件：	总6页 (文件大小：104K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PF827-03

SRM2B256SLMX55/70/10

256K-Bit Static RAM

● Wide Temperature Range

● Extremely Low Standby Current

● Access Time 100ns (2.7V) /55ns (4.5V)

● 32,768 Words✕8-bit Asynchronous

■ DESCRIPTION

The SRM2B256SLMX is a low voltage operating 32,768 words✕8-bit asynchronous, static, random access

memory fabricated using an advanced CMOS technology. Its very low standby power consumption makes it

ideal for applications requiring non-volatile storage with back-up batteries. And –25 to 85°C operating temperature

range makes it ideal for industrial use. The asynchronous and static nature of the memory requires no external

clock or refresh circuit. Output ports are 3-state output allows easy

expansion of memory capacity. These features makes the

■ PIN CONFIGURATION

SRM2B256SLMX usable for wide range of applications from

(DIP/SOP2)

28 V^DD

27 WE

26 A13

25 A8

24 A9

23 A11

22 OE

21 A10

20 CS

19 I/O8

18 I/O7

17 I/O6

16 I/O5

15 I/O4

A14

A12

I/O1 11

I/O2 12

I/O3 13

V^SS14

microprocesser systems to terminal devices.

■ FEATURES

● Wide temperature range ................... –25 to 85°C

● Extended supply voltage range ......... 2.7 to 5.5V

● Fast access time ............................... 100ns (3V±10%)

55ns (5V±10%)

● Extremely low standby current .......... SL Version

● Completely static ............................... no clock required

● 3-state output

(TSOP)

● Battery back-up operation

21 A10

20 CS

● Package .............. SRM2B256SLCX

DIP2-28pin (plastic)

SOP2-28pin (plastic)

A11 23

19 I/O8

18 I/O7

17 I/O6

16 I/O5

15 I/O4

14 V^SS

13 I/O3

12 I/O2

11 I/O1

10 A0

SRM2B256SLMX

A13 26

V^DD

A14

A12

SRM2B256SLTMX TSOP (I)-28pin (plastic)

SRM2B256SLRMX TSOP (I)-28pin-R1 (plastic)

SRM2B256SLTMX

■ BLOCK DIAGRAM

(TSOP-R1)(Reverse bending)

A10

A11

A12

A13

A14

512

Memory Cell Array

10 A0

512✕64✕8

11 I/O1

12 I/O2

13 I/O3

16 I/O5

17 I/O6

18 I/O7

19 I/O8

20 CS

A12

A14

V^DD

V^SS

I/O4

SRM2B256SLRMX

64✕8

A13 26

Column Gate

A11 23

OE 22

21 A10

■ PIN DESCRIPTION

A0 to A14 Address Input

Write Enable

Output Enable

Chip Select

I/O Buffer

I/O1 to I/O8 Data Input/Output

VDD

VSS

Power Supply (2.7 to 5.5V)

Power Supply (0V)

I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8

SRM2B256SLMX55/70/10

■ ABSOLUTE MAXIMUM RATINGS

(V_SS=0V)

Parameter

Symbol

V_DD

V_I

Rating

Unit

Supply voltage

–0.5 to 7.0

–0.5^✽to 7.0

Input voltage

V_I/O

P_D

–0.5^✽to V_DD+0.3

Input/Output voltage

Power dissipation

1.0

T_opr

T_stg

–25 to 85

–65 to 150

Operating temperature

Storage temperature

Soldering temperature and time

°C

–

T_sol

260°C, 10s (Lead only)

✽

V_I, V_I/O(Min.)= –3.0V when pulse width is less or equal to 50ns

■ DC RECOMMENDED OPERATING CONDITIONS

(V_SS=0V, Ta=–25 to 85°C)

V_DD=3V±10%

Typ.

V_DD=5V±10%

Typ.

Symbol

Parameter

Unit

Min.

2.7

2.2

–0.3^✽

Max.

3.3

Min.

4.5

2.2

–0.3^✽

Max.

5.5

V_DD

V_SS

V_IH

V_IL

–

Supply voltage

_DD+0.3

Input voltage

0.4

0.8

✽

V_IL(Min.)= –3V when pulse width is less or equal to 50ns

■ ELECTRICAL CHARACTERISTICS

● DC Electrical Characteristics

(V_SS=0V, Ta=–25 to 85°C)

_DD=3V±10%

V_DD=5V±10%

Parameter

Input leakage

Symbol

I_LI

Conditions

Unit

µA

Min. Typ.^✽1Max. Min. Typ.^✽2Max.

–

V_I=0 to V_DD

–1.0

1.0 –1.0

1.0

CS=V_IHor WE=V_IL

or OE=V_IH, V_I/O=0 to V_DD

Output leakage

I_LO

–1.0

–

1.0 –1.0

–

1.0

µA

I_DDS

CS=V_IH

–

3.0

Standby supply current

CS≥V_DD–0.2V

I_DDS1

0.3

0.5

µA

V_I=V_IL, V_IH

I_DDA

–

I_I/O=0mA, tcyc=Min.

Average operating current

Operating supply current

V_I=V_IL, V_IH

I_I/O=0mA, tcyc=1µs

I_DDA1

I_DDO

V_I=V_IL, V_IH

I_I/O=0mA

–

I_OH=–1.0mA, –0.5mA^✽3

I_OL=2.1mA, 1.0mA^✽3

2.4

–

2.4

–

High level output voltage

Low level output voltage

V_OH

V_OL

0.4

✽1 Typical values are measured at Ta=25°C and V_DD=3.0V

✽2 Typical values are measured at Ta=25°C and V_DD=5.0V

✽3 V_DD=3V±10%

(f=1MHz, Ta=25°C)

● Terminal Capacitance

Parameter

Input Capacitance

I/O Capacitance

Symbol

C_I

C_I/O

Conditions

V_I=0V

V_I/O=0V

Min.

Typ.

Max.

Unit

–

Note : This parameter is made by the inspection data of sample, not for all products.

● AC Electrical Characteristics

❍ Read Cycle

(V_SS=0V, Ta=–25 to 85°C)

55 SRM2B256SLMX70 SRM2B256SLMX10

SRM2B256SLMX

Parameter

Symbol Conditions V_DD=3V±10% V_DD=5V±10% V_DD=3V±10% V_DD=5V±10% V_DD=3V±10% V_DD=5V±10%

Unit

Min. Max. Min. Max. Min. Max. Min. Max. Min.

Max. Min. Max.

t_RC

100

–

100

–

120

–

120

–

180

–

180

–

100

–

100

–

Read cycle time

Address access time

CS access time

t_ACC

t_ACS

t_OE

t_CLZ

t_CHZ

t_OLZ

t_OHZ

t_OH

✽1

OE access time

CS output set time

CS output floating

OE output set time

OE output floating

Output hold time

✽2

✽1

SRM2B256SLMX55/70/10

❍ Write Cycle

(V_SS=0V, Ta=–25 to 85°C)

55 SRM2B256SLMX70 SRM2B256SLMX10

SRM2B256SLMX

Parameter

Symbol Conditions V_DD=3V±10%

V_DD=5V±10%

V_DD=3V±10%

V_DD=5V±10%

V_DD=3V±10%

V_DD=5V±10%

Unit

Min. Max. Min. Max. Min. Max. Min. Max. Min.

Max. Min. Max.

Write cycle time

t_WC

t_CW

t_AW

t_AS

100

–

120

–

180

110

–

100

–

Chip select time

–

Address valid to end of write

Address setup time

Write pulse width

–

✽1

✽2

t_WP

t_WR

t_DW

t_DH

–

100

–

Address hold time

–

Input data set time

Input data hold time

Write to Output floating

Output Active from end to wirte

–

t_WHZ

t_OW

–

✽1 Test Conditions

✽2 Test Conditions

1. Input pulse level: 0.6V to 2.4V

2. t^r=tf=5n=s

1. Input pulse level : 0.6V to 2.4V

2. t^r=tf=5ns

3. Input and output timing reference levels : 1.5V

4. Output load C^L=100pF

3. Input timing reference levels: 1.5V

4. Output timing reference levels:

±200mV (the level displaced from stable output voltage level)

5. Output load C^L=5pF

1TTL

I/O

C_L=100pF (Includes Jig Capacitance)

C_L=5pF (Includes Jig Capacitance)

● Timing chart

❍ Read Cycle^✽1

❍ Write Cycle (1) (CS Control)^✽2

ADDRESS

ACC

ACS

tOH

CLZ

CHZ

OHZ

tWHZ

CLZ

OLZ

DOUT

tDH

Din

Note :

✽1 During read cycle time, WE is to be "H" level.

❍ Write Cycle (2) (WE Control)^✽3

✽2 During write cycle time that is controlled by CS, Output Buffer is in

high impedance state, whether OE level is "H" or "L".

✽3 During write cycle time that is controlled by WE, Output Buffer is in

high impedance state if OE is "H" level.

ADDRESS

tWR

WHZ

OUT

tDH

Din

SRM2B256SLMX55/70/10

● DATA RETENTION CHARACTERISTIC WITH LOW VOLTAGE POWER SUPPLY

(V_SS=0V, Ta=–25 to 85°C)

Parameter

Symbol

V_DDR

Conditions

Min.

2.0

Typ.^✽1

–

Max. Unit

Data retention Supply voltage

5.5

V_DD=3V,

I_DDR

Data retention current

20(2^✽2

µA

)

–

0.25

CS≥V_DD–0.2V

–

Chip select data hold time

Operation recovery time

t_CDR

t_R

✽1 Typical values are measured at 25 °C

✽2 Typical values are measured at 40 °C

Data retention timing

Data hold mode

VDD

2.7V

VDDR ≥2.0V

CDR

CS ≥V^DD– 0.2V

VIH

Note: During standby mode in which the data is retentive, the supply voltage (VDD) can be in low voltage until VDD=VDDR.

At this mode data reading and writing are impossible.

■ FUNCTIONS

● Truth Table

DATA I/O

Hi-Z

Mode

Standby

Write

I_DD

I_DDS

I_DDS1

I_DDA1

I_DDA

D_IN

Read

D_OUT

Hi-Z

Output disable

X : "H" or "L", – "H", "L" or "Hi-Z"

● Read Mode

The data appear when the address is set while holding CS= "L", OE= "L" and WE= "H".When OE= "L", DATA I/

O terminals are in high impedance state, that makes circuit design and bus control easy.

● Write Mode

There are the following 3 ways of writing data into memory.

(1) Hold CS= "L" and WE= "L", set address

(2) Hold CS= "L" then set address and give "L" pulse to WE.

(3) After setting addresses, give "L" pulse to both CS and WE.

In above any case data on the DATA I/O terminals are latched up into the chip when CS or WE is in positive-

going. Since DATA I/O terminals are high impedance when CS or OE= "H", bus contention between data driver

and memory outputs can be avoided.

● Standby Mode

When CS is "H" the chip become in the standby mode. In this mode, DATA I/O terminals are high impedance and

all inputs of addresses, WE and data can be any "H" or "L" . When CS is over than VDD-0.2V, the chip is in the

data retention battery backup mode, in this case, there is a small current in the chip which flow through the high

resistances of the memory cells.

SRM2B256SLMX55/70/10

■ PACKAGE DIMENSIONS

Plastic DIP-28 pin (600mil)

37.4max

(1.472max)

±0.1

36.7

(1.445

+0.003

–0.004

)

1.5

(0.059)

2.54^±0.25

(0.1)

0.46^±0.1

(0.018)

15.24

(0.6)

0°

15°

Unit:mm(inch)

Plastic TSOP(I) - 28 pin -R1

Plastic TSOP(I) - 28 pin

±0.3

13.4

(0.528

13.4

(0.528

+0.011

–0.012

)

±0.2

11.8

+0.007

–0.008

(0.465

±0.1

0.15

(0.006

±0.1

+0.003

0.15

(0.006

–0.004

+0.003

)

–0.004

)

±0.1

0.5

(0.02

±0.1

+0.003

0.5

(0.02

INDEX

–0.004

+0.003

)

–0.004

)

0.8

(0.031)

±0.1

0.2

0.55

(0.022)

+0.003

–0.004

)

(0.008

±0.1

0.2

0.55

(0.022)

+0.003

–0.004

)

(0.008

0°

10°

0°

10°

Unit:mm(inch)

Plastic SOP2-28 pin (450mil)

18.1max

(0.712max)

±0.1

17.8

(0.701

+0.003

–0.004

)

±0.1

0.4

1.27

(0.05)

+0.003

–0.004

)

(0.016

±0.05

0.15

(0.006

+0.001

–0.002

)

1^±0.3

(0.039

+0.012

–0.011

)

1.7

(0.067)

0°

10°

Unit:mm(inch)

SRM2B256SLMX55/70/10

■ CHARACTERISTICS CURVES

Normalized I_DDA–Ta

Normalized I_DDA–Frequency

Normalized I_DDA–V_DD

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

1.3

1.2

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.1

0.0

0.7

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

–

–25

25 50 75 100

Ta (°C)

Frequency (MHz)

_DD(V)

Ta=25°C

Normalized I_DDS1–Ta

Normalized I_DDS1–V_DD

Normalized I_OH–V_OH

100.0

10.0

1.0

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

2.5

1.5

0.1

0.5

0.0

–

–25

25 50 75 100

Ta (°C)

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

0.0 1.0 2.0 3.0 4.0 5.0 6.0

V_OH(V)

Ta=25°C

Normalized t_ACC,t_ACS–V_DD

Normalized t_ACC–t_ACS

Normalized I_OL–V_OL

1.3

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

2.5

2.0

1.5

1.2

1.1

1.0

0.9

0.8

0.7

0.5

–

–25

25 50 75 100

Ta (°C)

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

0.0 0.2

0.4 0.6 0.8 1.0

V_OH(V)

Ta=25°C

NOTICE:

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko

Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of

any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that

this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual

property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this

material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the

subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an

export license from the Ministry of International Trade and Industry or other approval from another government agency.

ELECTRONIC DEVICES MARKETING DIVISION

IC Marketing & Engineering Group

ED International Marketing Department I (Europe & U.S.A.)

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

Phone : 042-587-5812 FAX : 042-587-5564

ED International Marketing Department II (Asia)

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

Phone : 042-587-5814 FAX : 042-587-5110

SRM2B256SLMX55 [SEIKO]

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