E4717DBG [SEMTECH]
Quad Channel, Per Pin Precision Measurement Unit; 四通道，每针精密测量单元
| 型号： | E4717DBG |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Quad Channel, Per Pin Precision Measurement Unit |
| 文件： | 总22页 (文件大小：211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Edge4717D
Quad Channel, Per Pin
Precision Measurement Unit
TEST AND MEASUREMENT PRODUCTS
Features
Description
The Edge4717D is a precision measurement unit designed
for automated test equipment and instrumentation.
Manufactured in a wide voltage CMOS process, it is a
monolithic solution for a quad channel per pin PMU.
•
•
•
•
•
FV / MI Capability
FI / MV Capability
FV / MV Capability
FI / MI Capability
4 Current Ranges (± 3.2 µA, ± 80 µA, ± 2 mA,
± 30 mA)
–5.5V to 9.5V Nominal Output Range (Zero Current)
–3.5 to 7.5V Nominal Output Range (Full Scale
Current)
Each channel of the Edge4717D features a PMU that
can force or measure voltage over a typical 15V I/O range,
and supports 4 current ranges: ± 3.2 µA, ± 80 µA,
± 2 mA, ± 30 mA.
•
•
•
•
•
On-board Voltage Clamps
Internal Sample and Hold
228 Pin 23 mm x 23 mm TBGA Package
The Edge4717D has an on-board window comparator per
channel that provides two bits of information — DUT too
high and DUT too low. There is also a monitor pin which
provides a real time analog signal proportional to either
the voltage or current measured at the DUT.
Functional Block Diagram
DUT_GND
The Edge4717D is designed to be a low power, low cost,
small footprint solution to allow high pin count testers to
support a PMU per pin.
CHANNEL 0
OVER-CURRENT
SNK_MON
DETECT
SNK_OUT
OPEN_RLY
OVER-CURRENT
SRC_MON
SRC_OUT
DETECT
HiZ
VINP
FORCE
GUARD
2.5
÷
REF
On-board voltage clamps, with over-current detection,
provide protection to the DUT and 4717D.
FV / FI*
MI / MV*
SENSE
DUTLTH
IVMAX
IVMIN
COMP_IN
DISABLE
COMPARATORS
DETECTOR LOGIC
DUTGTL
IVMON
VOLTAGE MONITOR
The Edge4717D also has a sample-and-hold feature
a va ila ble for ca pturing DUT curre nt or volta ge
measurements.
CHANNEL 1
OVER-CURRENT
DETECT
SNK_MON
SNK_OUT
OPEN_RLY
OVER-CURRENT
DETECT
SRC_MON
HiZ
SRC_OUT
VINP
FORCE
GUARD
2.5
÷
The Edge4717D is a design improvement to the Edge4717
that features:
REF
FV / FI*
MI / MV*
SENSE
DUTLTH
IVMAX
IVMIN
COMP_IN
DISABLE
COMPARATORS
DETECTOR LOGIC
DUTGTL
IVMON
– Increased FV/MV range
VOLTAGE MONITOR
– Improved over-current detection circuit
functionality
CHANNEL 2
OVER-CURRENT
DETECT
SNK_MON
SNK_OUT
OPEN_RLY
OVER-CURRENT
DETECT
– LVTTL comparator outputs (pull-up resistors
no longer required)
– Improved HiZ switching characteristics
– Improved Force Voltage Linearity
SRC_MON
HiZ
SRC_OUT
VINP
FORCE
GUARD
2.5
÷
REF
FV / FI*
MI / MV*
SENSE
DUTLTH
IVMAX
IVMIN
COMP_IN
DISABLE
COMPARATORS
DETECTOR LOGIC
DUTGTL
IVMON
VOLTAGE MONITOR
CHANNEL 3
OVER-CURRENT
DETECT
SNK_MON
SNK_OUT
OPEN_RLY
Applications
OVER-CURRENT
DETECT
SRC_MON
HiZ
SRC_OUT
VINP
•
Automated Test Equipment
- Memory Testers
- VLSI Testers
FORCE
GUARD
2.5
÷
REF
FV / FI*
MI / MV*
SENSE
DUTLTH
IVMAX
IVMIN
COMP_IN
DISABLE
COMPARATORS
DETECTOR LOGIC
VOLTAGE MONITOR
- Mixed Signal Tester
DUTGTL
IVMON
www.semtech.com
1
Revision 5 / October 14, 2005
Edge4717D
TEST AND MEASUREMENT PRODUCTS
PIN Description
Pin Name
Pin #
Description
VINP[0:3]
B19, H22, N21, V22
Analog voltage input which forces the output voltage (FV mode) and the
output current (FI mode) (one per channel).
REF[0:3]
A19, G22, M21, U22
Reference pin for divide by 2.5 circuit for force current mode; this reference
is typically set to 2.25V.
FORCE[0:3]
SENSE[0:3]
FV_FI*[0:3]
E2, J2, N2, U2
E3, J3, N3, U3
Analog output pin which forces current or voltage.
Analog input pin which senses voltage.
A7, C11, A14, B17
TTL compatible input which determines whether the PMU is forcing current
or forcing voltage.
MI_MV*[0:3]
C9, B11, B14, C16
TTL compatible input which determines whether the PMU is measuring
current or measuring voltage.
RS0[0:3]
RS1[0:3]
IVMIN[0:3]
C7, B9, C12, B15
C6, A8, B12, A15
TTL compatible current range select inputs.
TTL compatible current range select inputs.
C17, H20, M20, U21
Analog input voltages which establish the lower threshold level for the
measurement comparator.
IVMAX[0:3]
C18, H21, N22, U20
Analog input voltages which establish the upper threshold level for the
measurement comparator.
COMP_IN[0:3]
DUT_LTH[0:3]
D2, H2, M2, T2
Analog voltage input to measurement comparator.
AA13, Y12, AA10, Y9
Digital comparator output that indicates the DUT measurement is less than
the upper threshold.
DUT_GTL[0:3]
DISABLE[0:3]
HIZ[0:3]
AA14, AA12, Y11, AA9 Digital comparator output that indicates the DUT measurement is greater
than the lower threshold.
A6, B10, B13, B16
TTL compatible input which places IVMON output in high impedance.
B7, A10, C13, A17
TTL compatible input that places the FORCE output into high impedance.
RA[0:3]
F3, K3, P3, V3
F2, K2, P2, V2
F1, K1, P1, V1
G3, L3, R3, W3
External resistor input corresponding to Range A.
External resistor input corresponding to Range B.
External resistor input corresponding to Range C.
External resistor input corresponding to Range D.
RB[0:3]
RC[0:3]
RD[0:3]
SNK_MON[0:3]
SRC_MON[0:3]
SNK_OUT[0:3]
SRC_OUT[0:3]
F21, K22, R22, AA17 Analog voltage input to sink current clamp.
F22, L22, T22, Y16
C1, G1, L1, R1
Analog voltage input to source current clamp.
Clamp output.
E1, J1, N1, U1
Clamp output.
2005 Semtech Corp. / Rev. 5, 10/14/05
2
www.semtech.com
Edge4717D
TEST AND MEASUREMENT PRODUCTS
PIN Description (continued)
Pin Name
Pin #
Description
OPEN_RLY[0:3]
Y14, Y13, AA11, Y10
Open drain output that is used for opening relays between tester and DUT
in case of an over-current condition.
IVMON[0:3]
B18, G21, M22, T21
B6, C10, A12, A16
C8, A9, A13, C15
Analog voltage output that provides a real time monitor of either the
measured voltage or measured current level.
LTCH_MODE[0:3]
SAMPLE[0:3]
Controls a mux for determination of whether IVMONITOR is from sample-
and-hold or not sampled.
Used for sampling the voltage on the SENSE[0:3] voltage monitor pins.
Driven guard pin used for guard traces.
GUARD[0:3]
D1, H1, M1, T1
TEST[0:3]
B8, A11, C14, A18
C19, J22, N20, V21
Digital input control pin for mux for testing sample-and-hold.
Analog input for testing the sample-and-hold.
TEST_IN[0:3]
COMP1[0:3]
COMP2[0:3]
D20, J20, P21, V20
D21, J21, P20, Y19
Internal compensation pins that require an external capacitor connection
between the two pins.
COMP3[0:3]
E21, K21, R21, Y18
F20, K20, R20, Y17
Y6
Internal compensation pin that requires an external capacitor connection
between the pin and ground.
COMP4[0:3]
Internal compensation pin that requires an external capacitor connection
between the pin and FORCE output.
DUT_GND
Power Pins
VCC
Input reference pin that should be connected to DUT ground line.
A1, A2, A21, A22,
B1, B2, B21, B22,
Positive analog power supply.
C3, C20, Y3, Y20, AA1,
AA2, AA21, AA22, AB1,
AB2, AB21, AB22
VDD
VEE
Y15
Positive digital supply (comparator).
Negative analog power supply.
A20, B20, C21, C22,
D22, E22, G2, L2, R2,
W2, W21, W22, Y21, Y22,
AA15, AA18, AA19, AA20,
AB13, AB14, AB15, AB16,
AB17, AB18, AB19, AB20
GND
NC
A3, A4, A5, B3, B4, B5,
C2, C4, C5, W1, Y1, Y2,
Y4, Y5, Y7, Y8, AA3, AA4,
AA5, AA6, AA7, AA8, AB3,
AB4, AB5, AB6, AB7, AB8,
AB9, AB10, AB11, AB12
Ground.
D3, E20, H3, G20, L20,
L21, M3, P22, T3, T20,
W20, AA16
No Connection. (Unused pins; leave unconnected).
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3
2005 Semtech Corp. / Rev. 5, 10/14/05
Edge4717D
TEST AND MEASUREMENT PRODUCTS
PIN Description (continued)
A1 Ball Pad
Indicator
S E
M T ECH
Top View
23mm x 23mm 228 Pin TBGA
E4717
228 Pin TBGA
23mm x 23mm
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
21
22
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
HIZ1
A11
A12
A13
A14
A15
RS13
A16
A17
HIZ3
A18
A19
IREF0
A20
VEE
A21
VCC
A22
VCC
A
B
VCC
VCC
GND
GND
GND
DISABLE0
FV_FIN0
RS11
SAMPLE1
TEST1
LTCH_MODE2
SAMPLE2
FV_FIN2
LTCH_MODE3
TEST3
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
RS12
B13
B14
B15
RS03
B16
B17
B18
B19
VINP0
B20
VEE
B21
VCC
B22
VCC
VCC
VCC
GND
GND
GND
LTCH_MODE0
HIZ0
TEST0
RS01
DISABLE1
MI_MVN1
DISABLE2
MI_MVN2
DISABLE3
FV_FIN3
IVMON0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
RS02
C13
HIZ2
C14
TEST2
C15
C16
C17
C18
C19
C20
VCC
C21
VEE
C22
VEE
C
SNK_OUT0
GND
VCC
GND
GND
RS10
RS00
SAMPLE0
MI_MVN0
LTCH_MODE1
FV_FIN1
SAMPLE3
MI_MVN3
IV_MIN0
IV_MAX0
TEST_IN0
D1
D2
D3
NC
D4
E4
D5
E5
D6
E6
D7
E7
D8
E8
D9
E9
D10
E10
D11
E11
D12
E12
D13
E13
D14
E14
D15
E15
D16
E16
D17
E17
D18
E18
D19
E19
D20
D21
D22
VEE
D
E
GUARD0
COMP_IN0
COMP10
COMP20
E1
E2
E3
E20
NC
E21
E22
VEE
SRC_OUT0
FORCE0
SENSE0
COMP30
F1
F2
F3
F4
G4
H4
J4
F5
G5
H5
J5
F6
G6
H6
J6
F7
G7
H7
J7
F8
G8
H8
J8
F9
G9
H9
J9
F10
G10
H10
J10
F11
G11
H11
J11
F12
G12
H12
J12
F13
G13
H13
J13
F14
G14
H14
J14
F15
G15
H15
J15
F16
G16
H16
J16
F17
G17
H17
J17
F18
G18
H18
J18
F19
G19
H19
J19
F20
F21
F22
F
RC0
RB0
RA0
COMP40
SNK_MON0
SRC_MON0
G1
G2
VEE
G3
G20
G21
G22
IREF1
G
H
J
HLD_CAP0
(NC)
SNK_OUT1
RD0
IVMON1
H1
H2
H3
NC
H20
H21
H22
VINP1
GUARD1
COMP_IN1
IV_MIN1
IV_MAX1
J1
J2
J3
J20
J21
J22
SRC_OUT1
FORCE1
SENSE1
COMP11
COMP21
TEST_IN1
K1
K2
K3
RA1
K4
L4
K5
L5
K6
L6
K7
L7
K8
L8
K9
L9
K10
L10
K11
L11
K12
L12
K13
L13
K14
L14
K15
L15
K16
L16
K17
L17
K18
L18
K19
L19
K20
K21
K22
K
L
RC1
RB1
COMP41
COMP31
SNK_MON1
L1
L2
L3
L20
NC
L21
L22
HLD_CAP1
(NC)
SNK_OUT2
VEE
RD1
SRC_MON1
M1
M2
M3
NC
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
IREF2
M22
M
N
P
GUARD2
COMP_IN2
IV_MIN2
IVMON2
N1
N2
N3
N4
P4
R4
T4
N5
P5
R5
T5
N6
P6
R6
T6
N7
P7
R7
T7
N8
P8
R8
T8
N9
P9
R9
T9
N10
P10
R10
T10
U10
N11
P11
R11
T11
U11
N12
P12
R12
T12
U12
N13
P13
R13
T13
U13
N14
P14
R14
T14
U14
N15
P15
R15
T15
U15
N16
P16
R16
T16
U16
N17
P17
R17
T17
U17
N18
P18
R18
T18
U18
N19
P19
R19
T19
U19
N20
N21
VINP2
N22
SRC_OUT2
FORCE2
SENSE2
TEST_IN2
IV_MAX2
P1
P2
P3
P20
P21
P22
NC
RC2
RB2
RA2
COMP22
COMP12
R1
R2
R3
R20
R21
R22
R
SNK_OUT3
VEE
RD2
COMP42
COMP32
SNK_MON2
T1
T2
T3
NC
T20
T21
T22
T
HLD_CAP2
(NC)
GUARD3
COMP_IN3
IVMON3
SRC_MON2
U1
U2
U3
U4
U5
U6
U7
U8
U9
U20
U21
U22
IREF3
U
V
W
Y
AA
AB
SRC_OUT3
FORCE3
SENSE3
IV_MAX3
IV_MIN3
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
VINP3
RC3
RB3
RA3
COMP13
TEST_IN3
W1
W2
VEE
W3
RD3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
NC
W21
VEE
W22
VEE
GND
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
VDD
Y16
Y17
Y18
Y19
Y20
VCC
Y21
VEE
Y22
VEE
GND
GND
VCC
GND
GND
DUT_GND
GND
GND
DUT_LTH3
OPEN_RLY3
DUT_GTL2
DUT_LTH1
OPEN_RLY1
OPEN_RLY0
SRC_MON3
COMP43
COMP33
COMP23
AA1
VCC
AA2
VCC
AA3
GND
AA4
GND
AA5
GND
AA6
GND
AA7
GND
AA8
GND
AA9
AA10
AA11
AA12
AA13
AA14
AA15
VEE
AA16
AA17
AA18
VEE
AA19
VEE
AA20
VEE
AA21
VCC
AA22
VCC
HLD_CAP3
(NC)
DUT_GTL3
DUT_LTH2
OPEN_RLY2
DUT_GTL1
DUT_LTH0
DUT_GTL0
SNK_MON3
AB1
VCC
AB2
VCC
AB3
GND
AB4
GND
AB5
GND
AB6
GND
AB7
GND
AB8
GND
AB9
GND
AB10
GND
AB11
GND
AB12
GND
AB13
VEE
AB14
VEE
AB15
VEE
AB16
VEE
AB17
VEE
AB18
VEE
AB19
VEE
AB20
VEE
AB21
VCC
AB22
VCC
2005 Semtech Corp. / Rev. 5, 10/14/05
4
www.semtech.com
Edge4717D
TEST AND MEASUREMENT PRODUCTS
PIN Description (continued)
A1 Ball Pad
Indicator
(see gold triangle
located at the
corner)
Bottom View
23mm x 23mm 228 Pin TBGA
22 21
20
19 18
17 16
15
14
13
12
11 10
9
8
7
6
5
4
3
2
1
A22
VCC
A21
VCC
A20
VEE
A19
A18
A17
A16
A15
RS13
A14
A13
A12
A11
A10
HIZ1
A9
A8
A7
A6
A5
A4
A3
A2
A1
A
B
IREF0
TEST3
HIZ3
LTCH_MODE3
FV_FIN2
SAMPLE2
LTCH_MODE2
TEST1
SAMPLE1
RS11
FV_FIN0
DISABLE0
GND
GND
GND
VCC
VCC
B22
VCC
B21
VCC
B20
VEE
B19
VINP0
B18
B17
B16
B15
RS03
B14
B13
B12
RS12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
IVMONITOR0
FV_FIN3
DISABLE3
MI_MVN2
DISABLE2
MI_MVN1
DISABLE1
RS01
TEST0
HIZ0
LTCH_MODE0
GND
GND
GND
VCC
VCC
C22
VEE
C21
VEE
C20
VCC
C19
C18
C17
C16
C15
C14
TEST2
C13
HIZ2
C12
RS02
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C
TEST_IN0
IV_MAX0
IV_MIN0
MI_MVN3
SAMPLE3
FV_FIN1
LTCH_MODE1
MI_MVN0
SAMPLE0
RS00
RS10
GND
GND
VCC
GND
SNK_OUT0
D22
VEE
D21
D20
D19
E19
D18
E18
D17
E17
D16
E16
D15
E15
D14
E14
D13
E13
D12
E12
D11
E11
D10
E10
D9
E9
D8
E8
D7
E7
D6
E6
D5
E5
D4
E4
D3
NC
D2
D1
D
E
COMP20
COMP10
COMP_IN0
GUARD0
E22
VEE
E21
E20
NC
E3
E2
E1
COMP30
SENSE0
FORCE0
SRC_OUT0
F22
F21
F20
F19
G19
H19
J19
F18
G18
H18
J18
F17
G17
H17
J17
F16
G16
H16
J16
F15
G15
H15
J15
F14
G14
H14
J14
F13
G13
H13
J13
F12
G12
H12
J12
F11
G11
H11
J11
F10
G10
H10
J10
F9
G9
H9
J9
F8
G8
H8
J8
F7
G7
H7
J7
F6
G6
H6
J6
F5
G5
H5
J5
F4
G4
H4
J4
F3
F2
F1
F
SRC_MON0
SNK_MON0
COMP40
RA0
RB0
RC0
G22
IREF1
G21
G20
G3
G2
VEE
G1
G
H
J
HLD_CAP0
(NC)
IVMON1
RD0
SNK_OUT1
H22
VINP1
H21
H20
H3
NC
H2
H1
IV_MAX1
IV_MIN1
COMP_IN1
GUARD1
J22
J21
J20
J3
J2
J1
TEST_IN1
COMP21
COMP11
SENSE1
FORCE1
SRC_OUT1
K22
K21
K20
K19
L19
K18
L18
K17
L17
K16
L16
K15
L15
K14
L14
K13
L13
K12
L12
K11
L11
K10
L10
K9
L9
K8
L8
K7
L7
K6
L6
K5
L5
K4
L4
K3
RA1
K2
K1
K
L
SNK_MON1
COMP31
COMP41
RB1
RC1
L22
L21
L20
NC
L3
L2
L1
HLD_CAP1
(NC)
SRC_MON1
RD1
VEE
SNK_OUT2
M22
M21
IREF2
M20
M19
M18
M17
M16
M15
M14
M13
M12
M11
M10
M9
M8
M7
M6
M5
M4
M3
NC
M2
M1
M
N
P
IVMON2
IV_MIN2
COMP_IN2
GUARD2
N22
N21
VINP2
N20
N19
P19
R19
T19
U19
N18
P18
R18
T18
U18
N17
P17
R17
T17
U17
N16
P16
R16
T16
U16
N15
P15
R15
T15
U15
N14
P14
R14
T14
U14
N13
P13
R13
T13
U13
N12
P12
R12
T12
U12
N11
P11
R11
T11
U11
N10
P10
R10
T10
U10
N9
P9
R9
T9
N8
P8
R8
T8
N7
P7
R7
T7
N6
P6
R6
T6
N5
P5
R5
T5
N4
P4
R4
T4
N3
N2
N1
IV_MAX2
TEST_IN2
SENSE2
FORCE2
SRC_OUT2
P22
NC
P21
P20
P3
P2
P1
COMP12
COMP22
RA2
RB2
RC2
R22
R21
R20
R3
R2
R1
R
SNK_MON2
COMP32
COMP42
RD2
VEE
SNK_OUT3
T22
T21
T20
T3
NC
T2
T1
T
HLD_CAP2
(NC)
SRC_MON2
IVMON3
COMP_IN3
GUARD3
U22
IREF3
U21
U20
U9
U8
U7
U6
U5
U4
U3
U2
U1
U
V
W
Y
AA
AB
IV_MIN3
IV_MAX3
SENSE3
FORCE3
SRC_OUT3
V22
VINP3
V21
V20
V19
V18
V17
V16
V15
V14
V13
V12
V11
V10
V9
V8
V7
V6
V5
V4
V3
V2
V1
TEST_IN3
COMP13
RA3
RB3
RC3
W22
VEE
W21
VEE
W20
NC
W19
W18
W17
W16
W15
W14
W13
W12
W11
W10
W9
W8
W7
W6
W5
W4
W3
RD3
W2
VEE
W1
GND
Y22
VEE
Y21
VEE
Y20
VCC
Y19
Y18
Y17
Y16
Y15
VDD
Y14
Y13
Y12
Y11
Y10
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
COMP23
COMP33
COMP43
SRC_MON3
OPEN_RLY0
OPEN_RLY1
DUT_LTH1
DUT_GTL2
OPEN_RLY3
DUT_LTH3
GND
GND
DUT_GND
GND
GND
VCC
GND
GND
AA22
VCC
AA21
VCC
AA20
VEE
AA19
VEE
AA18
VEE
AA17
AA16
AA15
VEE
AA14
AA13
AA12
AA11
AA10
AA9
AA8
GND
AA7
GND
AA6
GND
AA5
GND
AA4
GND
AA3
GND
AA2
VCC
AA1
VCC
HLD_CAP3
(NC)
SNK_MON3
DUT_GTL0
DUT_LTH0
DUT_GTL1
OPEN_RLY2
DUT_LTH2
DUT_GTL3
AB22
VCC
AB21
VCC
AB20
VEE
AB19
VEE
AB18
VEE
AB17
VEE
AB16
VEE
AB15
VEE
AB14
VEE
AB13
VEE
AB12
GND
AB11
GND
AB10
GND
AB9
GND
AB8
GND
AB7
GND
AB6
GND
AB5
GND
AB4
GND
AB3
GND
AB2
VCC
AB1
VCC
www.semtech.com
5
2005 Semtech Corp. / Rev. 5, 10/14/05
Edge4717D
TEST AND MEASUREMENT PRODUCTS
Circuit Description
Circuit Overview
Control Inputs
The Edge4717D is a quad channel parametric test and
measurement unit that can :
FV / FI* is a TTL compatible input which determines whether
the PMU forces current or voltage, and MI/MV* is a TTL
compatible input which determines whether the PMU
measures current or voltage. FV/FI* and MI/MV* are
independent for each channel of the Edge4717D. HIZ is
a TTL compatible input which can be used to place the
PMU’s force amp into a high impedance state. Tables 1
and 2 describe the modes of operation related to these
three input pins.
• Force Voltage / Measure Current
• Force Current / Measure Voltage
• Force Voltage / Measure Voltage
• Force Current / Measure Current
• Measure Voltage / Force Disable
The Edge4717D features a PMU (per channel) that can
force or measure voltage over a 15V range and force or
measure current over four distinct ranges:
• ± 3.2 µA
HIZ
1
FV / FI*
MI/MV*
Mode of Operation
High Impedance
X
0
X
0
• ± 80 µA
• ± 2 mA
• ± 30 mA
0
Force Current, Measure Voltage
Force Current, Measure Current
Force Voltage, Measure Voltage
Force Voltage, Measure Current
0
0
1
The Edge4717D features an on-board window comparator
(per channel) that provides two bit measurement range
classification.
0
1
0
0
1
1
Also, a monitor pin, IVMON, is capable of outputting either
a real time analog voltage signal which tracks the measured
parameter, or a sampled value of the measurement
parameter captured using the sample and hold circuitry.
Table 1.
RS0 and RS1 are TTL compatible inputs to an internal
a na log MUX which se le cts a n e xte rna l re sistor
corresponding to a desired current range. The truth table
for RS0 and RS1, along with the associated external
resistor values and current ranges, is shown in Table 2.
RS0 and RS1 are independent for each channel of the
Edge4717D.
PMU Functionality
The trapezoid in Figure 1 describes the current-voltage
functionality of the PMU with VCC = 12V and VEE =
–8V, in Range D.
V
V
= 12
V
(@ I = 0) = 9.25V
CC
OUT
Current
RS1
RS0
Range
"Nominal" Ext. R
Range
3.2 µA
80 µA
2 mA
V
(@ 30 mA) = 9V
OUT
0
0
1
1
0
1
0
1
A
B
C
D
RA = 625KΩ
RB = 25KΩ
RC = 1KΩ
RD = 40Ω
No restrictions
I
(30 mA)
I
(–30 mA)
30 mA
MAX
MIN
Table 2.
V
(@ –30 mA) = –2.5V
OUT
V
(@ –10 mA) = –5.1 (in Range D)
OUT
V
= –8V
V
(@ I = 0) = –5.5V
EE
OUT
NOTE: Negative current is defined as current flowing into PMU from DUT.
Figure 1. PMU Functionality
2005 Semtech Corp. / Rev. 5, 10/14/05
6
www.semtech.com
Edge4717D
TEST AND MEASUREMENT PRODUCTS
Circuit Description (continued)
FORCE/SENSE
Disable
MI / MV*
Sensed Parameter
High Impedance
FORCE is an analog output which either forces a current
or forces a voltage, depending on which operating mode
is selected. In FV mode, the voltage forced is equivalent
to the voltage applied to the VINP pin. In FI mode, the
current forced is mapped to the input as described in the
Force Current section. FORCE can be placed in a high-
impedance state through the setting of the HIZ input pin.
1
0
0
X
0
Measured Voltage
Measured Current
1
Table 3.
Sample and Hold
When the HIZ input pin is set to logical “0”, the Edge4717D
FORCE output will be controlled by the internal driver
amplifier, and the Edge4717D will force a user-defined
current or voltage (depending upon the setting of FV/FI*)
at the FORCE pin. When HIZ is set to logical “1”, the
FORCE output is placed into a low-leakage, high impedance
state.
The Edge4717D features a sample and hold circuit (per
channel) which can be used to capture the corresponding
voltage value of the sensed parameter (MI or MV) to be
displayed at IVMON.
The output of the sample and hold is internally connected
to IVMON through a latch controlled by LTCH_MODE. The
setting of LTCH_MODE determines whether the data at
IVMON comes from the sample and hold circuit or directly
from the sensed parameter (see Table 4).
SENSE is a high impedance analog input which measures
the DUT voltage in the MV operating mode.
(FORCE and SENSE are brought out to separate pins to
allow remote sensing.)
LTCH_MODE
Sample
Sample-and_Hold State
Transparent
IVMON
0
1
1
1
X
(Falling Edge)
Sample Data
IVMON is a real time analog voltage output which tracks
the sensed parameter.
0
1
Hold Data
Transparent
In the MV mode (MI/MV* = 0), the output voltage
displayed at IVMON is a 1:1 mapping of the SENSE voltage.
In the MI mode (MI/MV* = 1), IVMON follows the equation:
Table 4.
Note: No update is performed on the sample-and-hold.
IVMON = I(measured) * REXT
Sample and Hold Testing
Using nominal values for the external resistors (RA, RB,
and RC), a voltage at IVMON of + 2V corresponds to Imax,
and –2V corresponds to Imin of the selected current range.
For Range D, + 1.2V corresponds to Imax and –1.2V
corresponds to Imin.
An analog MUX in the 4717D allows for testing of the
sample-and-hold circuit.
The MUX control pin, TEST, is a TTL compatible input
whose operation is described in Table 5. To test the sample
and hold circuitry, an analog signal can be applied to the
TEST_IN pin and sampled.
The IVMON pin can also be placed into a high impedance
state by using the DISABLE input (see Table 3).
www.semtech.com
7
2005 Semtech Corp. / Rev. 5, 10/14/05
Edge4717D
TEST AND MEASUREMENT PRODUCTS
Circuit Description (continued)
VINP
Corresponding Forced Current
≥ Imax (Full-Scale, Ranges A, B, C)
≥ Imax (Full-Scale, Range D)
VREF + 5.5V
VREF + 3.5V
VREF
TEST
Function
0
Normal Operation
0
TEST_IN used for sample-
and-hold testing
1
≤ Imin (Full-Scale, Range D)
VREF – 3.5V
VREF – 5.5V
≤ Imin (Full-Scale, Ranges A, B, C)
Table 5.
Test Head Ground Reference
Table 6.
The Edge4717D features a test head ground referencing
feature which allows the force voltage function to be
referenced to a separate ground reference other than the
ground (GND) power used for the device. The test head
ground should be connected to the DUT_GND pin of the
Edge4717D. The maximum allowed variation between
DUT_GND and GND is ± 250 mV.
In the Force Current mode, the voltage at VINP is divided
by 2.5 internally on the chip, so that a ± 2V range is used
internally for forcing currents on Ranges A, B, and C. Range
D uses a ± 1.2V range across REXT for forcing currents.
Measure Voltage Mode
In the MV mode (MI/MV* = 0), DUT voltage is measured
via the SENSE input pin. This measured voltage can be
displayed on the IVMON pin and tested using the internal
window comparator.
Force Voltage Mode
In the FV mode (FV/FI* = 1), VINP is a high impedance,
analog voltage input that maps directly to the voltage forced
at the FORCE pin.
Comparator
Measure Current Mode
The Edge4717D features an on-board window compara-
tor which provides two-bit measurement range classifica-
tion. IVMAX and IVMIN are high impedance analog inputs
that establish the upper and lower thresholds for the win-
dow comparator. COMP_IN is the window comparator in-
put pin. COMP_IN should be connected to IVMON on
each channel if it is desired to use the comparator to
indicate PMU measurements.
In the MI mode (MI/MV* = 1), a current monitor is
connected in series with the PMU forcing amplifier. This
monitor generates a voltage that is proportional to the
current passing through it, and is brought out to IVMON.
This voltage (corresponding to the measured current) can
also be tested by the on-board window comparator.
Force Current Mode
In the MI mode, an I/V MAX input of + 2V will set the
upper threshold of the window comparator to a voltage
corresponding to + FSC (full-scale current), and an I/V MIN
input of –2V will set the lower threshold to a voltage
corresponding to –FSC for Ranges A, B, and C. Similarly
for Range D, –1.2V corresponds to sinking full-scale
current, and + 1.2V corresponds to sourcing full-scale
current (positive current is defined as current flowing out
of the PMU).
In the FI mode (FV/FI* = 0), VINP is a high impedance,
analog voltage input that is converted into a current at
the FORCE pin (see Figure 1) using the following
relationship:
VINP – VREF
Forced Current =
(REXT * 2.5)
where VREF is the reference voltage input at the REF pin
which is nominally set at 2.25V. (Positive current is de-
fined as current flowing out of the PMU.) Table 6 de-
scribes the relationship between the voltage applied to
VINP and the current at FORCE for Ranges A, B, and C.
DUTGTL the DUTLTH are LVTTL compatible outputs which
indicate the range of the measured parameter in relation
to IVMIN and IVMAX. Comparator functionality is sum-
marized in Table 7.
2005 Semtech Corp. / Rev. 5, 10/14/05
8
www.semtech.com
Edge4717D
TEST AND MEASUREMENT PRODUCTS
Circuit Description (continued)
Clamp Diode
Current
TEST CONDITION
DUT LTH
DUT GTL
Clamp Condition
OPEN_RLY
COMP_IN > IVMAX
COMP_IN < IVMAX
0
1
SRC_OUT < FORCE–V
diode
N/A
1
N/A
I
I
> 55 mA
0
1
CLAMP
SRC_OUT > FORCE–V
diode
COMP_IN > IVMIN
COMP_IN < IVMIN
1
0
< 55 mA
CLAMP
N/A
1
I
I
> 55 mA
< 55 mA
0
1
CLAMP
CLAMP
SNK_OUT < FORCE+ V
diode
COMP_IN < IVMAX
and
COMP_IN > IVMIN
1
SNK_OUT > FORCE+ V
diode
N/A
1
Table 7. Comparator Truth Table
Table 8. Over-Current Detection Circuit Functionality
(V
is the forward voltage of the
external clamp diode).
diode
REXT Selection
For applications that require the use of external resistors
that are much smaller in Ohmic value than those that are
outlined in Table 2, one will need to account for the
variation in switch resistance vs. common mode voltage
of the range selection switches (A-D in Figure 3) when
specifying the overall accuracy of the application.
The Edge4717D is designed such that the maximum
voltage drop across REXT (RA, RB, RC, or RD depending
on range selected using RS0 and RS1 inputs) is ≤ 2V.
Resistor values can be chosen to operate the PMU at any
current range up to ± 50 mA in accordance with the
following equation:
Common Mode Error/Calibration
2 [V]
IMAX[A]
REXT[Ω] =
, IMAX ≤ 50 mA for Range D
IMAX ≤ 2 mA for Range C
IMAX ≤ 80 µA for Range B
IMAX ≤ 3.2 mA for Range A
In order to attain a high degree of accuracy in a typical
ATE application, offset and gain errors are accounted for
through software calibration. When operating the
Edge4717D in the Measure Current (MI) or Force Current
(FI) modes, an additional source of error, common mode
error, should be accounted for. Common mode error is a
Voltage Clamps/Over-Current Detection
measure of how the common mode voltage, V , at the
CM
input of the current sense amplifier affects the forced or
measured current values (see Figure 2). Since this error
is created by internal resistors in the current sense
amplifier, it is very linear in nature.
The Edge4717D features four pairs of on-board clamps
(one pair per channel), which can be used to clamp the
voltage of pins connected to SRC_OUT and SNK_OUT
between limits set by the voltages applied to SRC_MON
and SNK_MON. SNK_MON is a high impedance input
that establishes the upper clamping limit, while SRC_MON
is a high impedance analog input that establishes the lower
clamping limit. In addition to voltage clamping functionality,
the clamp circuitry of the Edge4717D also features over-
current detection capability. Over-current detection is only
enabled when one of the voltage clamping thresholds is
Using the common mode error and common mode linearity
specifications, one can see that with a small number of
calibration steps (see Applications note PMU-A1), the
effect of this error can be significantly reduced.
exceeded (FORCE + V
> SNK_MON or FORCE –
diode
V
diode
< SRC_MON). When enabled, an over-current
condition is signaled via the OPEN-RLY pin. OPEN_RLY is
an open drain output pin that pulls down when an over-
current condition is detected. OPEN_RLY functionality is
depicted in Table 8.
www.semtech.com
9
2005 Semtech Corp. / Rev. 5, 10/14/05
Edge4717D
TEST AND MEASUREMENT PRODUCTS
Circuit Description (continued)
V
OS@IVMON
Power Supply Sequencing
CM Linearity
In order to avoid the possibility of latch-up, the following
power-up requirements must be satisified:
1. VEE ≤ GND ≤ VDD ≤ VCC at all times
2. VEE ≤ All inputs ≤ VCC
CM Error = Slope
2 mV
V
CM@FORCE
The following power supply sequencing can be used as a
guideline when operating the Edge4717D:
–3.5V
9.5V
–2 mV
Power Up Sequence
1. VCC (substrate)
2. VEE/VDD
3. Digital Inputs
4. Analog Inputs
(Note: Slope may be negative)
Power Down Sequence
1. Analog Inputs
2. Digital Inputs
3. VEE/VDD
Figure 2. Graphical Representation of
Common Mode Error
4. VCC (substrate)
Transient Clamps
The Edge4717D has on-board transient clamps to limit
the voltage and current spikes that might result from either
changing the current range or changing the operating
mode.
Driven Guard Pin
The Edge4717D features a pin (per channel), GUARD,
which can be used to drive the guard traces of a FORCE/
SENSE pair. By surrounding FORCE and SENSE traces
with guard traces which connect to the GUARD pin, an
effective method to achieve minimal leakage can be
achieved.
2005 Semtech Corp. / Rev. 5, 10/14/05
10
www.semtech.com
Edge4717D
TEST AND MEASUREMENT PRODUCTS
Circuit Description (continued)
Figure 3. Functional Schematic
www.semtech.com
11
2005 Semtech Corp. / Rev. 5, 10/14/05
Edge4717D
TEST AND MEASUREMENT PRODUCTS
Application Information
120 pF
VDD
COMP1
COMP2
OPEN_RLY
R
PU
120 pF
COMP4
RA
625 KΩ
Edge4717D
25 KΩ
1 KΩ
RB
RC
RD
DUT LTH
To LVTTL Gate
To LVTTL Gate
40 Ω
DUT GTL
FORCE
SENSE
To DUT
+ V
diode
–
SRC_OUT
COMP3
VCC
– V
diode
+
100 pF to 1 nF
(exact value
is TBD)
SNK_OUT
DUT_GND
VDD
VEE
Use of diodes with a low
reverse leakage current,
such as the Zetex
FLLD261 or equivalent
are recommended.
.01 µF
.1 µF
.01 µF
.1 µF
.01 µF
VCC
VDD
VEE
Test Head Ground
Actual decoupling capacitor values depend
on the actual system environment.
Figure 4. Required External Components (Per Channel)
2005 Semtech Corp. / Rev. 5, 10/14/05
12
www.semtech.com
Edge4717D
TEST AND MEASUREMENT PRODUCTS
Package Information
0.10
–A–
D
PIN Descriptions
11
Corner
–B–
E
The entire top-side of the
E4717D package is constructed
of copper, which offers a path
of high thermal conductivity for
cooling.
45 degree 0.5 mm Chamfer (4 PLCS)
Top View
10
A
B
C
D
E
F
e
G
H
J
K
L
E1
M
N
P
R
T
U
V
W
Y
AA
AB
e
Detail B
D1
Bottom View
www.semtech.com
13
2005 Semtech Corp. / Rev. 5, 10/14/05
Edge4717D
TEST AND MEASUREMENT PRODUCTS
Package Information (continued)
Detail A
Side View
g
A
c
A1
P
/ / ccc C
g
–C–
6
b
0.30
0.10
S
S
C
C
A S B S
aaa C
5
4
Detail A
Detail B
NOTES:
Dimensional References
1.
2.
3.
All dimensions are in millimeters.
“e” represents the basic solder ball grid pitch.
REF.
MIN.
1.25
NOM.
1.4
MAX.
1.55
A
“M” represents the basic solder ball matrix size, and
symbol “N” is the maximum allowable number of
balls after depopulating.
A1
D
0.40
0.50
0.60
22.80
23.00
21.00 BSC
23.00
21.00 BSC
0.65
23.20
D1
E
22.80
23.20
4.
“b” is measured at the maximum solder ball diameter
(after reflow) parallel to primary datum –C– .
Dimension “aaa” is measured parallel to primary datum –C– .
Primary datum –C– and seating plane are defined by the
spherical crowns of the solder balls.
E1
b
0.525
0.85
0.775
0.95
5.
6.
c
0.90
M
N
22
228
7.
8.
9.
Package surface shall be black oxide.
aaa
ccc
e
0.15
0.25
Cavity depth varies with die thickness.
1.00 TYP
Substrate material base is copper.
g
0.35
0.15
10. Bilateral tolerance zone is applied to each side of package body.
11. 45 degree 0.5 mm Chamfer corner and white dot for Pin 1
identification.
P
2005 Semtech Corp. / Rev. 5, 10/14/05
14
www.semtech.com
Edge4717D
TEST AND MEASUREMENT PRODUCTS
Recommended Operating Conditions
Parameter
Symbol
VCC
Min
11.5
–8.5
19
Typ
12
Max
12.5
–7.5
21
Units
V
Positive Analog Power Supply
Negative Analog Power Supply
Total Analog Power Supply
Digital Power Supply
VEE
–8
V
VCC – VEE
VDD
20
V
3.0
3.3
5.25
+ 65
V
Case Temperature
TC
25
˚ C
θjc
Thermal Resistance of Package
(Junction to Case)
0.3
˚ C/W
Absolute Maximum Ratings
Parameter
Symbol
VCC
Min
Typ
Max
Units
V
Positive Power Supply
Negative Power Supply
Total Power Supply
Digital Power Supply
Digital Inputs
+ 15
VEE
–15
V
VCC – VEE
VDD
0
0
22
+ 7
V
V
–.5
7.0
V
Analog Inputs
VEE – .5
–55
VCC + .5
+ 125
100
V
Storage Temperature
Case Temperature
Soldering Temperature
˚ C
˚ C
˚ C
260
Stresses above listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
www.semtech.com
15
2005 Semtech Corp. / Rev. 5, 10/14/05
Edge4717D
TEST AND MEASUREMENT PRODUCTS
DC Characteristics
Parameter
Symbol
Min
Typ
Max
Units
Power Supplies
Power Supply Consumption (No-Load)
Positive Supply
ICC
IEE
IDD
35
35
72
72
5
mA
mA
mA
Negative Supply
"Digital" Supply
Power Supply Rejection Ratio
PSRR
VCC to any Analog Output (except in Hold mode)
1 MHz
500 kHz
100 kHz
20
20
25
dB
dB
dB
VEE to any Analog Output (except in Hold mode)
1 MHz
500 kHz
100 kHz
16
18
25
dB
dB
dB
VDD to any Analog Output (except in Hold mode)
< 1 MHz
60
dB
VCC to IVMON (Hold Mode)
1 MHz
0.6
6
20
30
dB
dB
dB
dB
500 kHz
100 kHz
200 Hz
VEE to IVMON (Hold Mode)
1 MHz
1.7
7
21
30
dB
dB
dB
dB
500 kHz
100 kHz
200 Hz
VDD to IVMON (Hold Mode)
< 1 MHz
60
0
dB
Force Voltage Mode
Input Voltage Range
Input Leakage Current
VINP
Ileak
VEE + 2.0
VCC – 2.0
V
µA
–1
1
Output Forcing Voltage (Positive Full-Scale Current
VFORCE
VEE + 2.5
VCC – 4.5
V
through R
)
EXT
Output Forcing Voltage (0 Current through R
)
VFORCE
VFORCE
VEE + 2.5
VEE + 4.5
VCC – 2.5
VCC – 2.5
V
V
EXT
Output Forcing Voltage (Negative Full-Scale Current
through R
)
EXT
Voltage Accuracy
Offset
VOS
Gain
–200
.985
200
1.015
mV
V/V
Gain
Linearity
FV INL
–0.025
.01
+ 0.025
% FSVR
2005 Semtech Corp. / Rev. 5, 10/14/05
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Edge4717D
TEST AND MEASUREMENT PRODUCTS
DC Characteristics (continued)
Parameter
Symbol
Min
Typ
Max
Units
Measure Current Mode
Current Measurement Range
Range A
I
M EAS U R E
–3.2
–80
–2
3.2
80
2
µA
µA
mA
mA
Range B
Range C
Range D
–30
30
Current Measurement Accuracy
Offset (@ IVMON)
Gain (Note 1)
VOS
Gain
–150
.985
150
1.015
mV
V/V
Linearity
MI INL
Ranges A, B, C
Range D
–.08
–80
.08
+ 80
% FSCR
µA
Common Mode Error
Common Mode Linearity
FORCE = VEE + 4.5V to VCC – 4.75V
IVMON Output Impedance
IVMON Leakage Current
CM Error
CM INL
–5.5
–.05
5.5
.05
mV/V
%FSCR
Ω
nA
500
R
O U T
I
–100
100
LEAK
(IVMON = VEE+ 2.5V TO VCC–2.5V)
Force Current Mode
Input Voltage Range
Input Leakage Current
REF Input Voltage Range
REF Leakage Current
VINP
VREF – 5.5
VREF + 5.5
V
µA
V
I
–1
0
–1
1
2.5
–1
LEAK
VR EF
I
0
µA
LEAK
Output Forcing Current
Range A
I
FO R C E
–3.2
–80
–2
3.2
80
2
µA
µA
mA
mA
Range B
Range C
Range D
–30
30
Compliance Voltage Range
Positive Full-Scale Current
0 Current
VFORCE
VEE + 2.5
VEE + 2.5
VEE + 3.0
VCC – 3.0
VCC – 2.5
VCC – 2.5
V
V
V
Negative Full-Scale Current
Current Accuracy
Offset
IOS
Gain
FI INL
–3.6
.385
3.6
.415
% FSCR
V/V
Gain (Note 2)
Linearity
.4
Ranges A, B, C
Range D
–.08
–80
.08
+ 80
% FSCR
µA
Common Mode Error
Common Mode Linearity
CM Error
CM INL
–5.5
–.05
5.5
.05
mV/V
FORCE = VEE + 4.5V to VCC – 4.5V
% FSCR
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17
2005 Semtech Corp. / Rev. 5, 10/14/05
Edge4717D
TEST AND MEASUREMENT PRODUCTS
DC Characteristics (continued)
Parameter
Symbol
Min
Typ
Max
Units
Measure Voltage Mode
Voltage Measurement Range
VSENSE
VEE + 2.5
VCC – 2.5
V
Voltage Measurement Accuracy
Offset
VOS
Gain
MV INL
–200
.985
–.025
–10
200
1.015
.025
10
mV
V/V
%FSVR
nA
Gain
Linearity
± .01
500
FORCE/SENSE Combined Leakage Current in HiZ
(FV/FI*= 0, FORCE/SENSE = VEE+ 2.5V to VCC–2.5V)
IVMON Output Impedance
IVMON Leakage Current
I
LEAK
R
O U T
Ω
nA
I
–100
100
LEAK
(IVMON = VEE+ 2.5V to VCC–2.5V)
Digital Inputs (FV/FI*, MI/MV*, RS0, RS1,
DISABLE, TEST, HiZ, LTCH_MODE, SAMPLE)
Input Low Level
Input High Level
Input Leakage Current
Voltage Clamps
Range
VIL
VIH
0.8
1
V
V
2.0
Ileak
–1
0
µA
SNK_MON –
.5
16.0
V
SRC_MON
Ω
V
Effective Output Impedance of Clamps
Sink Clamp Voltage Range
R
10
VCC – 2.0
VCC – 2.5
1
O U T
SNK_MON
SRC_MON
VEE + 2.5
VEE + 2.0
–1
Source Clamp Voltage Range
SRC_MON Leakage Current
V
I
µA
LEAK
SNK_MON Leakage Current
I
–1
1
µA
LEAK
Linearity @ 5 mA Constant Current
Offset @ 5 mA Constant Current
CLAMP INL
VOS
–.400
–150
35
+ .400
+ 150
95
% FSVR
mV
mA
PPMU Voltage Clamps
I
C LAM P
Current Interrupt Limit (OPEN_RLY Trigger Current)
PPMU Voltage Clamps Current Limiting Range
Output Low Voltage for OPEN_RLY Pin @ 1 mA
TEST_IN Leakage Current
I
35
95
500
1
mA
mV
µA
LIM IT
V
O L
I
–1
–1
LEAK
OPEN_RLY Leakage Current @ 5V
Sample and Hold Circuit
I
1
µA
LEAK
Linearity Error
S&H INL
–.025
.01
16
.025
20
% FSVR
mV
Hold Step
V
H S
∆V / ∆˚ C
TempCo of Hold Step (Note 3)
Output Impedance of IVMON (Note 3)
50
µV/˚ C
Ω
R
O U T
500
2005 Semtech Corp. / Rev. 5, 10/14/05
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Edge4717D
TEST AND MEASUREMENT PRODUCTS
DC Characteristics (continued)
Parameter
Symbol
Min
Typ
Max
Units
Short Circuit Protection
Forcing Op-Amp Current Limit (Note 3)
Driven Guard / Test Head Ground
I
35
75
mA
mV
M AX
GUARD – SENSE
@ DUT_GND = 0
SENSE = 5V
V
–100
+ 100
D IFF
DUT_GND to GND Voltage Range
DUT_GND Leakage Current
Comparator
V
–250
–1
+ 250
1
mV
µA
O S
I
LEAK
IVMAX Voltage Range
IVMAX
IVMIN
VEE + 1.75
VEE + 1.75
–100
VCC – 1.75
VCC – 1.75
+ 100
V
V
IVMIN Voltage Range
Comparator Offset (IVMIN, IVMAX)
Input Bias Current at (IVMIN, IVMAX, COMP_IN)
Digital Outputs (DUTLTH, DUTGTL)
V
O S
mV
µA
I
–1
+ 1
b ia s
Output Low Level (TBD load)
Output High Level (TBD load)
V
400
mV
V
O L
V
O H
2.4
VDD
IVMON
V
EXT
Note 1: Gain =
Note 2: Gain =
, where V
is the voltage across R , which corresponds to measured current.
EXT EXT
V
EXT
, REF = 2.25V nominal, V is the voltage across R , which corresponds to
EXT
EXT
VINP – REF
forced current.
Note 3: Guaranteed by design and characterization. Not production tested.
Unit Definitions:
FSCR = Full Scale Current Range
Range A, ± 3.2 µA
Range B, ± 80 µA
Range C, ± 2 mA
Range D, ± 30 mA
FSVR = Full Scale Voltage Range
FV mode, no current = 14V minimum
FV mode, current load = 12V minimum
MV mode = 14V minimum
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19
2005 Semtech Corp. / Rev. 5, 10/14/05
Edge4717D
TEST AND MEASUREMENT PRODUCTS
AC Characteristics
Parameter
Symbol
Min
Typ
Max
Units
Force Voltage / Measure Current
FORCE Output Voltage Settling Time (Note 1)
(To 0.1% of 10V step)
RANGE A
ts e ttle
2
300
ms
µs
RANGES B, C, D
Measured Current Settling Time (Note 1)
(To 0.1% of FSCR step)
RANGE A
ts e ttle
4
300
ms
µs
RANGES B, C, D
Stability (Note 1)
Capacitive Loading Range for Stable Operation
CLO AD
0
10
nF
Force Amp
Saturation Recovery Time
HiZ True to FORCE Disable Time
HiZ False to FORCE Enable Time
ts r
tz
to e
25
µs
µs
µs
1
15
Force Current / Measure Voltage
FORCE Output Current Settling Time (Note 1)
(To 0.1% of FSCR step)
RANGE A
ts e ttle
4
300
ms
µs
RANGES B, C, D
SENSE (Measure) Voltage Settling Time (Note 1)
(To 0.1% of 10V step)
RANGE A
ts e ttle
4
300
ms
µs
RANGES B, C, D
Stability (Note 1)
Capacitive Loading Range for Stable Operation
CLO AD
0
10
nF
Force Amp
Saturation Recovery Time
HiZ True to FORCE Disable Time
HiZ False to FORCE Enable Time
ts r
tz
to e
25
µs
µs
µs
1
15
I/V Monitor
Enable Time
Disable Time
to e
tz
500
500
ns
ns
2005 Semtech Corp. / Rev. 5, 10/14/05
20
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Edge4717D
TEST AND MEASUREMENT PRODUCTS
AC Characteristics (continued)
Parameter
Symbol
Min
Typ
Max
Units
Sample and Hold Circuit
Droop Rate
∆V/∆t
40
10
mV/s
µs
Acquisition Time (to 0.025% of Sampled Value)
tAQ
1
Hold Mode Settling Time (Notes 1, 2)
Measure Voltage Mode
tH S ETTLE
To 0.1% of 10V Step
To 0.025% of 10V Step
0.8
1.4
1.5
2
µs
µs
Measure Current Mode (Notes 1, 2)
To 0.1% of 4V Step
tHSETTLE
1.3
1.8
2
3
µs
µsf
To 0.025% of 4V Step
Comparators
Propagation Delay
tpd
25
µs
AC Test Conditions: COMP3 = 120 pF to Ground; COMP4 = 120 pF to FORCE; Capacitor between COMP1
and
COMP2 = 120 pF; Load at FORCE/SENSE combined output = 100 pF.
Note 1: Guaranteed by design and characterization. Not production tested.
Note 2: Sample and Hold Circuit Acquisition Time (t ) and Settling Time (t
) are described below:
AQ
HSETTLE
1
t
AQ
SAMPLE
0
t
HSETTLE
VCC – 4.5
V
HS
IVMON
VEE + 4.5
CONDITIONS:
LTCH_MODE = 1
IVMON = 100 pF to GND
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21
2005 Semtech Corp. / Rev. 5, 10/14/05
Edge4717D
TEST AND MEASUREMENT PRODUCTS
Ordering Information
Model Number
Package
E4717DBG
228 Pin 23 mm x 23 mm TBGA
EVM4717DBG
Edge4717D Evaluation Board
This device is ESD sensitive. Care should be taken when handling
and installing this device to avoid damaging it.
Contact Information
Semtech Corporation
Test and Measurement Division
10021 Willow Creek Rd., San Diego, CA 92131
Phone: (858)695-1808 FAX (858)695-2633
2005 Semtech Corp. / Rev. 5, 10/14/05
22
www.semtech.com
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