EDGE710 [SEMTECH]
500 MHz Pin Electronics Driver, Window Comparator, and Load; 500兆赫引脚电子驱动器，窗口比较器和负载
| 型号： | EDGE710 |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | 500 MHz Pin Electronics Driver, Window Comparator, and Load |
| 文件： | 总17页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Edge710
500 MHz Pin Electronics Driver,
Window Comparator, and Load
EDGE HIGH-PERFORMANCE PRODUCTS
Features
Description
The Edge710 is a totally monolithic ATE pin electronics
solution manufactured in a high-performance
complementary bipolar process. In Automatic Test
Equipment (ATE) applications, the Edge710 incorporates
a driver, a load, and a window comparator suitable for
very fast bidirectional channels in VLSI, Mixed-Signal, and
Memory test systems.
•
Fully Integrated Three-Statable Driver, Window
Comparator, and Dynamic Active Load
12V Driver, Load, Compare Range
13V Super Voltage Capable
•
•
•
•
•
•
•
± 35 mA Programmable Load
Comparator Input Tracking >6V/ns
Leakage (L+D+C) < 1 µA (normal mode)
Leakage (L+D+C) < 25 nA (IPD mode)
Small footprint (52 pin MQFP)
The three-statable driver is capable of generating 9V swings
over a 12V range. In addition, 13V super voltage may be
obtained under certain operating conditions. Separate
rise and fall edge adjustments support both high speed
and low speed applications, and allow for superior rise
and fall time matching. An input power down mode allows
extremely low leakage current in HiZ.
Functional Block Diagram
The load supports programmable source and sink currents
of ± 35 mA over a 12V range, or it can be completely
disabled. The source current, sink current, and
commutating voltage are all independently set. In addition,
the load is configurable and may be used as a
programmable voltage clamp.
BIAS
DVH
RADJ
DOUT
FADJ
DHI
DHI*
DVR_EN
DVR_EN*
The window comparator spans a 12V common mode
range, tracks input signals with edge rates greater than 6
V/ns, and passes sub-ns pulses. An input power down
mode allows for extremely low leakage measurements.
DVL
IPD_D
QA*
QA
CVA
The inclusion of all pin electronics building blocks into a
52 lead MQFP (10 mm body w/ internal heat spreader)
offers a highly integrated solution that is traditionally
implemented with multiple integrated circuits or discretes.
PECL
VINP
IPD_C
QB
CVB
QB*
VCC
1KΩ
1KΩ
Applications
ISC_IN
BRIDGE_SC
LOAD
VCM_IN
VCM_OUT_A
VCM_OUT_B
• VLSI Test Equipment
• Mixed-Signal Test Equipment
• Memory Testers (Bidirectional Channels)
• ASIC Verifiers
BRIDGE_SK
ISK_IN
LD_EN
LD_EN*
VEE
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Revision 2 / December 1, 2000
1
Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
PIN Description
Pin Name
Driver
Pin #
Description
DOUT
30
Driver Output.
DHI/DHI*
12, 13
Wide voltage differential input digital pins which determine the driver high or
low level.
DVR_EN/DVR_EN*
DVH, DVL
14, 15
20, 19
Wide voltage differential input digital pins which control the driver being active
or in a high impedance state.
High impedance analog voltage inputs which determine the driver high and low
level.
DVH_CAP
DVL_CAP
24
25
Op amp compensation pin. A 100 pF capacitor should be connected to DVH.
Op amp compensation pin. A 100 pF capacitor should be connected to DVL.
RADJ, FADJ
17, 16
Input currents which determine the driver transition times.
Analog current input which sets an internal bias current.
BIAS
18
34
IPD_D
TTL driver input power down control which slows the driver down and reduces
the driver HiZ leakage current.
Comparator
VINP
33
Analog voltage input to the positive input of comparators.
Analog inputs which set the comparator thresholds.
CVA, CVB
50, 51
QA/QA*
QB/QB*
6, 5
10, 11
Differential ECL (or PECL) digital outputs of comparators A and B.
IPD_C
35
TTL input power down input which slows the comparator down, but
significantly reduces the VINP bias current.
PECL
7, 8
Unbuffered power supply level for the comparator output stages which
establishes either ECL or PECL digital levels.
Load
LOAD
38
2, 3
Load Output.
LD_EN/LD_EN*
VCM_IN
Wide voltage differential inputs which activate and disable the load.
High impedance analog voltage input that programs the commutating voltage.
44
ISC_IN, ISK_IN
48, 45
Analog current inputs which program the load source and sink currents.
Should be connected to external voltage or current source through minimum
500 Ω series resistors.
VCM_CAP
43
Commutating buffer op amp compensation pin.
Commutating voltage pins.
VCM_OUT_A
VCM_OUT_B
42
41
BRIDGE_SC
BRIDGE_SK
40
39
Diode bridge connections to the output bridge that bypass the internal current
sources.
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EDGE HIGH-PERFORMANCE PRODUCTS
PIN Description (continued)
Pin Name
Pin #
Description
Power Supplies,
Miscellaneous
CATHODE
ANODE
27
26
Terminals of the on-chip thermal diode string.
VCC
VEE
GND
N/C
4, 31, 32, 49
1, 28, 29, 52
Positive power supply level.
Negative power supply level.
9, 21, 22, 36, Device Ground.
37, 46, 47
23
No connect.
VEE
LD_EN
LD_EN*
VCC
BRIDGE_SK
LOAD
GND
GND
QA*
IPD_C
IPD_D
VINP
52 MQFP
10 mm X 10 mm
Top Side
QA
PECL
PECL
GND
QB
VCC
VCC
DOUT
VEE
QB*
DHI
VEE
DHI*
CATHODE
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
Circuit Description
Driver Levels
Driver
DVH and DVL are high input impedance voltage controlled
inputs which establish the driver levels of a logical "1" and
"0" respectively.
Introduction
The driver will force DOUT to one of three states:
Driver Level Buffer Compensation
1. DVH (Drive High)
2. DVL (Drive Low)
DVH_CAP and DVL_CAP are op amp compensation pins
for the high and low level on-chip buffers. Each pin requires
a 0.01 µF chip capacitor (with good high frequency
characteristics) connected to ground. A tight layout with
minimal distance between the pin and the capacitor is
recommended.
3. HiZ (High Impedance).
Both driver digital control inputs (DHI / DHI*, DRV_EN /
DRV_EN*) are "Flex Inputs" - wide voltage differential inputs
capable of receiving ECL, TTL, CMOS, or custom level
signals. Single-ended operation is supported by
connecting the inverting input to the appropriate DC
threshold level.
Driver Bias
The BIAS pin is an analog current input which establishes
an on-chip bias current, from which other currents are
generated. This current, to some degree, also establishes
the overall power consumption and performance of the
chip. Ideally, an external current source would be used to
minimize any part-to-part performance variation within a
test system. However, a precision external resistor tied to
a large positive voltage is acceptable. (See figure below.)
The optimal BIAS current is a function of the RADJ and
FADJ settings, and cannot be set independently.
Drive Enable
The drive enable (DRV_EN / DRV_EN*) inputs control
whether the driver is forcing a voltage, or is placed in a
high-impedance state. If DRV_EN is more positive than
DRV_EN*, the output will force either DVH or DVL,
depending on the driver data input. If DRV_EN is more
negative that DRV_EN*, the output goes into a high
impedance state.
Do NOT leave DRV_EN / DRV_EN* floating.
The established bias current follows the equation:
BIAS = (VCC - 0.7) / (Rext + 1.5).
Driver Data
The driver data inputs (DHI / DHI*) determine whether the
driver output is forcing a high or a low. If DHI is more
positive than DHI*, the driver will force DVH when the
driver is active. If DHI is more negative than DHI*, the
driver will force DVL when active.
VCC
REXT
Do NOT leave DHI / DHI* floating.
BIAS
Driver Enable
Driver Data
DOUT
1.5K
DRV_EN > DRV_EN*
DHI > DHI*
DVH
DRV_EN > DRV_EN*
DRV_EN < DRV_EN*
DHI < DHI*
X
DVL
HiZ
Table 1. Driver Control Truth Table
VEE
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EDGE HIGH-PERFORMANCE PRODUCTS
Circuit Description (continued)
Driver Slew Rate Adjustment
Load
The driver rising and falling transition times are
independently adjustable. The RADJ and FADJ pins are
analog current inputs which establish the driver rise and
fall times.
The load is capable of sourcing and sinking at least 35
mA dynamically, or being placed into a high impedance
state. The load may also be configured with separate
commutating voltage to act as a programmable voltage
clamp. In addition, the load may act as a 50Ω
transmission line termination.
Ideally, an external current source would be used for RADJ
and FADJ. However, for most applications (where the rise
and fall times are fixed), precision external resistors to a
positive voltage are acceptable. The currents into RADJ
and FADJ follow the equation:
Load Enable
The load enable input determines whether the load is active
or in high impedance. If LD_EN is more positive than
LD_EN*, the load is active and is capable of sourcing and
sinking currents. If LD_EN is more negative than LD_EN*,
the load is placed into a high impedance state.
RADJ, FADJ = (VCC - 0.7) / (Rext + 1.5).
RADJ (FADJ)
LD_EN / LD_EN* are "Flex In" - wide voltage differential
inputs capable of receiving ECL, TTL, CMOS, or custom
levels. Single-ended operation is supported by connecting
the inverting input to the appropriate DC threshold level.
1.5KΩ
Do NOT leave LD_EN / LD_EN* floating.
Rise/Fall
Adjust Current
Commutating Voltage
Input Power Down
VCM_IN is a high input impedance analog voltage input
which sets the commutating voltage of the load. If LOAD
is more positive than VCM_IN, the bridge will sink current
from the DUT into the load. If LOAD is more negative than
VCM_IN, the load will source current from the load into
the DUT.
IPD_D is a TTL compatible input which affects both the
driver speed as well as high impedance leakage. With
IPD_D = 0, the driver functions normally. With IPD_D =
1, the driver is in IPD mode, where it still functions,
although with slower rise and fall times, but with an
extremely low HiZ leakage current.
Do not leave IPD_D floating !! If IPD_D is not used,
connect it to ground.
DUT
DUT
VCM_IN
VCM_IN
LOAD < VCM_IN
LOAD > VCM_IN
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
Circuit Description (continued)
Source and Sink Current Levels
Commutating Voltage Compensation
The amount of current that the diode bridge can source The VCM_CAP pin is an op amp compensation node that
and sink is adjustable from 0 mA to 35 mA. The source requires a fixed .01 µF chip capacitor (with good high
and sink levels are separate and independent.
frequency characteristics) to ground. This capacitor is
used to compensate an internal node on the on-chip buffer
ISC_IN and ISK_IN are current controlled inputs whose for the commutating voltage input.
voltage level is held very close to ground (<100 mV
variation) over the entire legal current input range.
Split Load
There is a nominal gain of 20 between the ISC_IN current The VCM_OUT_A is the actual commutating voltage
and the bridge source current.
ISOURCE = 20 * ISC_IN
generated by the on-chip buffer. VCM_OUT_A is also
connected to the upper half of the diode bridge, and is
responsible for sinking the programmed source current
when the load is sinking current from the DUT.
There is a nominal gain of –20 between the ISK_IN current
and the bridge sink current.
VCM_OUT_B is connected to the lower half of the diode
bridge, and is responsible for providing the sink current
when the load is sourcing current to the DUT.
ISINK = –20 * ISK_IN
Because the inversion creates a 180˚ phase shift between VCM_OUT_B does NOT have an on-chip buffer. To
ISK_IN and ISINK, there is a tendency toward instability. configure the load as a standard active diode bridge,
A minimum of 500 W of external series resistance should connect VCM_OUT_A and VCM_OUT_B together off-chip.
be used between an external voltage or current source Or, to configure the load as a split load, an external buffer
and the ISC_IN and ISK_IN pins to ensure stability. Stray must be used for VCM_OUT_B.
capacitance at the ISK_IN pin should be kept to a
minimum. PCB layout should minimize coupling between External Bridge Connections
ISK_IN and LOAD.
Access to the top and bottom of the diode bridge is granted
Caution: The ISKIN and ISCIN inputs are designed for through a 1 KW resistor. Pins BRIDGE_SC and BRIDGE_SK
positive current between 0 mA and 1.75 mA flowing into allow external current sources to be used instead of the
the part. Care should be taken to insure that current is internal I_SOURCE and I_SINK sources. These external
never required to flow out of the part on these two nodes. pins are useful when extremely accurate source and sink
currents are required for low current operation.
I_SOURCE
1KΩ
BRIDGE_SC
VCM_IN
LOAD
1KΩ
BRIDGE_SK
I_SINK
VCM_OUT_A
VCM_OUT_B
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
Circuit Description (continued)
Window Comparator
Two comparators are connected on-chip to form a window
comparator to determine whether the DUT is high, low, or
in an indeterminant state. VINP is tied to the positive
inputs of both comparators.
The power supply driving the PECL pin must be capable of
sourcing all the current flowing out of the QA/QA* and QB/
QB* open emitter outputs.
The selection of either comparator A or B for the DUT high
versus the DUT low is arbitrary. However, because the
positive input is used on both comparators, the comparator
used to detect DUT low will have an inversion at it digital
outputs.
Comparator Input Protection
VINP connect to over-voltage diodes connected to the
positive and negative power supplies. These diodes are
sized to handle up to 100 mA current.
The figure below shows the correct polarity for the
comparator connections.
Thermal Monitor
An on-chip thermal diode string of five diodes in series
exists (see figure below). This string allows accurate die
temperature measurements.
QA*
QA
CVA
ANODE
IPD_C
PECL
VINP
Bias Current
QB
QB*
CVB
Temperature Coefficient = –9 mV / ˚C
Thresholds
CVA and CVB are the two comparator threshold levels.
These inputs are high impedance voltage controlled inputs
that determine at which VINP voltage the comparators
will change output states.
CATHODE
An external bias current of 100 µA is injected through the
string, and the measured voltage corresponds to a specific
junction temperature with the following equation:
PECL Level Capability
PECL is the power supply level for the output stage of the
comparators. When connected to ground, the comparator
outputs will be standard ECL outputs. However, by making
PECL more positive, QA / QA* and QB / QB* will track
PECL and also become more positive.
Tj[°C] = {(ANODE - CATHODE)/5 – .7752} / (–.0018).
By raising these voltage levels, the comparators may
connect directly with CMOS ICs.
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
Application Information
Super Voltage Operation
Extremely Low Leakage Usage
The Edge710 may be used to generate a super voltage
level up to 13V at the driver output. To generate this high
voltage, an analog input mux may be used to switch
between the normal high and low drive levels, and a super
voltage level.
The Edge710 is capable of supporting total load + drive
+ comparator leakage ≤ ~15 nA. This low leakage mode
may be very useful during PMU operation if the pin
electronics are not isolated by a relay, thus eliminating
the need for 1 relay per pin.
To realize this low leakage, the following conditions must
be met:
DVH
A
B
Y
1. IPD_D = 1 (place the driver in "power down" mode)
2. IPD_C = 1 (place the comparator in "power down"
mode)
3. CVA, CVB ≥ VINP (program the comparator
thresholds ≥ any expected voltage at the comparator
inputs.)
S/V
710
D_OUT
S/V SELECT
B
A
Y
DVL
Certain Power Supply conditions must be met to support
this functionality.
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2000 Semtech Corp.
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
Package Information
4
D
0.25
C
4X
A – B
D
D2
PIN Descriptions
D
3
A
3
4
E
E2
B
3
e
SEE DETAIL "A"
TOP VIEW
5
7
D1
Z
D
O
E1
5
7
2
5
7
0.20
C
4X
A – B
D
Z
E
BOTTOM VIEW
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
Package Information (continued)
0.40 MIN.
0
MIN.
˚
e
A2
–
0.10 S
0.13 / 0.30 R.
C
0.13
R. MIN.
GAGE PLANE
0.25
–A, B, D–
3
C
A1
0 – 7
˚
L
DETAIL "A"
1.60 REF.
DETAIL "B"
ccc
M
S
S
D
C
A – B
8
SEE DETAIL "B"
12 – 16
˚
WITH LEAD FINISH
b
1.41 REF.
A
2
H
C
12
0.13 / 0.23
0.13 / 0.17
0.076
b
12 – 16
1
˚
BASE METAL
SECTION C-C
Notes:
JEDEC Variation
(all dimensions in millimeters)
1.
2.
All dimensions and tolerances conform to ANSI Y14.5-1982.
Datum plane -H- located at mold parting line and coincident
with lead, where lead exits plastic body at bottom of parting
line.
Symbol
A
Min
Nom
2.15
Max
2.35
0.25
2.10
Note Comments
Height above PCB
3.
Datums A-B and -D- to be determined where centerline
between leads exits plastic body at datum plane -H-.
To be determined at seating plane -C-.
Dimensions D1 and E1 do not include mold protrusion.
Allowable mold protrusion is 0.254 mm per side.
Dimensions D1 and E1 do include mold mismatch and
are determined at datum plan -H-.
A1
A2
D
0.10
1.95
0.15
PCB Clearance
Body Thickness
2.00
4.
5.
13.20 BSC
10.00 BSC
7.80 REF
1.10 REF
13.20 BSC
10.00 BSC
7.80 REF
1.10 REF
0.88
4
5
D1
D2
ZD
E
Body Length
6.
7.
“N” is the total # of terminals.
Package top dimensions are smaller than bottom
dimensions by 0.20 mm, and top of package will not
overhang bottom of package.
4
5
E1
E2
ZE
L
Body Width
8.
Dimension b does not include dambar protrusion.
Allowable dambar protrusion shall be 0.08 mm total in
excess of the b dimension at maximum material
condition. Dambar cannot be located on the lower
radius or the foot.
0.73
1.03
N
52
6
8
Pin Count
Lead Pitch
9.
All dimensions are in millimeters.
e
0.65
10. Maximum allowable die thickness to be assembled
in this package family is 0.635 millimeters.
b
0.22
0.22
0.38
0.33
11. This drawing conforms to JEDEC registered outline MS-108.
12. These dimensions apply to the flat section of the lead
between 0.10 mm and 0.25 mm from the lead tip.
b1
aaa
0.30
0.12
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
Recommended Operating Conditions
Parameter
Symbol
Min
9.0
-8.0
13.2
0
Max
15.5
-4.2
20.5
5.0
Units
Positive Power Supply
Negative Power Supply
Total Analog Supply
Comparator Output Supply
VCC
VEE
V
V
V
V
VCC - VEE
PECL
Analog Inputs
Driver High Level
DVH
DVL
VEE + 3.5
VEE + 2.9
VEE + 3.5
.4
VCC - 2.9
VCC - 3.5
VCC - 2.0
1.3
V
V
Driver Low Level
Super Voltage Levels
Slew Rate Adjustments
Chip Bias
DVH, DVL
RADJ, FADJ
BIAS
V
mA
mA
mA
V
.6
1.25
Source, Sink Currents
Comparator Thresholds
Ambient Operating Temperature
Junction Temperature
ISC_IN, ISK_IN
CVA, CVB
TA
0
1.65
VEE + 3.5
VCC - 3.5
+70
oC
oC
TJ
25
+125
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
Absolute Maximum Ratings
Parameter
Symbol
VCC
Min
0
Max
16.5
0
Units
VCC (relative to GND)
VEE (relative to GND)
Total Power Supply
V
V
V
VEE
-10
VCC - VEE
21.0
Digital Input Voltages
Analog Input Voltages
Analog Input Currents
Digital Output Currents
Driver Output Current
Driver Swing
DHI(*), DVR_EN(*), LD_EN(*)
CVA, CVB, DVH, DVL, VCM_IN
ISC_IN, ISK_IN
VEE
VEE
0
+7.0
VCC
3.0
50
V
V
mA
mA
mA
V
QA/QA*, QB/QB*
Iout
0
-40
0
+40
13
DVH - DVL
Comparator Input Voltage
CVA(B) - VINP
-13
+13
V
Ambient Operating Temperature
Storage Temperature
TA
TS
-50
-65
+125
+150
+150
+260
oC
oC
oC
oC
Junction Temperature
TJ
Soldering Temperature
TSOL
(5 seconds, .25" from the pin)
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these, or any other conditions beyond
those listed, is not implied. Exposure to absolute maximum conditions for extended periods may affect device
reliability.
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
DC Characteristics
Parameter
Symbol
Min
Typ
Max
Units
LOAD Circuit
Commutating Voltage
Programmable Range
Offset Voltage
VCM_IN
VCM_OUT_A - VCM_IN
Iin
VEE + 3.5
-100
VCC - 3.5
+100
+100
V
mV
µA
V
VCM_IN_A Current In
Diff Voltage Range
-100
-10
5
LOAD - VCM_OUT_A
+10
Load Output
Output Voltage Range
Output Current Range
V - LOAD
I - LOAD
VEE + 3.5
-35
VCC - 3.5
+35
V
mA
Load Enable
Input Voltage Range
Differential Input Swing
Input Current
LD_EN, LD_EN*
LD_EN - LD_EN*
Iin
-2.0
0.25
-100
+5.0
4.0
+100
V
V
µA
Source Current
Input Current
ISC_IN Voltage
Current Gain
ISC_IN
V_ISC_IN
I_SOURCE/ ISC_IN
0
-100
18.2
2.0
+100
21.8
mA
mV
0
20
Sink Current
Input Current
ISK_IN Voltage
Current Gain
ISK_IN
V_ISK_IN
I_SINK/ ISK_IN
0
-100
18.2
2.0
+100
21.8
mA
mV
0
20
Load Linearity
0 mA <= Output < 5 mA
5 mA <= Output < 35 mA
Actual - Programmed
Actual - Programmed
-1µA - 1%
-50
+1µA + 1%
+50
µA
µA
HiZ Leakage Current
HiZ Compliance
Ibias
-100
0
+100
nA
VEE + .5
.5
VCC
2.0
V
KΩ
Source/Sink Bridge Resistance
(measured @ I = 500 µA)
1.0
Source/Sink Error
Cal Points
Test Point
20 µA / 30 µA
25 µA
80 µA
-(1% + 1)
-(1% + 1)
-50
1% + 1
1% + 1
+50
+50
+50
+50
+50
+50
+50
µA
µA
µA
µA
µA
µA
µA
µA
µA
30 µA / 130 µA
130 µA / 500 µA
500 µA / 750 µA
750 µA / 1 mA
1 mA / 1.2 mA
1.2 mA / 1.4 mA
1.4 mA / 1.6 mA
1.6 mA / 1.8 mA
315 µA
625 µA
875 µA
1.1 mA
1.3 mA
1.5 mA
1.7 mA
-50
-50
-50
-50
-50
-50
DC test conditions (unless otherwise specified): "Recommended Operating Conditions".
RADJ = FADJ = 1.1 mA. BIAS = .6 mA.
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
DC Characteristics (continued)
Parameter
Symbol
Min
Typ
Max
Units
COMPARATOR Circuit
V_INP Leakage (IPD = 0)
@ +8V
@ +5V
@ -2V
@ -4V
I_BIAS
I_BIAS
I_BIAS
I_BIAS
-2
-1
-1
-1
1 <
+2
+1
+1
+1
µA
µA
µA
µA
V_INP Leakage (IPD = 1)
@ VEE + 3.5V
I_BIAS
I_BIAS
-250
-250
100 <
100 <
+250
+250
nA
nA
@ VCC - 3.5V
Offset Voltage (Note 1)
IPD_C = 0
Vos
Vos
-10
-10
+10
+10
mV
mV
IPD_C = 1
Threshold Voltage
CVA, CVB
I_BIAS CVA(B)
V_INP
VEE + 2.9
-50
VCC - 2.9
+50
V
µA
V
Threshold Input Current
Input Voltage Range
VEE + 3.5
VCC - 3.5
Input Diffierential Range
Differential Output Swing
V_INP - CVA(B)
-12
+8
V
|QA - QA*|, |QB - QB*|
400
mV
Common Mode Output (Note 2)
Logical 1
QA, QA*, QB, QB*
QA, QA*, QB, QB*
PECL - 1.3
PECL - 1.8
PECL - 1.13
PECL - 1.64
PECL - 0.9
PECL - 1.4
V
V
Logical 0
POWER SUPPLIES
Power Supply Consumption
(Note 3)
Positive Supply
Negative Supply
ICC
IEE
120
-200
180
-160
mA
mA
DC test conditions (unless otherwise specified): "Recommended Operating Conditions".
RADJ = FADJ = 1.1 mA. BIAS = .6 mA.
Note 1: This parameter is guaranteed by characterization. It is tested in production against ± 100 mV
limits.
Note 2: Tested at PECL = 0V, PECL = +4V.
Note 3: No Load Conditions.
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
DC Characteristics (continued)
Parameter
Symbol
Min
Typ
Max
Units
DRIVER Circuit
Analog Inputs
High Level
DVH
DVL
DVH, DVL
DVH - DVL
I_in
VEE + 3.5
VEE + 2.9
VEE + 3.5
0
VCC - 2.9
VCC - 3.5
VCC - 2.0
9.0
V
V
V
Low Level
Super Voltage Levels
Driver Swing
Input Current
Slew Rate Adjustments
Chip Bias Current
V
–50
0.4
.6
+50
1.3
1.25
µA
mA
mA
RADJ, FADJ
BIAS
0.6
Driver Output
DC Output Current
Imax
Rout
Ibias
Ibias
-35
0.5
–250
–5
+35
3.0
+250
+5
mA
Ω
nA
nA
Output Impedance (@ 25 mA)
HiZ Leakage (IPD_D = 0)
HiZ Leakage (IPD_D = 1) (Note 1)
DC "High" Accuracy
Offset Voltage
DVH - DOUT
∆DVH/∆DOUT
DVH - DOUT
DVH - DOUT
–100
.985
-10
+100
1.0
+10
+15
mV
V/V
mV
Gain (Note 2)
Linearity (-2V to +7V)
Linearity (@ -3V, @ +8V)
-15
mV
DC "Low" Accuracy
Offset Voltage
DVL - DOUT
∆DVL/∆DOUT
DVL - DOUT
DVL - DOUT
–100
.985
–10
+100
1.0
+10
+15
mV
V/V
mV
Gain (Note 3)
Linearity (-3V to +6V)
Linearity (@ -4V, @ +7V)
–15
mV
Digital Inputs
Input Voltage Range
Differential Input Swing
Input Current
DHI(*), DVR_EN(*)
Input - Input*
Iin
–2.0
0.25
–350
+5.0
4.0
+350
V
V
µA
Note 1: This parameter is guaranteed by characterization. It is tested in production against ± 200 nA
limits.
Note 2: Gain is computed from 2 points: DVH = –1V, +4V.
Note 3: Gain is computed from 2 points: DVL = –1V, +4V.
2000 Semtech Corp.
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
AC Characteristics
Parameter
Symbol
Min
Typ
Max
Units
LOAD Circuit
Propagation Delay
Inhibit to Iout
Tpd_on
Tpd_off
3
<.8
ns
ns
Iout to Inhibit
Output Capacitance
Load Active
Cout
Cout
3.5
2.0
pF
pF
Load Off
COMPARATOR Circuit
Propagation Delay
Tpd
1.5
ns
Input Slew Rate Tracking
IPD_C = 0
6.0
25
V/ns
mV/ns
IPD_C = 1
Input Capacitance
Cin
2.0
pF
ps
Digital Output Rise and Fall Times
(20% - 80%)
Tr, Tr
250
Minimum Pulse Width
1.0
ns
DRIVER Circuit
Propagation Delay
Data to Output
Tpd
Tpd
Tpd
1.5
1.5
1.5
ns
ns
ns
Enable to HiZ
Enable to Output Active
Rise/Fall Times
800 mV (20% - 80%)
3V (10% - 90%)
5V (10% - 90%)
Tr/Tf
Tr/Tf
Tr/Tf
500
800
1.0
ps
ps
ns
Fmax
800 mV
3V
Fmax
Fmax
Fmax
600
400
200
MHz
MHz
MHz
5V
Minimum Pulse Width
800 mV
3V
5V
800
1.2
2.4
ps
ns
ns
Output Capacitance
Cout
2.0
pF
DC test conditions (unless otherwise specified): "Recommended Operating Conditions".
RADJ = FADJ = 1.1 mA. BIAS = .6 mA.
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2000 Semtech Corp.
16
Edge710
EDGE HIGH-PERFORMANCE PRODUCTS
Ordering Information
Model Number
Package
52 Lead MQFP (10 mm x 10 mm Body)
with Internal Heat Spreader
E710AHF
D710
Die Form
EVM710AHF
Edge710 Evaluation Board
Contact Information
Semtech Corporation
Edge High-Performance Division
10021 Willow Creek Rd., San Diego, CA 92131
Phone: (858)695-1808 FAX (858)695-2633
2000 Semtech Corp.
17
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