GS12341 [SEMTECH]
12G UHD-SDI Reclocking Adaptive Cable Equalizer;
| 型号： | GS12341 |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | 12G UHD-SDI Reclocking Adaptive Cable Equalizer |
| 文件： | 总109页 (文件大小：4169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GS12341
12G UHD-SDI Reclocking
Adaptive Cable Equalizer
Key Features
Additional Features
•
•
75Ω cable input interface with on-chip termination
•
•
•
•
•
•
Single 1.8V power supply for analog and digital core
GSPI serial control and monitoring interface
Four configurable GPIO pins for control or status monitoring
Wide operating temperature range: -40ºC to +85ºC
Small 6mm x 4mm 40-pin QFN
SMPTE ST 2082-1, ST 2081-1, ST 424, ST 292-1 and ST 259
compliant input/output
•
•
Multi-standard operation from 1Mb/s to 11.88Gb/s
In addition to standard SMPTE rates, the device also supports
reclocking of DVB-ASI at 270Mb/s, and MADI at 125Mb/s
Pin compatible with the GS12241, GS12141, GS12142, and
GS3241
•
•
•
3D Input Signal Eye Monitor
PRBS generator and checker
Automatic cable equalization—typical equalized cable
lengths of Belden 1694A cable:
•
Pb-free/Halogen-free/RoHS and WEEE compliant package
Applications
80m at 11.88Gb/s
Next Generation 12G UHD-SDI infrastructures designed to
support UHDTV1, UHDTV2, 4K D-Cinema and 3D HFR and HDR
production image formats. Typical applications: Monitors,
Switchers, Distribution Amplifiers and Routers.
100m at 5.94Gb/s
190m at 2.97Gb/s
260m at 1.485Gb/s
450m at 270Mb/s and 125Mb/s
•
•
•
Cable equalizer features:
Description
Improved reach with stress patterns
The GS12341 is a low-power, multi-rate reclocking Cable Equalizer
supporting rates up to 12G UHD-SDI. It is designed to equalize and
restore signals received over 80 meters coaxial cable at 12G,
compensate for DC content of SMPTE pathological signals, and
reclock the incoming data.
Automatic power down on loss of signal
Programmable carrier detect with squelch threshold
adjustment
Programmable launch swing compensation for
non-compliant source
The integrated eye monitor provides non-disruptive mission
mode analysis of the post equalized input signal. The 256x128
resolution scan matrix allows accurate signal analysis to speed up
prototyping and enable field analysis.
Built in macros enable customizable cross section analysis and
quick horizontal and vertical eye opening measurements.
With high phase consistency between scans and configurable
space and time thresholds, algorithms can be deployed in the
field to analyse long term signal quality variation (Bathtub Plot) to
reduce costly system installation debug time for intermittent
errors.
The two independently controlled trace drivers feature highly
configurable pre-emphasis and swing controls to compensate for
long trace and connector losses. The pre-emphasis pulse width
can be optimized to compensate for perturbations to frequency
response of transmission lines due to vias connectors and stubs.
The GS12341 is pin compatible with the GS12241 and GS12141
single input, and GS12142 dual input, 12G UHD-SDI Multi-rate
Reclocking Cable Equalizers. It is also pin compatible with the
GS3241 3G-SDI Multi-rate Reclocking Cable Equalizer.
Manual and automatic cable equalizer bypass
Trace driver features:
Integrated 100Ω, differential output termination
Extends output DC-coupling support with 1.2V to 2.5V
output supply range
Trace driver data output pre-emphasis to compensate for
up to 20”FR4 at 11.88Gb/s
Manual or automatic reclocker bypass
Manual or automatic mute or disable on LOS
Reclocker features:
Manual or automatic rate modes
Wide Loop bandwidth control
Reclocking at the following data rates: 125Mb/s, 270Mb/s,
1.485Gb/s, 2.97Gb/s, 5.94Gb/s, and 11.88Gb/s—this
includes the f/1.001 rates
Note: For the GS12341 to be pin compatible with the GS12142,
careful design considerations are required. Contact for your local
Semtech FAE for details.
GS12341
Final Data Sheet
PDS-061928
1 of 109
Semtech
Proprietary & Confidential
www.semtech.com
Rev.1
August 2019
GPIO2
GPIO3
GPIO4
SDOUT
GPIO1
SCLK
SDIN
CS
Control & Status
DDO0
Signal Selector
Trace Driver
PRBS
Generator
Data:
(Reclocked/Bypassed)
DDO0
PRBS Generator
Swing and Pre-emphasis
Control
Cable Equalizer
Reclocker
SDI
DDO1
Signal Selector
Trace Driver
Data:
(Reclocked/Bypassed)
PRBS
Checker
DDO1
PRBS Generator
Swing and Pre-emphasis
Control
EYE
Monitor
GS12341 Functional Block Diagram
GS12341
Final Data Sheet
PDS-061928
2 of 109
Semtech
Proprietary & Confidential
www.semtech.com
Rev.1
August 2019
Revision History
Version
ECO
PCN
Date
Changes and/or Modifications
Data Sheet status changed from Draft to Final. Updated Key
Features, Description, DC Electrical Characteristics, and AC
Electrical Characteristics.
1
0
048049
046248
—
—
August 2019
May 2019
New Document.
Contents
1. Pin Out.................................................................................................................................................................5
1.1 GS12341 Pin Assignment ................................................................................................................5
1.2 GS12341 Pin Descriptions ...............................................................................................................6
2. Electrical Characteristics................................................................................................................................9
2.1 Absolute Maximum Ratings ...........................................................................................................9
2.2 DC Electrical Characteristics ........................................................................................................ 10
2.3 AC Electrical Characteristics ......................................................................................................... 12
3. Input/Output Circuits.................................................................................................................................. 14
4. Detailed Description.................................................................................................................................... 15
4.1 Device Description .......................................................................................................................... 15
4.1.1 Sleep Mode............................................................................................................................ 15
4.2 Cable Equalizer ................................................................................................................................. 16
4.2.1 Cable Equalizer Bypass...................................................................................................... 16
4.2.2 Upstream Launch Swing Compensation.................................................................... 16
4.2.3 Carrier Detect, Squelch Control, and Loss of Signal ............................................... 17
4.3 Serial Digital Reclocker .................................................................................................................. 19
4.3.1 PLL Loop Bandwidth Control.......................................................................................... 20
4.3.2 Automatic and Manual Rate Detection....................................................................... 20
4.3.3 Lock Time ............................................................................................................................... 21
4.4 PRBS Checker .................................................................................................................................... 23
4.4.1 Timed PRBS Check Measurement Procedure............................................................ 23
4.4.2 Continuous PRBS Check Measurement Procedure................................................. 24
4.5 EYE Monitor ....................................................................................................................................... 27
4.5.1 Shape Scan and Measurement Time............................................................................ 28
4.5.2 Matrix-Scan and Shape-Scan Operation..................................................................... 30
4.6 PRBS Generator ................................................................................................................................ 36
4.7 Output Drivers .................................................................................................................................. 38
4.7.1 Bypassed Reclocker Signal Output Control ............................................................... 38
4.7.2 Output Driver Polarity Inversion.................................................................................... 39
4.7.3 Output Driver Data Rate Selection................................................................................ 39
4.7.4 Amplitude and Pre-Emphasis Control ......................................................................... 39
4.7.5 Trace Driver DC coupling requirements ..................................................................... 47
GS12341
Final Data Sheet
3 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
4.7.6 Output State Control Modes........................................................................................... 48
4.8 GPIO Controls .................................................................................................................................... 50
4.9 GSPI Host Interface ......................................................................................................................... 50
4.9.1 CS Pin....................................................................................................................................... 50
4.9.2 SDIN Pin .................................................................................................................................. 50
4.9.3 SDOUT Pin.............................................................................................................................. 51
4.9.4 SCLK Pin .................................................................................................................................. 52
4.9.5 Command Word 1 Description....................................................................................... 52
4.9.6 GSPI Transaction Timing................................................................................................... 55
4.9.7 Single Read/Write Access................................................................................................. 56
4.9.8 Auto-increment Read/Write Access ............................................................................. 58
4.9.9 Setting a Device Unit Address ........................................................................................ 59
4.9.10 Default GSPI Operation................................................................................................... 60
4.9.11 Clear Sticky Counts Through Four Way Handshake............................................. 61
4.9.12 Device Power-up Sequence.......................................................................................... 61
4.9.13 Host Initiated Device Reset ........................................................................................... 62
5. Register Map................................................................................................................................................... 64
5.1 Control Registers ............................................................................................................................. 64
5.2 Status Registers ................................................................................................................................ 67
5.3 Register Descriptions ..................................................................................................................... 68
6. Application Information...........................................................................................................................104
6.1 Typical Application Circuit .........................................................................................................104
7. Package & Ordering Information ..........................................................................................................105
7.1 Package Dimensions ....................................................................................................................105
7.2 Recommended PCB Footprint ..................................................................................................106
7.3 Packaging Data ..............................................................................................................................106
7.4 Marking Diagram ...........................................................................................................................107
7.5 Solder Reflow Profiles ..................................................................................................................107
7.6 Ordering Information ...................................................................................................................108
GS12341
Final Data Sheet
4 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
1. Pin Out
1.1 GS12341 Pin Assignment
40
39
38
37
36
35
34
33
32
31
30
29
VEE_SDI
SDI
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
VEEO
DDO0
SDI_TERM
VCC_SDI
RSVD
DDO0
GS12341
40-pin QFN
6mm x 4mm
VCCO_0
VCCO_1
DDO1/RCO
DDO1/RCO
VEEO
RSVD
RSVD
VEE_SDI
9
10
11
12
13
14
15
16
17
18
19
20
Figure 1-1: GS12341 Pin Assignment
GS12341
Final Data Sheet
5 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
1.2 GS12341 Pin Descriptions
Table 1-1: GS12341 Pin Descriptions
Pin Number
Name
Type
Description
Most negative power supply connection for the Cable Equalizer.
Connect to ground.
1, 8
2
VEE_SDI
SDI
Power
Input
—
Single-ended CML input with internal 75Ω termination.
Input Common Mode termination. Decouple to ground through
resistor and capacitor. See Section 6.1 for recommended values.
3
SDI_TERM
Most positive power supply connection for the Cable Equalizer.
4
VCC_SDI
RSVD
Power
—
Connect to 1.8V and decouple to ground. See Section 6.1 for
recommended values.
These pins may be left floating. Please contact your Semtech FAE for
additional information on circuit compatibility with the GS12281.
5, 6, 7, 9, 30, 32
Chip Select input for the Gennum Serial Peripheral Interface (GSPI)
host control/status port.
1.8V CMOS input with 100kΩ pull-up.
Active-LOW input.
10
CS
Digital Input
Refer to Section 4.9.1 for more details.
Serial digital data input for the Gennum Serial Peripheral Interface
(GSPI) host control/status port.
11
12
13
SDIN
SDOUT
SCLK
Digital Input
Digital Output
Digital Input
1.8V CMOS input with 100kΩ pull-down.
Refer to Section 4.9.2 for more details.
Serial digital data output for the Gennum Serial Peripheral Interface
(GSPI) host control/status port.
1.8V CMOS output.
Refer to Section 4.9.3 for more details.
Burst-mode clock input for the Gennum Serial Peripheral Interface
(GSPI) host control/status port.
1.8V CMOS input with 100kΩ pull-down.
Refer to Section 4.9.4 for more details.
Most negative power supply for digital core logic.
Connect to ground.
14, 15
16
VSS
Power
Power
Most positive power supply connection for digital core logic.
VDD
Connect to 1.8V and decouple to ground. See Section 6.1 for
recommended values.
Multi-function Control/Status Input/Output 0.
Default function:
Digital
Input/Output
Direction = Output
Signal = High indicates LOS (Loss of Signal, inverse of Carrier Detect)
17
GPIO0
Pin is 1.8V CMOS I/O, please refer to GPIO0_CFG for more information
on how to configure GPIO0.
GS12341
Final Data Sheet
PDS-061928
6 of 109
Semtech
Proprietary & Confidential
www.semtech.com
Rev.1
August 2019
Table 1-1: GS12341 Pin Descriptions (Continued)
Pin Number
Name
Type
Description
Multi-function Control/Status Input/Output 1.
Default function:
Digital
Input/Output
Direction = Output
Signal = High indicates PLL is locked
18
GPIO1
Pin is 1.8V CMOS I/O, please refer to GPIO1_CFG for more information
on how to configure GPIO1.
Most negative power supply connection for the analog core.
Connect to ground.
19, 31, 37, 38
20
VEE_CORE
Power
Power
Most positive power supply connection for trace driver pre driver.
Connect to 1.8V and decouple to ground. See Section 6.1 for
recommended values.
VCCO1P8_1
Most negative power supply connection for the output drivers.
Connect to ground.
21, 28
22, 23
VEEO
Power
Differential CML output with two internal 50Ω pull-ups. The data
signal or PRBS generator can be selected for this output. The PRBS
generator can be configured to generate a PRBS7 or a clock pattern.
DDO1/RCO,
DDO1/RCO
Output
Most positive power supply connection for the DDO1/ DDO1 output
driver.
24
25
VCCO_1
VCCO_0
Power
Power
Connect to 1.2V – 2.5V and decouple to ground. See Section 6.1 for
recommended values.
Most positive power supply connection for the DDO0/DDO0 output
driver.
Connect to 1.2V – 2.5V and decouple to ground. See Section 6.1 for
recommended values.
Differential CML output with two internal 50Ω pull-ups. The data
signal or PRBS generator can be selected for this output. The PRBS
generator can be configured to generate a PRBS7 or a clock pattern.
26, 27
29
DDO0/DDO0
VCCO1P8_0
Output
Power
Most positive power supply connection for trace driver pre driver.
Connect to 1.8V and decouple to ground. See Section 6.1 for
recommended values.
Multi-function Control/Status Input/Output 2.
Default function:
Digital
Input/Output
Direction = Input
Signal = Set HIGH to put device in sleep
33
GPIO2
Pin is 1.8V CMOS I/O, please refer to GPIO2_CFG for more information
on how to configure GPIO2.
VCO filter capacitor connection. Decouple to ground. See Section 6.1
for recommended values.
34
35
VCO_FILT
Passive
Power
Most positive power supply connection for the analog core.
VCC_CORE
Connect to 1.8V and decouple to ground. See Section 6.1 for
recommended values.
GS12341
Final Data Sheet
PDS-061928
7 of 109
Semtech
Proprietary & Confidential
www.semtech.com
Rev.1
August 2019
Table 1-1: GS12341 Pin Descriptions (Continued)
Pin Number
Name
Type
Description
Multi-function Control/Status Input/Output 3.
Default function:
Digital
Input/Output
Direction = Input
Signal = Set HIGH to disable DDO1
36
GPIO3
Pin is 1.8V CMOS I/O, please refer to GPIO3_CFG for more information
on how to configure GPIO3.
Loop filter capacitor connection. Connect to pin 40 through capacitor.
See Section 6.1 for recommended values.
39
40
LF+
LF-
Passive
Passive
Loop filter capacitor connection. Connect to pin 39 through capacitor.
See Section 6.1 for recommended values.
Central paddle can be connected to ground or left unconnected. Its
purpose is to provide increased mechanical stability. It is not required
for thermal dissipation. It is not recommended to connect device
ground pins to the central paddle.
Tab
—
—
GS12341
Final Data Sheet
PDS-061928
8 of 109
Semtech
Proprietary & Confidential
www.semtech.com
Rev.1
August 2019
2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Table 2-1: Absolute Maximum Ratings
Parameter
Value
Supply Voltage—Core
(VCC_SDI, VCC_CORE, VDD)
-0.5V to +2.2V
Supply Voltage—Output Driver
(VCCO_0, VCCO_1)
-0.5V to +2.8V
Input ESD Voltage (any pin)
2kV HBM
Storage Temperature Range (TS)
-50°C to +125°C
Input Voltage Range (SDI, SDI)
-0.3 to (VCC_SDI +0.3)V
-0.3 to (VCC_CORE +0.3)V
Input Voltage Range (GPIO2, GPIO3)
Input Voltage Range (CS, SDIN, SCLK, VSS,
VDD, GPIO0, GPIO1)
-0.3 to (VDD +0.3)V
260°C
Solder Reflow Temperature
Note: Absolute Maximum Ratings are those values beyond which damage may occur.
Functional operation outside of the ranges shown in the AC/DC electrical characteristics
tables is not guaranteed.
GS12341
Final Data Sheet
9 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
2.2 DC Electrical Characteristics
Table 2-2: DC Electrical Characteristics
TA = -40°C to +85°C, unless otherwise shown.
Parameter
Symbol
Conditions
Min
Typ
Max
Units Notes
VCC_SDI,
VCC_CORE,
VDD
Supply Voltage
1.71
1.8
1.89
V
—
1.14
1.71
2.38
1.2
1.8
2.5
1.26
1.89
2.63
V
V
V
—
—
—
Supply Voltage - Output
Driver
VCCO_0,
VCCO_1
VCCO_0 = 1.2V,
Output Swing = 400mVppd
—
—
—
—
405
410
430
420
—
—
—
—
mW
mW
mW
mW
1
1
1
1
VCCO_0 = 1.8V,
Output Swing = 400mVppd
Power—Mission Mode
VCCO_0 = 1.8V,
Output Swing = 800mVppd
(DDO0/DDO0 enabled,
DDO1/DDO1 disabled)
PD
VCCO_0 = 2.5V,
Output Swing = 400mVppd
VCCO_0 = 2.5V,
Output Swing = 800mVppd
—
—
—
440
35
9
—
50
16
mW
mW
mA
1
PD
Power—Sleep Mode
Sleep
—
VCCO = 1.2V,
Output Swing = 400mVppd
1, 3
VCCO = 1.8V,
Output Swing = 400mVppd
—
—
—
—
—
—
9
16
27
16
27
32
32
mA
mA
mA
mA
mA
mA
1, 3
1, 3
1, 3
1, 3
1, 3
1, 3
VCCO = 1.8V,
Output Swing = 800mVppd
ICCO_0, ICCO_1
Supply Current—Trace Driver
18
9
VCCO = 2.5V,
Output Swing = 400mVppd
VCCO = 2.5V,
Output Swing = 800mVppd
18
25
25
VCCO1P8_0
Output Swing = 800mVppd
ICCO1P8_0
ICCO1P8_1
,
SupplyCurrent—TraceDriver
Pre-driver
VCCO1P8_1
Output Swing = 800mVppd
GS12341
Final Data Sheet
10 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 2-2: DC Electrical Characteristics (Continued)
TA = -40°C to +85°C, unless otherwise shown.
Parameter
Symbol
Conditions
Min
Typ
Max
Units Notes
CDR Locked to Rate
—
124
142
mA
mA
—
—
CDR Unlocked During
Rate Search
—
182
208
Supply Current—Analog
Core
ICC_CORE
PRBS Generator Enabled
PRBS Checker Enabled
Eye Monitor Enabled
—
—
—
119
55
140
94
mA
mA
mA
4,5
4
50
92
4
Supply Current—Cable
Equalizer
ICC_SDI
—
—
—
—
—
—
55
15
75
18
—
mA
mA
—
—
2
Supply Current—Digital
Logic
IDD
DDO Output Common
Mode Voltage
V
-
CCO
VCMOUT
V
/2
DDO
DDO
Output Termination
Differential
—
—
100
75
—
—
Ω
Ω
V
2
SDI Input Termination
Between SDI and GND
—
—
0.65*
VDD
VIH
VIL
VIH
VIL
—
VDD
Input Voltage—Digital Pins
(CS, SDIN, SCLK, GPIO[0:1])
0.35*
VDD
0
—
—
—
V
V
V
—
—
—
0.65*
VCC_CORE
VCC_CORE
Input Voltage—Digital Pins
(GPIO[2:3])
0.35*
VCC_CORE
0
VDD -
0.45
VOH
VOL
VOH
VOL
IOH = -5mA
IOL = +5mA
IOH = -5mA
IOL = +5mA
—
—
—
—
—
0.45
—
V
V
V
V
—
—
—
—
Output Voltage—Digital Pins
(SDOUT, GPIO[0:1])
—
VCC_CORE
- 0.45
Output Voltage—Digital Pins
(GPIO[2:3])
—
0.45
Notes:
1. Pre-emphasis is disabled.
2. This applies for DDO0 and DDO1.
3. The specifications provided are per symbol, not a combined value.
4. Current listed is an increase to ICC_CORE when stated condition is true.
5. Selected clock source = VCO free running.
GS12341
Final Data Sheet
11 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
2.3 AC Electrical Characteristics
Table 2-3: AC Electrical Characteristics
VCC_SDI, VCC_CORE, VDD = 1.8V 5ꢀ and VCCO_0, VCCO_1 = +1.2/1.8/2.5V 5ꢀ, TA = -40°C to +85°C, unless otherwise shown.
Parameter
Symbol
DRSDI
Conditions
Min
0.001
720
Typ
—
Max
11.88
880
Units Notes
Serial Input Data Rate
Upstream Launch Swing
—
Gb/s
mVpp
12
3
VSDI
—
800
200
mVppd
mVppd
200mV
150
250
8
Differential Output
Voltage Swing
VDDO
800mV
600
0.7
0.8
800
0.85
0.95
1000
—
9
12G
UI
UI
—
—
Intrinsic Input Jitter Tolerance
IIJT
MADI/SD/HD/3G/6G
—
PLL Lock Time—
Asynchronous
tALOCK
tSLOCK
triseDDO
—
—
75
—
ms
5
SD
—
—
—
—
10
2
μs
μs
5
5
PLL Lock Time—Synchronous
DDO, DDO, Rise/Fall Time
HD/3G/6G/12G
,
All rates
—
—
—
—
—
40
8
ps
ps
6,11
6
tfallDDO
DDO Mismatch in
Rise/Fall Time
—
—
DDO Duty Cycle Distortion
—
—
—
—
—
—
—
—
—
10
-17
-12
-8
ps
dB
6,11
1
5MHz to 1.485GHz
1.485GHz to 2.97GHz
2.97GHz to 5.94GHz
5.94GHz to 11.88GHz
Belden 1694A, 450m
—
dB
1
Input Return Loss
—
—
dB
1
—
-5
dB
1
tOJ(125Mb/s)
tOJ(270Mb/s)
tOJ(1.485Gb/s)
tOJ(2.97Gb/s)
tOJ(5.94Gb/s)
tOJ(11.88Gb/s)
UIpp
0.01
0.05
2,10
UIpp
UIpp
UIpp
UIpp
UIpp
Belden 1694A, 450m
Belden 1694A, 260m
Belden 1694A, 190m
Belden 1694A, 100m
Belden 1694A, 80m
—
—
—
—
—
0.05
0.03
0.05
0.07
0.07
0.15
0.10
0.10
0.15
0.15
2,10
2,10
2,10
2,10
10
Serial Data Output Jitter
DDO0, DDO0
DDO1, DDO1
GS12341
Final Data Sheet
12 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 2-3: AC Electrical Characteristics (Continued)
VCC_SDI, VCC_CORE, VDD = 1.8V 5ꢀ and VCCO_0, VCCO_1 = +1.2/1.8/2.5V 5ꢀ, TA = -40°C to +85°C, unless otherwise shown.
Parameter
Symbol
Conditions
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ
10
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units Notes
Setting 0.0625x
Setting 0.125x
Setting 0.25x
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
MHz
MHz
kHz
kHz
MHz
MHz
MHz
kHz
MHz
MHz
MHz
MHz
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
20
BWLOOP(125Mb/s)
38
Setting 0.5x (Default)
Setting 1.0x
76
150
20
Setting 0.0625x
Setting 0.125x
Setting 0.25x
40
BWLOOP(270Mb/s)
BWLOOP(1.485Gb/s)
BWLOOP(2.97Gb/s)
BWLOOP(5.94Gb/s)
BWLOOP(11.88Gb/s)
80
Setting 0.5x
160
316
110
220
440
876
1750
220
440
880
1.76
3.5
Setting 1.0x (Default)
Setting 0.0625x
Setting 0.125x
Setting 0.25x
Setting 0.5x (Default)
Setting 1.0x
PLL Loop Bandwidth
Setting 0.0625x
Setting 0.125x
Setting 0.25x
Setting 0.5x (Default)
Setting 1.0x
Setting 0.0625x
Setting 0.125x
Setting 0.25x
440
880
1.76
3.5
Setting 0.5x (Default)
Setting 1.0x
7
Setting 0.0625x
Setting 0.125x
Setting 0.25x
880
1.76
3.5
Setting 0.5x (Default)
Setting 1.0x
7
14
Table Notes:
1. Values achieved with Semtech evaluation board and connector.
2. Measured using a clean input source.
3. Default value for CFG_EQ_INPUT_LAUNCH_SWING_COMP parameter in control register 0x18. The default parameter value is 80d (50h).
4. Default trace driver swing Setting.
5. Please see 4.3.3.1 for the further definition on Synchronous and Asynchronous Lock Time.
6. This specification applies to and DDO1/DDO1 and DDO0/DDO0.
7. Please see PLL_LOOP_ BANDWIDTH_ 0 for the full range of loop bandwidth settings.
8. Output Driver Setting of 8.
9. Output Driver Setting of 36.
10.Max jitter occurs at the maximum cable length.
11.Rise/fall time was measured between 80ꢀ and 20ꢀ.
12.The rise/fall time of signals at source should not be more than 62ns.
GS12341
Final Data Sheet
13 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
3. Input/Output Circuits
2
VCCO_<n>
VCCO_<n>
VCCO_<n>
VCC_SDI
VCC_SDI
VCC_SDI
1kΩ
50Ω
50Ω
75Ω
RC
SDI
SDI_TERM
DDO
DDO
RC
3.5kΩ
Note: The <n> in VCCO_<n> refers to the ouput power supply number. VCCO_1 is
the power supply connection for DDO1/DDO1, and VCCO_0 is the power supply
connection for DDO0/DDO0.
Figure 3-1: SDI, SDI_TERM
Figure 3-2: DDO1/DDO1, DDO0/DDO0
VDD
VDD
VDD
VDD
VDD
100kΩ
SDIN,
SCLK
CS
100kΩ
Figure 3-3: SDIN, SCLK
Figure 3-4:
.
CS
VCC_IO*
VCC_IO*
VCC_IO*
1kΩ
GPIO[0:3]
100kΩ
VDD
VDD
VCC_IO*
SDOUT
Note: VCC_IO makes reference to the following power supplies and pins:
VCC_IO = VDD for GPIO[0:1]
VCC_IO = VCC_CORE for GPIO[2:3]
Figure 3-5: SDOUT
Figure 3-6: GPIO[0:3]
GS12341
Final Data Sheet
PDS-061928
14 of 109
Semtech
Proprietary & Confidential
www.semtech.com
Rev.1
August 2019
4. Detailed Description
4.1 Device Description
The GS12341 features a 75Ω internally terminated Cable Equalizer, which can equalize
up to TBD meters of Belden1694A cable at 12G. The device includes a Reclocker which
will lock to and re-sample valid SMPTE, MADI, and DVB-ASI signals to produce extremely
low output jitter, even at extended cable lengths. The Reclocker has extensive loop
bandwidth control to enable jitter transfer optimization. To facilitate system testing, the
device also includes 3D eye monitor, PRBS7 checker and generator. The two trace
drivers have independent amplitude and pre-emphasis control which can compensate
for 14dB of insertion loss at 5.94GHz. The pre-emphasis control is two dimensional in
both drivers, where both pre-emphasis pulse amplitude and width adjustments can be
made to help optimize for interconnect mismatches such as vias and connectors.
4.1.1 Sleep Mode
To enable low power operation, the GS12341 has manual and automatic sleep mode
control.
The default mode is automatic sleep mode on LOS (Loss Of Signal). The device can also
be manually put into sleep mode. When the device is in sleep mode, all the core blocks
are powered down, except the host interface and carrier detect circuits. The trace driver
can be configured to be disabled or muted during sleep.
The CTRL_AUTO_SLEEP and CTRL_MANUAL_SLEEP parameters in register 0x3,
control the sleep mode of the device. The default value of the CTRL_AUTO_SLEEP
parameter is 1 (auto sleep). While in auto sleep mode, the CTRL_MANUAL_SLEEP
b
parameter has no effect. To enable host control of the sleep mode, set the
CTRL_AUTO_SLEEP parameter to 0 manual sleep control. To prevent the device from
b
entering sleep, set the CTRL_MANUAL_SLEEP parameter to 0 (not sleep). To manually
b
configure the device to sleep, set the CTRL_MANUAL_SLEEP parameter to 1 (sleep).
b
The device can also be manually made to sleep through the GPIO pins. The default GPIO
pin to control sleep is GPIO2 (pin 33). Drive this pin HIGH to make the device sleep.
Section 4.6 describes the PRBS generator function. If the device's PRBS generator is
intended to be used without a valid input signal, the device should be manually set to
not sleep as described above. Without a valid input signal, an LOS status will be
generated and the device will enter sleep mode and the PRBS block will be disabled. For
a description of LOS thresholds and settings, see Section 4.2.3.
GS12341
Final Data Sheet
15 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
4.2 Cable Equalizer
The GS12341 can automatically adjust its gain to equalize and restore SMPTE compliant
signals received over different lengths of coaxial cable having loss characteristics similar
to Belden 1694A, 4964R, or Canare L-5.5CUHD. With the default settings, the device will
automatically equalize MADI at 125Mb/s and SMPTE compliant signals between SD at
270Mb/s and UHD-SDI at 11.88Gb/s and bypass signals below 125Mb/s.
The GS12341 features programmable Launch Swing Compensation, squelch threshold
adjust, and bypass, all of which can be set through the device's host interface. The
equalized or bypassed signal is then routed to the eye monitor and serial digital
Reclocker block.
4.2.1 Cable Equalizer Bypass
With the default settings, the device will automatically bypass signals below 125Mb/s.
During cable equalizer-bypass mode, the device supports low data rate and slow edge
signals such as SMPTE310 and AES3id. The rise/fall times must not exceed 62ns. While in
cable equalizer bypass mode, signal will not be reclocked.
To force the device to bypass the cable equalizer, DC restoration stage, and Reclocker,
the following two methods can be used:
Host Interface Control:
Set the following parameters in register 17 :
h
•
•
CTRL_CEQ_AUTO_BYPASS = 0
CTRL_CEQ_MANUAL_BYPASS = 1
GPIO Control:
1. Configure a GPIO as an input by writing 0 to the CFG_GPIO<n>_OUTPUT_ENA.
h
2. Configure the GPIO function as “cable equalizer bypass enable,” by writing 84 to
h
CFG_GPIO<n>_FUNCTION.
3. Drive the selected GPIO pin HIGH.
Note: The <n> in the control parameter names refers to the GPIO pin number.
4.2.2 Upstream Launch Swing Compensation
The GS12341 cable equalizer has an automatic gain control circuit, that is optimized on
the assumption that the trace driver in the upstream device is SMPTE compliant and has
a launch swing of 800mV
10ꢀ. When the source amplitude is known to be
pp
non-SMPTE compliant, a compensation adjustment can be made in the GS12341. The
GS12341 can adjust for launch swings in the range of 250mV to 1V in approximately
50mV
increments. Upstream launch swing compensation can be adjusted through
ppd
the CFG_EQ_INPUT_LAUNCH_SWING_COMP parameter in control register 0x18. The
default parameter value is 80 (50 ), which corresponds to a nominal launch swing of
d
h
800mV
.
ppd
GS12341
Final Data Sheet
16 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
4.2.3 Carrier Detect, Squelch Control, and Loss of Signal
The GS12341 cable equalizer has highly configurable carrier detection and squelching
capability. The carrier detection can be made more robust against spurious signals and
noise at the inputs and the squelch control can be configured and enabled to reduce
false outputs to low level signals such as crosstalk.
The GS12341 reports two separate carrier detect parameters—STAT_PRI_CD and
STAT_SEC_CD. They are described in Section 4.2.3.1 and Section 4.2.3.2 respectively.
Note: The parameters referred to within Section 4.2.3 to Section 4.2.3.2 are linked to
their respective registers in Table 4-1.
4.2.3.1 Primary Carrier Detection (STAT_PRI_CD) Configuration
Primary carrier detection (STAT_PRI_CD) can be configured for higher stability by
filtering out longer transients or glitches. This can be achieved by increasing the
sampling window over which the signal is sampled and the number of samples required
to assert or de-assert it.
There are three configuration parameters that control assertion or de-assertion of
STAT_PRI_CD:
CFG_CD_FILTER_SAMPLE_WIN
CFG_FILTER_DEASSERT_CNT
CFG_CD_FILTER_ASSERT_CNT
See Figure 4-1 for a visual representation of the STAT_PRI_CD configuration
parameters.
With the default values in place:
An assertion (setting HIGH) of STAT_PRI_CD will take place after a valid signal is
present for ~6.5ms
A de-assertion (setting LOW) of STAT_PRI_CD will take place after loss of a valid
signal for ~96μs
If the application requires any adjustment of the sampling window, assertion count, or
de-assertion count, please consult the following equations to calculate the associated
time to assert or de-assert STAT_PRI_CD.
STAT_PRI_CD de-assert time:
(1.6μs) * (CFG_CD_FILTER_SAMPLE_WIN + 1) * CFG_CD_FILTER_ DEASSERT_CNT
STAT_PRI_CD assert time:
(1.6ꢁs) * (CFG_CD_FILTER_SAMPLE_WIN + 1) * CFG_CD_FILTER_ASSERT_CNT
GS12341
Final Data Sheet
17 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
= ASSERT Threshold
CFG_CD_FILTER_ASSERT_CNT =n
n=1
n=2
n=3
…
Time in clock cycles
CFG_CD_FILTER_SAMPLE_WIN
= DEASSERT Threshold
…
CFG_CD_FILTER_DEASSERT_CNT =n
n=1
n=2
n=3
Time in clock cycles
CFG_CD_FILTER_SAMPLE_WIN
Figure 4-1: STAT_PRI_CD Configuration Parameters
4.2.3.2 Secondary Carrier Detection (STAT_SEC_CD) Configuration
The secondary carrier detection signal acts as an additional carrier detection which can
be further filtered through squelch controls. It also serves as the control signal for Mute
on LOS (Loss Of Signal) and Disable on LOS. Please refer to Section 4.7.6 to
Section 4.7.6.2 for further information on this.
If the application requires the use of squelch settings, start by setting the following:
CFG_SEC_CD_INCL_CLI_SQUELCH = 1
Once this parameter is set, the device will apply squelch based off of the settings found
within the following parameters:
CFG_CLI_SQUELCH_THRESHOLD
CFG_CLI_SQUELCH_HYSTERESIS
The device will use these parameters to determine squelch status and set that within
STAT_CLI_SQUELCH. Based off of this, secondary carrier detection can be described as:
STAT_SEC_CD = inverse of (STAT_CLI_SQUELCH & STAT_PRI_CD).
To help detail how the device determines the state of Squelch, we define the following
variables:
CLI = STAT_CABLE_LEN_INDICATION
THR = CFG_CLI_SQUELCH_THRESHOLD
HYS = CFG_CLI_SQUELCH_HYSTERESIS
SQL = STAT_CLI_SQUELCH
The following rules define the state of SQL. Note: If the cable equalizer is in bypass
(STAT_CEQ_BYPASS = 1), the device will set SQL to 0.
If CLI > (THR + HYS), the device will set SQL to 1, otherwise:
If CLI < (THR - HYS), the device will set SQL to 0, otherwise:
GS12341
Final Data Sheet
18 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
If CLI ≥ (THR - HYS) and CLI ≤ (THR + HYS), SQL remains unchanged
If SQL = 1, the device will not indicate lock and the trace driver state will be
defined by output state control parameters settings, see Section 4.7.6 for more
details
Table 4-1: Cable Equalizer Status and Configuration Parameters
Register Address and Name
Parameter Name
CFG_SEC_CD_INCL_CLI_SQUELCH Enables or disables squelch control.
Used to tune the squelch threshold based on the
Parameter Description
h
15,
CARR_ DET_CFG
CFG_CLI_SQUELCH_THRESHOLD
CFG_CLI_SQUELCH_HYSTERESIS
CFG_CD_FILTER_SAMPLE_WIN
CFG_CD_FILTER_DEASSERT_CNT
CFG_CD_FILTER_ASSERT_CNT
STAT_CNT_PRI_CD_CHANGES
STAT_CNT_SEC_CD_CHANGES
STAT_CLI_SQUELCH
tolerance requirements of the application.
16,
SQUELCH_ PARAMETERS
Used to tune the squelch hysteresis based on the
tolerance requirements of the application.
20,
Primary carrier detect sampling window size.
Primary carrier detect de-assertion count.
Primary carrier detect assertion count.
CD_FILTER_ DELAYS_0
21,
CD_FILTER_ DELAYS_1
22,
CD_FILTER_ DELAYS_2
A counter showing the number of times the primary
Carrier Detect signal changed.
84,
STICKY_ COUNTS_0
A counter showing the number of times the secondary
Carrier Detect signal changed.
86,
Cable equalizer Squelch status.
CURRENT_ STATUS_0
Primary filtered carrier detect of the analog carrier detect
signal.
STAT_PRI_CD
87,
CURRENT_ STATUS_1
Secondary filtered carrier detect of the analog carrier
detect signal.
STAT_SEC_CD
88,
STAT_CABLE_LEN_INDICATION
SDI cable length indicator.
EQ_GAIN_IND
4.3 Serial Digital Reclocker
The GS12341 includes an integrated Reclocker, whose purpose is to lock to a valid
incoming signal from the cable equalizer stage and produce a lower jitter signal at the
cable or trace driver outputs. The Reclocker will attempt to lock to any of the following
data rates: MADI (125Mb/s), SD-SDI (270Mb/s), HD-SDI (1.485Gb/s), 3G-SDI (2.97Gb/s),
6G-SDI (5.94Gb/s) and 12G-SDI (11.88Gb/s). This includes the f/1.001 rates. The default
settings of the Reclocker block are optimal for most applications. However, the
following controls allow for customized behaviour of the Reclocker: loop bandwidth
control, Automatic and Manual Rate Detection. Please see Section 4.3.1 to Section 4.3.2
for a description of these functionalities.
GS12341
Final Data Sheet
19 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Note: The parameters referred to within Section 4.3.1 to Section 4.3.2 are linked to their
respective registers in Table 4-3. For a complete list of registers and functions, please see
Section 5.
4.3.1 PLL Loop Bandwidth Control
The ratio of output peak-to-peak jitter to input peak-to-peak jitter of the Reclocker can
be represented by a low-pass jitter transfer function, with a bandwidth equal to the PLL
loop bandwidth. Although the default loop bandwidth settings for the GS12341
Reclocker are ideal for most SDI signals, the GS12341 allows the user to adjust the loop
bandwidth for each supported rate.
Registers 0x0A through 0x0C contain the following parameters which allow the user to
configure rate dependent loop bandwidth: CFG_PLL_LBW_12G, CFG_PLL_LBW_6G,
CFG_PLL_LBW_3G, CFG_PLL_LBW_HD, CFG_PLL_LBW_SD, and
CFG_PLL_LBW_MADI. The loop bandwidth settings are defined in terms of ratios of the
nominal loop bandwidth. For each rate, where '1.0x' is the nominal loop bandwidth, the
following ratios are available: 0.0625x, 0.125x, 0.25x, 0.5x, and 1.0x. Table 2-3 provides
the specific loop bandwidths for each data rate and loop bandwidth setting. Lowering
the loop bandwidth will lower the jitter amplitude above the loop bandwidth
frequency. Although lower output jitter is desirable, the lower loop bandwidth may
reduce the device’s IJT to very high jitter that may be present outside the loop
bandwidth.
4.3.2 Automatic and Manual Rate Detection
With the default rate detect setting, the Reclocker will automatically attempt to lock to
any of following data rates: MADI (125Mb/s), SD-SDI (270Mb/s), HD-SDI (1.485Gb/s),
3G-SDI (2.97Gb/s), 6G-SDI (5.94Gb/s) and 12G-SDI (11.88Gb/s). This includes the f/1.001
rates. However, the Reclocker can be configured to only lock to a single rate, by setting
the CFG_AUTO_RATE_DETECT_ENA and CFG_MANUAL_RATE parameters in register
0x06.
The STAT_LOCK parameter in register 0x86 will indicate that the Reclocker is locked
when its value is 1 and unlocked when its value is 0 . The lock status can also be
b
b
monitored externally on any GPIO pin, however it is the default mode for GPIO1, pin 18.
The STAT_DETECTED_RATE parameter in register 0x87 will indicate the data rate at
which the Reclocker is locked to. A value of 0 in the STAT_DETECTED_RATE parameter
d
indicates that the device is not locked, while values between 1 and 6 will indicate that
d
d
the device is locked to one of the six available rates between MADI at 125Mb/s and
UHD-SDI at 11.88Gb/s.
GS12341
Final Data Sheet
20 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 4-2: Detected Data Rates
STAT_DETECTED_
Detected Data Rate
RATE [2:0]
0
1
2
3
4
5
6
7
Unlocked
MADI (125Mb/s)
SD (270Mb/s)
HD (1.485Gb/s)
3G (2.97Gb/s)
6G (5.94Gb/s)
12G (11.88Gb/s)
Reserved
If the Reclocker cannot lock to any of the valid rates in automatic mode or the selected
rate in manual mode, the signal can automatically be bypassed to the output. If the
Reclocker does lock to the incoming signal, the reclocked and bypassed (if manual
bypass control enabled) signals are available at the appropriate output. See the
Section 4.7 for more details.
4.3.3 Lock Time
4.3.3.1 Synchronous and Asynchronous Lock Time
Synchronous lock time is defined as the time it takes the device to re-lock to an existing
signal that has been momentarily interrupted or to a new signal of the same data rate
as the previous signal which has been quickly switched in.
Asynchronous lock time is defined as the time it takes the device to lock when a signal
is first applied to the serial digital inputs, or when the signal rate changes. The
asynchronous and synchronous lock times are defined in Table 2-3.
Note: To ensure synchronous lock times are met, the maximum interruption time of the
signal is 10μs for an SD-SDI signal. HD, 3G, 6G, or 12G signals must have a maximum
interruption time of 6μs. The new signal, after interruption, must have the same
frequency as the original signal but may have an arbitrary phase.
GS12341
Final Data Sheet
21 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 4-3: Reclocker Control and Status Parameters
Register Address
and Name
h
Parameter Name
Description
Enables or disables the automatic rate detection mode of the
Reclocker.
CFG_AUTO_RATE_DETECT_ENA
CFG_MANUAL_RATE
06,
RATE_ DETECT_ MODE
Select a single rate for Reclocker rate detection when
CFG_AUTO_RATE_DETECT_ENA is 0b.
0A,
CFG_PLL_LBW_12G
CFG_PLL_LBW_6G
CFG_PLL_LBW_3G
CFG_PLL_LBW_HD
CFG_PLL_LBW_SD
CFG_PLL_LBW_MADI
Configures the Loop Bandwidth for 12G signals.
Configures the Loop Bandwidth for 6G signals.
Configures the Loop Bandwidth for 3G signals.
Configures the Loop Bandwidth for HD signals.
Configures the Loop Bandwidth for SD signals.
Configures the Loop Bandwidth for MADI signals.
PLL_LOOP_
BANDWIDTH_ 0
0B,
PLL_LOOP_
BANDWIDTH_ 1
0C,
PLL_LOOP_
BANDWIDTH_ 2
CFG_GPIO1_FUNCTION
Sets the function of GPIO1.
11,
GPIO1_CFG
CFG_GPIO1_OUTPUT_ ENA
Sets the GPIO pin as either an output or an input.
Counter showing the number of times the PLL lock status
changed.
STAT_CNT_PLL_LOCK_CHANGES
STAT_CNT_RATE_CHANGES
STAT_LOCK
85,
STICKY_ COUNTS_1
Counter showing the number of times the PLL lock rate
changed.
86,
The status of the PLL. Locked, or unlocked.
The rate at which the PLL is locked to.
CURRENT_ STATUS_0
87,
STAT_DETECTED_RATE
CURRENT_ STATUS_1
GS12341
Final Data Sheet
PDS-061928
22 of 109
Semtech
Proprietary & Confidential
www.semtech.com
Rev.1
August 2019
4.4 PRBS Checker
The GS12341 includes an integrated PRBS checker, which can error check a PRBS7 signal
out of the cable equalizer input block.
There are two modes of operation for the PRBS checker:
•
•
Timed Mode: Used for precise measurements of up to ~3.334s.
In timed mode, the host sets the measurement time and executes the checker
operation. The device ends the PRBS error check measurement when the timer
expires, and the host reads back the measurement status and error count.
Continuous Mode: Can be used for longer measurements but with less precision in
the time interval.
In continuous mode, the host controls the starts and stops of the PRBS error
checking operation then reads back the measurement status and error count.
Note: When working with the PRBS Checker, please note the following:
•
The parameters referred to in this Section 4.4.1 to Section 4.4.2 are briefly described
and linked to their respective registers in Table 4-4. For a complete list of registers
and functions, please see Section 5.
•
The PRBS generator and checker can be active at the same time, however, the
generator can not be looped back on itself for error checking.
4.4.1 Timed PRBS Check Measurement Procedure
For applications where measurement times are ~3.34s or less, the timed PRBS check
mode is the most suitable. Alternatively, to achieve precise timing for lower BER signals,
the timed PRBS check measurement can be repeated by the host and the total
measurement time and error count is determined by summing the individual
measurements.
In timed mode, the host sets the total measurement time by setting the
CFG_PRBS_CHECK_PREDIVIDER and the CFG_PRBS_CHECK_MEAS_TIME
parameters to the required values to achieve the total measurement time required by
the application.
To perform a timed PRBS measurement, please complete the following steps:
1. Set the appropriate settings within CFG_PRBS_CHECK_PREDIVIDER and
CFG_PRBS_CHECK_MEAS_TIME to achieve the total measurement time required
by the application. The TMT (Total Measurement Time) is determined by the
following equation:
TMT = CFG_PRBS_CHECK_PREDIVIDER * (CFG_PRBS_CHECK_MEAS_TIME
*256+1) * (1/40MHz)
Note: Using the default CFG_PRBS_CHECK_PREDIVIDER setting of 0 (pre-divider
= 4) and CFG_PRBS_CHECK_MEAS_TIME setting of 3 (MEAS_TIME = 3), the TMT
(total measurement time) is ~77μs per measurement.
2. Follow the steps outlined in Figure 4-2: Timed PRBS Check Flow.
GS12341
Final Data Sheet
23 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
4.4.2 Continuous PRBS Check Measurement Procedure
As previously mentioned, the maximum measurement time for a timed PRBS error
measurement is ~3.35 seconds. For links with very low error rates, this time is insufficient
to capture an adequate number of errors. For these situations, the continuous PRBS
check measurement is more appropriate.
In continuous PRBS measurement mode, the measurement can run as long as required
(assuming the device remains locked) to ensure the BER test level is met.
To perform a continuous PRBS measurement, please follow the steps outlined in the
flowchart found within Figure 4-3: Continuous PRBS Check Flow.
Table 4-4: PRBS Checker Parameter Description
Register Address
and Name
h
Parameter Name
Description
CFG_PRBS_CHECK_PREDIVIDER
CFG_PRBS_CHECK_MEAS_TIME
Selects pre-divider for PRBS check measurement timer.
50,
Selects PRBS check measurement interval for timed
measurements.
PRBS_ CHK_CFG
Selects between timed and continuous type PRBS
measurement.
CTRL_PRBS_CHECK_TIMED_CONT_B
TRL_PRBS_CHECK_START
51,
PRBS_CHK_ CTRL
Used to start and stop PRBS measurements.
PRBS error count storage location.
89,
STAT_PRBS_CHK_ERR_CNT
PRBS_ CHK_ERR_CNT
STAT_PRBS_CHECK_STATUS
Status indication of PRBS checker.
8A,
PRBS_ CHK_STATUS
STAT_PRBS_CHECK_LAST_ABORT
Indication bit for PRBS successful completion or abort.
GS12341
Final Data Sheet
PDS-061928
24 of 109
Semtech
Proprietary & Confidential
www.semtech.com
Rev.1
August 2019
Note:
Start Timed PRBS Check Measurement
The host must not change ctrl_prbs_check_start
during a PRBS timed check except as described in
this diagram. There is no capability for the host to
abort a timed PRBS check once requested.
In particular, after setting ctrl_prbs_check_start to
1 for a timed check, the host is not permitted to
write ctrl_prbs_check_start back to 0 until the
device sets stat_prbs_check_status to 2 or 3
indicating completion or abort. Behaviour is
undefined if it does so; it would lead to race
conditions in the host <-> device handshake.
Host sets
CTRL_PRBS_CHECK_TIMED_CONT_B = 1
CTRL_PRBS_CHECK_START = 1
Device clears error count
And attempts to start PRBS
checker based on lock
condition of device
Device Sets
STAT_PRBS_CHK_ERR_CNT = 0
Loss of lock occurred during measurement
or at the beginning of measurement
initiation. Error count is invalid
Resets PRBS
checker.
STAT_PRBS_CHECK_STATUS
= 3
Host sets
CTRL_PRBS_CHECK_START = 0
YES
YES
Prepares device
for next
operation
NO
NO
Device Sets
STAT_PRBS_CHECK_STATUS =
0
STAT_PRBS_CHECK_STATUS
= 1
YES
PRBS Checker is ready for new
operation
NO
Status indicates that
timer Expired, PRBS
Timed Measurement
Complete
NO
STAT_PRBS_CHECK_STATUS
= 2
Resets PRBS
checker.
YES
Host sets
CTRL_PRBS_CHECK_START = 0
NO
STAT_PRBS_CHECK_STATUS
= 0
YES
PRBS Error Check Completed
Successfully
User reads Error count from
STAT_PRBS_CHK_ERR_CNT
Figure 4-2: Timed PRBS Check Flow
GS12341
Final Data Sheet
25 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Start Continuous PRBS Check
Measurement
Device clears error count
And attempts to start PRBS
checker based on lock
condition of device
Host sets
CTRL_PRBS_CHECK_TIMED_CONT_B = 0
CTRL_PRBS_CHECK_START = 1
Device Sets
STAT_PRBS_CHK_ERR_CNT = 0
Loss of lock occurred during
measurement or at the
beginning of measurement
initiation. Error count is invalid
Resets PRBS
checker.
STAT_PRBS_CHECK_STATUS
= 3
Host sets
CTRL_PRBS_CHECK_START = 0
YES
Prepares device
for next
operation
NO
Device Sets
STAT_PRBS_CHECK_STATUS =
0
STAT_PRBS_CHECK_STATUS
= 1
NO
YES
NO
Host may terminate PRBS
measurement at anytime
by completing this action.
PRBS Checker is ready for new
operation
Host sets
CTRL_PRBS_CHECK_START
=0
YES
YES
NO
STAT_PRBS_CHECK_STATUS
= 0
YES
STAT_PRBS_CHECK_LAST_ABORT
= 1
This step is to ensure that an error did
not occur between ending the PRBS
measurement and the last polling of
STAT_PRBS_CHECK_STATUS.
NO
PRBS Error Check Completed
Successfully
User reads Error count from
STAT_PRBS_CHK_ERR_CNT
Figure 4-3: Continuous PRBS Check Flow
GS12341
Final Data Sheet
26 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
4.5 EYE Monitor
The GS12341 includes an integrated eye monitor, which can scan the equalized signal
from the cable equalizer block. The eye monitor is capable of performing a full 128h x
256v matrix-scan or simply a 4 coordinate shape-scan of the equalized signal (See
Figure 4-4).
Note: If the eye monitor will be used during normal operation of the device (cable
equalizer mission mode), the user must ensure that the Device Power-up Sequence in
Section 4.9.12 is completed to prevent temporary signal disturbance when enabling the
eye monitor.
Figure 4-4: Full Matrix Scan (left) and 4-Point Shape Scan (right)
The eye monitor is highly configurable, and the host can configure the offset, resolution,
sample time, and error threshold parameters to control the depth and execution time of
the scan. The EYE Monitor scans the signal from the cable equalizer block. Similar to the
PRBS Checker, the eye monitor is controlled through a 4-way handshake mechanism.
The following sections outline the scan parameters and procedure to configure the eye
scan area, error threshold, and run a shape or full scan.
GS12341
Final Data Sheet
27 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
4.5.1 Shape Scan and Measurement Time
0
Max Horizontal Scan Resolution
Default
128
Vertical
Offset
Start
Vertical Offset Step = 1
Phase Step = 1
Vertical
Offset Start
Vertical
Offset Stop
Phase Start
Phase Stop
Vertical Offset Step = 2
Phase Step = 1
Default
Vertical
Offset
Stop
255
0
127
Default
Default
Phase
Start
Phase
Stop
Vertical Offset Step = 4
Phase Step = 4
Figure 4-5: Eye Scan Matrix Parameters
Figure 4-5 shows a visual representation of the scan matrix and indicates the spatial
parameters that determine the scan area and resolution. Running a scan using the
default offset and step parameters, results in 32768 (128x256) samples. The number of
samples and thus, the total scan time can be reduced to meet the needs of the
application. The scan area can be reduced by reducing the span determined by the
vertical and phase start and stop offsets, or the resolution can be reduced by increasing
the step size between adjacent samples. On the right in Figure 4-5, there are three step
settings used as examples, however there are a total of nine combinations possible. See
Table 4-6 for the register addresses and parameter names of the spatial eye scan
parameters.
For example, by increasing the vertical and phase step size to 4, the resolution is
2
reduced to (1/4) , thus reducing the number of samples down to 2048 (32768x1/16).
GS12341
Final Data Sheet
28 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
The vertical and horizontal scan information is useful when adjusting pre-emphasis and
equalization of a link. However, once this is accomplished, it may be sufficient to use the
eye scanner to only monitor jitter by setting the offsets to simply slice the eye at the
centre offset position, thus obtaining a simple 128 sample horizontal scan. A horizontal
eye can be configured to run in just over a millisecond.
In addition to the spatial parameters, the sample time, and thus the bit error rate
resolution for the eye scan can be adjusted; longer scans can detect finer bit error rates.
However, this proportionally increases the total scan time. The sample time in
microseconds is determined by a 32-bit time-out value split across two 16 bit registers.
See Table 4-6 for the register addresses and parameter names of the time-out eye scan
parameters.
For example, using the default spatial and temporal measurement scan parameters, the
scan time is approximately 6.6 seconds (32768 x 2 x 100μs). However, by changing the
vertical and horizontal step size to 4, the scan time can be reduced to 400ms
(2048x2x100μs).
The error count information can be used as is to determine the minimum inner contour
based on the measurement time. However, the basic data can be post processed to
determine things like error rate, and error threshold.
The following equations provide guidance for user post-processing:
Equation 4-1
Equation 4-2
Equation 4-3
sample1error1count
error1rate = -------------------------------------------------------------
sample1time
Contour maps can be created by defining error rate thresholds, and grouping sampled
points that fall between thresholds.
For example:
sample1time
sample1time
-----------------------------------------------------------------------
-----------------------------------------------------------------------
sample1error1threshold
error1rate1threshold11
error1rate1threshold12
Some sampling scopes provide eye maps with BER contours; similar limited BER contour
approximations can be obtained from the eye scan by using BER threshold groups.
For example:
sample1time1x1data1rate
error1rate1threshold11
sample1time1x1data1rate
error1rate1threshold12
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
sample1error1threshold
GS12341
Final Data Sheet
29 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 4-5: Spatial Scan Configuration Parameters
Register Address and Name
Parameter Name
Description
h
CTRL_EYE_PHASE_START
Horizontal phase start index
Horizontal phase stop index
Horizontal phase step size
Vertical offset start index
Vertical offset stop index
Vertical offset step size
5A, EYE_MON_ SCAN_CTRL_0
5B, EYE_MON_ SCAN_CTRL_1
5C, EYE_MON_ SCAN_CTRL_2
CTRL_EYE_PHASE_STOP
CTRL_EYE_PHASE_STEP
CTRL_EYE_VERT_OFFSET_START
CTRL_EYE_VERT_OFFSET_STOP
CTRL_EYE_VERT_OFFSET_STEP
The next section describes the implementation of the matrix-scan and shape-scan.
4.5.2 Matrix-Scan and Shape-Scan Operation
The previous section described the parameters used to adjust the spatial and temporal
eye scan settings. Each sample of the eye scan can record up to 65536 errors. A full eye
scan would require 64KB (256 x 128 x 2 Bytes) of memory to store the data of a full scan.
The eye monitor was implemented to use device resources more efficiently by
segmenting a full scan into several partial scan segments. Each partial scans segment
can contain up to 512B of scan data.
In the case of a full matrix-scan, there are 128 partial scan segments and each partial
scan segment contains two complete scan lines (2 x 128 x 2B = 512B). In the case of a
partial matrix-scan, each scan segment contains multiple partial scan lines including
partial lines (see Figure 4-6).
GS12341
Final Data Sheet
30 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
1st Partial Scan
Error Count = Max
0 <Error Count < Max
Error Count = 0
1st Partial Scan
1st
1 st
Vertical Offset Start
2nd
2nd
2nd
2nd
...
...
...
...
Last
Last
Vertical Offset Stop
128th Partial Scan
Phase Start
Phase Stop
Figure 4-6: Full Matrix Scan (left) and Partial Matrix Scan (right)
Figure 4-6 illustrates an example of an eye scan, where the sampled eye data is not
centred within the scan matrix. The eye scan data has an arbitrary centre phase relative
to the centre of the matrix which is determined when the eye monitor is powered up.
While the eye monitor remains powered, subsequent scans will maintain the same
relative phase allowing for consecutive scans to be compared for changes.
Although the scan data is not centred, a simple algorithm can be applied to the data to
shift the eye data and extract the relevant information.
In addition to the matrix-scan, the eye monitor includes a built-in function called a
shape-scan. The shape-scan returns four coordinates corresponding to the horizontal
and vertical extremes of the inner eye (Figure 4-7).
GS12341
Final Data Sheet
31 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Error Count = Max
> error count threshold
Error Count = 0
Positive Edge
(PE)
Right Edge
(RE)
Left Edge
(LE)
Negative Edge
(NE)
Figure 4-7: 4-Point Scan Coordinates Relative to the Eye
The four points obtained from the shape-scan can be used to quickly and easily
calculate the eye height and width of the signal eye. The shape-scan alone will most
likely meet the signal analysis requirements of most applications. Alternatively, the
coordinates obtained from the shape-scan can be used to optimize the bounds of a
partial matrix-scan. The four points returned from the shape-scan are determined by the
error rate threshold set by the error threshold parameter and the time-out parameters
previously discussed.
Table 4-6: Time-out Eye Scan Parameters
Register Address and Name
Parameter Name
Description
h
56, EYE_MON_ INT_CFG_2
54, EYE_MON_ INT_CFG_0
55, EYE_MON_ INT_CFG_1
CFG_EYE_BER_THRESHOLD
CFG_EYE_MON_TIMEOUT_MS
CFG_EYE_MON_TIMEOUT_LS
Number of sample errors to determine fail
MSB of measurement time in microseconds
LSB of measurement time in microseconds
This section provides a step-by-step procedure to run a matrix and shape-scan. The
shape-scan procedure is described first.
GS12341
Final Data Sheet
32 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Shape-Scan Procedure:
1. Ensure the offset and step parameters described in Table 4-5 are set to their default
values.
2. Configure the 4-point error rate threshold by setting each of the parameters listed
in Table 4-6.
3. Configure the eye monitor to run a shape-scan by setting
CTRL_EYE_SHAPE_SCAN_B to 1.
Start the scan and poll the scanner status register until the scan is complete. Please refer
to the flow diagram in Figure 4-8.
Please Note the Following:
Run Shape Scan
- While the eye monitor is
powered-up, the cable equalizer
only has partial adaptation
enabled.
Host powers up eye monitor and starts
Shape Scan by setting:
CTRL_EYE_MON_POWER_CTRL = 1
CTRL_EYE_MON_START = 1
Note: the host can write
ctrl_eye_mon_power_ctrl = 1 and
ctrl_eye_mon_start = 1 in the
same GSPI write, i.e. at the same
time. It is not necessary to set the
power up first.
- Status = STAT_EYE_MON_STATUS
Host reads scan status from
STAT_EYE_MON_STATUS
3
1 or 0
Status
2
Host determines Eye Width and Eye Height by reading from
the following 4 registers:
le = STAT_EYE_SHAPE_LEFT_EDGE_PHASE
re = STAT_EYE_SHAPE_RIGHT_EDGE_PHASE
pe =STAT_EYE_SHAPE_POS_EDGE_OFFSET
ne =STAT_EYE_SHAPE_NEG_EDGE_OFFSET
if pe > ne:
Scan Failed
Reset Eye Scanner
EyeHeight = (256 + ne - pe)
else:
EyeHeight = (ne - pe)
if le > re:
EyeWidtht = (128 + re - le)
else:
EyeWidtht = (re - le)
Host Resets Eye Scanner for new scan by
setting CTRL_EYE_MON_START = 0
Or power down by setting
CTRL_EYE_MON_POWER_CTRL = 0
NO
Status = 0?
Shape Scan
Complete
Figure 4-8: Shape-Scan Flow Diagram
GS12341
Final Data Sheet
33 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Matrix-Scan Procedure:
1. Set the bounds of the matrix-scan with the offset and step parameters described in
Table 4-5. The default value results in a full matrix-scan. Alternatively, the
shape-scan can be executed and the coordinates returned can be used to minimize
the scan time and data size of the scan.
2. Configure the 4-point error rate threshold by setting each of the parameters listed
in Table 4-6.
3. Configure the eye monitor to run a matrix-scan by setting
CTRL_EYE_SHAPE_SCAN_B to 0.
4. Start the scan and poll the scanner status register until the scan is complete. Please
refer to the flow diagram in Figure 4-9.
Read Eye Scan Buffer Procedure:
1. Host reads image size from STAT_EYE_IMAGE_SIZE.
Note: The matrix-scan is composed of multiple partial scan segments. The size (in
Bytes) of the last partial scan segment is stored in STAT_EYE_IMAGE_SIZE.
2. Host reads scan buffer data from register 0x6CC1 to (0x6CC1 + (size read from
STAT_EYE_IMAGE_SIZE)/2).
Address 0x6CC1 is the first header word corresponding to the last vertical offset
position in the matrix that was read
Address 0x6CC2 is the second header word corresponding to the image size.
This value is a copy of the image size that was read from
STAT_EYE_IMAGE_SIZE.
Address 0x6CC3 to (0x6CC1 + (size read from STAT_EYE_IMAGE_SIZE)/2) is the
eye scan data.
The image data is 2 bytes per sample point
Making reference to the Matrix shown in Figure 4-5, the eye scan data
starting at 0x6CC3 is stored in order from left to right, top to bottom, from
the last stored vertical/horizontal position in the matrix
The number of samples contained in the scan buffer is equal to (size read from
STAT_EYE_IMAGE_SIZE - 4)/2.
GS12341
Final Data Sheet
34 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Please Note the Following:
Run Scan
- While the eye monitor is powered-up,
the cable equalizer only has partial
adaptation enabled.
YES
Status = 0?
Host powers up eye monitor and starts
Matrix Scan by setting:
CTRL_EYE_MON_POWER_CTRL = 1
CTRL_EYE_MON_START = 1
- Status = STAT_EYE_MON_STATUS
Note: the host can write
- Partial = STAT_EYE_SCAN_PARTIAL_OR_FULL
ctrl_eye_mon_power_ctrl = 1 and
ctrl_eye_mon_start = 1 in the
same GSPI write, i.e. at the same
time. It is not necessary to set the
power up first.
NO
Host reads scan status from
STAT_EYE_MON_STATUS
3
1 or 0
status
2
Host preforms
Read Buffer
Scan
Host Resets Eye Scanner for
new scan by setting
CTRL_EYE_MON_START = 0
Scan Failed
Reset Eye Scanner
Eye Scan
Data
Procedure
NO
Partial = 1?
YES
Host Resets Eye Scanner for new scan by
setting CTRL_EYE_MON_START = 0
Or power down by setting
CTRL_EYE_MON_POWER_CTRL = 0
NO
Status = 0?
Full Eye Scan
Complete
Figure 4-9: Matrix-Scan Flow Diagram
GS12341
Final Data Sheet
35 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
4.6 PRBS Generator
The GS12341 includes an integrated PRBS generator which can produce a differential
PRBS7 or a divided clock signal on either output for system testing.
Note: When working with the PRBS Generator, please note the following.
•
•
•
The PRBS generator and checker can be active at the same time, however, the
generator can not be looped back on itself for error checking.
If the application requires adjustments to the default output swing, please see
Section 4.7.4.
The parameters referred to within this section are linked to their respective
registers in Table 4-7. For a complete list of registers and functions, please see
Section 5.
1. Select the PRBS generator as the source on the appropriate output:
To switch DDO0/DDO0 from data mode to PRBS generator mode, set
CTRL_OUTPUT0_SIGNAL_SEL = 1
To switch DDO1/DDO1 from data mode to PRBS generator mode, set
CTRL_OUTPUT1_SIGNAL_SEL = 1
2. The default device settings are configured to power down the device on loss of
input signal. If the PRBS generator is to be used without a valid input signal, then
the following automatic setting parameters must be disabled. This must be done to
ensure device is powered up and the outputs are active for the PRBS generator.
The following settings are required for PRBS generator on either output:
CTRL_AUTO_SLEEP = 0
CTRL_MANUAL_SLEEP = 0
The following settings are required when DDO1/DDO1 is selected as PRBS
output:
CTRL_OUTPUT1_AUTO_MUTE = 0
CTRL_OUTPUT1_MANUAL_MUTE = 0
CTRL_OUTPUT1_AUTO_DISABLE = 0
CTRL_OUTPUT1_MANUAL_DISABLE = 0
The following settings are required when DDO0/DDO0 is selected as PRBS
output:
CTRL_OUTPUT0_AUTO_MUTE = 0
CTRL_OUTPUT0_MANUAL_MUTE = 0
CTRL_OUTPUT0_AUTO_DISABLE = 0
CTRL_OUTPUT0_MANUAL_DISABLE = 0
3. Set the values within the following parameters which meet the needs of the
application:
CTRL_PRBS_GEN_SIGNAL_SELECT
CTRL_PRBS_GEN_CLK_SRC
CTRL_PRBS_GEN_DATA_RATE
GS12341
Final Data Sheet
36 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Note: If CTRL_PRBS_GEN_CLK_SRC is set to use a recovered clock, a valid
signal that the Reclocker has locked to must be present for proper operation,
and the PRBS generator will match this data rate regardless of what rate
CTRL_PRBS_GEN_DATA_RATE is set to.
CTRL_PRBS_GEN_CLK_DIVIDER
CTRL_PRBS_GEN_INVERT
4. Start the generator by setting CTRL_PRBS_GEN_ENABLE = 1.
To stop the generator at any time, set CTRL_PRBS_GEN_ENABLE = 0. If the use of the
PRBS generator is complete, revert any settings made in steps 1, 2 and/or 4 to return to
normal operation.
Table 4-7: PRBS Generator Parameter Descriptions
Register Address
and Name
h
Parameter Name
Description
CTRL_AUTO_SLEEP
Set the device to auto or manual sleep.
3, CONTROL_ SLEEP
Manually set the sleep setting of the device when auto
sleep mode is turned off.
CTRL_MANUAL_SLEEP
Selects between data or PRBS generator as the driver
source for DDO1/DDO1.
CTRL_OUTPUT1_SIGNAL_SEL
CTRL_OUTPUT0_SIGNAL_SEL
CTRL_OUTPUT1_AUTO_MUTE
CTRL_OUTPUT1_MANUAL_MUTE
CTRL_OUTPUT0_AUTO_MUTE
CTRL_OUTPUT0_MANUAL_MUTE
CTRL_OUTPUT1_AUTO_DISABLE
CTRL_OUTPUT1_MANUAL_DISABLE
CTRL_OUTPUT0_AUTO_DISABLE
CTRL_OUTPUT0_MANUAL_DISABLE
48, OUTPUT_ SIG_SELECT
Selects between data or PRBS generator as the driver
source for DDO0/DDO0.
Select automatic or manual mute control for
DDO1/DDO1.
Manually set the mute control for DDO1/DDO1 when
auto mute mode is turned off.
49, CONTROL_ OUTPUT_
MUTE
Select automatic or manual mute control for
DDO0/DDO0.
Manually set the mute control of the DDO0/DDO0 when
auto mute mode is turned off.
Selects automatic or manual disable control for
DDO1/DDO1.
Manually set the disable control of the DDO1/DDO1
when auto disable mode is turned off.
4A, CONTROL_ OUTPUT_
DISABLE
Selects automatic or manual disable control for
DDO0/DDO0.
Manually set the disable control of the DDO0/DDO0
when auto disable mode is turned off.
GS12341
Final Data Sheet
PDS-061928
37 of 109
Semtech
Proprietary & Confidential
www.semtech.com
Rev.1
August 2019
Table 4-7: PRBS Generator Parameter Descriptions (Continued)
Register Address
and Name
h
Parameter Name
Description
Selects between setting the output of the PRBS
generator to being a clock or a PRBS test signal.
CTRL_PRBS_GEN_SIGNAL_SELECT
CTRL_PRBS_GEN_CLK_SRC
CTRL_PRBS_GEN_CLK_DIVIDER
CTRL_PRBS_GEN_INVERT
Selects the clock source used by the PRBS generator.
If a clock is selected as the PRBS output signal, this
parameter sets the divide ratio of the clock.
52, PRBS_GEN_ CTRL
Allows the polarity of the PRBS signal to be inverted.
If a PRBS test signal is selected as the output signal, this
parameter sets the data rate of the PRBS7 signal.
CTRL_PRBS_GEN_DATA_RATE
CTRL_PRBS_GEN_ENABLE
Used to enable or disable the PRBS generator.
4.7 Output Drivers
The GS12341 features two independently-configurable output drivers (see Figure 3-2),
with data (reclocked or bypassed) available on both outputs. The two drivers provide
highly-configurable amplitude and pre-emphasis control. The signal on the outputs can
be inverted to help with signal polarity when layout requires trace inversion. The PRBS
generator is available on both outputs. The LOS (Loss Of Signal) status from the
equalizer stage can be used to automatically mute or disable the outputs on their
assertion. The Loss of Lock status from the Reclocker block can be used to mute the
outputs. The trace drivers can be configured to mute or disable during sleep. The sleep
control modes takes precedence over the manual or automatic LOS and Loss of Lock
output control modes.
Note: The <n> in the control parameter names refers to the output number. Output 0 is
DDO0/DDO0 and output 1 is DDO1/DDO1.
4.7.1 Bypassed Reclocker Signal Output Control
With the default power-up settings, the GS12341 outputs will automatically switch to
the bypassed signal (non-reclocked) whenever the PLL is unlocked. Alternatively,
manual reclocker bypass may be configured by setting the
CTRL_OUTPUT<n>_RETIMER_ AUTO_BYPASS and
CTRL_OUTPUT<n>_RETIMER_MANUAL_BYPASS parameters in register 0x4C to 0
b
and 1 respectively via the host interface, in which case the PLL will remain bypassed for
b
all rates.
The reclocker bypass function, manual or automatic, does not affect the input
equalization function of the device.
If both outputs are manually disabled, then the device will power down the Reclocker
block and features of the reclocker such as rate detect and lock detect will no longer be
accessible in this mode.
GS12341
Final Data Sheet
38 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
4.7.2 Output Driver Polarity Inversion
While in data mode, the signal polarity may be inverted at the outputs through the
CTRL_OUTPUT<n>_ DATA_ INVERT parameters in register 0x48. This may be useful to
compensate for an inverted upstream signal or to facilitate board signal routing. To
invert the polarity of either of the two output drivers, write 1 to control parameter
b
CTRL_OUTPUT<n>_DATA_ INVERT.
4.7.3 Output Driver Data Rate Selection
By default, the GS12341 uses the SD trace driver output group settings for all data rates,
regardless of Reclocker lock condition or data rate being applied. The following
parameters are used to control the output for all data rates in the default condition:
CFG_OUTPUT<n>_TD_SD_DRIVER_SWING
CFG_OUTPUT<n>_TD_SD_PREEMPH_WIDTH
CFG_OUTPUT<n>_TD_SD_PREEMPH_AMPL
CFG_OUTPUT<n>_TD_SD_PREEMPH_PWRDWN
If required, per-rate selection of the trace driver output group setting is possible by
setting CTRL_OUTPUT<n>_TRDR_PER_RATE = 1. Once set, the trace driver output
group will be determined by the rate to which the Reclocker is locked. For example, if
the Reclocker is locked to 12G, the following parameters will be used to control the
output drivers.
CFG_OUTPUT<n>_TD_12G_DRIVER_SWING
CFG_OUTPUT<n>_TD_12G_PREEMPH_WIDTH
CFG_OUTPUT<n>_TD_12G_PREEMPH_AMPL
CFG_OUTPUT<n>_TD_12G_PREEMPH_PWRDWN
Note: If per-rate settings are being used, when the Reclocker is not locked the trace
driver will use the 12G trace driver output group settings.
4.7.4 Amplitude and Pre-Emphasis Control
The two output drivers offer very granular amplitude and pre-emphasis control. For
optimal loss compensation, both the pre-emphasis pulse amplitude and the
pre-emphasis pulse width can be independently configured on both output drivers.
This extra flexibility provides a mechanism to better shape the pre-emphasis gain to
match the frequency loss response of interconnect composed of trace, connector and
via losses. The swing and pre-emphasis can be independently configured for specific
data rates.
CFG_OUTPUT<n>_TD_SD_DRIVER_SWING (SD)
CFG_OUTPUT<n>_TD_HD_DRIVER_SWING (HD)
CFG_OUTPUT<n>_TD_3G_DRIVER_SWING (3G)
CFG_OUTPUT<n>_TD_6G_DRIVER_SWING (6G)
CFG_OUTPUT<n>_TD_12G_DRIVER_SWING (12G)
GS12341
Final Data Sheet
39 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
The output pre-emphasis on the trace driver can be configured for the following five
rates:
CFG_OUTPUT<n>_TD_SD_PREEMPH_WIDTH (SD)
CFG_OUTPUT<n>_TD_SD_PREEMPH_AMPL (SD)
CFG_OUTPUT<n>_TD_HD_PREEMPH_WIDTH (HD)
CFG_OUTPUT<n>_TD_HD_PREEMPH_AMPL (HD)
CFG_OUTPUT<n>_TD_3G_PREEMPH_WIDTH (3G)
CFG_OUTPUT<n>_TD_3G_PREEMPH_AMPL (3G)
CFG_OUTPUT<n>_TD_6G_PREEMPH_WIDTH (6G)
CFG_OUTPUT<n>_TD_6G_PREEMPH_AMPL (6G)
CFG_OUTPUT<n>_TD_12G_PREEMPH_WIDTH (12G)
CFG_OUTPUT<n>_TD_12G_PREEMPH_AMPL (12G)
The trace driver swing can be adjusted in ≈25mV increments. The default swing value
pp
is 400mV
into an external 100Ω differential load. Although an adequate swing and
ppd
pre-emphasis can be achieved with a 1.8V output supply, for long traces where
maximum output swing and pre-emphasis range is desired, it is recommended that the
device VCC_DDO output supply pin be connected to a 2.5V supply. The default
pre-emphasis settings provide minimal insertion loss compensation.
4.7.4.1 Pre-emphasis Optimization
The goal of pre-emphasis is to open the eye at the downstream receiver as much as
possible. This means minimizing ISI jitter while meeting sufficient inner eye amplitude
to meet a receiver's input sensitivity.
The only requirement of the trace driver pre-emphasis settings is to minimize ISI
introduced by a lossy link and maximize the eye opening at the receiver. The
Pre-emphasis compensation of the GS12341 output channel is a two-step process. The
first step is to use the settings from Figure 4-10 to Figure 4-17 that best match the
insertion loss of the link in the application, while the second step is a fine optimization
procedure.
In most cases, where the downstream device has a Reclocker, first step alone may meet
the design target. However, if the downstream device is a non-reclocked buffer or
crosspoint, it may be required to further optimize the settings to minimize the jitter
thereby maximizing the system jitter budget. To do this, please see the Fine
Optimization Procedure.
In the remainder of this section the following abbreviations are used for clarity:
DS = Driver Swing
PPA = Pre-emphasis Pulse Amplitude
PPW = Pre-emphasis Pulse Width
Note: The <n> in the VCCO refers to the output power supply number. Where VCCO_1
is the power supply connection for DDO1/DDO1, and VCCO_0 is the power supply
connection for DDO0/DDO0.
GS12341
Final Data Sheet
40 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
7
6
5
5
10 15
3
5 10 15 10 15 20 10 15 20 15 20 25 15 20 25 20 25 30
PPA
4
7
8
11
12
15
PPW
Figure 4-10: Pre-emphasis settings for VCCO_<n> = 1.2V and DS = 7 (swing =
200mVpp)
4
3
10
20
15
30
PPA
PPW
Figure 4-11: Pre-emphasis settings for VCCO_<n> = 1.2V and DS = 16 (swing =
400mVpp)
12
10
8
6
5
10 15
3
5 10 15 10 15 20 10 15 20 15 20 25 15 20 25 20 25 30 35 40 45 50
PPA
4
7
8
11
12
15
PPW
Figure 4-12: Pre-emphasis settings for VCCO_<n> = 1.8V and DS = 7 (swing =
200mVpp)
8
7
6
5
4
3
2
5
15 25
3
5
15 25 10 20 30 10 20 30 15 25 35 15 25 35 20 30 40 45 50 PPA
11 12 15
4
7
8
PPW
Figure 4-13: Pre-emphasis settings for VCCO_<n> = 1.8V and DS = 16 (swing =
400mVpp)
GS12341
Final Data Sheet
41 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
3.5
3
2.5
2
1.5
10
20
30
15
40
50
PPA
PPW
Figure 4-14: Pre-emphasis settings for VCCO_<n> = 1.8V and DS = 35 (swing =
800mVpp)
13
12
11
10
9
8
7
6
5
10 15 5 10 15 10 15 20 10 15 20 15 20 25 15 20 25 20 25 30 35 40 45 50
PPA
3
4
7
8
11
12
15
PPW
Figure 4-15: Pre-emphasis settings for VCCO_<n> = 2.5V and DS = 7 (swing =
200mVpp)
8
7
6
5
4
3
5
15 25
3
5 15 25 10 20 30 10 20 30 15 25 35 15 25 35 20 30 40 45 50
PPA
4
7
8
11
12
15
PPW
Figure 4-16: Pre-emphasis settings for VCCO_<n> = 2.5V and DS = 16 (swing =
400mVpp)
3.5
3
2.5
2
1.5
40
30
15
50
10
20
PPA
PPW
Figure 4-17: Pre-emphasis settings for VCCO_<n> = 2.5V and DS = 35 (swing =
800mVpp)
GS12341
Final Data Sheet
42 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Fine Optimization Procedure:
The procedure requires access to the signal at the downstream device input, or
non-reclocked device output. If there are multiple stages between the initial
downstream device input and final measurement point, it is still possible to perform
optimization; however link settings within the other stages must be fairly optimized.
The pre-emphasis amplitude (PPA) and pre-emphasis width (PPW) settings can be
optimized by sweeping the PPA and PPW settings in increments of 'a' and 'w' and
selecting the setting which results in the lowest jitter. For the trace driver optimization,
'a' and 'w' increments of 5 should be sufficient.
The procedure has three steps.
1. Pre-emphasis Amplitude (PPA) Optimization: Set the PPA and PPW to the values
obtained from the graph selected out of Figure 4-10 to Figure 4-17, and then
measure the downstream jitter. While keeping PPW constant, increment the PPA by
'a'. If the jitter is lower after the first increment, continue to increment by 'a' until the
jitter begins increasing or a setting of 50 is reached. If there was a setting which
resulted in a lower jitter measurement than the initial setting, that is the Optimized
Pre-emphasis Amplitude setting: PPAOptimal, and the PPA optimization procedure
is complete.
However, if the jitter increased after the first increment, decrement the setting by 'a'
below the initial value. If the jitter is lower after the first decrement, continue to
decrement by 'a' until the jitter begins increasing or a setting of 0 is reached. If there
was a setting which resulted in a lower jitter measurement than the initial setting,
that is the Optimized Pre-emphasis Amplitude: PPAOptimal.
If incrementing the PPA or decrementing the PPA did not result in a setting with
lower jitter, then the initial setting obtained from the graph selected out of
Figure 4-10 to Figure 4-17 is the PPA optimized Pre-emphasis Amplitude setting:
PPA
Optimal.
2. The second step is to set the PPA to the optimized setting PPA
determined in
Optimal
step 1 and PPW to the values obtained from the graph selected out of Figure 4-10
to Figure 4-17, then measure the downstream jitter. While keeping PPA constant,
increment the PPW by 'w'. If the jitter is lower after the first increment, continue to
increment by 'w' until the jitter begins increasing or a setting of 15 is reached. If
there was a setting which resulted in a lower jitter measurement than the initial
setting, that is the Optimized Pre-emphasis Width setting: PPW
, and the
Optimal
optimization procedure is complete.
However, if the jitter increased after the first increment, decrement the setting by
'w' below the initial value. If the jitter is lower after the first decrement, continue to
decrement by 1 until the jitter begins increasing or a value of 0 is reached. If there
was a setting which resulted in a lower jitter measurement than the initial setting,
that is the Optimized Pre-emphasis Width setting: PPW
and the optimization
Optimal,
procedure is complete.
If incrementing the PPW or decrementing the PPW did not result in a setting with
lower jitter, then the initial setting value obtained from the graph selected out of
Figure 4-10 to Figure 4-17 is the optimized Pre-emphasis Width setting: PPW
.
Optimal
GS12341
Final Data Sheet
43 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
3. Pre-emphasis pulse amplitude has a direct impact on swing amplitude. The third
and final step is to readjust the driver swing until the swing amplitude design
target is met. The fine optimization procedure maybe repeated to ensure that the
PPA
and PPW
settings previously determined still hold with the new
Optimal
Optimal
DS setting.
Steps 1 and 2 are illustrated in Figure 4-18 and Figure 4-19 below.
Parameter and Variable Definition
PPAinit: Initial PPA value from equation result.
PPWinit: Initial PPW value from equation result.
DSinit: Measurement sweep Initial Driver Swing Setting = 9.
PPAoptimal: Post measurement sweep Optimal Pre-emphasis Pulse Amplitude setting.
PPWoptimal: Post measurement sweep Optimal Pre-emphasis Pulse Width setting.
a: Measurement sweep PPA increment value.
Start Optimization
n: Measurement sweep test number value.
Set
PPA: Current Measurement Pre-emphasis Pulse Amplitude setting.
PPW: Current Measurement Pre-emphasis Pulse Width setting.
DS: Current Measurement Driver Swing Amplitude setting.
PPA = PPAinit
PPW = PPWinit
DS = DSinit
Recorded
Jitter
Measurement
1, 2, 3, …, n
Measure initial Jitter
record results for
measurement# n=0
Record Data
Read Data
PPA Optimization
Complete
PPAoptimal = PPA(n-1)
no
no
If (PPA – a) > 0
yes
If (PPA + a) < 50
yes
PPA = PPA + a
n = n + 1
PPA = PPA - a
n = n + 1
Measure Jitter
record results for
measurement# n
Measure Jitter
record results for
measurement# n
If n > 1
Or
PPA – (2*a) < 0
PPA Optimization
Complete
PPAoptimal = PPA(n-1)
yes
no
no
PPA Optimization
Complete
PPAoptimal = PPA(n-1)
no
If Jitter(n) <
jitter(n-1)
Is Jitter(n) <
jitter(n-1)
PPA = PPAinit
PPW = PPWinit
yes
yes
Figure 4-18: PPA Optimization Flow Chart
GS12341
Final Data Sheet
44 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Parameter and Variable Definition
PPWinit: Initial PPW value from equation result.
DSinit: Measurement sweep Initial Driver Swing Setting = 9.
PPAoptimal: Post measurement sweep Optimal Pre-emphasis Pulse Amplitude setting.
PPWoptimal: Post measurement sweep Optimal Pre-emphasis Pulse Width setting.
w: Measurement sweep PPW increment value.
Start Optimization
n: Measurement sweep test number value.
Set
PPA: Current Measurement Pre-emphasis Pulse Amplitude setting.
PPW: Current Measurement Pre-emphasis Pulse Width setting.
DS: Current Measurement Driver Swing Amplitude setting.
PPA = PPAoptimal
PPW = PPWinit
DS = DSinit
Recorded
Jitter
Measurement
1, 2, 3, …, n
Measure initial Jitter
record results for
measurement# n = 0
Record Data
Read Data
PPW Optimization
Complete
PPWoptimal = PPW(n-1)
no
no
If (PPW + w) <
16
If (PPW – w) > 0
yes
yes
PPW = PPW + w
n = n + 1
PPW = PPW - w
n = n + 1
Measure Jitter
record results for
measurement# n
Measure Jitter
record results for
measurement# n
If n > 1
Or
PPW – (2*w) < 0
PPW Optimization
Complete
PPWoptimal = PPW(n-1)
yes
no
no
PPW Optimization
Complete
PPWoptimal = PPW(n-1)
no
If Jitter(n) <
jitter(n-1)
Is Jitter(n) <
jitter(n-1)
PPW = PPWinit
yes
yes
Figure 4-19: PPW Optimization Flow Chart
GS12341
Final Data Sheet
45 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 4-8: Output Swing and Pre-Emphasis Control Parameters
Register Address
and Name
h
Parameter Name
Description
2B/29
OUTPUT_ PARAM_TD_
SD_3/
OUTPUT_ PARAM_TD_
SD_1
Output amplitude configuration parameter for SD or all rates* on
DDO0 and DDO1, where <n> is the output number.
CFG_OUTPUT<n>_TD_SD_
DRIVER_SWING
Note: If CTRL_OUTPUT<n>_TRDR_PER_RATE = 0, this setting will
be used for all data rates.
Output pre-emphasis pulse width configuration parameter for
SD or all rates* on DDO0 and DDO1, where <n> is the output
number.
CFG_OUTPUT<n>_TD_
SD_PREEMPH_WIDTH
Note: If CTRL_OUTPUT<n>_TRDR_PER_RATE = 0, this setting will
be used for all data rates.
2A/28
OUTPUT_ PARAM_TD_
SD_2/
OUTPUT_ PARAM_TD_
SD_0
Output pre-emphasis power down configuration parameter for
SD or all rates* on DDO0 and DDO1, where <n> is the output
number.
CFG_OUTPUT<n>_TD_
SD_PREEMPH_PWRDWN
Note: If CTRL_OUTPUT<n>_TRDR_PER_RATE = 0, this setting will
be used for all data rates.
Output amplitude configuration parameter for SD or all rates* on
DDO0 and DDO1, where <n> is the output number.
CFG_OUTPUT<n>_TD_
SD_PREEMPH_AMPL
Note: If CTRL_OUTPUT<n>_TRDR_PER_RATE = 0, this setting will
be used for all data rates.
2D/2F
OUTPUT_ PARAM_
TD_HD_1/
OUTPUT_ PARAM_TD_
HD_3
Output amplitude configuration parameter for HD on DDO0 and
DDO1, where <n> is the output number.
CFG_OUTPUT<n>_TD_
HD_DRIVER_SWING
CFG_OUTPUT<n>_TD_
HD_PREEMPH_WIDTH
Output pre-emphasis pulse width configuration parameter for
HD on DDO0 and DDO1, where <n> is the output number.
2C/2E
OUTPUT_ PARAM_TD_
HD_0/
OUTPUT_ PARAM_TD_
HD_2
CFG_OUTPUT<n>_TD_
HD_PREEMPH_PWRDWN
Output pre-emphasis power down configuration parameter for
HD on DDO0 and DDO1, where <n> is the output number.
CFG_OUTPUT<n>_TD_
HD_PREEMPH_AMPL
Output pre-emphasis pulse amplitude configuration parameter
for HD on DDO0 and DDO1, where <n> is the output number.
31/33
OUTPUT_ PARAM_
TD_3G_1/
OUTPUT_ PARAM_
TD_3G_3
CFG_OUTPUT<n>_TD_
3G_DRIVER_SWING
Output amplitude configuration parameter for 3G on DDO0 and
DDO1, where <n> is the output number.
CFG_OUTPUT<n>_TD_
3G_PREEMPH_WIDTH
Output pre-emphasis pulse width configuration parameter for
3G on DDO0 and DDO1, where <n> is the output number.
30/32
OUTPUT_ PARAM_
TD_3G_0/
OUTPUT_ PARAM_
TD_3G_2
CFG_OUTPUT<n>_TD_
3G_PREEMPH_PWRDWN
Output pre-emphasis power down configuration parameter for
3G on DDO0 and DDO1, where <n> is the output number.
CFG_OUTPUT<n>_TD_
3G_PREEMPH_AMPL
Output pre-emphasis pulse amplitude configuration parameter
for 3G on DDO0 and DDO1, where <n> is the output number.
GS12341
Final Data Sheet
PDS-061928
46 of 109
Semtech
Proprietary & Confidential
www.semtech.com
Rev.1
August 2019
Table 4-8: Output Swing and Pre-Emphasis Control Parameters (Continued)
Register Address
and Name
h
Parameter Name
Description
35/37
OUTPUT_ PARAM_
TD_6G_1/
OUTPUT_ PARAM_
TD_6G_3
Output amplitude configuration parameter for 6G on DDO0 and
DDO1, where <n> is the output number.
CFG_OUTPUT<n>_TD_6G_
DRIVER_SWING
CFG_OUTPUT<n>_TD_6G_
PREEMPH_WIDTH
Output pre-emphasis pulse width configuration parameter for
6G on DDO0 and DDO1, where <n> is the output number.
34/36
OUTPUT_ PARAM_
TD_6G_0/
OUTPUT_ PARAM_
TD_6G_2
CFG_OUTPUT<n>_TD_6G_
PREEMPH_PWRDWN
Output pre-emphasis power down configuration parameter for
6G on DDO0 and DDO1, where <n> is the output number.
CFG_OUTPUT<n>_TD_6G_
PREEMPH_AMPL
Output pre-emphasis pulse amplitude configuration parameter
for 6G on DDO0 and DDO1, where <n> is the output number.
39/3B
OUTPUT_ PARAM_
TD_12G_1/
OUTPUT_ PARAM_
TD_12G_3
CFG_OUTPUT<n>_TD_12G_
DRIVER_SWING
Output amplitude configuration parameter for 12G on DDO0
and DDO1, where <n> is the output number.
CFG_OUTPUT<n>_TD_12G_
PREEMPH_WIDTH
Output pre-emphasis pulse width configuration parameter for
12G on DDO0 and DDO1, where <n> is the output number.
38/3A
OUTPUT_ PARAM_
TD_12G_0/
OUTPUT_ PARAM_
TD_12G_2
CFG_OUTPUT<n>_TD_12G_
PREEMPH_PWRDWN
Output pre-emphasis power down configuration parameter for
12G on DDO0 and DDO1, where <n> is the output number.
CFG_OUTPUT<n>_TD_12G_
PREEMPH_AMPL
Output pre-emphasis pulse amplitude configuration parameter
for 12G on DDO0 and DDO1, where <n> is the output number.
4.7.5 Trace Driver DC coupling requirements
Table 4-9 lists the required V (Driver Supply voltage) and DS (Driver Swing) required
cco
to achieve three common nominal VDDO
(peak-to-peak differential output voltages)
ppd
and their associated nominal V
(output common mode voltage).
cmout
In the DC-coupled case, where V is connected to the same supply as the input buffer
cco
supply voltage of the downstream device, V
in Table 4-9 is the common mode
cmount
voltage at the output of the GS12341 driver. For short low loss transmission lines, this
will also be the common mode voltage created at the input termination of the
downstream input buffer. However, for long and lossy transmission lines, the amplitude
will be attenuated at the downstream receiver and therefore the common mode
voltage created at the input termination will be higher and must be measured or
simulated for accuracy. For proper link operation, the common mode voltage created at
the input termination of the downstream input buffer must be within the V
specified by that device.
range
cmin
GS12341
Final Data Sheet
47 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
In the AC-coupled case, V
is the common mode voltage at the driver side of the
cmout
AC-coupling capacitor placed near the driver. In the AC-coupled case, V
does not
cmout
need to be within the V
range specified by the downstream device. However, the
cmin
capacitor should have a voltage rating that exceeds |V
-V
|. In addition to the
cmout cmin
voltage rating, the recommended value of the AC-coupling capacitor should be at least
4.7ꢁF to meet the low cut-off frequency requirement of low transition density signals
such as the check-field pattern defined in SMPTE RP-198. The capacitor should have a
temperature rating that maintains the capacitance over the required operating range.
Table 4-9: ΔV
(mV ) and V
(V) vs. DS Setting and V
CCO
DDO
ppd
CMOUT
DC-Coupled
AC-Coupled
(V) vs. DS Setting
ΔV
(mV ) vs. DS Setting
DDO
ppd
V
(V) vs. DS Setting
V
CMOUT
CMOUT
V
(V)
8
17
37
8
17
37
8
17
37
cco
1.2
200
400
400
400
—
1.15
1.75
2.45
1.1
1.7
2.4
—
1.6
2.3
1.1
1.7
2.4
1
—
1.4
2.1
1.8
2.5
200
200
800
800
1.6
2.3
4.7.6 Output State Control Modes
The GS12341 provides several output state control modes to meet specific application
requirements. The trace driver has the following three output modes: operational,
muted, or disabled. During non-sleep, if the control modes are configured such that
multiple output modes are enabled, the priorities of the control modes from highest to
lowest are the following: disabled, and then muted. Section 4.7.6.1 through
Section 4.7.6.2 describe how to configure the output control modes that are enabled
during non-sleep.
If the device enters sleep, either manually or automatically, the sleep output control
modes take precedence over the non-sleep control modes. The default trace driver
configuration is for it to be disabled during sleep; however the trace driver can be
configured to mute during sleep by setting the CFG_SLEEP_OUTPUT<n>_MUTE
parameter in register 0x5 to 1 .
b
GS12341
Final Data Sheet
48 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
4.7.6.1 Output Mute Control Mode
Each of the outputs on the GS12341 have independent mute control modes, which can
be configured through the host interface.
The following are the four output mute control modes:
1. The outputs automatically mute on LOS (default).
2. The outputs automatically mute on LOS and during rate search.
3. The outputs never mute.
4. The outputs are always muted.
The first mute control mode is the default power-up configuration for both output
drivers (the CTRL_OUTPUT<n>_AUTO_MUTE control parameter in register 0x49 is set
to 1b). In this mode, the outputs will automatically mute on the assertion of LOS. This
includes LOS as a result of setting up Squelch Adjust (see Section 4.2.1 for more details).
In addition to mute on LOS, with auto mute control mode configured, setting the
CTRL_OUTPUT<n>_AUTO_MUTE_DURING_RATE_SEARCH control parameter in
register 0x49 to 1 , will configure the outputs to also mute when the device loses lock
b
and begins to rate search.
The outputs can be manually configured to never mute by setting both the
CTRL_OUTPUT<n>_AUTO_MUTE and CTRL_OUTPUT<n>_MANUAL_MUTE control
parameters in register 0x49 to 0 . Alternatively, the outputs can be manually configured
b
to always be muted by setting the CTRL_OUTPUT<n>_AUTO_MUTE and
CTRL_OUTPUT<n>_ MANUAL_MUTE control parameters to 0 and 1 respectively.
b
b
4.7.6.2 Output Disable Control Mode
Each of the outputs on the GS12341 also have independent disable control modes,
which can be configured through the host interface.
The following are the three output disable control modes:
1. The outputs are never disabled (default).
2. The outputs are automatically disabled on LOS.
3. The outputs are always disabled.
The first disable control mode is the default power-up configuration for both output
drivers (the CTRL_OUTPUT<n>_AUTO_DISABLE and
CTRL_OUTPUT<n>_MANUAL_DISABLE control parameters in register 0x4A are both
set to 0 ). In this mode, the outputs will never disable. By setting the
b
CTRL_OUTPUT<n>_AUTO_DISABLE control parameter in register 0x4A to 1 , the
b
outputs will automatically disable on the assertion of LOS. This includes LOS as a result
of setting up Squelch Adjust (see Section 4.2.1 for more details).
The output can be manually disabled by leaving the
CTRL_OUTPUT<n>_AUTO_DISABLE control parameter set to 0 and setting the
b
CTRL_OUTPUT<n>_MANUAL_DISABLE control parameter to 1 .
b
The disable control mode takes precedence over the output mute control mode.
GS12341
Final Data Sheet
49 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
4.8 GPIO Controls
There are four configurable GPIO pins which can independently be configured as inputs
or outputs. Each GPIO has a default function which can be re-configured through the
host interface.
If there is a conflict between the internal register configuration of a given device
function and the logic-level applied to a GPIO pin that is configured to control that same
device function, the GPIO logic-level takes precedence over the internal register
configuration. The logic HIGH and LOW levels of the GPIO[3:0] pin to which LOS is
connected are specified by the EIA/JESD8-5A standard for 1.8V operation.
For a list of available functions and configuration details of GPIO[3:0], please refer to the
GPIO Configuration registers in Section 5.
4.9 GSPI Host Interface
The GS12341 is configured via the Gennum Serial Peripheral Interface (GSPI).
The GSPI host interface is comprised of a serial data input signal (SDIN pin), serial data
output signal (SDOUT pin), an active-low chip select (CS pin) and a burst clock (SCLK pin).
The GS12341 is a slave device, so the SCLK, SDIN and CS signals must be sourced by the
application host processor.
All read and write access to the device is initiated and terminated by the application
host processor.
4.9.1 CS Pin
The Chip Select pin (CS) is an active-LOW signal provided by the host processor to the
GS12341.
The HIGH-to-LOW transition of this pin marks the start of serial communication to the
GS12341.
The LOW-to-HIGH transition of this pin marks the end of serial communication to the
GS12341.
Each device may use its own separate Chip Select signal from the host processor or up
to 32 devices may be connected to a single Chip Select when making use of the Unit
Address feature.
Only those devices whose Unit Address matches the UNIT ADDRESS in GSPI Command
Word 1 will respond to communication from the host processor (unless the B’CAST ALL
bit in GSPI Command Word 1 is set to 1).
4.9.2 SDIN Pin
The SDIN pin is the GSPI serial data input pin of the GS12341.
The 32-bit Command and 16-bit Data Words from the host processor or from the SDOUT
pin of other devices are shifted into the device on the rising edge of SCLK when the CS
pin is LOW.
GS12341
Final Data Sheet
50 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
4.9.3 SDOUT Pin
The SDOUT pin is the GSPI serial data output of the GS12341.
All data transfers out of the GS12341 to the host processor or to the SDIN pin of other
connected devices occur from this pin.
By default at power up or after system reset, the SDOUT pin provides a non-clocked path
directly from the SDIN pin, regardless of the CS pin state, except during the GSPI Data
Word portion for read operations from the device. This allows multiple devices to be
connected in Loop-Through configuration.
For read operations, the SDOUT pin is used to output data read from an internal
Configuration and Status Register (CSR) when CS is LOW. Data is shifted out of the
device on the falling edge of SCLK, so that it can be read by the host processor or other
downstream connected device on the subsequent SCLK rising edge.
4.9.3.1 GSPI Link Disable Operation
It is possible to disable the direct SDIN to SDOUT (Loop-Through) connection by writing
a value of 1 to the GSPI_LINK_DISABLE bit in CONTROL_REG. When disabled, any data
appearing at the SDIN pin will not appear at the SDOUT pin and the SDOUT pin is HIGH.
Note: Disabling the Loop-Through operation is temporarily required when initializing
the Unit Address for up to 32 connected devices.
The time required to enable/disable the Loop-Through operation from assertion of the
register bit is less than the GSPI configuration command delay as defined by the
parameter t
(4 SCLK cycles).
cmd_GSPI_config
Table 4-10: GSPI_LINK_DISABLE Bit Operation
Bit State
Description
0
1
SDIN pin is looped through to the SDOUT pin
Data appearing at SDIN does not appear at SDOUT, and SDOUT pin is HIGH.
SDIN pin
Configuration and
Status Register
SDOUT pin
GSPI_LINK
_DISABLE
High-Z
BUS_THROUGH_
ENABLE
CS pin
Figure 4-20: GSPI_LINK_DISABLE Operation
GS12341
Final Data Sheet
51 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
4.9.3.2 GSPI Bus-Through Operation
Using GSPI Bus-Through operation, the GS12341 can share a common PCB trace with
other GSPI devices for SDOUT output.
When configured for Bus-Through operation, by setting GSPI_BUS_THROUGH_ENABLE
bit to 1, the SDOUT pin will be high-impedance when the CS pin is HIGH.
When the CS pin is LOW, the SDOUT pin will be driven and will follow regular read and
write operation as described in Section 4.9.3.
Multiple chains of GS12341 devices can share a single SDOUT bus connection to host by
configuring the devices for Bus-Through operation. In such configuration, each chain
requires a separate Chip Select (CS).
SDIN pin
Configuration and
Status Register
SDOUT pin
GSPI_LINK
_DISABLE
High-Z
BUS_THROUGH_
ENABLE
CS pin
Figure 4-21: GSPI_BUS_THROUGH_ENABLE Operation
4.9.4 SCLK Pin
The SCLK pin is the GSPI serial data shift clock input to the device, and must be provided
by the host processor.
Serial data is clocked into the GS12341 SDIN pin on the rising edge of SCLK. Serial data
is clocked out of the device from the SDOUT pin on the falling edge of SCLK (read
operation). SCLK is ignored when CS is HIGH.
The maximum interface clock rate is 27MHz.
4.9.5 Command Word 1 Description
All GSPI accesses are a minimum of 48 bits in length (two 16-bit Command Words
followed by a 16-bit Data Word) and the start of each access is indicated by the
HIGH-to-LOW transition of the chip select (CS) pin of the GS12341.
The format of the Command Words and Data Word are shown in Figure 4-22.
Data received immediately following this HIGH-to-LOW transition will be interpreted as
a new Command Word.
GS12341
Final Data Sheet
52 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
4.9.5.1 R/W bit—B15 Command Word 1
This bit indicates a read or write operation.
When R/W is set to 1, a read operation is indicated, and data is read from the register
specified by the ADDRESS field of the Command Word.
When R/W is set to 0, a write operation is indicated, and data is written to the register
specified by the ADDRESS field of the Command Word.
4.9.5.2 B'CAST ALL—B14 Command Word 1
This bit is used in write operations to configure all devices connected in Loop-Through
and Bus-Through configuration with a single command.
When B’CAST ALL is set to 1, the following Data Word (AUTOINC = 0) or Data Words
(AUTOINC = 1) are written to the register specified by the ADDRESS field of the
Command Words (and subsequent addresses when AUTOINC = 1), regardless of the
setting of the UNIT ADDRESS(es).
When B’CAST ALL is set to 0, a normal write operation is indicated. Only those devices
that have a Unit Address matching the UNIT ADDRESS field of Command Word 1 write
the Data Word to the register specified by the ADDRESS field of the Command Words.
4.9.5.3 EMEM—B13 Command Word 1
The EMEM bit must be set to 1 in Command Word 1. When EMEM is set to 1, a 23-bit
address split between Command Word 1 and Command Word 2 is used to access the
registers in this device.
4.9.5.4 AUTOINC—B12 Command Word 1
When AUTOINC is set to 1, Auto-Increment read or write access is enabled.
In Auto-Increment Mode, the device automatically increments the register address for
each contiguous read or write access, starting from the address defined in the ADDRESS
field of the Command Word.
The internal address is incremented for each 16-bit read or write access until a
LOW-to-HIGH transition on the CS pin is detected.
When AUTOINC is set to 0, single read or write access is required.
Auto-Increment write must not be used to update values in CONTROL_REG.
4.9.5.5 UNIT ADDRESS—B11:B7 Command Word 1
The 5 bits of the UNIT ADDRESS field of the Command Word are used to select one of 32
devices connected on a single chip select in Loop-Through or Bus-Through
configurations.
Read and write accesses are only accepted if the UNIT ADDRESS field matches the
programmed DEV_UNIT_ADDRESS in CONTROL_REG.
By default at power-up or after a device reset, the DEV_UNIT_ADDRESS is set to 00 .
h
GS12341
Final Data Sheet
53 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
4.9.5.6 ADDRESS—B6:B0 Command Word 1 and B15:B0 Command Word 2
The Command and Data Word formats are shown in Figure 4-22 and Figure 4-23. As an
example of the command word structure, reading register 0x90 from a device with unit
address 3, that has AUTOINC = 0, and B’CAST ALL = 0 would be structured as follows:
•
•
Command word 1: 1010 0001 1000 0000 (0xA180)
Command word 2: 0000 0000 1001 0000 (0x90)
Command Words
MSB
LSB
UNIT ADDRESS
ADDRESS[22:16]
A19
B’CAST
ALL
EMEM
A13
AUTOINC
A12
UA4
A11
UA3
A10
UA2
A9
UA1
UA0
A22
A6
A21
A5
A20
A4
A18
A2
A17
A1
A16
R / W
ADDRESS[15:0]
A8 A7
A15
A14
A3
D3
A0
D0
Data Word
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D2
D1
Figure 4-22: Command and Data Word Format
Command Word 1
MSB
R / W
LSB
UNIT ADDRESS
UA2
ADDRESS[22:16]
A19
B’CAST
ALL
EMEM
AUTOINC
UA4
UA3
UA1
UA0
A22
A21
A20
A18
A17
A16
23-bit CSR address field.
5-bit UNIT ADDRESS field providing up to
32 devices to be connected on a single CS.
Auto increment read/write access when set.
Single read write access when reset.
Extended memory mode. When set, the extended memory mode is
enabled. When reset, normal GSPI addressing is enabled.
When set, the UNIT ADDRESS field is ignored and
all data accesses are actioned by the device.
When reset, the Unit Address is used to
manage data accesses in the device.
Read access when this bit is set.
Write access when this bit is reset.
Command Word 2
ADDRESS[15:0]
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Figure 4-23: Command Word 1 and Command Word 2 Details
Note: Please see Section 4.9.5.6 ADDRESS—B6:B0 Command Word 1 and B15:B0
Command Word 2 for an example of the command word structure.
GS12341
Final Data Sheet
54 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
4.9.6 GSPI Transaction Timing
tcmd_GSPI_config
tcmd
t9
SCLK
CS
X
X
SDIN
SDOUT
t0
t1
t2
t4
t7
SCLK
CSb
t3
t8
R/W
BCST
EMEM
Auto_Inc
UA4
UA3
UA2
UA1
UA0
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDIN
SDOUT
R/W
BCST
EMEM
Auto_Inc
UA4
UA3
UA2
UA1
UA0
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D
12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDIN signal is looped out on SDOUT
Write Mode
t5
t9
SCLK
CSb
t6
R/W
RSV
EMEM
Auto_Inc
UA4
UA3
UA2
UA1
UA0
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
SDIN
SDOUT
R/W
RSV
EMEM
Auto_Inc
UA4
UA3
UA2
UA1
UA0
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Read Data is output on SDOUT
SDIN signal is looped out on SDOUT
Read Mode
Figure 4-24: GSPI External Interface Timing
GS12341
Final Data Sheet
55 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 4-11: GSPI Timing Parameters
Equivalent
SCLK
Parameter
Symbol
Min
Typ
Max
Units
Cycles
SCLK Frequency
—
t0
—
—
—
—
—
1
—
1.7
—
—
—
50
—
—
—
—
27
—
—
60
—
—
—
—
MHz
ns
CS LOW Before SCLK Rising Edge
SCLK Period
t1
t2
37
ns
SCLK Duty Cycle
40
ꢀ
t3
Input Data Setup Time
SCLK Idle Time – Write
SCLK Idle Time – Read
Inter–Command Delay Time
2.3
ns
t4
1/SCLK
138
115
ns
t5
—
3
ns
tcmd
ns
Inter–Command Delay Time (after
GSPI configuration write)
1
4
139
1.3
0
—
—
—
—
6.4
—
ns
ns
ns
tcmd_GSPI_conf
t6
t7
SDOUT After SCLK Falling Edge
—
—
CS HIGH After Final SCLK Falling
Edge
t8
t9
Input Data Hold Time
CS HIGH Time
—
—
1.2
58
—
—
—
—
ns
ns
SDIN to SDOUT Combinatorial
Delay
—
—
—
—
—
—
—
—
3.4
ns
# of
Max chips daisy-chained at max
SCLK frequency (26 MHz)
When host clocks in SDOUT
data on falling edge of SCLK
compatible
Semtech
devices
8
Max frequency for 32
daisy-chained devices
When host clocks in SDOUT
data on falling edge of SCLK
7.5
MHz
Note:
1. tcmd_GSPI_conf inter-command delay must be used whenever modifying CONTROL_REG register at address 0x00.
4.9.7 Single Read/Write Access
Single read/write access timing for the GSPI interface is shown in Figure 4-25 to
Figure 4-29.
When performing a single read or write access, one Data Word is read from/written to
the device per access. Each access is a minimum of 48-bits long, consisting of two
Command Words and a single Data Word. The read or write cycle begins with a
HIGH-to-LOW transition of the CS pin. The read or write access is terminated by a
LOW-to-HIGH transition of the CS pin.
GS12341
Final Data Sheet
PDS-061928
56 of 109
Semtech
Proprietary & Confidential
www.semtech.com
Rev.1
August 2019
The maximum interface clock rate is 27MHz and the inter-command delay time
indicated in the figures as t , is a minimum of 3 SCLK clock cycles. After modifying
cmd
values in CONTROL_REG, the inter-command delay time, t
, is a minimum
cmd_GSPI_config
of 4 SCLK clock cycles.
For read access, the time from the last bit of Command Word 2 to the start of the data
output, as defined by t , corresponds to no less than 4 SCLK clock cycles at 27MHz.
5
t
cmd
SCLK
CS
COMMAND WORD 1
COMMAND WORD 1
COMMAND WORD 2
COMMAND WORD 2
DATA WORD
DATA WORD
X
X
COMMAND WORD 1
COMMAND WORD 1
SDIN
SDOUT
Figure 4-25: GSPI Write Timing—Single Write Access with Loop-Through Operation (default)
t
cmd
SCLK
CS
SDIN
COMMAND WORD 2
COMMAND WORD 1
DATA WORD
X
COMMAND WORD 1
SDOUT
Figure 4-26: GSPI Write Timing—Single Write Access with GSPI Link-Disable Operation
t
cmd
SCLK
CS
COMMAND WORD 2
COMMAND WORD 2
COMMAND WORD 1
COMMAND WORD 1
DATA WORD
DATA WORD
X
High-z
COMMAND WORD 1
COMMAND WORD 1
SDIN
High-Z
SDOUT
Figure 4-27: GSPI Write Timing—Single Write Access with Bus-Through Operation
SCLK
t
5
CS
COMMAND WORD 1
COMMAND WORD 1
COMMAND WORD 2
COMMAND WORD 2
SDIN
DATA WORD
SDOUT
Figure 4-28: GSPI Read Timing—Single Read Access with Loop-Through Operation (default)
SCLK
t
5
CS
SDIN
COMMAND WORD
COMMAND WORD
1
1
COMMAND WORD
COMMAND WORD
2
2
High-z
X
DATA WORD
SDOUT
Figure 4-29: GSPI Read Timing—Single Read Access with Bus-Through Operation
GS12341
Final Data Sheet
57 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
4.9.8 Auto-increment Read/Write Access
Auto-increment read/write access timing for the GSPI interface is shown in Figure 4-30
to Figure 4-34.
Auto-increment mode is enabled by the setting the AUTOINC bit of Command Word 1.
In this mode, multiple Data Words can be read from/written to the device using only one
starting address. Each access is initiated by a HIGH-to-LOW transition of the CS pin, and
consists of two Command Words and one or more Data Words. The internal address is
automatically incremented after the first read or write Data Word, and continues to
increment until the read or write access is terminated by a LOW-to-HIGH transition of
the CS pin.
Note: Writing to CONTROL_REG using Auto-increment access is not allowed.
The maximum interface clock rate is 27MHz and the inter-command delay time
indicated in the diagram as t , is a minimum of 3 SCLK clock cycles.
cmd
For read access, the time from the last bit of the second Command Word to the start of
the data output of the first Data Word as defined by t will be no less than 4 SCLK cycles
5
at 27MHz. All subsequent read data accesses will not be subject to this delay during an
Auto-Increment read.
SCLK
CS
SDIN
COMMAND WORD 1
COMMAND WORD 1
COMMAND WORD 2
COMMAND WORD 2
DATA 1
DATA 1
DATA 2
DATA 2
SDOUT
Figure 4-30: GSPI Write Timing—Auto-Increment with Loop-Through Operation (default)
SCLK
CS
COMMAND WORD 1
COMMAND WORD 2
DATA 1
DATA 2
SDIN
SDOUT
Figure 4-31: GSPI Write Timing—Auto-Increment with GSPI Link Disable
Operation
SCLK
CS
SDIN
COMMAND WORD 2
COMMAND WORD 2
COMMAND WORD 1
COMMAND WORD 1
DATA 1
DATA 1
DATA 2
DATA 2
High-Z
SDOUT
Figure 4-32: GSPI Write Timing—Auto-Increment with Bus-Through Operation
SCLK
t
5
CS
SDIN
COMMAND WORD 1
COMMAND WORD 1
COMMAND WORD 2
COMMAND WORD 2
SDOUT
DATA 1
DATA 2
Figure 4-33: GSPI Read Timing—Auto-Increment Read with Loop-Through Operation (default)
GS12341
Final Data Sheet
58 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
SCLK
CS
t
5
SDIN
COMMAND WORD 1
COMMAND WORD 1
COMMAND WORD 2
COMMAND WORD 2
High-z
SDOUT
X
DATA 1
DATA 2
Figure 4-34: GSPI Read Timing—Auto-Increment Read with Bus-through Operation
4.9.9 Setting a Device Unit Address
Multiple (up to 32) GS12341 devices can be connected to a common Chip Select (CS) in
Loop-Through or Bus-Through operation.
To ensure that each device selected by a common CS can be separately addressed, a
unique Unit Address must be programmed by the host processor at start-up as part of
system initialization or following a device reset.
Note: By default at power up or after a device reset, the DEV_UNIT_ADDRESS of each
device is set to 0 and the SDINSDOUT non-clocked loop-through for each device is
h
enabled.
These are the steps required to set the DEV_UNIT_ADDRESS of devices in a chain to
values other than 0:
1. Write to Unit Address 0 selecting CONTROL_REG (ADDRESS = 0), with the
GSPI_LINK_DISABLE bit set to 1 and the DEV_UNIT_ADDRESS field set to 0. This
disables the direct SDINSDOUT non-clocked path for all devices on chip select.
2. Write to Unit Address 0 selecting CONTROL_REG (ADDRESS = 0), with the
GSPI_LINK_DISABLE bit set to 0 and the DEV_UNIT_ADDRESS field set to a
unique Unit Address. This configures DEV_UNIT_ADDRESS for the first device in
the chain. Each subsequent such write to Unit Address 0 will configure the next
device in the chain. If there are 32 devices in a chain, the last (32nd) device in the
chain must use DEV_UNIT_ADDRESS value 0.
3. Repeat step 2 using new, unique values for the DEV_UNIT_ADDRESS field in
CONTROL_REG until all devices in the chain have been configured with their own
unique Unit Address value.
Note: t
delay must be observed after every write that modifies
cmd_GSPI_conf
CONTROL_REG.
All connected devices receive this command (by default the Unit Address of all devices
is 0), and the Loop-Through operation will be re-established for all connected devices.
Once configured, each device will only respond to Command Words with a
UNIT ADDRESS field matching the DEV_UNIT_ADDRESS in CONTROL_REG.
Note: Although the Loop-Through and Bus-Through configurations are compatible
with previous generation GSPI enabled devices (backward compatibility), only devices
supporting Unit Addressing can share a chip select. All devices on any single chip select
must be connected in a contiguous chain with only the last device's SDOUT connected
to the application host processor. Multiple chains configured in Bus-Through mode can
have their final SDOUT outputs connected to a single application host processor input.
GS12341
Final Data Sheet
59 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
4.9.10 Default GSPI Operation
By default at power up or after a device reset, the GS12341 is set for Loop-Through
Operation and the internal DEV_UNIT_ADDRESS field of the device is set to 0.
Figure 4-35 shows a functional block diagram of the Configuration and Status Register
(CSR) map in the GS12341.
At power-up or after a device reset, DEV_UNIT_ADDRESS = 00h
[15]
R/W
[14]
[13]
[12]
[11:7]
[6:0]
bits
BCAST
ALL
Auto
Inc
Unit Address
32 devices
Register Address
Upper 7 bits
EMEM
COMMAND 1
[15:0]
bits
COMMAND 2
Lower 16 bits of Register Address
[15:0]
bits
Compare
DATA
Data to be written / Read Data
[4:0]
[15]
[14]
[12:5]
bits
[13]
Read/Write
GSPI_BUS_
THROUGH
_ENABLE
GSPI_LINK
_DISABLE
Reg 0
RESERVED
DEV_UNIT_ADDRESS
RESERVED
Configuration and Status Registers
Figure 4-35: Internal Register Map Functional Block Diagram
The steps required for the application host processor to write to the Configuration and
Status Registers via the GSPI, are as follows:
1. Set Command Word 1 for write access (R/W = 0); set Auto Increment; set the Unit
Address field in the Command Word 1 to match the configured
DEV_UNIT_ADDRESS which will be zero after power-up. Set the Register Address
bits in Command Word 1 to match the upper 7 bits of the register address to be
accessed. Set the bits in Command Word 2 to match the lower 16 bits of the register
address to be accessed. Write Command Word 1 and Command Word 2.
2. Write the Data Word to be written to the first register.
3. Write the Data Word to be written to the next register in Auto Increment mode, etc.
Read access is the same as the above with the exception of step 1, where the Command
Word 1 is set for read access (R/W = 1).
Note: The UNIT ADDRESS field of Command Word 1 must always match
DEV_UNIT_ADDRESS for an access to be accepted by the device. Changing
DEV_UNIT_ADDRESS to a value other than 0 is only required if multiple devices are
connected to a single chip select (in Loop-Through or Bus-Through configuration).
GS12341
Final Data Sheet
60 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
4.9.11 Clear Sticky Counts Through Four Way Handshake
There are four sticky counters that keep count of changes in status of primary and
secondary carrier detect, rate changes, and lock changes. The counters can be read from
the following four parameters in register 0x84 and 0x85:
STAT_CNT_PRI_CD_CHANGES, STAT_CNT_SEC_CD_CHANGES,
STAT_CNT_RATE_CHANGES, and STAT_CNT_PLL_LOCK_CHANGES. The counters
saturate at 255 (0xFF) and must be cleared before additional status changes can be
counted. The following four way handshake procedures clears the counters.
1. Poll STAT_CLEAR_COUNTS_STATUS parameter until equal to 0 (idle), then set
CTRL_CLEAR_COUNTS = 1 (clear sticky counts).
2. Poll STAT_CLEAR_COUNTS_STATUS parameter until equal to 2 (cleared), then
reset CTRL_CLEAR_COUNTS to 0.
The device will now reset STAT_CLEAR_COUNTS_STATUS to 0 (idle) and the clearing
process can be repeated at any time.
4.9.12 Device Power-up Sequence
If all power supplies cannot be guaranteed to power up simultaneously, ensure that
VCC_SDI powers up first. Please note that there is no minimum time requirement
between power supply initializations after VCC_SDI is energized.
Note: Please check with your local FAE (field applications engineer), as some devices
may need updated configuration settings. If a configuration file has been provided by
the FAE, see the timing information in the Serial Routing and Distribution Product
Configuration Loading Procedure Application Note (PDS-061176).
4.9.12.1 Power-Up Timing Sequence
The following timing sequence must be observed after power-up when no external
configuration loading is required. See Figure 4-36 for the timing requirements of Steps
1 and 2 below.
Step 1 – No GSPI Access Allowed
a) Device supply reaches 90ꢀ of target. POR (Power On Reset) is activated.
b) Internal blocks reset, default device configuration boot-up begins.
c) Default device configuration boot-up process.
Step 2 – GSPI Access Allowed
a) Host sets EYE_MON_INT_CFG_3 (register address 0x57) to 0x8006.
b) If there are multiple devices on the GSPI chain, the host should configure the unit
address of each device. See Section 4.9.9 for further information on unit addressing.
c) Host sets custom application specific settings.
d) Normal operation begins.
GS12341
Final Data Sheet
61 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
5.11 ms – no GSPI Access Allowed
GSPI Access Allowed
All blocks reset.
After Completion of Reset, device
automatically initiates default
configuration boot-up.
Eye Monitor
Reset:
Host
writes 0x8006
to register 0x57
at unit address
0.
Normal Operation Begins.
Host must reconfigure the unit addresses of
devices that were reset to 0.
After which, host may read/write any
register of a specific device on the chain, or
use broadcast write to concurrently write a
command to all devices on the GSPI chain.
All devices that
received reset
command will
have their unit
address reset to
0.
Command will
be broadcast to
all devices that
were reset.
Device Blocks
Resetting.
Device
Configuration
Booting.
Application Defined GSPI Read/Write
Access.
GSPI Access..
110 μs
5 ms
Host writes
0xAD00 to
Internal Reset
Sequence
Complete.
Default
Configuration
Boot-Up
Eye
Monitor
Reset.
Register 0x007F
to reset device.
Host may reset
all devices by
using broadcast
mode.
Complete.
Figure 4-36: Power-Up Sequence.
4.9.13 Host Initiated Device Reset
The GS12341 includes a reset function accessible via the device's host interface, which
reverts all internal logic and register values to their default values.
The device can be reset with a single write of AD00 to the RESET_CONTROL bits of the
h
CONTROL_RESET register, which will assert and de-assert the device reset within the
duration of the GSPI write access Data Word.
The device can be placed and held in reset by writing AA00 to the RESET_CONTROL
h
bits of the CONTROL_RESET register. Subsequent writes of DD00 to the
h
RESET_CONTROL bits will de-assert device reset.
The current state of user-initiated device reset can be read from the RESET_CONTROL
bits of CONTROL_RESET register.
While in reset, host interface access to any other register will not be functional and all
logic and configuration registers will be in reset state. While in reset, output behaviour
is undefined. The digital logic and registers within the device will exit the reset state 5ms
after device reset is de-asserted.
The following timing sequence must be observed to initiate a device reset.
Note: Please check with your local FAE (field applications engineer), as some devices
may need updated configuration settings. If a configuration file has been provided by
the FAE, see the timing information in the Serial Routing and Distribution Product
Configuration Loading Procedure Application Note (PDS-061176).
GS12341
Final Data Sheet
62 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
4.9.13.1 Host Initiated Device Reset Timing Sequence
The following timing sequence must be observed after a Host Initiated Device Reset
when no external configuration loading is required. See Figure 4-37 for the timing
requirements of the Steps 1 to 3 below.
Step 1 – GSPI Access Allowed
a) Host writes 0xAD00 to register 0x007F to reset selected devices, or all devices using
broadcast.
Step 2– No GSPI Access Allowed
a) Internal blocks reset, default device configuration boot-up begins.
b) Default device configuration boot-up completes.
Step 3 – GSPI Access Allowed
a) Host sets EYE_MON_INT_CFG_3 (register address 0x57) to 0x8006.
b) If there are multiple devices on the GSPI chain, host must reconfigure unit address
of each device that was reset. See Section 4.9.9 for further information on unit
addressing.
c) Host sets custom application specific settings.
d) Normal operation begins.
5.11 ms – No GSPI Access Allowed
GSPI Access Allowed
All blocks reset.
After Completion of Reset, device
automatically initiates default
configuration boot-up.
Eye Monitor
Reset:
Host
writes 0x8006
to register 0x57
at unit address
0.
Normal Operation Begins.
Host must reconfigure the unit addresses of
devices that were reset to 0.
After which, the host may read/write any
register of specific device on the chain, or
use broadcast write to concurrently write a
command to all devices on the GSPI chain.
All devices that
received reset
command will
have their unit
address reset to
0.
Command will
be broadcast to
all devices that
were reset.
Device Blocks
Resetting.
Device
Configuration
Booting.
Application Defined GSPI Read/Write
Access.
GSPI Access.
110 μs
5 ms
Host writes
0xAD00 to
Internal Reset
Sequence
Complete.
Default
Configuration
Boot-Up
Eye
Monitor
Reset.
Register 0x007F
to reset device.
Host may reset
all devices by
using broadcast
mode.
Complete.
Figure 4-37: Host Initiated Device Reset Timing Sequence.
GS12341
Final Data Sheet
63 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
5. Register Map
The host interface on the GS12341 provides users complete control of key features such
as GPIO configuration, PLL loop bandwidth settings, reclock parameters, carrier
detection, cable equalization, bypass modes, output swing controls, mute functions,
pre-emphasis control and many others.
It also includes a wide selection of Status registers which allow the user to read back
several key metrics of information from the GS12341 to add more flexibility to their
designs. Section 5.1 to Section 5.3 cover each Control and Status register in detail.
5.1 Control Registers
Table 5-1: Control Registers
GSPI
Address
Register Name
R/W
h
0
1
CONTROL_ REG
DEVICE_ID
RW
RO
2
RSVD
RW
RW
RW
RW
RW
RW
RW
7F
3
CONTROL_ RESET
CONTROL_ SLEEP
MISC_CNTRL
4
5
MISC_CFG
6
RATE_ DETECT_ MODE
RATE_ DETECT_ CFG
7
Reclocker Configuration
8
9
RSVD
RW
RW
RW
RW
RW
RW
FACTORY_ CDR_ PARAMETERS
PLL_LOOP_ BANDWIDTH_ 0
PLL_LOOP_ BANDWIDTH_ 1
PLL_LOOP_ BANDWIDTH_ 2
RSVD
0A
0B
0C
0D to 0F
GPIO Configuration
10
11
12
13
GPIO0_CFG
RW
RW
RW
RW
GPIO1_CFG
GPIO2_CFG
GPIO3_CFG
GS12341
Final Data Sheet
64 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-1: Control Registers (Continued)
GSPI
Address
Register Name
R/W
h
Equalizer Configuration
14
15
RSVD
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
CARR_ DET_CFG
16
SQUELCH_ PARAMETERS
CABLE_ EQ_BYPASS_ MODE
INPUT_ LAUNCH_ SWING_CFG
RSVD
17
18
19 to 1F
20
CD_FILTER_ DELAYS_0
CD_FILTER_ DELAYS_1
CD_FILTER_ DELAYS_2
RSVD
21
22
23 to 25
Output Configuration
26 to 27
28
RSVD
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
OUTPUT_ PARAM_TD_ SD_0
OUTPUT_ PARAM_TD_ SD_1
OUTPUT_ PARAM_TD_ SD_2
OUTPUT_ PARAM_TD_ SD_3
OUTPUT_ PARAM_TD_ HD_0
OUTPUT_ PARAM_ TD_HD_1
OUTPUT_ PARAM_TD_ HD_2
OUTPUT_ PARAM_TD_ HD_3
OUTPUT_ PARAM_ TD_3G_0
OUTPUT_ PARAM_ TD_3G_1
OUTPUT_ PARAM_ TD_3G_2
OUTPUT_ PARAM_ TD_3G_3
OUTPUT_ PARAM_ TD_6G_0
OUTPUT_ PARAM_ TD_6G_1
OUTPUT_ PARAM_ TD_6G_2
OUTPUT_ PARAM_ TD_6G_3
OUTPUT_ PARAM_ TD_12G_0
OUTPUT_ PARAM_ TD_12G_1
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
GS12341
Final Data Sheet
65 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-1: Control Registers (Continued)
GSPI
Address
Register Name
R/W
h
3A
3B
OUTPUT_ PARAM_ TD_12G_2
OUTPUT_ PARAM_ TD_12G_3
RSVD
RW
RW
RW
RW
RW
RW
RW
3C to 40
41
OUTPUT_ PARAM_ MUTE_1
RSVD
42
43
OUTPUT_ PARAM_ MUTE_3
RSVD
44 to 47
Output Control
48
OUTPUT_ SIG_SELECT
RW
RW
RW
RW
RW
RW
49
CONTROL_ OUTPUT_ MUTE
CONTROL_ OUTPUT_ DISABLE
CONTROL_ OUTPUT_ SLEW
CONTROL_ RETIMER_ BYPASS
RSVD
4A
4B
4C
4D to 4F
Test Functions
50
51
PRBS_ CHK_CFG
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
PRBS_CHK_ CTRL
PRBS_GEN_ CTRL
RSVD
52
53
54
EYE_MON_ INT_CFG_0
EYE_MON_ INT_CFG_1
EYE_MON_ INT_CFG_2
EYE_MON_ INT_CFG_3
RSVD
55
56
57
58 to 59
5A
EYE_MON_ SCAN_CTRL_0
EYE_MON_ SCAN_CTRL_1
EYE_MON_ SCAN_CTRL_2
EYE_MON_ SCAN_CTRL_3
RSVD
5B
5C
5D
5E to 5F
Factory Settings
60 to 7E RSVD
RW
GS12341
Final Data Sheet
66 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
5.2 Status Registers
Table 5-2: Status Registers
GSPI
Address
Register Name
R/W
h
80
81
RSVD
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
VERSION_0
82
VERSION_1
83
VERSION_2
84
STICKY_ COUNTS_0
STICKY_ COUNTS_1
CURRENT_ STATUS_0
CURRENT_ STATUS_1
EQ_GAIN_IND
85
86
87
88
89
PRBS_ CHK_ERR_CNT
PRBS_ CHK_STATUS
EYE_MON_ SCAN_ SIZE_OUTPUT
EYE_MON_ SHAPE_ OUTPUT_0
EYE_MON_ SHAPE_ OUTPUT_1
EYE_MON_ SHAPE_ OUTPUT_2
EYE_MON_ SHAPE_ OUTPUT_3
EYE_MON_ STATUS
RSVD
8A
8B
8C
8D
8E
8F
90
91 to BF
GS12341
Final Data Sheet
67 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
5.3 Register Descriptions
Table 5-3: Control Register Descriptions
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
Device Configuration And Control
RSVD
15
RW
0
Reserved do not modify.
0 = Enable loop-through. SDIN pin is
looped through to the SDOUT pin.
1 = Disable loop-through. Data
GSPI_LINK_DISABLE
14
RW
0
appearing at SDIN does not appear at
SDOUT, and SDOUT pin is HIGH.
CONTROL_
REG
0
GSPI_BUS_THROUGH_
ENABLE
0 = Disable bus-through mode
1 = Enable bus-through mode
13
RW
RW
0
0
RSVD
12:5
Reserved - do not modify.
Device address programmed by
application. See Section 4.9.10 for
further information
DEV_UNIT_ADDRESS
4:0
RW
0
This register contains the device’s
identification, including revision.
Contact the local technical sales
representative for more details.
1
2
DEVICE_ID
RSVD
DEVICE_VERSION
RSVD
15:0
15:0
RO
—
0
R/W
Reserved - do not modify.
Device Reset, Reverts all internal logic
and register values to defaults.
Write Values:
AA00h = Asserts device reset
DD00h = De-assert device reset
AD00h = Assert/de-assert device reset in
a single write
CONTROL_
RESET
7F
RESET_CONTROL
15:0
R/W
DD00
Read Values:
AA00h = User-initiated reset is asserted
DD00h = User-initiated reset is
de-asserted
See Section 4.9.13 for further
information
GS12341
Final Data Sheet
68 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
RSVD
15:2
R/W
0
Reserved - do not modify.
Sleep manual mode control:
0 = Never Sleep
CTRL_MANUAL_SLEEP
CTRL_AUTO_SLEEP
1
R/W
R/W
0
1 = Always Sleep
Controls sleep mode when auto sleep
(CTRL_AUTO_SLEEP) is disabled.
CONTROL_
SLEEP
Sleep auto mode control:
3
0 = Disable auto sleep mode
1 = Enable auto sleep mode
If CTRL_AUTO_SLEEP = 0 (manual sleep
mode), then CTRL_MANUAL_SLEEP
controls sleep.
0
1
If CTRL_AUTO_SLEEP = 1 (auto sleep
mode), sleep is automatically entered
on loss of signal.
RSVD
15:1
0
R/W
R/W
0
0
Reserved - do not modify.
Clear sticky counts control register.
0 = no action
1 = clear sticky counts.
Part of a four way handshake with
STAT_CLEAR_COUNTS_STATUS. See
Section 4.9.11 for more details on
implementing the four way handshake
for this operation.
4
MISC_CNTRL
CTRL_CLEAR_COUNTS
RSVD
15:4
3
R/W
R/W
0
0
Reserved - do not modify.
Controls whether trace driver (DDO1) is
muted or disabled (powered down)
during sleep:
CFG_SLEEP_OUTPUT1_
MUTE
0 = disable (power down) output during
sleep.
1 = mute output during sleep.
5
MISC_CFG
Controls whether trace driver (DDO0) is
muted or disabled (powered down)
during sleep:
0 = disable (power down) output during
sleep.
CFG_SLEEP_OUTPUT0_
MUTE
2
R/W
R/W
0
1
1 = mute output during sleep.
RSVD
1:0
Reserved - do not modify.
GS12341
Final Data Sheet
69 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
Reclocker Configuration
RSVD
15:5
4:1
R/W
R/W
1F0
Reserved - do not modify.
Manual rate selection. The Reclocker will
only lock to the selected rate if
CFG_AUTO_RATE_DETECT_ENA = 0:
0 = Bypass cable equalizer and
Reclocker for low data rates.
1 = MADI
CFG_MANUAL_RATE
0
2 = SD
3 = HD
4 = 3G
5 = 6G
6 = 12G
RATE_
DETECT_
MODE
6
7 = Reserved - do not modify.
Set or disable auto rate detection mode
for the Reclocker.
0 = Disable auto rate detection
1 = Enable auto rate detection
When automatic rate detection is
disabled
CFG_AUTO_RATE_
DETECT_ENA
0
R/W
1
(CFG_AUTO_RATE_DETECT_ENA = 0),
the rate is set by CFG_MANUAL_RATE.
RSVD
15:5
4
R/W
R/W
0
0
Reserved - do not modify.
Select data rate threshold between SD
and MADI:
0 = 181Mb/s
CFG_RD_SD_MADI_
THRESHOLD
1 = 198Mb/s
CFG_RD_SD_MADI_THRESHOLD and
CFG_RD_MADI_LTMADI_DATADIV (bit
slice [3:0]) determines the rate detection
threshold between MADI and <MADI
rates. The following threshold settings
are available:
0x0 = 53Mb/s
0x2 = 32Mb/s
0x3 = 79Mb/s (default)
RATE_
DETECT_
CFG
7
CFG_RD_MADI_
LTMADI_DATADIV
3:2
R/W
0
0x6 = 63Mb/s
0x9 = 48Mb/s
0xA = 95Mb/s
0xC = 111Mb/s
0x1, 0x4, 0x5, 0x7, 0x8, 0xB, 0xD, and 0xE
= Reserved - do not use.
CFG_RD_MADI_
LTMADI_CLKDIV
1:0
R/W
R/W
3
3
See CFG_RD_MADI_ LTMADI_DATADIV.
Reserved - do not modify.
8
RSVD
RSVD
15:0
GS12341
Final Data Sheet
70 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
RSVD
15:2
R/W
1C
0
Reserved - do not modify.
To maximize loop bandwidth of PLL and
consequently IJT of the Reclocker, set
this parameter to 0.
FACTORY_
CDR_
PARAMETERS
9
CFG_MIN_LBW
1
R/W
RSVD
RSVD
0
R/W
R/W
0
0
Reserved - do not modify.
Reserved - do not modify.
15:13
Configure PLL loop bandwidth in terms
of ratio to nominal loop bandwidth 'x'
(see Table 2-3).
11.88Gb/s (12G) loop bandwidth
setting:
0x00 = Reserved - do not use
0x01 = 0.0625x
0x02 = 0.125x
0x03 = 0.1875x
0x04 = 0.25x
0x05 = 0.3125x
0x06 = 0.375x
0x07 = 0.4375x
0x08 = 0.5x
CFG_PLL_LBW_12G
12:8
R/W
8
0x09 = 0.5625x
0x0A = 0.625x
0x0B = 0.6875x
0x0C = 0.75x
PLL_LOOP_
BANDWIDTH_
0
0A
0x0D = 0.8125x
0x0E = 0.875x
0x0F = 0.9375x
0x10 to 0x1B = Reserved - do not use
0x1C = 1.0x (nominal)
0x1D = 1.0625x
0x1E = 1.125x
0x1F = 1.1875x
RSVD
7:5
4:0
R/W
R/W
0
8
Reserved - do not modify.
Configure 5.94Gb/s (6G) PLL loop
bandwidth in terms of ratio to nominal
loop bandwidth 'x' (see Table 2-3).
See CFG_PLL_LBW_12G parameter for
available settings.
CFG_PLL_LBW_6G
GS12341
Final Data Sheet
71 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
RSVD
15:13
12:8
7:5
R/W
0
Reserved - do not modify.
Configure 2.97Gb/s (3G) PLL loop
bandwidth in terms of ratio to nominal
loop bandwidth 'x' (see Table 2-3).
See CFG_PLL_LBW_12G parameter for
available settings.
CFG_PLL_LBW_3G
RSVD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
PLL_LOOP_
BANDWIDTH_
1
0B
0
Reserved - do not modify.
Configure 1.485Gb/s (HD) PLL loop
bandwidth in terms of ratio to nominal
loop bandwidth 'x' (see Table 2-3).
See CFG_PLL_LBW_12G parameter for
available settings.
CFG_PLL_LBW_HD
RSVD
4:0
8
15:13
12:8
7:5
0
Reserved - do not modify.
Configure 270Mb/s (SD) PLL loop
bandwidth in terms of ratio to nominal
loop bandwidth 'x' (see Table 2-3).
See CFG_PLL_LBW_12G parameter for
available settings.
CFG_PLL_LBW_SD
RSVD
1C
0
PLL_LOOP_
BANDWIDTH_
2
0C
Reserved - do not modify.
Configure 125Mb/s (MADI) PLL loop
bandwidth in terms of ratio to nominal
loop bandwidth 'x' (see Table 2-3).
See CFG_PLL_LBW_12G parameter for
available settings.
CFG_PLL_LBW_MADI
4:0
8
0D
RSVD
RSVD
RSVD
RSVD
15:0
15:0
R/W
R/W
8
0
Reserved - do not modify.
Reserved - do not modify.
0E to 0F
GS12341
Final Data Sheet
72 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
GPIO Configuration
RSVD
15:9
R/W
0
1
Reserved - do not modify.
GPIO0 buffer mode control.
0 = GPIO pin is configured as an input
(tri-stated / high impedance).
CFG_GPIO0_
OUTPUT_ENA
8
R/W
1 = GPIO pin is configured as an output.
Function select for GPIO0 pin.
GPIO0 output functions:
0x00 = Output driven LOW
0x01 = Output driven HIGH
0x02 = PLL lock status (HIGH — PLL
locked)
0x03 to 0x7F= Reserved - do not use.
0x80 = LOS equivalent to inverse of
STAT_SEC_CD (Default mode for GPIO0)
0x81 = carrier detect status
(STAT_SEC_CD)
0x82 = Sleep mode status (HIGH —
Device in sleep mode)
0x83 = HIGH for SD, LOW for all other
rates.
0x84 = Rate detected [0]
0x85 = Rate detected [1]
10
GPIO0_CFG
0x86 = Rate detected [2]
Note: To have full rate range using the
GPIO rate detect function, one GPIO pin
must be used for each Rate Detect bit
[2:0]. Please see Table 4-2: Detected
Data Rates for the indication values.
CFG_GPIO0_FUNCTION
7:0
R/W
80
0x87 to 0xFF = Reserved - do not use.
GPIO0 input functions:
0x00 to 0x80 = Reserved - do not use.
0x81 = DDO0 disable control (HIGH —
disable)
0x82 = DDO1 disable control (HIGH —
disable)
0x83 = Reserved - do not modify.
0x84 = Cable equalizer bypass enable
(HIGH — Bypass enabled)
0x85 = Reclocker bypass enable (HIGH
— Bypass enabled)
0x86 = Sleep control (HIGH — Sleep)
0x87 to 0xFF = Reserved - do not use.
GS12341
Final Data Sheet
73 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
RSVD
15:9
R/W
0
Reserved - do not modify.
GPIO1 buffer mode control.
See GPIO0_CFG:
CFG_GPIO0_OUTPUT_ENA parameter
for description and available settings.
Default mode: Output
CFG_GPIO1_
OUTPUT_ENA
8
R/W
1
11
GPIO1_CFG
Function select for GPIO1 pin.
See GPIO0_CFG:
CFG_GPIO1_FUNCTION
RSVD
7:0
15:9
8
R/W
R/W
R/W
2
0
0
CFG_GPIO0_FUNCTION parameter for
description and available settings.
Default Function: 0x02 = PLL lock status
Reserved - do not modify.
GPIO2 buffer mode control.
See GPIO0_CFG:
CFG_GPIO0_OUTPUT_ENA parameter
for description and available settings.
Default mode: Input
CFG_GPIO2_
OUTPUT_ENA
12
GPIO2_CFG
Function select for GPIO2 pin.
See GPIO0_CFG:
CFG_GPIO2_FUNCTION
RSVD
7:0
15:9
8
R/W
R/W
R/W
86
0
CFG_GPIO0_FUNCTION parameter for
description and available settings.
Default Function: 0x86 = Sleep control
Reserved - do not modify.
GPIO3 buffer mode control.
See GPIO0_CFG:
CFG_GPIO0_OUTPUT_ENA parameter
for description and available settings.
Default mode: Input
CFG_GPIO3_
OUTPUT_ENA
0
13
GPIO3_CFG
Function select for GPIO3 pin.
See GPIO0_CFG:
CFG_GPIO0_FUNCTION parameter for
description and available settings.
Default Function: 0x82 = DDO1 disable
control (HIGH disable)
CFG_GPIO3_FUNCTION
7:0
R/W
82
GS12341
Final Data Sheet
74 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
Cable Equalizer Configuration
14
RSVD
RSVD
RSVD
15:0
15:1
R/W
R/W
303
0
Reserved - do not modify.
Reserved - do not modify.
Enable or disable squelch control
conditions for deriving secondary
carrier detection (LOS) status for cable
equalizer (SDI) input.
CARR_
DET_CFG
15
CFG_SEC_CD_
INCL_CLI_SQUELCH
0
R/W
0
0 = Ignore CLI squelch.
1 = Take into account CLI squelch.
RSVD
15
R/W
R/W
0
Reserved - do not modify.
Set the input signal squelch threshold.
Range = 0 to 64d (64d is max cable reach
determined for specific rate, cable type,
and launch swing compensation).
CFG_CLI_SQUELCH_
THRESHOLD
14:8
40
SQUELCH_
PARAMETERS
16
RSVD
7
R/W
R/W
R/W
0
2
0
Reserved - do not modify.
Set the input signal squelch hysteresis
Range: 1 to 30d
CFG_CLI_SQUELCH_
HYSTERESIS
6:0
RSVD
15:2
Reserved - do not modify.
Controls cable equalizer (CEQ) bypass
when auto CEQ bypass is disabled
(CTRL_CEQ_AUTO_BYPASS= 0).
0 = Cable equalizer never bypassed
1 = Cable equalizer always bypassed
CTRL_CEQ_MANUAL_
BYPASS
1
0
R/W
0
CABLE_
EQ_BYPASS_
MODE
17
Auto cable equalizer bypass mode
control:
0 = Disable auto mode
CTRL_CEQ_AUTO_
BYPASS
R/W
1
1 = Enable auto mode
When CFG_CEQ_AUTO_BYPASS = 0,
CEQ bypass is controlled by
CFG_CEQ_BYPASS_MANUAL.
RSVD
15:7
6:0
R/W
R/W
0
Reserved - do not modify.
Input launch swing compensation
setting in units of 10 mVppd
Default setting of 80d (0x50)
corresponds to 800mV. Default for
upstream SMPTE compliant cable
drivers operating at 800mv 10ꢀ.
INPUT_
LAUNCH_
SWING_CFG
CFG_CEQ_INPUT_
LAUNCH_SWING_
COMP
18
50
19
1A
1B
1C
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
15:0
15:0
15:0
15:0
R/W
R/W
R/W
R/W
1
14
1
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
4
GS12341
Final Data Sheet
75 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
1D
1E
1F
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
15:0
15:0
15:0
15:8
R/W
R/W
R/W
R/W
0
4
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
43
0
CEQ (Cable Equalizer) carrier detect filter
sample window period in clock cycles.
Sample window size is this value plus 1
clock cycle.
CD_FILTER_
DELAYS_0
20
CFG_CD_FILTER_
SAMPLE_WIN
7:0
R/W
3
Valid Range: 0x03 to 0xFF
See Section 4.2.3 for details.
RSVD
15:10
9:0
R/W
R/W
R/W
R/W
R/W
0
F
Reserved - do not modify.
Number of samples required for
detecting CEQ (cable equalizer) carrier
detect de-assertion:
Valid Range: 0x00 to 0x3FF
See Section 4.2.3 for details.
CD_FILTER_
DELAYS_1
21
22
CFG_CD_FILTER_
DEASSERT_CNT
RSVD
15:10
9:0
0
Reserved - do not modify.
Number of samples required for
detecting CEQ (cable equalizer) carrier
detect assertion:
Valid Range: 0x00 to 0x3FF
See Section 4.2.3 for details.
CD_FILTER_
DELAYS_2
CFG_CD_FILTER_
ASSERT_CNT
3FF
0
23 to 25
26 to 27
RSVD
RSVD
RSVD
15:0
Reserved - do not modify.
Output Configuration
RSVD
RSVD
15:0
R/W
R/W
0
0
Reserved - do not modify.
Reserved - do not modify.
15:13
Configure the SD rate pre-emphasis
pulse width on trace driver output1
(DDO1).
Range: 0 to 15d.
Adjust the pre-emphasis pulse width to
better match the channel loss response
shape.
Note: By default, the trace driver SD
settings are applied for all rates (see
CTRL_OUTPUT1_TRDR_PER_RATE for
per rate setting).
OUTPUT_
PARAM_TD_
SD_0
CFG_OUTPUT1_TD_
SD_PREEMPH_WIDTH
28
12:8
R/W
R/W
2
0
RSVD
7
Reserved - do not modify.
GS12341
Final Data Sheet
76 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
Power down the SD rate pre-emphasis
on trace driver output1 (DDO1).
0 = Pre-emphasis driver powered up
(pre-emphasis enabled).
1 = Pre-emphasis driver powered down
(pre-emphasis disabled).
Note: By default, the trace driver SD
settings are applied for all rates (see
CTRL_OUTPUT1_TRDR_PER_RATE for
per rate setting).
CFG_OUTPUT1_TD_
SD_PREEMPH_
PWRDWN
6
R/W
0
OUTPUT_
PARAM_TD_
SD_0
28
Configure the SD rate pre-emphasis
amplitude on trace driver output1
(DDO1).
(Continued)
(Continued)
Range: 0 to 50d.
Adjust the pre-emphasis pulse
amplitude to better match the channel
loss at Nyquist.
CFG_OUTPUT1_TD_
SD_PREEMPH_AMPL
5:0
R/W
1
Note: By default, the trace driver SD
settings are applied for all rates (see
CTRL_OUTPUT1_TRDR_PER_RATE for
per rate setting).
RSVD
15:14
13:8
7:0
R/W
R/W
R/W
0
Reserved - do not modify.
Configure the SD rate amplitude on
trace driver output1 (DDO1). amplitude.
Range: 0 to 40d.
Adjust the differential trace driver
amplitude. The default value produces
an amplitude of 400mVppd.
Note: By default, the trace driver SD
settings are applied for all rates (see
CTRL_OUTPUT1_TRDR_PER_RATE for
per rate setting).
OUTPUT_
PARAM_TD_
SD_1
CFG_OUTPUT1_TD_
SD_DRIVER_SWING
29
11
70
RSVD
Reserved - do not modify.
GS12341
Final Data Sheet
77 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
RSVD
15:13
R/W
0
Reserved - do not modify.
Configure the SD rate pre-emphasis
pulse width on trace driver output0
(DDO0).
Range: 0 to 15d.
Adjust the pre-emphasis pulse width to
better match the channel loss response
shape.
CFG_OUTPUT0_TD_
SD_PREEMPH_WIDTH
12:8
R/W
2
Note: By default, the trace driver SD
settings are applied for all rates (see
CTRL_OUTPUT0_TRDR_PER_RATE for
per rate setting).
RSVD
7
6
R/W
R/W
0
0
Reserved - do not modify.
Power down the SD rate pre-emphasis
on trace driver output0 (DDO0).
0 = Pre-emphasis driver powered up
(pre-emphasis enabled).
1 = Pre-emphasis driver powered down
(pre-emphasis disabled).
Note: By default, the trace driver SD
settings are applied for all rates (see
CTRL_OUTPUT0_TRDR_PER_RATE for
per rate setting).
OUTPUT_
PARAM_TD_
SD_2
2A
CFG_OUTPUT0_TD_
SD_PREEMPH_
PWRDWN
Configure the SD rate pre-emphasis
amplitude on trace driver output0
(DDO0).
Range: 0 to 50d.
Adjust the pre-emphasis pulse
amplitude to better match the channel
loss at Nyquist.
CFG_OUTPUT0_TD_
SD_PREEMPH_AMPL
5:0
R/W
1
Note: By default, the trace driver SD
settings are applied for all rates (see
CTRL_OUTPUT0_TRDR_PER_RATE for
per rate setting).
RSVD
15:14
13:8
7:0
R/W
R/W
R/W
0
Reserved - do not modify.
Configure the SD rate amplitude on
trace driver output0 (DDO0). amplitude.
Range: 0 to 40d.
Adjust the differential trace driver
amplitude. The default value produces
an amplitude of 400mVppd.
Note: By default, the trace driver SD
settings are applied for all rates (see
CTRL_OUTPUT0_TRDR_PER_RATE for
per rate setting).
OUTPUT_
PARAM_TD_
SD_3
CFG_OUTPUT0_TD_
SD_DRIVER_SWING
2B
11
70
RSVD
Reserved - do not modify.
GS12341
Final Data Sheet
78 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
RSVD
15:13
12:8
R/W
0
Reserved - do not modify.
Configure the HD rate pre-emphasis
pulse width on trace driver output1
(DDO1).
CFG_OUTPUT1_TD_
HD_PREEMPH_WIDTH
Range: 0 to 15d.
R/W
2
Adjust the pre-emphasis pulse width to
better match the channel loss response
shape.
RSVD
7
6
R/W
R/W
0
0
Reserved - do not modify.
OUTPUT_
PARAM_TD_
HD_0
Power down the HD rate pre-emphasis
on trace driver output1 (DDO1)
0 = Pre-emphasis driver powered up
(pre-emphasis enabled).
2C
CFG_OUTPUT1_TD_
HD_PREEMPH_
PWRDWN
1 = Pre-emphasis driver powered down
(pre-emphasis disabled).
Configure the HD rate pre-emphasis
amplitude on trace driver output1
(DDO1).
CFG_OUTPUT1_TD_
HD_PREEMPH_AMPL
Range: 0 to 50d.
5:0
R/W
1
Adjust the pre-emphasis pulse
amplitude to better match the channel
loss at Nyquist.
RSVD
15:14
13:8
7:0
R/W
R/W
R/W
0
Reserved - do not modify.
Configure the HD rate amplitude on
trace driver output1 (DDO1). amplitude.
Range: 0 to 40d.
Adjust the differential trace driver
amplitude. The default value produces
OUTPUT_
PARAM_
TD_HD_1
CFG_OUTPUT1_TD_
HD_DRIVER_SWING
2D
11
70
an amplitude of 400mVppd
.
RSVD
Reserved - do not modify.
GS12341
Final Data Sheet
79 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
RSVD
15:13
12:8
R/W
0
Reserved - do not modify.
Configure the HD rate pre-emphasis
pulse width on trace driver output0
(DDO0).
CFG_OUTPUT0_TD_
HD_PREEMPH_WIDTH
Range: 0 to 15d.
R/W
2
Adjust the pre-emphasis pulse width to
better match the channel loss response
shape.
RSVD
7
6
R/W
R/W
0
0
Reserved - do not modify.
OUTPUT_
PARAM_TD_
HD_2
Power down the HD rate pre-emphasis
on trace driver output0 (DDO0)
0 = Pre-emphasis driver powered up
(pre-emphasis enabled).
2E
CFG_OUTPUT0_TD_
HD_PREEMPH_
PWRDWN
1 = Pre-emphasis driver powered down
(pre-emphasis disabled).
Configure the HD rate pre-emphasis
amplitude on trace driver output0
(DDO0).
CFG_OUTPUT0_TD_
HD_PREEMPH_AMPL
Range: 0 to 50d.
5:0
R/W
1
Adjust the pre-emphasis pulse
amplitude to better match the channel
loss at Nyquist.
RSVD
15:14
13:8
7:0
R/W
R/W
R/W
0
Reserved - do not modify.
Configure the HD rate amplitude on
trace driver output0 (DDO0). amplitude.
Range: 0 to 40d.
Adjust the differential trace driver
amplitude. The default value produces
OUTPUT_
PARAM_TD_
HD_3
CFG_OUTPUT0_TD_
HD_DRIVER_SWING
2F
11
70
an amplitude of 400mVppd
.
RSVD
Reserved - do not modify.
GS12341
Final Data Sheet
80 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
RSVD
15:13
12:8
R/W
0
Reserved - do not modify.
Configure the 3G rate pre-emphasis
pulse width on trace driver output1
(DDO1).
CFG_OUTPUT1_TD_
3G_PREEMPH_WIDTH
Range: 0 to 15d.
R/W
2
Adjust the pre-emphasis pulse width to
better match the channel loss response
shape.
RSVD
7
6
R/W
R/W
0
0
Reserved - do not modify.
OUTPUT_
PARAM_
TD_3G_0
Power down the 3G rate pre-emphasis
on trace driver output1 (DDO1)
0 = Pre-emphasis driver powered up
(pre-emphasis enabled).
30
CFG_OUTPUT1_TD_
3G_PREEMPH_
PWRDWN
1 = Pre-emphasis driver powered down
(pre-emphasis disabled).
Configure the 3G rate pre-emphasis
amplitude on trace driver output1
(DDO1).
CFG_OUTPUT1_TD_
3G_PREEMPH_AMPL
Range: 0 to 50d.
5:0
R/W
1
Adjust the pre-emphasis pulse
amplitude to better match the channel
loss at Nyquist.
RSVD
15:14
13:8
7:0
R/W
R/W
R/W
0
Reserved - do not modify.
Configure the 3G rate amplitude on
trace driver output1 (DDO1). amplitude.
Range: 0 to 40d.
Adjust the differential trace driver
amplitude. The default value produces
OUTPUT_
PARAM_
TD_3G_1
CFG_OUTPUT1_TD_
3G_DRIVER_SWING
31
11
70
an amplitude of 400mVppd
.
RSVD
Reserved - do not modify.
GS12341
Final Data Sheet
81 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
RSVD
15:13
12:8
R/W
0
Reserved - do not modify.
Configure the 3G rate pre-emphasis
pulse width on trace driver output0
(DDO0).
CFG_OUTPUT0_TD_
3G_PREEMPH_WIDTH
Range: 0 to 15d.
R/W
2
Adjust the pre-emphasis pulse width to
better match the channel loss response
shape.
RSVD
7
6
R/W
R/W
0
0
Reserved - do not modify.
OUTPUT_
PARAM_
TD_3G_2
Power down the 3G rate pre-emphasis
on trace driver output0 (DDO0)
0 = Pre-emphasis driver powered up
(pre-emphasis enabled).
32
CFG_OUTPUT0_TD_
3G_PREEMPH_
PWRDWN
1 = Pre-emphasis driver powered down
(pre-emphasis disabled).
Configure the 3G rate pre-emphasis
amplitude on trace driver output0
(DDO0).
CFG_OUTPUT0_TD_
3G_PREEMPH_AMPL
Range: 0 to 50d.
5:0
R/W
1
Adjust the pre-emphasis pulse
amplitude to better match the channel
loss at Nyquist.
RSVD
15:14
13:8
7:0
R/W
R/W
R/W
0
Reserved - do not modify.
Configure the 3G rate amplitude on
trace driver output0 (DDO0). amplitude.
Range: 0 to 40d.
Adjust the differential trace driver
amplitude. The default value produces
OUTPUT_
PARAM_
TD_3G_3
CFG_OUTPUT0_TD_
3G_DRIVER_SWING
33
11
70
an amplitude of 400mVppd
.
RSVD
Reserved - do not modify.
GS12341
Final Data Sheet
82 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
RSVD
15:13
12:8
R/W
0
Reserved - do not modify.
Configure the 6G rate pre-emphasis
pulse width on trace driver output1
(DDO1).
CFG_OUTPUT1_TD_
6G_PREEMPH_WIDTH
Range: 0 to 15d.
R/W
2
Adjust the pre-emphasis pulse width to
better match the channel loss response
shape.
RSVD
7
6
R/W
R/W
0
0
Reserved - do not modify.
OUTPUT_
PARAM_
TD_6G_0
Power down the 6G rate pre-emphasis
on trace driver output1 (DDO1)
0 = Pre-emphasis driver powered up
(pre-emphasis enabled).
34
CFG_OUTPUT1_TD_
6G_PREEMPH_
PWRDWN
1 = Pre-emphasis driver powered down
(pre-emphasis disabled).
Configure the 6G rate pre-emphasis
amplitude on trace driver output1
(DDO1).
CFG_OUTPUT1_TD_
6G_PREEMPH_AMPL
Range: 0 to 50d.
5:0
R/W
1
Adjust the pre-emphasis pulse
amplitude to better match the channel
loss at Nyquist.
RSVD
15:14
13:8
7:0
R/W
R/W
R/W
0
Reserved - do not modify.
Configure the 6G rate amplitude on
trace driver output1 (DDO1). amplitude.
Range: 0 to 40d.
Adjust the differential trace driver
amplitude. The default value produces
an amplitude of 400mVppd
OUTPUT_
PARAM_
TD_6G_1
CFG_OUTPUT1_TD_
6G_DRIVER_SWING
35
11
70
RSVD
Reserved - do not modify.
GS12341
Final Data Sheet
83 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
RSVD
15:13
12:8
R/W
0
Reserved - do not modify.
Configure the 6G rate pre-emphasis
pulse width on trace driver output0
(DDO0).
CFG_OUTPUT0_TD_
6G_PREEMPH_WIDTH
Range: 0 to 15d.
R/W
2
Adjust the pre-emphasis pulse width to
better match the channel loss response
shape.
RSVD
7
6
R/W
R/W
0
0
Reserved - do not modify.
OUTPUT_
PARAM_
TD_6G_2
Power down the 6G rate pre-emphasis
on trace driver output0 (DDO0)
0 = Pre-emphasis driver powered up
(pre-emphasis enabled).
36
CFG_OUTPUT0_TD_
6G_PREEMPH_
PWRDWN
1 = Pre-emphasis driver powered down
(pre-emphasis disabled).
Configure the 6G rate pre-emphasis
amplitude on trace driver output0
(DDO0).
CFG_OUTPUT0_TD_
6G_PREEMPH_AMPL
Range: 0 to 50d.
5:0
R/W
1
Adjust the pre-emphasis pulse
amplitude to better match the channel
loss at Nyquist.
RSVD
15:14
13:8
7:0
R/W
R/W
R/W
0
Reserved - do not modify.
Configure the 6G rate amplitude on
trace driver output0 (DDO0). amplitude.
Range: 0 to 40d.
Adjust the differential trace driver
amplitude. The default value produces
OUTPUT_
PARAM_
TD_6G_3
37
CFG_OUTPUT0_TD_
6G_DRIVER_SWING
11
70
an amplitude of 400mVppd
.
RSVD
Reserved - do not modify.
GS12341
Final Data Sheet
84 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
RSVD
15:13
R/W
0
Reserved - do not modify.
Configure the 12G rate pre-emphasis
pulse width on trace driver output1
(DDO1).
Range: 0 to 15d.
Adjust the pre-emphasis pulse width to
better match the channel loss response
shape.
Note: When per rate settings are
chosen, the trace driver 12G settings are
applied for all rates when the Reclocker
is unlocked
CFG_OUTPUT1_TD_
12G_PREEMPH_WIDTH
12:8
R/W
2
(see CTRL_OUTPUT1_TRDR_PER_RATE
for per rate setting).
RSVD
7
6
R/W
R/W
0
0
Reserved - do not modify.
Power down the 12G rate pre-emphasis
on trace driver output1 (DDO1)
0 = Pre-emphasis driver powered up
(pre-emphasis enabled).
1 = Pre-emphasis driver powered down
(pre-emphasis disabled).
OUTPUT_
PARAM_
TD_12G_0
38
CFG_OUTPUT1_TD_
12G_PREEMPH_
PWRDWN
Note: When per rate settings are
chosen, the trace driver 12G settings are
applied for all rates when the Reclocker
is unlocked
(see CTRL_OUTPUT1_TRDR_PER_RATE
for per rate setting).
Configure the 12G rate pre-emphasis
amplitude on trace driver output1
(DDO1).
Range: 0 to 50d.
Adjust the pre-emphasis pulse
amplitude to better match the channel
loss at Nyquist.
Note: When per rate settings are
chosen, the trace driver 12G settings are
applied for all rates when the Reclocker
is unlocked
CFG_OUTPUT1_TD_
12G_PREEMPH_AMPL
5:0
R/W
1
(see CTRL_OUTPUT1_TRDR_PER_RATE
for per rate setting).
GS12341
Final Data Sheet
85 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
RSVD
15:14
R/W
0
Reserved - do not modify.
Configure the 12G rate amplitude on
trace driver output1 (DDO1). amplitude.
Range: 0 to 40d.
Adjust the differential trace driver
amplitude. The default value produces
an amplitude of 400mVppd
Note: When per rate settings are
chosen, the trace driver 12G settings are
applied for all rates when the Reclocker
is unlocked
OUTPUT_
PARAM_
TD_12G_1
CFG_OUTPUT1_TD_
12G_DRIVER_SWING
39
13:8
R/W
11
(see CTRL_OUTPUT1_TRDR_PER_RATE
for per rate setting).
RSVD
RSVD
7:0
R/W
R/W
70
0
Reserved - do not modify.
Reserved - do not modify.
15:13
Configure the 12G rate pre-emphasis
pulse width on trace driver output0
(DDO0).
Range: 0 to 15d.
Adjust the pre-emphasis pulse width to
better match the channel loss response
shape.
Note: When per rate settings are
chosen, the trace driver 12G settings are
applied for all rates when the Reclocker
is unlocked
CFG_OUTPUT0_TD_
12G_PREEMPH_WIDTH
12:8
R/W
2
(see CTRL_OUTPUT0_TRDR_PER_RATE
for per rate setting)
OUTPUT_
PARAM_
TD_12G_2
3A
RSVD
7
6
R/W
R/W
0
0
Reserved - do not modify.
Power down the 12G rate pre-emphasis
on trace driver output0 (DDO0)
0 = Pre-emphasis driver powered up
(pre-emphasis enabled).
1 = Pre-emphasis driver powered down
(pre-emphasis disabled).
CFG_OUTPUT0_TD_
12G_PREEMPH_
PWRDWN
Note: When per rate settings are
chosen, the trace driver 12G settings are
applied for all rates when the Reclocker
is unlocked
(see CTRL_OUTPUT0_TRDR_PER_RATE
for per rate setting).
GS12341
Final Data Sheet
86 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
Configure the 12G rate pre-emphasis
amplitude on trace driver output0
(DDO0).
Range: 0 to 50d.
Adjust the pre-emphasis pulse
amplitude to better match the channel
loss at Nyquist.
OUTPUT_
PARAM_
TD_12G_2
(Continued)
CFG_OUTPUT0_TD_
12G_PREEMPH_AMPL
3A
(Continued)
5:0
R/W
1
Note: When per rate settings are
chosen, the trace driver 12G settings are
applied for all rates when the Reclocker
is unlocked
(see CTRL_OUTPUT0_TRDR_PER_RATE
for per rate setting).
RSVD
15:14
13:8
R/W
R/W
0
Reserved - do not modify.
Configure the 12G rate amplitude on
trace driver output0 (DDO0). amplitude.
Range: 0 to 40d.
Adjust the differential trace driver
amplitude. The default value produces
OUTPUT_
PARAM_
TD_12G_3
an amplitude of 400mVppd
.
CFG_OUTPUT0_TD_
12G_DRIVER_SWING
3B
11
Note: When per rate settings are
chosen, the trace driver 12G settings are
applied for all rates when the Reclocker
is unlocked
(see CTRL_OUTPUT0_TRDR_PER_RATE
for per rate setting).
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
7:0
15:0
15:0
15:0
15:0
15:0
15:14
R/W
R/W
R/W
R/W
R/W
R/W
R/W
70
342
1C90
342
1C90
340
0
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
3C
3D
3E
3F
40
RSVD
RSVD
RSVD
RSVD
RSVD
Controls the output mute differential
latch voltage on output1 (DDO1) trace
driver. Default is 8 = ~200mVdiff
.
OUTPUT_
PARAM_
MUTE_1
CFG_OUTPUT1_MUTE_
DRIVER_SWING
Increasing the setting may be required
for noisy environment, but mute power
increases proportionally to mute
differential latch voltage.
41
42
13:8
R/W
8
Range: 0 to 63d
RSVD
RSVD
7:0
R/W
R/W
50
Reserved - do not modify.
Reserved - do not modify.
RSVD
15:0
340
GS12341
Final Data Sheet
87 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
RSVD
15:14
R/W
0
Reserved - do not modify.
Controls the output mute differential
latch voltage on output0 (DDO0) trace
driver. Default is 8=~200mVdiff
.
OUTPUT_
PARAM_
MUTE_3
CFG_OUTPUT0_MUTE_
DRIVER_SWING
Increasing the setting may be required
for noisy environment, but mute power
increases proportionally to mute
differential latch voltage.
43
13:8
R/W
8
Range: 0 to 63d
RSVD
RSVD
RSVD
RSVD
RSVD
7:0
R/W
R/W
R/W
R/W
R/W
50
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
44
45
46
47
RSVD
RSVD
RSVD
RSVD
15:0
15:0
15:0
15:0
342
1C90
342
1C90
Output Control
RSVD
15:4
R/W
10
0
Reserved - do not modify.
Controls optional signal polarity
inversion on trace driver output 0
(DDO0) when data is selected
(CTRL_OUTPUT0_SIGNAL_SEL = 0).
CTRL_OUTPUT0_
DATA_INVERT
3
R/W
Controls optional signal polarity
inversion on trace driver output 0
(DDO1) when data is selected
(CTRL_OUTPUT1_SIGNAL_SEL = 0).
CTRL_OUTPUT1_
DATA_INVERT
2
1
R/W
R/W
0
0
OUTPUT_
SIG_SELECT
48
Select between data or PRBS generator
on output 0 (DDO0).
0 = Data
CTRL_OUTPUT0_
SIGNAL_SEL
1 = PRBS generator output (PRBS7 or
divided version of PRBS generator clock)
Select between data or PRBS generator
on output 1 (DDO1).
0 = Data
CTRL_OUTPUT1_
SIGNAL_SEL
0
R/W
0
1 = PRBS generator output (PRBS7 or
divided version of PRBS generator clock)
GS12341
Final Data Sheet
88 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
RSVD
15:6
R/W
0
Reserved - do not modify.
Selects if device is auto muted during
rate search, based on loss of lock.
1= Mutes DDO1 when the Reclocker is
not locked to the applied signal.
CTRL_OUTPUT1_
AUTO_MUTE_DURING_
RATE_SEARCH
5
R/W
0
0= Device does not auto mute.
Note: If passing non-standard rates
through the device or using the PRBS
generator, set this parameter to 0.
Selects if device is auto muted during
rate search, based on loss of lock.
1= Mutes DDO0 when the Reclocker is
not locked to the applied signal.
CTRL_OUTPUT0_
AUTO_MUTE_DURING_
RATE_SEARCH
4
R/W
0
0= Device does not auto mute.
Note: If passing non-standard rates
through the device or using the PRBS
generator, set this parameter to 0.
Controls mute for trace driver output1
(DDO1) when auto mute
(CTRL_OUTPUT1_AUTO_MUTE = 0) is
disabled.
0 = Unmute output driver
1 = Mute output driver
CTRL_OUTPUT1_
MANUAL_MUTE
CONTROL_
OUTPUT_
MUTE
3
2
1
0
R/W
R/W
R/W
R/W
0
1
0
1
49
Select automatic or manual mute
control for trace driver output1 (DDO1).
0 = Disable auto mute mode
CTRL_OUTPUT1_
AUTO_MUTE
1 = Enable auto mute mode
If CTRL_OUTPUT1_AUTO_MUTE = 0,
then CTRL_OUTPUT1_MANUAL_MUTE
controls mute for DDO1.
Controls mute for trace driver output0
(DDO0) when auto mute
(CTRL_OUTPUT0_AUTO_MUTE = 0) is
disabled.
0 = Unmute output driver
1 = Mute output driver
CTRL_OUTPUT0_
MANUAL_MUTE
Select automatic or manual mute
control for trace driver output0 (DDO0).
0 = Disable auto mute mode
CTRL_OUTPUT0_
AUTO_MUTE
1 = Enable auto mute mode
If CTRL_OUTPUT0_AUTO_MUTE = 0,
then CTRL_OUTPUT0_MANUAL_MUTE
controls mute for DDO0.
GS12341
Final Data Sheet
89 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
RSVD
15:4
R/W
0
Reserved - do not modify.
Controls disable for trace driver output1
(DDO1) when auto disable
CTRL_OUTPUT1_
MANUAL_DISABLE
(CTRL_OUTPUT1_AUTO_DISABLE = 0) is
disabled.
0 = Enable output driver
3
R/W
R/W
R/W
R/W
0
1 = Disable (power down) output driver.
Select automatic or manual disable
control for trace driver output1 (DDO1).
0 = Disable auto disable mode
1 = Enable auto disable mode
If CTRL_OUTPUT1_AUTO_DISABLE = 0,
then
CTRL_OUTPUT1_
AUTO_DISABLE
2
1
0
0
0
0
CTRL_OUTPUT1_MANUAL_DISABLE
controls mute for DDO1.
CONTROL_
OUTPUT_
DISABLE
4A
Controls disable for trace driver output0
(DDO0) when auto disable
(CTRL_OUTPUT0_AUTO_DISABLE = 0) is
disabled.
0 = Enable output driver
CTRL_OUTPUT0_
MANUAL_DISABLE
1 = Disable (power down) output driver.
Select automatic or manual disable
control for trace driver output0 (DDO0).
0 = Disable auto disable mode
1 = Enable auto disable mode
If CTRL_OUTPUT0_AUTO_DISABLE = 0,
then
CTRL_OUTPUT0_
AUTO_DISABLE
CTRL_OUTPUT0_MANUAL_DISABLE
controls mute for DDO0.
GS12341
Final Data Sheet
90 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
RSVD
15:13
R/W
0
Reserved - do not modify.
Controls whether common or per rate
trace driver settings are used for
output1 (DDO1):
0 = Common trace driver settings:
CFG_OUTPUT1_TD_SD_* settings are
used for all rates.
1 = Per rate trace driver settings:
CFG_OUTPUT1_TD_<rate>_* are used
when the Reclocker is locked to <rate>.
CFG_OUTPUT1_TD_12G_* are
used when the Reclocker is not locked.
CTRL_OUTPUT1_
TRDR_PER_RATE
12
R/W
0
CONTROL_
OUTPUT_
SLEW
4B
RSVD
11:5
4
R/W
R/W
28
0
Reserved - do not modify.
Controls whether common or per rate
trace driver settings are used for
output1 (DDO0).
CTRL_OUTPUT0_
TRDR_PER_RATE
Same description as
CTRL_OUTPUT1_TRDR_PER_RATE.
RSVD
RSVD
3:0
R/W
R/W
5
0
Reserved - do not modify.
Reserved - do not modify.
15:4
Controls reclocker bypass for trace
driver output1 (DDO1), when auto
mode is disabled
(CTRL_OUTPUT1_RETIMER_AUTO_BYPA
SS = 0).
CTRL_OUTPUT1_
RETIMER_MANUAL_
BYPASS
3
2
1
R/W
R/W
R/W
0
1
0
0 = Disable reclocker bypass
1 = Enable reclocker bypass
Selects between auto and manual
control of reclocker bypass for trace
driver output1 (DDO1).
0 = Disable auto mode
1 = Enable auto mode
CTRL_OUTPUT1_
RETIMER_AUTO_
BYPASS
CONTROL_
RETIMER_
BYPASS
4C
Controls reclocker bypass for trace
driver output0 (DDO0), when auto
mode is disabled
(CTRL_OUTPUT0_RETIMER_AUTO_BYPA
SS = 0).
CTRL_OUTPUT0_
RETIMER_MANUAL_
BYPASS
0 = Disable reclocker bypass
1 = Enable reclocker bypass
Selects between auto and manual
control of reclocker bypass for trace
driver output0 (DDO0).
0 = Disable auto mode
1 = Enable auto mode
CTRL_OUTPUT0_
RETIMER_AUTO_
BYPASS
0
R/W
R/W
1
0
4D to 4F
RSVD
RSVD
15:0
Reserved - do not modify.
GS12341
Final Data Sheet
91 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
Diagnostic Control Features
RSVD
15
R/W
0
0
Reserved - do not modify.
Adjusts the phase of the clock to the
PRBS checker. Values are:
0 = 0
1 = 90
2 = 180
3 = 270
CFG_PRBS_CHECK_
PHASEADJUST
14:13
R/W
Note: A setting of 0 is ideal for most
applications. Adjustment is not
expected.
Optionally inverts the reclocked data at
the input to the PRBS checker:
0 = no inversion
CFG_PRBS_CHECK_
INVERT
12
R/W
0
1 = data inverted
PRBS_
CHK_CFG
50
Selects pre-divider for PRBS check
measurement timer:
setting: pre-divider value
0 = 4
1 = 8
2 = 16
3 = 32
4 = 64
CFG_PRBS_CHECK_
PREDIVIDER
11:8
R/W
0
5 = 128
6 = 256
7 = 512
8 = 1024
9 = 2048
Selects PRBS check measurement
interval for timed measurements.
See Section 4.4.1 for more details.
CFG_PRBS_CHECK_
MEAS_TIME
7:0
R/W
R/W
3
0
RSVD
15:9
Reserved - do not modify.
Selects between timed and continuous
PRBS check mode.
0 = Selects continuous PRBS check
CTRL_PRBS_CHECK_
TIMED_CONT_B
8
R/W
R/W
0
0
mode.
1 = Selects timed PRBS check mode.
RSVD
7:1
Reserved - do not modify.
PRBS_CHK_
CTRL
51
Set to 1 by host to start a timed
operation.
Set to 0 by host after completion or
abort of the operation (by the device
due to loss of lock) to tell the device that
PRBS result has been read by the host.
See Section 4.4 for more details on PRBS
checker function.
CTRL_PRBS_CHECK_
START
0
R/W
0
GS12341
Final Data Sheet
92 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
RSVD
15:10
R/W
0
Reserved - do not modify.
Selects whether the PRBS generator is
enabled or not
0 = PRBS Generator disabled
1 = PRBS Generator enabled
Note: enabling the PRBS generator does
not automatically override other device
modes such as auto sleep, auto output
mute, auto output disable, etc. These
continue to function normally. The
user/host may need to adjust those
settings to ensure the part will output
the PRBS signal.
CTRL_PRBS_GEN_
ENABLE
9
R/W
0
Select output signal from PRBS
generator as either PRBS7 or divided
clock (divided version of the PRBS
generator clock source):
0 = clock divider (using ratio set by
CTRL_PRBS_GEN_CLK_DIVIDER)
1 = PRBS7
CTRL_PRBS_GEN_
SIGNAL_SELECT
8
R/W
R/W
1
0
PRBS_GEN_
CTRL
52
Selects clock source for PRBS generator:
0 = VCO (free running)
1 = Reserved
CTRL_PRBS_GEN_
CLK_SRC
7:6
2 = Reserved
3 = Data reference PLL (Reclocker
recovered clock)
Selects clock divider ratio for when host
selects divided clock to output on PRBS
generator
CTRL_PRBS_GEN_
CLK_DIVIDER
(CTRL_PRBS_GEN_SIGNAL_SELECT = 0):
0 = divide by 2
1 = divide by 4
2 = divide by 8
3 = divide by 16
5:4
R/W
R/W
0
0
Controls optional inversion of the
generated PRBS pattern:
0 = true sense
CTRL_PRBS_GEN_
INVERT
3
1 = inverted
GS12341
Final Data Sheet
93 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
Select PRBS7 data rate when PRBS clock
source not recovered clock
(CTRL_PRBS_GEN_CLK_SRC ≠ 3)
0 = Reserved - do not use.
1 = MADI
2 = SD
3 = HD
4 = 3G
5 = 6G
6 = 12G
PRBS_GEN_
CTRL
(Continued)
CTRL_PRBS_GEN_
DATA_RATE
52
2:0
R/W
6
(Continued)
7 = Reserved - do not use.
If CTRL_PRBS_GEN_CLK_SRC = 3, then
CTRL_PRBS_GEN_DATA_RATE setting
has no effect and the Reclocker rate is
used (based on automatic rate
detection or manual rate selection).
Additionally, if the device is locked to an
input signal, only the same rate can be
selected for the PRBS generator.
53
54
RSVD
RSVD
15:0
15:0
R/W
R/W
0
0
Reserved - do not modify.
CFG_EYE_MON_TIMEOUT[31:16] Most
significant 16 bits of the measurement
time. This is the time spent measuring
bit errors at each point in the eye scan,
i.e. the time to measure one point in the
eye. Units are in microseconds. The Eye
Scanner scans each point twice and
there is some overhead, so the actual
measurement time is twice the number
entered.
CFG_EYE_MON_
TIMEOUT_MS
EYE_MON_
INT_CFG_0
CFG_EYE_MONT_TIMEOUT[15:0] Least
significant 16 bits of the measurement
time.
CFG_EYE_MON_
TIMEOUT_LS
EYE_MON_
INT_CFG_1
55
56
15:0
15:0
R/W
R/W
64
64
See CFG_EYE_MON_ TIMEOUT_MS
Threshold of bit error counts to define
good vs bad points in eye for shape
scan.
CFG_EYE_BER_
THRESHOLD
EYE_MON_
INT_CFG_2
See Section 4.5 for further details.
GS12341
Final Data Sheet
94 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
The vertical offset slice that will be used
for eye shape queries. Offset values: 0 to
255d. 0 represents the most negative
slice since 128d is the 0V slice level and
255d is the most positive slice level.
Default is 128d
CFG_EYE_DEFAULT_
VERT_OFFSET
15:8
R/W
80
EYE_MON_
INT_CFG_3
57
RSVD
7:3
2
R/W
R/W
0
0
Reserved - do not modify.
Eye monitor initialization bit. Set HIGH
during Device Power-up Sequence. See
Section 4.9.12 for details.
CFG_EYE_INIT_RESET
RSVD
RSVD
RSVD
RSVD
1:0
15:0
15:0
15
R/W
R/W
R/W
R/W
2
D982
100
0
Reserved - do not modify.
Reserved - do not modify
Reserved - do not modify
Reserved - do not modify.
58
59
RSVD
RSVD
Starting phase offset.
Valid range is 0 to 127d.
Reset value must be used for shape
scan.
CTRL_EYE_PHASE_
START
14:8
7
R/W
R/W
0
0
EYE_MON_
SCAN_CTRL_0
5A
RSVD
Reserved - do not modify.
Phase offset limit. Valid range is 0 to
127d. CTRL_EYE_PHASE_STOP must be
greater or equal to
CTRL_EYE_PHASE_START. Reset value
must be used for shape scan.
CTRL_EYE_PHASE_
STOP
6:0
15
R/W
R/W
7F
0
RSVD
Reserved - do not modify.
Unsigned value for phase step size. Valid
values are 1,2, and 4.
Reset value must be used for shape
scan.
CTRL_EYE_PHASE_
STEP
14:8
R/W
1
Behaviour is undefined for other values.
In order to use a step size of 2 or 4,
CTRL_EYE_PHASE_START and
CTRL_EYE_PHASE_STOP must be set to
their default values.
EYE_MON_
SCAN_CTRL_1
5B
RSVD
7
R/W
R/W
0
0
Reserved - do not modify.
Starting voltage offset.
Valid range is 0 to 255d.
CTRL_EYE_VERT_
OFFSET_START
6:0
GS12341
Final Data Sheet
95 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
Voltage offset limit.
Valid range is 0 to 255d.
CTRL_EYE_VERT_
OFFSET_STOP
CTRL_EYE_VERT_OFFSET_STOP must be
greater or equal to
CTRL_EYE_VERT_OFFSET_START. Reset
value must be used for shape scan.
15:8
7
R/W
R/W
FF
0
RSVD
Reserved - do not modify.
EYE_MON_
SCAN_CTRL_2
5C
Unsigned value for voltage offset step
size.
Valid values are 1,2, and 4.
CTRL_EYE_VERT_
OFFSET_STEP
Behaviour is undefined for other values.
In order to use a step size of 2 or 4,
CTRL_EYE_VERT_ OFFSET_START and
CTRL_EYE_VERT_ OFFSET_STOP must
be set to their default values.
6:0
R/W
1
RSVD
15:9
8
R/W
R/W
R/W
0
0
0
Reserved - do not modify.
Selects whether the eye monitor should
perform an eye scan or eye shape
capture:
0 = Selects eye scan (new or continued).
1 = Selects eye shape capture.
CTRL_EYE_SHAPE_
SCAN_B
RSVD
7:2
Reserved - do not modify.
Power control for the eye monitor:
0 = Power down the eye monitor
1 = Power up the eye monitor
Host is permitted to change this any
time between eye scans (but not
between partial eye scans).
This must be set to 1 to run an eye scan.
Behaviour is undefined if host sets
CTRL_EYE_MON_START = 1 without
setting this bit to 1.
CTRL_EYE_MON_
POWER_CTRL
1
R/W
0
EYE_MON_
SCAN_CTRL_3
5D
Part of a four way handshake with
STAT_EYE_MON_STATUS:
0 = Set by host to tell the device to clear
the status bit.
1 = Set by host only in order to
begin/continue an eye scan or start an
eye shape capture.
See Section 4.5 for more details on
implementing the four way hand shake
for this operation.
CTRL_EYE_MON_START
0
R/W
—
0
5E to 5F
60 to 7E
RSVD
RSVD
RSVD
RSVD
15:0
—
—
Reserved.
Factory Settings
15:0
—
Reserved.
GS12341
Final Data Sheet
96 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-4: Status Register Descriptions
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
80
RSVD
RSVD
15:0
15:0
RO
—
Reserved.
This register contains the first part of the
device configuration version. Please
contact your local technical sales
representative for more details.
81
82
83
VERSION_0
VERSION_1
VERSION_2
STAT_CONFIG_VER0
STAT_CONFIG_VER1
STAT_HW_VERSION
RO
RO
RO
—
This register contains the second part of
the device configuration version. Please
contact your local technical sales
representative for more details.
15:0
15:0
—
—
This register contains the devices
identification, including revision. Please
contact your local technical sales
representative for more details.
Count of primary carrier detection
status changes (ignoring CLI squelch).
The count saturates at 255d (0xFF).
See Section 4.9.11 for procedure to clear
the counts.
STAT_CNT_PRI_CD_
CHANGES
15:8
7:0
RO
RO
—
—
Count of secondary carrier detection
status changes (based on
STAT_CLI_SQUELCH if CFG_SEC_CD_
INCL_CLI_SQUELCH = 1; otherwise this
parameter is based on STAT_PRI_CD).
The count saturates at 255d (0xFF).
STICKY_
COUNTS_0
84
STAT_CNT_SEC_CD_
CHANGES
See Section 4.9.11 for procedure to clear
the counts.
Count of rate changes.
The count saturates at 255d (0xFF).
See Section 4.9.11 for procedure to clear
the counts.
STAT_CNT_RATE_
CHANGES
15:8
7:0
RO
RO
—
—
STICKY_
COUNTS_1
85
Count of PLL lock status changes.
The count saturates at 255d (0xFF).
See Section 4.9.11 for procedure to clear
the counts.
STAT_CNT_PLL_
LOCK_CHANGES
GS12341
Final Data Sheet
97 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-4: Status Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
RSVD
15
RO
—
Reserved
Clear counts status:
0 = Idle
1 = Reserved
2 = indicates device has cleared the
sticky counts
3 = Reserved.
STAT_CLEAR_COUNTS_
STATUS
14:13
RO
—
Part of a four way handshake with
CTRL_CLEAR_COUNTS.
See Section 4.9.11 for more details on
implementing the four way handshake
for this operation.
PLL lock status:
STAT_LOCK
STAT_SLEEP
12
11
RO
RO
—
—
0 = PLL is unlocked
1 = PLL is locked
Sleep status:
0 = Device is not in sleep
1 = Device is currently in sleep
CURRENT_
STATUS_0
RSVD
RSVD
10
9
RO
RO
—
—
Reserved
86
Reserved
Cable Equalizer Squelch status.
STAT_CLI_SQUELCH
8
RO
—
0 = CLI squelch is de-asserted
1 = CLI squelch is asserted
Trace driver output1 (DDO1) output
status:
0 = Mission Trace Driver <= SD rate
1 = Mission Trace Driver HD rate
2 = Mission Trace Driver 3G rate
3 = Mission Trace Driver 6G rate
4 = Mission Trace Driver 12G
5 = Reserved
STAT_OUTPUT1_MODE
7:4
RO
—
6 = Muted
7 = Disabled
Note: The device will only indicate 1 - 4
if the per rate settings are enabled,
otherwise, it will always indicate 0 if it is
locked to a valid signal and the output is
not muted or disabled. See Section 4.7.3
for more details on per rate settings.
GS12341
Final Data Sheet
98 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-4: Status Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
Trace driver output0 (DDO0) output
status:
0 = Mission Trace Driver <= SD rate
1 = Mission Trace Driver HD rate
2 = Mission Trace Driver 3G rate
3 = Mission Trace Driver 6G rate
4 = Mission Trace Driver 12G
5 = Reserved
CURRENT_
STATUS_0
(Continued)
86
STAT_OUTPUT0_MODE
3:0
RO
—
6 = Muted
7 = Disabled
(Continued)
Note: The device will only indicate 1 - 4
if the per rate settings are enabled,
otherwise, it will always indicate 0 if it is
locked to a valid signal and the output is
not muted or disabled. See Section 4.7.3
for more details on per rate settings.
Trace driver output1 (DDO1) disable
status:
STAT_OUTPUT1_
DISABLE
15
14
13
12
RO
RO
RO
RO
—
—
—
—
0 = DDO1 is not disabled
1 = DDO1 is disabled
Trace driver output0 (DDO0) disable
status:
STAT_OUTPUT0_
DISABLE
0 = DDO0 is not disabled
1 = DDO0 is disabled
Trace driver output1 (DDO1) mute
status:
STAT_OUTPUT1_
MUTE
0 = DDO1 is not muted
1 = DDO1 is muted
CURRENT_
STATUS_1
Trace driver output0 (DDO0) mute
status:
87
STAT_OUTPUT0_MUTE
0 = DDO0 is not muted
1 = DDO0 is muted
Trace driver output1 (DDO1) reclocker
status:
STAT_OUTPUT1_
RETIMER_BYPASS
11
10
RO
RO
—
—
0 = Reclocker path to DDO1 is not
bypassed
1 = Reclocker path to DDO1 is bypassed
Trace driver output 0 (DDO0) reclocker
status:
STAT_OUTPUT0_
RETIMER_BYPASS
0 = Reclocker path to DDO0 is not
bypassed
1 = Reclocker path to DDO0 is bypassed
GS12341
Final Data Sheet
99 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-4: Status Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
Secondary carrier detection status
(based on STAT_CLI_SQUELCH if
CFG_SEC_CD_INCL_CLI_SQUELCH=1;
otherwise this parameter is based on
STAT_PRI_CD).
STAT_SEC_CD
9
RO
—
0 = Secondary carrier is not detected
1 = Secondary carrier is detected
Primary carrier detection status
(ignoring CLI squelch).
STAT_PRI_CD
8
7
RO
RO
—
—
0 = Primary carrier is not detected
1 = Primary carrier is detected
CEQ (Cable Equalizer) bypass status.
CURRENT_
STATUS_1
(Continued)
87
STAT_CEQ_BYPASS
0 = CEQ is not bypassed
(Continued)
1 = CEQ is bypassed
RSVD
RSVD
6:5
4:3
RO
RO
—
—
Reserved - do not modify.
Reserved
Rate at which the Reclocker is locked.
0 = Unlocked
1 = MADI (125Mb/s)
2 = SD (270Mb/s)
3 = HD (1.485Gb/s)
4 = 3G (2.97Gb/s)
STAT_DETECTED_RATE
2:0
RO
—
5 = 6G (5.94Gb/s)
6 = 12G (11.88Gb/s)
7 = Reserved
RSVD
15:8
7:0
RO
RO
—
—
Reserved
SDI cable length indication. Range = 0
to 64d (64d is max cable reach
determined for specific rate, cable type,
and launch swing compensation).
0xFF= Unknown cable length.
88
89
EQ_GAIN_IND
STAT_CABLE_LEN_
INDICATION
PRBS checker error count. Cleared to 0
at the start of a measurement. Updated
by the device on completion of a
measurement. Value is undefined in
case of abort due to loss of Reclocker
lock (STAT_PRBS_CHECK_LAST_ABORT
= 1).
STAT_PRBS_CHK_
ERR_CNT
PRBS_
CHK_ERR_CNT
15:0
RO
—
GS12341
Final Data Sheet
100 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-4: Status Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
RSVD
15:10
RO
—
Reserved
PRBS no data status:
0 = Normal
1 = No data transitions were seen during
the previous PRBS check. This bit is set
to 1 to indicate that the input data was
all 0's during a PRBS check. When that
happens, the error count will be zero
when in fact there was no valid PRBS
pattern.This bit is updated by the device
on completion of a measurement. It
retains its value until the next PRBS
check operation is requested. Value is
undefined in case of abort
STAT_PRBS_CHECK_
NODATA
9
RO
—
(STAT_PRBS_CHECK_LAST_ABORT = 1).
Value does not increment during a
measurement until it completes.
PRBS abort status.
0 = Normal.
STAT_PRBS_CHECK_
LAST_ABORT
1 = PRBS check was aborted due to loss
of lock or sleep.
This bit retains its value until the next
PRBS operation is requested.
PRBS_
CHK_STATUS
8A
8
RO
RO
—
—
RSVD
7:2
Reserved
Status for PRBS checker:
0 = PRBS check idle; ready for new
operation.
1 = PRBS check timed or continuous
operation in progress.
2 = PRBS check timed operation
completed (success)
STAT_PRBS_CHECK_
STATUS
3 = PRBS check timed or continuous
operation aborted (error). Part of a four
way handshake with
1:0
RO
—
CTRL_PRBS_CHECK_START
(Section 4.4).Abort will be reported if
loss of lock or sleep occurred during a
PRBS check operation or those
conditions existed when the operation
was requested by the host.
EYE_MON_
SCAN_
SIZE_OUTPUT
The size in bytes of the last partial scan
segment.
8B
STAT_EYE_IMAGE_SIZE
15:0
RO
—
GS12341
Final Data Sheet
101 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-4: Status Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
Left Edge Voltage Offset returned from
shape scan.
STAT_EYE_SHAPE_
LEFT_EDGE_OFFSET
Offset values 0 to 255d, 0 represents
most negative voltage, 127d is 0V 255d
is most positive voltage.
15:8
7:0
RO
—
—
—
—
—
—
—
—
EYE_MON_
SHAPE_
OUTPUT_0
8C
Left Edge Phase returned from shape
scan.
STAT_EYE_SHAPE_
LEFT_EDGE_PHASE
RO
RO
RO
RO
RO
RO
RO
Phase values 0 to 127d.
Positive (top) Edge Voltage Offset
returned from shape scan.
STAT_EYE_SHAPE_
POS_EDGE_OFFSET
15:8
7:0
Offset values 0 to 255d, 0 represents
most negative voltage, 127d is 0V 255d
is most positive voltage.
EYE_MON_
SHAPE_
8D
8E
8F
OUTPUT_1
Positive (top) Edge Phase returned from
shape scan.
STAT_EYE_SHAPE_
POS_EDGE_PHASE
Phase values 0 to 127d.
Right Edge Voltage Offset returned from
shape scan.
STAT_EYE_SHAPE_
RIGHT_EDGE_OFFSET
15:8
7:0
Offset values 0 to 255d, 0 represents
most negative voltage, 127d is 0V 255d
is most positive voltage.
EYE_MON_
SHAPE_
OUTPUT_2
Right Edge Phase returned from shape
scan.
STAT_EYE_SHAPE_
RIGHT_EDGE_PHASE
Phase values 0 to 127d.
Negative (bottom) Edge Voltage Offset
returned from shape scan.
STAT_EYE_SHAPE_
NEG_EDGE_OFFSET
15:8
7:0
Offset values 0 to 255d, 0 represents
most negative voltage, 127d is 0V 255d
is most positive voltage.
EYE_MON_
SHAPE_
OUTPUT_3
Negative (bottom) Edge Phase returned
from shape scan.
STAT_EYE_SHAPE_
NEG_EDGE_PHASE
Phase values 0 to 127d.
GS12341
Final Data Sheet
102 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
Table 5-4: Status Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
RSVD
15:9
RO
—
—
—
Reserved
Full scan status:
0 = Full scan complete.
1 = Partial scan complete.
On completion of an eye monitor eye
scan (CRTL_EYE_SHAPE_SCAN_B = 0),
indicates whether the eye monitor
completed the full scan or a partial scan.
Undefined for eye shape scan
STAT_EYE_SCAN_
PARTIAL_OR_FULL
8
RO
RO
(CTRL_EYE_SHAPE_SCAN_B = 1).
RSVD
7:2
Reserved
EYE_MON_
STATUS
Eye monitor status:
0 = Eye monitor idle; ready for new
90
operation
1 = Eye monitor operation in progress
2 = Eye monitor operation completed
(success)
3 = Eye monitor operation aborted
(error). Part of a four way handshake
with CTRL_EYE_MON_START, see
Section 4.5 for procedure.Abort will be
reported by device if loss of lock or sleep
occurred during an eye monitor
operation or those conditions existed
when the operation was requested by
the host.
STAT_EYE_MON_
STATUS
1:0
RO
—
—
91 - BF
RSVD
RSVD
15:0
—
Reserved
GS12341
Final Data Sheet
103 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
6. Application Information
6.1 Typical Application Circuit
VCC1V8
VCC1V8
29
470nF
10μF
100nF
10μF
40
39 38
37
36
35
34
33 32
31
30
1
2
3
VEE_SDI
4.7μF
4.7μF
28
VEEO
SDI
27
26
DDO0
OUT
OUT
2Ω
SDI_TERM
DDO0
Note: Pins 24/25 both
require a 100nF capacitor
VCC1V8
25
24
VCCO_0
VCCO_1
VCC_SDI
4
5
VCC1V8
GS12341
Note: The device central paddle is not an electrical
connection. Refrain from connecting device pins to
the central paddle.
1μF
100nF x2
RSVD
RSVD
23
22
OUT
OUT
DDO1/RCO
6
7
8
DDO1/RCO
VEEO
21
RSVD
VEE_SDI
9
10
11
12
13 14
15
16
17
18
19
20
VCC1V8
100nF
VCC1V8
100nF
Figure 6-1: Typical Application Circuit
Note 1: 4.7μF AC-coupling capacitors are required on DDO0/DDO0 and DDO1/RCO,
DDO1/RCO when the downstream IC has an input common mode range that is
incompatible with the output common mode range of the GS12341.
Note 2: Although 1μF AC-coupling capacitors may be adequate at the input of SDI for
most applications, it is recommended to use 4.7μF capacitors for increased margin to
pathological signals.
Note 3: It is recommended that separate filtered supplies are used for the following two
groups: (VCC_SDI, VCC_CORE), (VCCO1P8_0, VCCO1P8_1, VDD, VCCO_0*, VCCO_1*).
*Assuming VCCO_0 and VCCO_1 supplies are chosen as 1.8V.
Multiple devices can share the same filtered supply plane.
GS12341
Final Data Sheet
104 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
7. Package & Ordering Information
7.1 Package Dimensions
DIMENSIONS
A
D
MILLIMETERS
MIN NOM MAX
0.80 0.90 1.00
B
E
DIM
A
0.05
0.02
A1 0.00
A2
(0.02)
0.20 0.25
0.15
b
D
PIN 1
INDICATOR
5.95 6.00 6.05
(LASER MARK)
D1 3.45 3.60 3.70
E
3.95 4.00 4.05
E1 1.43 1.58 1.68
e
L
N
0.40 BSC
0.30 0.40 0.50
40
aaa
bbb
0.08
0.10
A
SEATING
PLANE
aaa C
C
A1
A2
D1
LxN
E/1
E1
2
1
N
bxN
0.30 x 45°
e/2
bbb
C A B
e
D/2
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
3. DIMENSION OF LEAD WIDTH APPLIES TO TERMINAL AND IS MEASURED BETWEEN
0.15 to 0.30mm FROM THE TERMINAL TIP.
Figure 7-1: Package Dimensions
GS12341
Final Data Sheet
105 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
7.2 Recommended PCB Footprint
0.20
0.60
Pin #1
3.60
0.40
5.20
Figure 7-2: Recommended PCB Footprint
7.3 Packaging Data
Table 7-1: Packaging Data
Parameter
Value
Package Type
6mm x 4mm 40-pin QFN
Moisture Sensitivity Level
3
Junction to Air Thermal Resistance, j-a (at zero airflow)
Junction to Board Thermal Resistance, j-b
Junction to Case Thermal Resistance, j-c
40.0°C/W
32.0°C/W
36.0°C/W
<1.0°C/W
Yes
Junction-to-Top Characterization Parameter, Psi,
Pb-free and RoHS compliant
GS12341
Final Data Sheet
106 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
7.4 Marking Diagram
GS12341
XXXXE3
YYWW
XXXX = Last 4 Digits (excluding decimal) of SAP
Batch Assembly (FIN) as listed on Packing Slip
E3 = Pb-free & Green Indicator
YYWW = Date Code (Example: 1952)
Figure 7-3: Marking Diagram
7.5 Solder Reflow Profiles
Temperature
60-150 sec.
20-40 sec.
260°C
250°C
3°C/sec max
217°C
6°C/sec max
200°C
150°C
25°C
Time
60-180 sec. max
8 min. max
Figure 7-4: Maximum Pb-free Solder Reflow Profile
GS12341
Final Data Sheet
107 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
7.6 Ordering Information
Table 7-2: Ordering Information
Minimum Order
Part Number
Format
Quantity
GS12341-INE3
GS12341-INTE3
GS12341-INTE3Z
490
250
Tray
Tape and Reel
Tape and Reel
2500
GS12341
Final Data Sheet
108 of 109
Semtech
www.semtech.com
Rev.1
Proprietary & Confidential
PDS-061928
August 2019
IMPORTANT NOTICE
Information relating to this product and the application or design described herein is believed to be reliable, however such information is
provided as a guide only and Semtech assumes no liability for any errors in this document, or for the application or design described herein.
Semtech reserves the right to make changes to the product or this document at any time without notice. Buyers should obtain the latest relevant
information before placing orders and should verify that such information is current and complete. Semtech warrants performance of its
products to the specifications applicable at the time of sale, and all sales are made in accordance with Semtech’s standard terms and conditions
of sale.
SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS,
DEVICES OR SYSTEMS, OR IN NUCLEAR APPLICATIONS IN WHICH THE FAILURE COULD BE REASONABLY EXPECTED TO RESULT IN PERSONAL
INJURY, LOSS OF LIFE OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS
UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such
unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs damages and attorney fees which could arise.
The Semtech name and logo are registered trademarks of the Semtech Corporation. All other trademarks and trade names mentioned may be
marks and names of Semtech or their respective companies. Semtech reserves the right to make changes to, or discontinue any products
described in this document without further notice. Semtech makes no warranty, representation or guarantee, express or implied, regarding the
suitability of its products for any particular purpose. All rights reserved.
© Semtech 2019
Contact Information
Semtech Corporation
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111, Fax: (805) 498-3804
www.semtech.com
GS12341
Final Data Sheet
109 of 109
Semtech
Rev.1
109Proprietary & Confidential
PDS-061928
August 2019
相关型号：
GS12401-1011-9F
Board Connector, 40 Contact(s), 1 Row(s), Female, Straight, Solder Terminal, Receptacle, LEAD FREE
FOXCONN
GS12441
Board Stacking Connector, Female, Right Angle, Surface Mount Terminal, Receptacle, LEAD FREE
FOXCONN
GS12441-0011-8F
Board Stacking Connector, 44 Contact(s), 2 Row(s), Female, Right Angle, 0.02 inch Pitch, Surface Mount Terminal, Locking, Black Insulator, Receptacle, LEAD FREE
FOXCONN
GS1284218GB-200I
Cache SRAM, 8MX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, ROHS COMPLIANT, FPBGA-119
GSI
GS1284218GB-200IT
Cache SRAM, 8MX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, ROHS COMPLIANT, FPBGA-119
GSI
GS1284218GB-200VIT
Cache SRAM, 8MX18, 7.5ns, CMOS, PBGA119, 22 X 14 MM, 1.27 MM PITCH, ROHS COMPLIANT, FPBGA-119
GSI
©2020 ICPDF网 联系我们和版权申明