SC1157CS [SEMTECH]
PROGRAMMABLE SYNCHRONOUS DC/DC CONTROLLER FOR ADVANCED PROCESSORS; 可编程同步DC / DC控制器的先进的处理器
| 型号： | SC1157CS |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | PROGRAMMABLE SYNCHRONOUS DC/DC CONTROLLER FOR ADVANCED PROCESSORS |
| 文件： | 总5页 (文件大小：74K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS
SC1157
Preliminary - August 7, 2000
TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com
DESCRIPTION
FEATURES
The SC1157 is a low-cost, full featured, synchronous
voltage-mode controller designed for use in single
ended power supply applications where efficiency is of
primary concern. Synchronous operation allows for the
elimination of heat sinks in many applications. The
SC1157 is ideal for implementing DC/DC converters
needed to power advanced microprocessors such as
Pentium® ll (Klamath), in both single and multiple pro-
cessor configurations. Internal level-shift, high-side
drive circuitry, and preset shoot-thru control, allows for
use of inexpensive n-channel power switches.
•= Low cost / full featured
•= Synchronous operation
•= 4 Bit VID DAC programmable output
(1% tolerance)
•= Designed to meet Intel VRM8.2 (Pentium® II)
•= 1.5% Reference
APPLICATIONS
•= Pentium® II Core Supply
•= Multiple Microprocessor Supplies
•= Voltage Regulator Modules (VRM)
•= Programmable Power Supplies
•= High Efficiency DC/DC Conversion
SC1157 features include an integrated 4-bit VID DAC,
temperature compensated voltage reference, triangle
wave oscillator, current limit comparator, frequency
shift over-current protection, and an internally compen-
sated error amplifier.
ORDERING INFORMATION
The SC1157 operates at a fixed 140KHz, providing an
optimum compromise between efficiency, external
component size, and cost.
DEVICE(1)
PACKAGE(2) TEMP. RANGE (TJ)
SO-16NB 0 - 125°C
SC1157CS.TR
Note:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
(2) “NB” indicates 150 MIL body.
PIN CONFIGURATION
BLOCK DIAGRAM
Top View
VCC
CS- CS+
SHUTDOWN
CURRENT
LIMIT
BSTH
DH
REF
REF
+
-
70mV
LEVEL SHIFT AND
HIGH SIDE DRIVE
VID3
+
-
-
+
D/A
VID2
VID1
VID0
ERROR
AMP
VOSENSE
GND
R
S
SHOOT-THRU
CONTROL
Q
OSCILLATOR
BSTL
DL
(16-Pin SOIC)
SYNCHRONOUS
MOSFET DRIVE
PGND
1
Pentium is a registered trademark of Intel Corporation
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS
SC1157
Preliminary - August 7, 2000
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Maximum
-0.3 to 7
± 1
Units
VCC to GND
VIN
V
V
V
PGND to GND
BST to GND
-0.3 to 15
Thermal Resistance Junction to Case
30
130
°C/W
°C/W
°C
θJC
θJA
Thermal Resistance Junction to Ambient
Operating Temperature Range
TA
0 to 70
-65 to +150
300
Storage Temperature Range
TSTG
TLEAD
ESD
°C
Lead Temperature (Soldering) 10 sec
ESD Rating (Human Body Model)
°C
1.5
kV
ELECTRICAL CHARACTERISTICS
Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; FB = VO; 0mV < (CS(+) - CS(-)) < 60mV; TJ = 25oC
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Output Voltage
See Table 1.
Supply Voltage
VCC
CC = 5.0
IO = 0.3A to 15A(1)
All VID codes(1)
VOSENSE to VO
4.5
7
V
mA
%
Supply Current
V
8
1
15
Load Regulation
Line Regulation
+0.15
35
%
Gain (AOL)
dB
mV
kHz
V
Current Limit Voltage
Oscillator Frequency
Buffered Reference Voltage
Oscillator Max Duty Cycle
DH Sink/Source Current
DL Sink/Source Current
Dead Time
60
70
80
125
140
1.25
95
155
IREF ≤=1mA
90
1
%
BSTH - DH = 4.5V, DH - PGNDH = 3V
BSTL - DL = 4.5V, DL - PGNDL = 3V
A
1
A
50
30
100
100
ns
uA
VID Pin Source current
VIDx < 2.4V
NOTE:
(1) Specification refers to application circuit (Figure 1.).
(2) This device is ESD sensitive. Use of standard ESD handling precautions is required.
2
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS
SC1157
Preliminary - August 7, 2000
PIN DESCRIPTION
Pin #
Pin Name
GND
Pin Function
1
Small Signal Analog and Digital Ground
Buffered Reference output
2
3
4
5
6
REF
VCC
Chip Supply Voltage
CS(-)
CS(+)
PGND
Current Sense Input (negative)
Current Sense Input (positive)
Power Ground for High and Low Side Drivers
7
8
DH
DL
High Side Driver Output
Low Side Driver Output
9
BSTL
Vcc for Low Side Driver (Boost)
Vcc for High Side Driver (Boost)
10
11
12
13
14
15
16
BSTH
SHUTDOWN
VOSENSE
VID3(1)
VID2(1)
VID1(1)
Logic Low shuts down the converter; High or open for normal operation.
Top end of internal feedback chain
Programming Input (MSB)
Programming Input
Programming Input
VID0(1)
Programming Input (LSB)
NOTE:
(1) All logic level inputs and outputs are open collector TTL compatible.
PIN CONFIGURATION
3
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS
SC1157
Preliminary - August 7, 2000
OUTPUT VOLTAGE TABLE
Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; FB = VO; 0mV < (CS(+) - CS(-)) < 60mV;
TJ = 0°C to 85°C
PARAMETER
CONDITIONS
VID
MIN
TYP
MAX
UNITS
3210
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Output Voltage(1)
IO = 2A in Application Circuit
(Figure 1)
1.287
1.337
1.386
1.436
1.485
1.535
1.584
1.634
1.683
1.733
1.782
1.832
1.881
1.931
1.980
2.030
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
2.050
1.313
1.364
1.414
1.465
1.515
1.566
1.616
1.667
1.717
1.768
1.818
1.869
1.919
1.970
2.020
2.070
V
NOTE:
(1) All VID codes not specifically listed are invalid and cause shutdown exactly as if the shutdown pin had been
asserted.
THEORY OF OPERATION
The voltage at the VOSENSE pin is applied, through the internal precision resistor feedback chain, to the inverting
input of the error amplifier. The non-inverting input of the error amplifier is supplied with a DC voltage derived by
the DAC from the internal trimmed bandgap voltage reference. The output of the error amplifier is compared to the
triangular output of the internal oscillator to generate a fixed frequency, variable duty cycle pulse train. The internal
oscillator uses an on-chip capacitor and precision trimmed current sources to set the frequency to 100 kHz.
The generated pulse train is gated with the output of the current limit latch and the inhibit signal to produce a drive
signal for the upper FET. It is also inverted to produce a drive signal for the lower FET. These FET drive signals
are modified by the “shoot-through control” circuitry so that the top FET turn-on is delayed until the bottom FET has
turned off, and visa-versa.
The current limit latch is set (ending the upper FET drive pulse early) if the current limit comparator indicates an
overcurrent condition. The latch is reset at the start of each oscillator period.
4
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS
SC1157
Preliminary - August 7, 2000
OUTLINE DRAWING SO-16
Jedec MS-012AC
LAND PATTERN SO-16
ECN00-1243
5
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
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