SC1165CSW.TRT [SEMTECH]
Switching Controller, Voltage-mode, 1A, 225kHz Switching Freq-Max, PDSO24, SOIC-24;
| 型号： | SC1165CSW.TRT |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Switching Controller, Voltage-mode, 1A, 225kHz Switching Freq-Max, PDSO24, SOIC-24 开关 光电二极管 |
| 文件： | 总14页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC1164 & SC1165
Programmable Synchronous DC/DC
Converter, Dual LDO Controller
POWER MANAGEMENT
Features
Description
The SC1164/5 combines a synchronous voltage mode con-
troller with two low-dropout linear regulators providing
most of the circuitry necessary to implement three DC/
DC converters for powering advanced microprocessors
such as Pentium® II .
uSynchronous design, enables no heatsink solution.
u95% efficiency (switching section).
u5 bit DAC for output programmability.
uOn chip power good function.
uDesigned for Intel Pentium® ll VRM8.1 requirements.
u1.5V, 2.5V or Adjustable @ 1% for linear section.
The SC1164/5 switching section features an integrated 5
bit D/A converter, pulse by pulse current limiting, inte-
grated power good signaling, and logic compatible shut-
down. The SC1164/5 switching section operates at a fixed
frequency of 200kHz, providing an optimum compromise
between size, efficiency and cost in the intended applica-
tion areas. The integrated D/A converter provides pro-
grammability of output voltage from 2.0V to 3.5V in 100mV
increments and 1.30V to 2.05V in 50mV increments with
no external components.
Applications
u
u
u
u
Pentium® ll microprocessor supplies
Flexible motherboards
1.3V to 3.5V microprocessor supplies
Programmable triple power supplies
The SC1164/5 linear sections are low dropout regulators.
The SC1164 supplies 1.5V for GTL bus and 2.5V for non-
GTL I/O, the SC1165 features adjustable LDO voltages.
Typical Application Circuit
12V
5V
+
4.7uF
10
+
0.1uF
1500uF
x2
U4
0.1uF
5
7
9
VCC
CS+
CS-
0.1uF
P W R G O O D
VID0
8
P W R G O O D
VID0
VID1
VID2
VID3
VID4
EN
22
21
20
19
18
16
1
17
15
11
14
13
10
12
6
IRLR3103N
1.00k
2.32k
VOSENSE
BSTH
DH
VID1
5mOhm
2R2
IRLR3103N
VID2
VCC_CORE
1.9uH
VID3
BSTL
VID4
DL
+
2R2
EN
0.1uF
PGNDH
PGNDL
OVP
AGND
LDOV
23
24
4
1500uF
x4
2
GATE2
LDOS2
GATE1
LDOS1
OVP
3
SC1164/5CSW
3.3V
+
1.5V
2.5V
330uF
IRLR024N
IRLR024N
+
+
330uF
330uF
1
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Revision 1, January 2001
SC1164 & SC1165
POWER MANAGEMENT
Absolute Maximum Ratings
Parameter
Symbol
Maximum
Units
VCC to AGND
VIN
-0.3 to +7
±1
V
V
PGNDL, PGNDH to GND
BSTH to PGNDH, BSTL to PGNDL
Operating Temperature Range
Junction Temperature Range
Storage Temperature Range
Lead Temperature (Soldering) 10 Sec.
Thermal Impedance Junction to Ambient
Thermal Impedance Junction to Case
VBOOST
TA
-0.3 to +15
0 to +70
0 to +125
-65 to +150
300
V
°C
TJ
°C
TSTG
TL
°C
°C
80
°C/W
°C/W
θJA
25
θJC
Electrical Characteristics
Unless specified: VIN=4.75V to 5.25V; AGND=PGNDH=PGNDL=0V; VOSENSE=VO; 0mV< (CS+-CS-)< 60mV; LDOV= VBOOST= 11.4V to 12.6V; TA = 25°C
Parameter
Conditions
Min
Typ
Max
Units
Switching Section
Output Voltage
IO = 2A in Application Circuit
See Output Voltage Table
Supply Voltage
4.5
7
V
mA
%
Supply Current
VIN = 5.0V
8
1
15
Load Regulation
IO = 0.8A to 15A
Line Regulation
0.5
%
Minimum operating voltage
Current Limit Voltage
Oscillator Frequency
Oscillator Max Duty Cycle
Peak DH Sink/Source Current
Peak DL Sink/Source Current
Output Voltage Tempco
Gain (AOL)
4.2
85
V
55
175
90
1
70
200
95
mV
kHz
%
225
BSTH - DH = 4.5V, DH - PGNDH = 2V
BSTL - DL = 4.5V, DL - PGNDL = 2V
A
1
A
65
35
ppm/oC
dB
%
VOSENSE to VO
VOVP = 3.0V
OVP threshold voltage
OVP source current
Power good threshold voltage
Dead time
120
10
85
50
mA
%
115
100
ns
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2001 Semtech Corp.
2
SC1164 & SC1165
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Linear Sections
Quiescent current
IQ
LDOV = 12V
5
mA
V
Output Voltage (LDO1 SC1182)
Output Voltage (LDO2 SC1182)
Reference Voltage (SC1183)
Feedback Pin Bias Current (SC1183)
Gain (AOL)
2.475
1.485
1.252
2.500
1.500
1.265
2.525
1.515
1.278
10
V
VREF
IFB
V
µA
dB
%
LDOS (1, 2) to GATE (1, 2)
IO = 0 to 8A
90
1
Load Regulation
0.3
0.3
Line Regulation
%
Output Impedance
VGATE = 6.5V
kΩ
NOTE:
(1) This device is ESD sensitive. Use of standard ESD handling precautions is required.
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2001 Semtech Corp.
3
SC1164 & SC1165
POWER MANAGEMENT
Pin Configuration
Ordering Information
TOP VIEW
(1)
Part Number
Package
Linear
Temp
Voltage
Range (TJ)
AGND
GATE1
LDOS1
LDOS2
VCC
1
24
23
22
21
20
19
18
17
16
15
14
13
GATE2
LDOV
VID0
2
SC1164CSW.TR
SC1165CSW.TR
SO-24
SO-24
1.5V/2.5V 0° to 125°C
Adjustable 0° to 125°C
3
4
VID1
5
VID2
OVP
6
VID3
PWRGOOD
CS-
7
VID4
Note:
8
VOSENSE
EN
(1) Only available in tape and reel packaging. A reel
contains 1000 devices.
CS+
9
PGNDH
DH
10
11
12
BSTH
BSTL
DL
PGNDL
(24 Pin SOIC)
Pin Descriptions
Pin #
Pin Name
Pin Function
1
2
AGND
GATE1
LDOS1
LSOS2
VCC
Small Signal Analog and Digital Ground
Gate Drive Output LDO1
3
Sense Input for LDO1
4
Sense Input for LDO2
5
Input Voltage
6
OVP
PWRGOOD(1)
High signal out if VO > setpoint +20%
Open collector logic output, high if VO within 10% of setpoint
Current Sense Input (negative)
Current Sense Input (positive)
Power Ground for High Side Switch
High Side Driver Output
7
8
CS-
9
CS+
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PGNDH
DH
PGNDL
DL
Power Ground for Low Side Swtch
Low side Driver Output
BSTL
Supply for Low Side Driver
BSTH
EN (1)
Supply for High Side Driver
Logic low shuts down the converter. High or open for normal operation.
Top end of internal feedback chain
Programming Input (MSB)
VOSENSE
VID4 (1)
VID3 (1)
VID2 (1)
VID1 (1)
VID0 (1)
LDOV
Programming Input
Programming Input
Programming Input
Programming Input (LSB)
+12V for LDO section
GATE2
Gate Drive Output LDO2
Note:
(1) All logic level inputs and outputs are open collector TTL compatible.
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2001 Semtech Corp.
4
SC1164 & SC1165
POWER MANAGEMENT
Block Diagram
CS- CS+
VCC
EN
BSTH
REF
+
-
70mV
LEVEL SHIFT
AND HIGH SIDE
DRIVE
VID4
VID3
DH
CURRENT LIMIT
D/A
R
S
VID2
Q
VID1
VID0
PGNDH
OSCILLATOR
VOSENSE
S H O O T
THRU
C O N T R O L
+
-
PWRGOOD
+
-
-
+
OPEN
COLLECTORS
E R R O R
A M P
BSTL
+
-
V C C
SYNCHRONOUS
DRIVE
DL
+
-
OVP
LDOS1
GATE1
A G N D
PGNDL
FET
CONTROLLER
2.5V/ADJ.
FET
CONTROLLER
1.5V/ADJ.
1.265V
REF
A G N D
LDOV
GATE2 LDOS2 AGND
Setting LDO Output Voltage.
For the SC1165, LDO Output voltages must be set by se-
lecting appropriate resistor values. These values may be
determined from the eqution below, or from the table at
right.
RB
RA
VOUT LDO1 (LDO2)
3.45V
105Ω
105Ω
102Ω
100Ω
100Ω
100Ω
100Ω
182Ω
169Ω
147Ω
130Ω
121Ω
97.6Ω
18.7Ω
1.265 (RA + RB)
VOUT
=
+ (IFB RA )
RB
3.30V
where :
3.10V
IFB = Feedback pinbias current
2.90V
RA = Top feedbackresistor
RB = Bottom feedbackresistor
2.80V
See layout diagram for clarification
RA must be low enough so that the (IFB RA ) term
doesnot cause significant error
2.50V
1.50V
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2001 Semtech Corp.
5
SC1164 & SC1165
POWER MANAGEMENT
Output Voltage Table
Unless specified: 4.75V < VCC < 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; TA = 25°C
Parameter
Conditions
Vid
Min
Typ
Max
Units
43210
Output Voltage
IO = 2A in Application circuit
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
11111
11110
11101
11100
11011
11010
11001
11000
10111
10110
10101
10100
10011
10010
10001
10000
1.274
1.323
1.372
1.421
1.470
1.527
1.576
1.625
1.675
1.724
1.773
1.822
1.871
1.921
1.970
2.019
1.940
2.058
2.156
2.254
2.352
2.450
2.548
2.646
2.744
2.842
2.940
3.038
3.136
3.234
3.332
3.430
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
2.050
2.000
2.100
2.200
2.300
2.400
2.500
2.600
2.700
2.800
2.900
3.000
3.100
3.200
3.300
3.400
3.500
1.326
1.377
1.428
1.479
1.530
1.573
1.624
1.675
1.726
1.776
1.827
1.878
1.929
1.979
2.030
2.081
2.060
2.142
2.244
2.346
2.448
2.550
2.652
2.754
2.856
2.958
3.060
3.162
3.264
3.366
3.468
3.570
V
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2001 Semtech Corp.
6
SC1164 & SC1165
POWER MANAGEMENT
Layout Guidelines
Careful attention to layout requirements are necessary for transition switching. Connections should be as wide and
successful implementation of the SC1164/5 PWM con- as short as possible to minimize loop inductance. Mini-
troller. High currents switching at 200kHz are present in mizing this loop area will a) reduce EMI, b) lower ground
the application and their effect on ground plane voltage injection currents, resulting in electrically cleaner grounds
differentials must be understood and minimized.
for the rest of the system and c) minimize source ringing,
resulting in more reliable gate switching signals.
1). The high power parts of the circuit should be laid out
first. A ground plane should be used, the number and 3). The connection between the junction of Q1, Q2 and
position of ground plane interruptions should be such as the output inductor should be a wide trace or copper re-
to not unnecessarily compromise ground plane integrity. gion. It should be as short as practical. Since this connec-
Isolated or semi-isolated areas of the ground plane may tion has fast voltage transitions, keeping this connection
be deliberately introduced to constrain ground currents to short will minimize EMI. The connection between the out-
particular areas, for example the input capacitor and bot- put inductor and the sense resistor should be a wide trace
tom FET ground.
or copper area, there are no fast voltage or current transi-
tions in this connection and length is not so important,
2). The loop formed by the Input Capacitor(s) (Cin), the Top however adding unnecessary impedance will reduce effi-
FET (Q1) and the Bottom FET (Q2) must be kept as small ciency.
as possible. This loop contains all the high current, fast
12V IN
5V
10
1
2
24
AGND
GATE1
LDOS1
LDOS2
VCC
GATE2
LDOV
VID0
23
22
21
20
19
18
17
16
15
14
13
2.32k
3
Cin
+
4
Q1
Q2
1.00k
VID1
0.1uF
0.1uF
5
5mOhm
VID2
Vout
6
OVP
VID3
L
+
7
PWRGOOD
CS-
VID4
Cout
8
VOSENSE
EN
9
CS+
10
11
12
PGNDH
DH
BSTH
BSTL
DL
PGNDL
SC1164
RA1
Heavy lines indicate
high current paths.
3.3V
Vo Lin1
Q3
+
+
RB1
Cout Lin1
Cin Lin
For SC1164, RA1, RA2, RB1 and RB2
are not required. LDOS1 connects to
Vo Lin1, LDOS2 connects to Vo Lin2
RA2
Vo Lin2
Layout Diagram
SC1164/5
Q4
+
RB2
Cout Lin2
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2001 Semtech Corp.
7
SC1164 & SC1165
POWER MANAGEMENT
Layout Guidelines
4) The Output Capacitor(s) (Cout) should be located as supply through a 10Ω resistor, the Vcc pin should be
close to the load as possible, fast transient load cur- decoupled directly to AGND by a 0.1µF ceramic capacitor,
rents are supplied by Cout only, and connections between trace lengths should be as short as possible.
Cout and the load must be short, wide copper areas to
minimize inductance and resistance.
7) The Current Sense resistor and the divider across it
should form as small a loop as possible, the traces run-
5) The SC1164/5 is best placed over a quiet ground plane ning back to CS+ and CS- on the SC1164/5 should run
area, avoid pulse currents in the Cin, Q1, Q2 loop flowing parallel and close to each other. The 0.1µF capacitor should
in this area. PGNDH and PGNDL should be returned to be mounted as close to the CS+ and CS- pins as possible.
the ground plane close to the package. The AGND pin
should be connected to the ground side of (one of) the 8) Ideally, the grounds for the two LDO sections should be
output capacitor(s). If this is not possible, the AGND pin returned to the ground side of (one of) the output
may be connected to the ground path between the Output capacitor(s).
Capacitor(s) and the Cin, Q1, Q2 loop. Under no circum-
stances should AGND be returned to a ground inside the
Cin, Q1, Q2 loop.
6) Vcc for the SC1164/5 should be supplied from the 5V
5V
+
Vout
+
Currents in various parts of the power section
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2001 Semtech Corp.
8
SC1164 & SC1165
POWER MANAGEMENT
Layout Guidelines
COMPONENT SELECTION
SWITCHING SECTION
The calculated maximum inductor value assumes 100%
and 0% duty cycle, so some allowance must be made.
OUTPUT CAPACITORS - Selection begins with the most Choosing an inductor value of 50 to 75% of the calculated
critical component. Because of fast transient load current maximum will guarantee that the inductor current will ramp
requirements in modern microprocessor core supplies, the fast enough to reduce the voltage dropped across the ESR
output capacitors must supply all transient load current at a faster rate than the capacitor sags, hence ensuring a
requirements until the current in the output inductor ramps good recovery from transient with no additional excursions.
up to the new level. Output capacitor ESR is therefore one
of the most important criteria. The maximum ESR can be We must also be concerned with ripple current in the out-
simply calculated from:
put inductor and a general rule of thumb has been to
allow 10% of maximum output current as ripple current.
Note that most of the output voltage ripple is produced by
the inductor ripple current flowing in the output capacitor
ESR. Ripple current can be calculated from:
Vt
RESR
≤
It
Where
Vt = Maximum transient voltage excursion
It = Transient current step
V
IN
=
IL
RIPPLE
4 L fOSC
Ripple current allowance will define the minimum permit-
ted inductor value.
For example, to meet a 100mV transient limit with a 10A
load step, the output capacitor ESR must be less than
10mΩ. To meet this kind of ESR level, there are three
available capacitor technologies.
POWER FETS - The FETs are chosen based on several
criteria with probably the most important being power dis-
sipation and power handling capability.
Each Cap.
ESR
Total
ESR
Qty.
Rqd.
Technology
TOP FET - The power dissipation in the top FET is a combi-
nation of conduction losses, switching losses and bottom
FET body diode recovery losses.
C
C
(µF) (mΩ)
(µF) (mΩ)
Low ESR Tantalum
OS-CON
330
330
60
25
44
6
3
5
2000
990
10
8.3
8.3
a) Conduction losses are simply calculated as:
2
Low ESR Aluminum
1500
7500
=
δ
PCOND IO RDS(on)
where
The choice of which to use is simply a cost/performance
issue, with Low ESR Aluminum being the cheapest, but
taking up the most space.
VO
δ
≈
= duty cycle
V
IN
b) Switching losses can be estimated by assuming a switch-
ing time, if we assume 100ns then:
INDUCTOR - Having decided on a suitable type and value
of output capacitor, the maximum allowable value of in-
ductor can be calculated. Too large an inductor will pro-
duce a slow current ramp rate and will cause the output
capacitor to supply more of the transient load current for
longer - leading to an output voltage sag below the ESR
excursion calculated above.
=
PSW IO
V
10−2
IN
or more generally,
IO
V
(tr + tf ) fOSC
IN
PSW
=
4
c) Body diode recovery losses are more difficult to esti-
mate, but to a first approximation, it is reasonable to as-
sume that the stored charge on the bottom FET body di-
ode will be moved through the top FET as it starts to turn
on. The resulting power dissipation in the top FET will be:
The maximum inductor value may be calculated from:
RESR
It
C
≤
L
VA
=
PRR QRR
V
fOSC
IN
(
−
)
where VA is the lesser of VO or V
VO
IN
To a first order approximation, it is convenient to only con-
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2001 Semtech Corp.
9
SC1164 & SC1165
POWER MANAGEMENT
Layout Guidelines
sider conduction losses to determine FET suitability. position, power dissipation will be approximately halved
For a 5V in; 2.8V out at 14.2A requirement, typical FET and temperature rise reduced by a factor of 4.
losses would be: Using 1.5X Room temp RDS(ON) to allow for
temperature rise.
INPUT CAPACITORS - since the RMS ripple current in the
input capacitors may be as high as 50% of the output
current, suitable capacitors must be chosen accordingly.
Also, during fast load transients, there may be restrictions
on input di/dt. These restrictions require useable energy
storage within the converter circuitry, either as extra out-
put capacitance or, more usually, additional input capaci-
tors. Choosing low ESR input capacitors will help maximize
ripple rating for a given size.
FET type
IRL34025
IRL2203
Si4410
RDS(on) (mΩ)
PD (W)
1.69
Package
D2Pak
D2Pak
S0-8
15
10.5
20
1.19
2.26
BOTTOM FET - Bottom FET losses are almost entirely due
to conduction. The body diode is forced into conduction at
the beginning and end of the bottom switch conduction
period, so when the FET turns on and off, there is very
little voltage across it, resulting in low switching losses.
Conduction losses for the FET can be determined by:
PCOND = IO2 RDS(on) (1− δ)
For the example above:
FET type
IRL34025
IRL2203
Si4410
RDS(on) (mΩ)
PD (W)
1.33
Package
D2Pak
D2Pak
S0-8
15
10.5
20
0.93
1.77
Each of the package types has a characteristic thermal
impedance, for the TO-220 package, thermal impedance
is mostly determined by the heatsink used. For the sur-
face mount packages on double sided FR4, 2 oz printed
circuit board material, thermal impedances of 40oC/W for
the D2PAK and 80oC/W for the SO-8 are readily achiev-
able. The corresponding temperature rise is detailed be-
low:
Temperature rise (oC)
FET type
IRL34025
IRL2203
Si4410
Top FET
67.6
Bottom FET
53.2
47.6
37.2
180.8
141.6
It is apparent that single SO-8 Si4410 are not adequate
for this application, but by using parallel pairs in each
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2001 Semtech Corp.
10
SC1164 & SC1165
POWER MANAGEMENT
Typical Characteristics
Typical Efficiency at Vo=3.5V
Typical Efficiency at Vo=2.8V
95%
90%
85%
80%
75%
70%
95%
90%
85%
80%
75%
70%
3.5V Std
2.8V Std
3.5V Sync
2.8V Sync
3.5V Sync Lo Rds
2.8V Sync Lo Rds
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
Io (Amps)
Io (Amps)
Typical Efficiency at Vo=2.5V
Typical Efficiency at Vo=2.0V
95%
90%
85%
80%
75%
70%
95%
90%
85%
80%
75%
70%
2.0V Std
2.5V Std
2.0V Sync
2.5V Sync
2.0V Sync Lo Rds
2.5V Sync Lo Rds
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
Io (Amps)
Io (Amps)
Typical Ripple, Vo=2.8V, Io=10A
Transient Response Vo=2.8V, Io=300mA to 10A
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11
SC1164 & SC1165
POWER MANAGEMENT
Typical Application Circuit
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2001 Semtech Corp.
12
SC1164 & SC1165
POWER MANAGEMENT
Materials List
Item
Qty.
4
Ref
Value
0.1uF
1500uF
330uF
4.7uF
Notes
1
2
3
4
C1, C4, C5, C10
6
C2, C3, C6, C7, C8, C9
C11, C12, C14, C15, C16, C17
C26
Sanyo MV-GX or equiv. Low ESR
6
1
6 Turns 16AWG on MICROMETALS
T50-52D core
5
1
L1
1.9uH
6
2
2
1
1
1
1
2
1
1
1
1
Q1, Q3
Q5, Q6
R1
IRLR3103N
IRLR024N
10
7
8
9
R3
EMPTY
1.00k
10
11
12
13
14
15
16
R4
R5
2.32k
R6, R9
R8
2R2
5mOhm
0
IRC OAR-1 Series
R11
S1
SW DIP-6
SC1164CS
U4
www.semtech.com
2001 Semtech Corp.
13
SC1164 & SC1165
POWER MANAGEMENT
Outline Drawing
Contact Information
Semtech Corporation
Power Management Products Division
652 Mitchell Rd., Newbury Park, CA 91320
Phone: (805)498-2111 FAX (805)498-3804
www.semtech.com
2001 Semtech Corp.
14
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