SC1218MLTRT [SEMTECH]
High Speed Synchronous MOSFET Driver; 高速同步MOSFET驱动器
| 型号： | SC1218MLTRT |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | High Speed Synchronous MOSFET Driver |
| 文件： | 总12页 (文件大小：396K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC1218
High Speed
Synchronous MOSFET Driver
POWER MANAGEMENT
Features
Description
The SC1218 is a high speed, robust, dual output driver to Advanced Digital Timing to Filter Out Very Narrow PWM
drive high-side and low-side N-MOSFETs in synchronous
buck converters. Combined with Semtech’s multi-phase
PWM controller SC2649, one can build high performance,
versatile voltage regulators for next generation micropro-
cessors.
Pulses
+12V Gate Drive Voltage
Integrated Bootstrap Diode
High Peak Drive Current
Adaptive Non-overlapping Gate Drives Provide Shoot-
through Protection
Support Dynamic VID operation
Ultra-low Propagation Delay
Floating Top Gate Drive
Crowbar Function for Over Voltage Protection
High Frequency (up to 2 MHz) Operation Allows Use of
Small Inductors and Low Cost Ceramic Capacitors
SC1218 is built upon a CMOS technology which provides
enough voltage capacity to handle computer applications.
In addition, the advanced timing circuitry is adopted to
filter out very narrow PWM pulses at the input of the driver.
The latched UVLO and enhanced adaptive shoot-through
protection further enhance the robustness of the SC1218.
With integrated bootstrap diode, the SC1218 is offered in Under Voltage Lockout
both SOIC-8 package and MLPQ-8 3x3mm package. These
features further reduce the thermal stress and BOM cost.
Low Quiescent Current
Enable Function for Both Gate OFF Shut Down
Lead-free Part and Fully WEEE and RoHS Compliant
Applications
Intel Next Generation Processor Power Supplies
AMD AthlonTM and AMD-K8TM Processor Power
Supplies
High Current Low Voltage DC-DC Converters
Typical Application Circuit
VIN
Cbst
Mtop
Cin
1uF
BST
CO
EN
TG
Lout
Rdrn
VOUT
PWM
EN
DRN
PGND
BG
(optional)
Rvin
2R2
Mbot
VIN
Cout
SC1218
Cvin
1uF
Revision: October 14, 2005
1
www.semtech.com
SC1218
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the
Electrical Characteristics section is not implied.
Parameter
Symbol
Conditions
Maximum
-0.3 to 16
-0.3 to 16
-0.3 to 16
-0.3 to 16
-2
Units
V
VIN Supply Voltage
BST to DRN
VI N
VBST-DRN
V
BST to VIN
VBST-VIN
V
TG to DRN
VTG-DRN
V
TG to DRN Pulse
BST to PGND
BST to PGND Pulse
DRN to PGND
VTG-DRN-PULSE
VBST-PGND
VBST-PGND-PULSE
VDRN-PGND
VPEAK with tPULSE < 20ns(1)
V
-0.3 to VIN+16
38
V
tPULSE <20ns
V
VBST-VDRN = 10V
-2 to VIN+16
-5 to 35
-8 to 35
-0.3 to VIN+0.3
-3.5
V
VPEAK with tPULSE < 200ns(1)
VPEAK with tPULSE < 20ns(1)
V
DRN to PGND Pulse
VDRN-PGND-PULSE
V
BG to PGND
BG to PGND Pulse
PWM Input
VBG-PGND
VBG-PGND-PULSE
CO
V
VPEAK with tPULSE < 20ns(1)
V
-0.3 to VIN+0.3
-0.3 to VIN+0.3
0.5
V
Enable Input
EN
V
SOIC-8
MLPQ-8
SOIC-8
MLPQ-8
Continuous Power Dissipation
TA=25oC, TJ=125oC
PD
W
2.56
40
Thermal Resistance Junction to Case
oC/W
θJC
8
Junction Temperature Range
Storage Temperature Range
TJ
0 to 150
-65 to 150
300
oC
oC
oC
oC
TSTG
SOIC-8
Lead Temperature (Soldering) 10 Sec.
TLEAD
MLPQ-8
260
Notes:
(1) Pulse width measured at 10% of the triangular spike waveform.
(2) This device is ESD sensitive. Use of standard ESD handling precautions is required.
Electrical Characteristics
Unless specified: TA = 25°C; VIN = 12V.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Power Supply
Supply Voltage
VI N
5
12
3.35
2.9
14
4.4
4
V
EN=5V; CO=0V
EN=5V; CO=5V
mA
mA
mA
VI N Quiescent Current
IQ
EN=0V
1.35
2.5
2005 Semtech Corp.
2
www.semtech.com
SC1218
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: TA = 25°C; VIN = 12V.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Under Voltage Lockout
Start Threshold of VIN Voltage
Hysteresis
VIN_START
4
4.3
V
VhysUVLO
250
mV
EN
Logic High Input Voltage
Logic Low Input Voltage
CO
VEN_H
VEN_L
2.65
2.9
V
V
0.8
0.8
Logic High Input Voltage
Logic Low Input Voltage
Internal Pull-down Resistor
High Side Driver (TG)
VCO_H
VCO_L
V
V
40
Kohm
RSRC_TG
RSINK_TG
ISRC_TG_PK
ISINK_TG_PK
tPDH_TG
1.68
0.52
2.8
6.5
37
2.1
Ohm
Ohm
A
Output Impedence
VBST-VDRN= 12V
0.78
VIN=12V, CTG=10nF
VIN=12V, CTG=10nF
VBST-VDRN= 12V
Output Peak Current
A
Propagation Delay, TG Going High
Propagation Delay, TG Going Low
TG Minimum On-time(1)
ns
tPDL_TG
VBST-VDRN= 12V
50
ns
tON_MIN_TG
For CO pulse width < 40ns
40
ns
Low Side Driver (BG)
RSRC_BG
RSINK_BG
ISRC_BG_PK
ISINK_BG_PK
tPDH_BG
1.36
0.52
3.5
7.5
20
2.0
Ohm
Ohm
A
Output Impedence
VIN = 12V
0.78
VIN=12V, CBG=10nF
VIN=12V, CBG=10nF
VIN = 12V
Output Peak Current
A
Propagation Delay, BG Going High
Propagation Delay, BG Going Low
BG Minimum OFF-time(1)
ns
tPDL_BG
VIN = 12V
27
ns
tOFF_MIN_BG
tDH_MAX_BG
For CO pulse width < 40ns
From CO=Low, VDRN>1V
140
175
ns
BG Maximum Turn ON Delay(1)
ns
NOTE: (1). Guaranteed by design.
2005 Semtech Corp.
3
www.semtech.com
SC1218
POWER MANAGEMENT
Timing Diagrams
VCO_HI
VCO_LO
CO
TG
t
PDL_TG
t
PDH_TG
BG
1.4V
t
PDL_BG
t
PDH_BG
1.0V
DRN
VIN & EN
VIN>UVLO
&
Rising Edge Transition
Falling Edge Transition
EN=“HI”
2005 Semtech Corp.
4
www.semtech.com
SC1218
POWER MANAGEMENT
Pin Configuration
MLPQ-8 3x3mm Top View
SOIC-8 Top View
BST TG
7
8
BST
CO
EN
1
2
3
4
8
7
6
5
TG
1
2
6
5
CO
EN
DRN
DRN
PGND
BG
PGND
3
4
VIN
VIN BG
EXPOSED PAD MUST BE SOLDERED TO
POWER GROUND PLANE
Pin Descriptions
SOIC-8 MLPQ-8 Pin Name
Pin Function
Bootstrap supply pin for the top gate drive. Connect a 1uF ceramic capacitor between BST and
DRN pin to develop a floating bootstrap voltage for the high side driver.
1
2
3
4
8
1
2
3
BST
CO
EN
PWM input signal from external controller. An internal 40Kohm resistor is connected from this pin
to the PGND.
When high, this pin enables the internal circuitry of the device. When low, TG and BG are forced
low.
Supply power for the bottom gate driver and the internal control circuitry. Connect to input power
rail of the converter and dcouple with a 1µF ceramic with lead length no more than 0.2" (5mm).
VIN
Output gate drive for the bottom (synchronous) MOSFET. An internal 20Kohm resistor is
connected from this pin to PGND.
5
6
4
5
BG
PGND
Supply power ground return. Keep this pin close to the bottom MOSFET source during layout.
Connect this pin to the power phase node of the synchronous buck converter (source of top
MOSFET and drain of bottom MOSFET). The DRN pin provides a return path for top gate drive.
Its voltage is deteced for adaptive shoot-through protection. This pin is subjected to a negative
spike of -8V relative to PGND without affecting the operation. An internal 20Kohm resistor is
connected from this pin to PGND.
7
8
6
7
DRN
TG
Output gate drive for the top (switching) MOSFET.
Ordering Information
Device
Package
SOIC-8
MLPQ-8
Temp Range (TJ)
0° to 150°C
SC1218STRT (1)(3)
SC1218MLTRT (2)(3)
0° to 150°C
Note:
(1) Only available in tape and reel packaging. Areel contains 2500 devices.
(2) Only available in tape and reel packaging. Areel contains 3000 devices.
(3) Devices are lead-free and fully WEEE and RoHS compliant.
2005 Semtech Corp.
5
www.semtech.com
SC1218
POWER MANAGEMENT
Block Diagram
VIN
EN
BST
UVLO
TG
CONTROL
DRN
&
OVERLAP
PROTECTION
CIRCUIT
R
R
CO
R
BG
PGND
Typical Performance Characteristics
CO
CO
TG
TG
BG
BG
Fig. 1. TG Rise and BG Fall Times
Fig. 2. TG Fall and BG Rise Times
2005 Semtech Corp.
6
www.semtech.com
SC1218
POWER MANAGEMENT
Typical Performance Characteristics (Cont.)
25
20
15
10
5
20
VIN=12V
TA=25°C
VIN=12V
C
Load=3.3nF
TG
19
18
17
16
15
TG
BG
BG
0
0
2
4
6
8
10
0
25
50
75
100
125
TEMPERATURE (°C)
LOAD CAPACITANCE (nF)
Fig. 6. TG and BG Fall Times vs. Load Capacitance.
Fig. 3. TG and BG Rise Times vs. Temperature.
160
11
VIN=12V
VIN=12V
Load=3.3nF
140
120
100
80
C
Load_TG=3.3nF
C
TG
CLoad_BG=3.3nF
TA=25°C
10
9
BG
8
60
40
7
20
6
0
0
25
50
75
100
125
0
200
400
600
800
1000 1200 1400 1600
TEMPERATURE (°C)
FREQUENCY (KHz)
Fig. 4. TG and BG Fall Times vs. Temperature.
Fig. 7. Supply Current vs. Frequency.
50
27
VIN=12V
TA=25°C
VIN=12V
TG
C
C
Load_TG=3.3nF
Load_BG=3.3nF
40
26
25
24
23
22
BG
Freq.=200KHz
30
20
10
0
0
25
50
75
100
125
0
2
4
6
8
10
TEMPERATURE (°C)
LOAD CAPACITANCE (nF)
Fig. 8. Supply Current vs. Temperature.
Fig. 5. TG and BG Rise Times vs. Load Capacitance.
2005 Semtech Corp.
7
www.semtech.com
SC1218
POWER MANAGEMENT
Typical Performance Characteristics (Cont.)
4.5
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
CLOAD_TG=10nF
CLOAD_BG=10nF
TA=25°C
CLOAD_TG=10nF
CLOAD_BG=10nF
TA=25°C
4.0
BG
BG
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
TG
TG
5
6
7
8
9
10
IN (V)
11
12
13
14
5
6
7
8
9
10
IN (V)
11
12
13
14
V
V
Fig. 10. Peak Sinking Current vs. Supply Voltage.
Fig. 9. Peak Sourcing Current vs. Supply Voltage.
2005 Semtech Corp.
8
www.semtech.com
SC1218
POWER MANAGEMENT
Applications Information
narrow pulse for the driver. The pulse is so narrow that it
reaches the rising edge threshold of the SC1218 at one
point then immediately falls below the falling edge thresh-
old. To prevent the SC1218 from reacting to such narrow
PWM pulses, which may cause driver output ringing or
shoot through, advanced PWM timing circuitry is added to
ease the gate transitions. A minimum off-time (typically
140ns) for the bottom gate and a minimum on-time (typi-
cally 40ns) for the top gate are enforced to make the op-
eration safe under such conditions.
THEORY OF OPERATION
The SC1218 is a high speed, robust, dual output driver
designed to drive top and bottom MOSFETs in a synchro-
nous Buck converter. It features internal bootstrap diode,
adaptive delay for shoot-through protection, 12V gate drive
voltage, and disable shutdown. It also supports dynamic
VID operation and CROWBAR function. This driver com-
bined with PWM controller SC2649 forms a multi-phase
voltage regulator for advanced microprocessors.
Startup and UVLO
Dynamic VID Operation
To startup the driver, a supply voltage is applied to the VIN
pin of the SC1218. The top and bottom gates are held
low until VIN exceeds the UVLO threshold of the driver,
typically 4.0V. The UVLO threshold has hysteresis, typi-
cally -250mV, to improve the nosie immunity from the VIN
pin.
Some processors changes VID dynamically during opera-
tion (Dynamic VID operation). A dynamic VID can occur
under light load or heavy load conditions. At light load, it
can force the converter to sink current. After turn-off of
the top FET, the reversed inductor current flows through
the body diode of the top FET instead of the bottom FET.
As a result, the phase node voltage remains high and voids
the adaptive circuit. SC1218 features a maximum BG
turn on delay (tDH_MAX_BG) to override the adaptive delay to
turn the bottom FET on. The preset maximum BG turn on
delay time (tDH_MAX_BG) from the PWM falling egde to the
bottom gate turn-on is set to be 175ns.
Gate Transition and Shoot-through Protection
Refer to the Timing Diagrams section, the rising edge of
the PWM input initiates the turn-off of bottom FET and the
turn-on of top FET. After a short propagation delay (tPDL_BG
)
from PWM rising edge, the bottom gate falls (tF_BG). The
adaptive circuit in the SC1218 detects the bottom gate
voltage. It holds the top gate off until the bottom gate
voltage drops below 1.4V for a preset delay time (tPDH_TG).
This prevents the top FET from turning on until the bottom
FET is off. During the transition, the inductor current is
freewheeling through the body diode of either bottom FET
or top FET, depended on the direction of the inductor cur-
rent. The phase node could be low (ground) or high (VIN).
Switching Frequency, Inductor and MOSFETs
The SC1218 is capable of providing more than 3.5A peak
drive current, and operating up to 2MHz PWM frequency
without causing thermal stress on the driver. The selec-
tion of switching frequency, together with inductor and
FETs is a trade-off between the cost, size, and thermal
management of a multi-phase voltage regulator. Typically,
these parameters could be in the range of:
The falling edge of the PWM input controls the turn-off of
top FET and the turn-on of bottom FET. After a short
propagation delay (tPDL_TG) from PWM falling edge, the top
gate falls (tF_TG). As the inductor current commutates from
the top FET to the body diode of the bottom FET, the phase
node falls. The adaptive circuit in the SC1218 detects the
phase node voltage. It holds the bottom FET off until the
phase node voltage drops below 1.0V. This prevents the
top and bottom FETs from conducting simultaneously
(shoot-through). If the phase node voltage remains high
during the transition for a preset maximum BG turn on
delay (tDH_MAX_BG) , then the bottom gate will be turned on.
This supports the CROWBAR function and the sinking cur-
rent capacity required from dynamic VID operation.
a) Switching Frequency: 100kHz to 500kHz per phase
b) Inductor Value: 0.2uH to 2uH
c) MOSFETs: 4mOhm to 20mOhm RDS(ON) and 20nC
to 100nC total gate charge
Bootstrap and Chip Decoupling Capacitors
The top gate driver of the SC1218 is a DRN refered gate
drive whose supply voltage is derived from a bootstrap
circuit comprising a capacitor,CBST, and a built-in diode.
The capacitor value can be calculated based on the total
gate charge of the top FET, QTOP, and an allowed voltage
ripple on the capacitor, ∆VBST, in one PWM cycle:
Narrow PWM Pulse Filtering
QTOP
>
CBST
During a load transient, soft start, or soft shutdown of the
voltage regulator, the PWM controller may generate a very
2005 Semtech Corp.
∆VBST
9
www.semtech.com
SC1218
POWER MANAGEMENT
Applications Information (Cont.)
The typical layout examples of SC1218 based on above
guidelines are shown in Fig.12 and Fig.13.
Typically, a 1uF/16V ceramic capacitor is used. In addi-
tion, a small resistor (one ohm) is recommended in be-
tween DRN pin of the SC1218 and the phase node. The
resistor is used to alleviate the stress of the SC1218, re-
sulting from the negative spike at the phase node, and
also to control the switching speed. A negative spike could
occur at the phase node during the top FET turn-off due to
parasitic inductance in the switching loop. The spike could
be minimized with a careful PCB layout. In the applica-
tions with TO-220 package FETs, it is suggested to use a
clamping diode on the DRN pin to mitigate the impact of
the excessive phase node negative spikes.
1000
Fsw=600kHz
800
600
Fsw=400kHz
400
Fsw=200kHz
200
For VIN pin of the SC1218, it is recommended to use a
1uF/16V ceramic capacitor for decoupling.
0
40
60
80
100
120
TOTAL GATE CHARGE (nC)
Driver Dissipation and Junction Temperature
The driver power dissipation is a function of chip quies-
cent current IQ, switching frequency FSW, and supply volt-
age VIN. It is approximated as:
Fig. 11. Power dissipation.
CBST
PD = (IQ + QTOTAL ⋅ FSW )⋅VIN
To top FET
RDRN
PWM
where QTOTAL is the total gate charge of the top-side and
bottom-side FETs. The power dissipation vs total gate
charge at the given switching frequency is plotted in Fig.11.
The driver junction temperature can be calculated based
on the juntion to case thermal resistance and Printed Cir-
cuit Board (PCB) temperature.
To phase node
To bottom FET
R
VIN
VIN
C
LAYOUT GUIDELINES
Fig. 12. Component placement for SOIC-8
The switching regulator is a high di/dt and dv/dt power
circuit. PCB layout is critical. A good layout can achieve
optimum circuit performance with minimized component
stress, resulting in better system reliability. For a multi-
phase voltage regulator, the SC1218 driver, FETs, induc-
tor, and supply decoupling capacitors in each phase have
to be considered as a unit. For the SC1218 driver, the
following guidelines are typically recommended during PCB
layout:
VIN
C
BST
To Top FET
R
VIN
VIN
To Phase Node
R
DRN
a) Place the SC1218 close to the FETs for shortest
gate drive traces and ground return paths;
b) Connect decoupling capacitor as close as possible
to the VIN pin and the PGND pin. The trace length of
the capacitor on the VIN pin should be no more than
0.2” (5mm); and
C
To Bottom FET
EN
Fig. 13. Component placement for MLPQ-8.
c) Locate the bootstrap capacitor close to the SC1218.
2005 Semtech Corp.
10
www.semtech.com
SC1218
POWER MANAGEMENT
Outline Drawing - SOIC-8
DIMENSIONS
INCHES MILLIMETERS
A
DIM
A
MIN NOM MAX MIN NOM MAX
D
E
e
-
-
-
-
-
-
-
-
-
-
.053
.069 1.35
.010 0.10
.065 1.25
.020 0.31
.010 0.17
1.75
0.25
1.65
0.51
0.25
N
A1 .004
A2 .049
2X E/2
b
.012
.007
c
D
.189 .193 .197 4.80 4.90 5.00
E1
E1 .150 .154 .157 3.80 3.90 4.00
E
.236 BSC
.050 BSC
-
6.00 BSC
1.27 BSC
-
0.50
e
1
2
h
L
.010
.020 0.25
ccc C
2X N/2 TIPS
.016 .028 .041 0.40 0.72 1.04
(.041)
(1.04)
e/2
L1
N
8
8
B
-
-
01
0°
8°
0°
8°
aaa
.004
.010
.008
0.10
0.25
0.20
bbb
ccc
D
aaa C
h
A2
A
SEATING
PLANE
C
h
A1
H
bxN
bbb
C A-B D
c
GAGE
PLANE
0.25
L
(L1)
01
SEE DETAIL A
DETAIL A
SIDE VIEW
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MS-012, VARIATION AA.
Land Pattern - SOIC-8
X
DIMENSIONS
DIM
INCHES
(.205)
.118
MILLIMETERS
(5.20)
3.00
1.27
0.60
2.20
7.40
C
G
P
X
Y
Z
(C)
G
Y
Z
.050
.024
.087
.291
P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2. REFERENCE IPC-SM-782A, RLP NO. 300A.
2005 Semtech Corp.
11
www.semtech.com
SC1218
POWER MANAGEMENT
Outline Drawing - MLPQ-8, 3 x 3mm
A
D
B
E
Top View
DIMENSIONS
INCHES MILLIMETERS
DIM
A
PIN 1
MIN NOM MAX MIN NOM MAX
INDICATOR
-
-
-
.032
0.08
.040
1.00
0.05
(LASER MARK)
-
A1 .000
A2
.002 0.00
0.20 REF
.008 BSC
.007
-
-
b
D
.012 0.19
0.30
.118 BSC
3.00 BSC
-
D2 .059
-
.071 1.50
.071 1.50
1.80
1.80
-
-
E2 .059
0
.118 BSC
.026 BSC
3.00 BSC
0.65 BSC
E
A2
e
A
L
K
.012 .016 .020 0.30 0.40 0.50
SEATING
PLANE
aaa C
-
-
-
-
.008
0.20
A1
C
N
8
8
D2
-
-
0
0°
12°
0°
12°
aaa
.003
.008
0.08
0.20
e/2
bbb
Bottom View
L
E/2
2
1
E2
N
K
e
b
D/2
bbb
C A B
Land Pattern - MLPQ-8, 3 x 3mm
H
DIMENSIONS
DIM
INCHES
(.122)
.089
MILLIMETERS
(3.10)
2.25
1.85
1.85
0.65
0.35
0.85
3.95
C
G
H
K
P
X
Y
Z
K
G
.073
(C)
Z
.073
.026
.014
Y
.033
.156
X
NOTES:
P/2
P
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2.
THE VIAS ON THE CENTER PAD SHOULD MAINTAIN THE GOOD
THERMAL CONTACT OF THE DEVICE TO THE PCB GROUND PLANE.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
2005 Semtech Corp.
12
www.semtech.com
相关型号：
©2020 ICPDF网 联系我们和版权申明