SC1544 [SEMTECH]
ACPI Controller for Advanced Motherboards; ACPI控制器的高级主板
| 型号： | SC1544 |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | ACPI Controller for Advanced Motherboards |
| 文件： | 总15页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC1544
ACPI Controller for
Advanced Motherboards
PRELIMINARY
POWER MANAGEMENT
Description
ꢀeatures
Semtechs SC1544, SC243x and SC1112A or SC1114
provide all the voltages necessary for an ACPI system.
u Complete programmable supply for instantly available
PC systems
u Supports 2.5V memory or 3.3V memory (-2.5 or -3.3
option in part number)
The SC1544 offers five independant supplies: a 5V dual
supply for USB, a 3.3V dual supply for PCI, a 3.3V or
2.5V dual supply for memory, a 1.5V or 3.3V supply for
AGP and a 1.8V supply. The AGP supply is programmble
using the system TYPEDET signal.
u 5V dual and 3.3V dual supplies are programmable to
be active or inactive in S5
u Integrated AGP voltage supply with TYPEDET signal
for 3.3V or 1.5V operation
An on-board internal charge pump eliminates the need
for P-channel MOSꢀETs and enables function from a single
5V supply (system 5VSB). All dual outputs are over current
protected.
u Integrated LDO for 1.8V supply
u Integrated charge pump removes the need for PMOS
ꢀETs, enables single supply operation
u Over current protection on all dual outputs
u Inherent soft-start capability
The SC1544 differs from the SC1547 in three important
ways: 1) the device initially starts up in S5, and not G0
like the SC1547; 2) the gate drives for the 1.8V and AGP
outputs are always high in normal operation; 3) no OCP
on the 1.8V and AGP outputs.
u TSSOP-24 package
Applications
u Instantly available motherboards
Typical Application Circuit
5V
C1
100uF/6.3V
GND
3.3V
C2
100uF/6.3V
GND
5VSB
C3
100uF/6.3V
GND
Q1
Q2
IRLR3103
IRLR3103
5V DUAL
C4
100uF/6.3V
GND
Q3
IRLR3103
Q4
IRLR3103
3.3V DUAL
C5
100uF/6.3V
GND
Q5
IRLR3103
Q6
IRLR3103
3.3V DUAL MEM
C6
100uF/6.3V
GND
AGP
GND
1.8V
GND
Q7
IRLR3103
C7
100uF/6.3V
Q8
IRLR3103
U1
1
SC1544-3.3
G8
C8
100uF/6.3V
24
23
22
21
20
19
18
17
16
15
14
13
G5
2
3
3.3VDM
G6
1.8V
G4
4
G7
3.3VD
GND
G2/3
G1
5
AGP
6
TYPEDET
PWR_OK
EN
TYPEDET
PWR_OK
EN
7
8
5VD
9
/SLP_S3
/SLP_S5
USB
/S3
5VSB
FC
10
11
12
/S5
USB
+CAP
-CAP
C10
0.1uF
C11
1uF
PCI
PCI
C9 0.01uF
Revision 3, May 2002
1
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SC1544
POWER MANAGEMENT
PRELIMINARY
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied.
Parameter
Symbol
Maximum
Units
Input Supply Voltage
V5VSB
-0.6 to 7
-0.6 to V5VSB
-0.6 to 13.2
15.6
V
V
Logic Input Pins
Charge Pump Output Voltage
Thermal Impedance Junction to Case
Thermal Resistance Junction to Ambient
Operating Ambient Temperature Range
Operating Junction Temperature Range
Storage Temperature Range
VFC
θJC
V
°C/W
°C/W
°C
83.8
θJA
TA
0 to 70
TJ
0 to 125
-65 to +150
300
°C
TSTG
TLEAD
°C
Lead Temperature (Soldering) 10 Sec.
°C
Electrical Characteristics(1)
Unless specified: all applicable silver box supplies (3.3V, 5V, 5VSB) ± 5%, GND = 0V, VSENSE PINS = VOUT(NOM), TA = 25°C. Values in bold apply over full
operating ambient temperature range.
Parameter
Symbol
Test Conditions
Min
4.5
Typ
Max
Units
IN
Supply Voltage
Quiescent Current
V5VSB
IQ
5.0
10
5.5
15
20
V
All states (S0, S3, S5, disabled)
mA
Undervoltage Lockout
Threshold Voltage
VUVLO
V5VSB Rising
3.5
4.0
4.4
V
Logic Inputs (EN, PCI, PWR_OK, /S3, /S5, TYPEDET, USB)
Logic Pin Sink Current(2)
Logic Pin Source Current
ISINK
VBIAS = 5V, all logic pins
EN, VEN = 0V
0.1
0.5
50
1
µA
µA
ISOURCE
3
PCI, TYPEDET, USB, VPIN = 0V
/S3, PWR_OK, VPIN = 0V
/S5, V/S5 = 0V
200
400
600
100
150
Threshold Voltage
VIH
VIL
2.4
V
V
0.8
1.8V Output
Output Voltage(3)
V1.8V
1mA ≤ IOUT ≤ 720mA
1.764
1.800
1.836
V
1.746
1.854
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2002 Semtech Corp.
2
SC1544
POWER MANAGEMENT
Electrical Characteristics (Cont.)(1)
PRELIMINARY
Unless specified: all applicable silver box supplies (3.3V, 5V, 5VSB) ± 5%, GND = 0V, VSENSE PINS = VOUT(NOM), TA = 25°C. Values in bold apply over full
operating ambient temperature range.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
1.8V Output (Cont.)
Line Regulation(3)
REGLINE
REGLOAD
VG8(HI)
V5VSB = 4.75V to 5.25V, IOUT = 0A
V5VSB = 5V, IOUT = 0A to 720mA
V1.8V = 1.7V, IG8 = 10µA
S3, IG8 = -10µA
0.01
0.01
8.75
0.8
0.10
0.20
%
%
V
Load Regulation(3)
Gate 8 Drive Voltage(4)
8.00
VG8(LO)
1.0
Gate 8 Drive Current(4)
Sense Pin Bias Current
IG8(SOURCE)
IG8(SINK)
I1.8V
V1.8V = 1.7V, VG8 = 5V
V1.8V = 1.9V, VG8 = 3V
Sinking, V1.8V = 1.8V
2
4
mA
µA
%
-3.5
-70
-5
-100
-130
2.5V/3.3V Dual Memory Output
Output Voltage(5)
V3.3VDM
1mA ≤ IOUT ≤ 720mA
-1.5
VOUT(NOM) +1.5
-2.5
+2.5
Line Regulation(5)
REGLINE
REGLOAD
VG5(HI)
V5VSB = 4.75V to 5.25V, IOUT = 0A
V5VSB = 5V, IOUT = 0A to 720mA
0.01
0.01
8.75
0.8
4
0.10
0.20
%
%
V
Load Regulation(5)
Gate 5 Drive Voltage(6)
V3.3VDM = VOUT(NOM) - 100mV, IG5 = 10µA, S0
IG5 = -10µA, S3
8.00
VG5(LO)
1.0
1.0
Gate 5 Drive Current(6)
Gate 6 Drive Voltage(7)
Gate 6 Drive Current(7)
Sense Pin Bias Current
IG5(SOURCE)
IG5(SINK)
V3.3VDM = VOUT(NOM) - 100mV, VG5 = 5V, S0
V3.3VDM = VOUT(NOM) + 100mV, VG5 = 3V, S0
V3.3VDM = VOUT(NOM) - 100mV, IG6 = 10µA, S3
IG6 = -10µA, S0
2
mA
V
-3.5
8.00
-5
VG6(HI)
8.75
0.8
4
VG6(LO)
IG6(SOURCE)
IG6(SINK)
V3.3VDM = VOUT(NOM) - 100mV, VG6 = 5V, S3
V3.3VDM = VOUT(NOM) + 100mV, VG6 = 3V, S3
Sinking, 3.3V option, V3.3VDM = 3.3V
Sinking, 2.5V option, V3.3VDM = 2.5V
2
mA
µA
-3.5
-330
-215
-5
I3.3VDM
-475
-310
-620
-405
3.3V Dual Output
Output Voltage(8)
V3.3VD
1mA ≤ IOUT ≤ 720mA
3.250
3.300
3.350
3.383
0.10
V
3.217
Line Regulation(8)
Load Regulation(8)
REGLINE
V5VSB = 4.75V to 5.25V, IOUT = 0A
V5VSB = 5V, IOUT = 0A to 720mA
0.01
0.01
%
%
REGLOAD
0.20
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2002 Semtech Corp.
3
SC1544
POWER MANAGEMENT
Electrical Characteristics (Cont.)(1)
PRELIMINARY
Unless specified: all applicable silver box supplies (3.3V, 5V, 5VSB) ± 5%, GND = 0V, VSENSE PINS = VOUT(NOM), TA = 25°C. Values in bold apply over full
operating ambient temperature range.
Parameter
Symbol
Test Conditions
Min
Typ
Max
100
Units
3.3V Dual Output (Cont.)
Gate 3 Drive Voltage(9)
VG3(HI)
VG3(LO)
IG3(SOURCE)
IG3(SINK)
VG4(HI)
IG3 = 10µA
IG3 = -10µA
8.00
8.75
40
V
mV
mA
Gate 3 Drive Current(9)
Gate 4 Drive Voltage(10)
Gate 4 Drive Current(10)
VG3 = 5V
0.5
-10
0.7
-14
8.75
0.8
4
VG3 = 3V
V3.3VD = 3.2V, IG4 = 10µA
V3.3VD = 3.4V, IG4 = -10µA
V3.3VD = VOUT(NOM) - 100mV, VG4 = 5V
V3.3VD = VOUT(NOM) + 100mV, VG4 = 3V
Sinking, V3.3VD = 3.3V
8.00
V
VG4(LO)
IG4(SOURCE)
IG4(SINK)
I3.3VD
1.0
-130
100
2
mA
µA
-3.5
-70
5
Sense Pin Bias Current
5V Dual Output
-100
Gate 2 Drive Voltage(11)
VG2(HI)
VG2(LO)
IG2(SOURCE)
IG2(SINK)
VG1(HI)
IG2 = 10µA
IG2 = -10µA
VG2 = 5V
8.00
8.75
40
V
mV
mA
Gate 2 Drive Current(11)
Gate 1 Drive Voltage(12)
Gate 1 Drive Current(12)
0.5
-10
0.7
-14
8.75
40
VG2 = 3V
IG1 = 10µA
IG1 = -10µA
VG1 = 5V
8.00
V
VG1(LO)
IG1(SOURCE)
IG1(SINK)
I5VD
100
16
mV
mA
0.5
-10
0.7
-14
VG1 = 3V
Sense Pin Bias Current(2)
AGP Output
V5VD = 5V
µA
%
Output Voltage(13)
VAGP
1mA ≤ IOUT ≤ 720mA
-2.0
VOUT(NOM) +2.0
-3.0
+3.0
Line Regulation(13)
REGLINE
REGLOAD
VG7(HI)
V5VSB = 4.75V to 5.25V, IOUT = 0A
V5VSB = 5V, IOUT = 0A to 720mA
0.01
0.01
8.75
0.8
0.10
0.20
%
%
V
Load Regulation(13)
Gate 7 Drive Voltage(4)
VAGP = VOUT(NOM) - 100mV, IG7 = 10µA
VAGP = VOUT(NOM) + 100mV, IG7 = -10µA
8.00
VG7(LO)
1.0
V
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SC1544
POWER MANAGEMENT
Electrical Characteristics (Cont.)(1)
PRELIMINARY
Unless specified: all applicable silver box supplies (3.3V, 5V, 5VSB) ± 5%, GND = 0V, VSENSE PINS = VOUT(NOM), TA = 25°C. Values in bold apply over full
operating ambient temperature range.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
mA
AGP Output (Cont.)
Gate 7 Drive Current(4)
IG7(SOURCE)
IG7(SINK)
IAGP
VAGP = VOUT(NOM) - 100mV, VG7 = 5V
VAGP = VOUT(NOM) + 100mV, VG7 = 3V
VAGP = 3.3V, TYPEDET = High
VAGP = 1.5V, TYPEDET = Low
2
4
-3.5
-235
-70
-5
Sense Pin Bias Current
-340
-105
-445
-140
µA
FC (Charge Pump)
Output Voltage
VFC
V5VSB = 5V
9.0
9.5
50
10.0
V
Overcurrent Protection(14)
Trip Threshold
VTH(OC)
30
70
%VOUT
ms
(15)
Short Circuit Immunity
1
75
Notes:
(1) This device is ESD sensitive. Use of standard ESD handling precautions is required.
(2) Guaranteed by design.
(3) Applies to S0 only.
(4) Gates 7 and 8 are high whenever 5VSB is present and greater than VUVLO, unless the over current protection
has been tripped.
(5) Applies to S3 sleep state only for 3.3V Dual Memory option. Applies to both S0 and S3 sleep state for 2.5V
Dual Memory Option
(6) Gate 5 is high in S0 and low in the S3 and S5 sleep states.
(7) Gate 6 is high in the S3 sleep state and low in S0 and in the S5 sleep state.
(8) Applies to S3 sleep state and S5 sleep state when the PCI pin is high.
(9) Gate 3 is high in S0 and low in the S3 and S5 sleep states.
(10) Gate 4 is high in the S3 sleep state and the S5 sleep state when the PCI pin is high. Gate 4 is low in S0,
and in the S5 sleep state when the PCI pin is low.
(11) Gate 2 is high in S0 and low in the S3 and S5 sleep states.
(12) Gate 1 is high in the S3 sleep state and the S5 sleep state when the USB pin is high. Gate 1 is low in S0,
and in the S5 sleep state when the USB pin is low.
(13) Applies to S0 only. VAGP = 3.3V when TYPEDET is high and 1.5V when the TYPEDET pin is low.
(14) Applies to 2.5V/3.3V Dual Memory, 3.3V Dual and 5V Dual outputs when enabled only. When an output is
disabled, that output is not monitored for OCP. The 1.8V and AGP outputs do not have over current protection.
(15) Minimum and maximum time limits for over current protection to trip when powered up (or enabled) into a
shorted output and when a short is applied to an enabled, OCP protected output.
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SC1544
POWER MANAGEMENT
PRELIMINARY
State Diagram Showing Gate Drive Status
Note:
(1) State machine will not allow illegal transitions such as S3 to S5. In order to get to S5 from S3, it is first
necessary to enter S0.
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SC1544
POWER MANAGEMENT
PRELIMINARY
Timing Diagrams
Startup
Normal
Operation
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SC1544
POWER MANAGEMENT
PRELIMINARY
Power Matrix
This table shows which output is powered from which supply under each system state.
System USB PCI /S3 /S5 PWR_OK 3.3V/2.5V Dual 3.3V
5V
3.3V/1.5V 1.8V(2)
AGP(2)
Comments
State
Memory
Dual Dual
S0
S3
S5
X(1)
X(1)
0
X(1)
X(1)
0
1
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
3.3V
5VSB
OFF
OFF
OFF
OFF
3.3V
5VSB 5VSB
OFF OFF
5V
3.3V
ON
ON
ON
ON
ON
3.3V
ON
ON
ON
ON
ON
All outputs off
PCI enabled
USB enabled
0
1
5VSB OFF
OFF 5VSB
5VSB 5VSB
1
0
1
1
PCI & USB
enabled
Notes:
(1) X = dont care. In S0 and S3, the 3.3V dual and 5V dual outputs are not affected by the state of the PCI and
USB pins. These outputs are only controlled by the sate of the PCI and USB pins in S5.
(2) Gate 7 and Gate 8 are high in all states with 5VSB > UVLO and OCP not tripped. If powered from 3.3V as shown
in the table, the AGP and 1.8V outputs are only present in S0, and will ramp with the 3.3V supply as it comes up.
This avoids dips in the 3.3V supply which would otherwise occur if Gate 7 and Gate 8 went high after the 3.3V
supply came up, demanding high currents to charge output capacitors. If powered from 5VSB they can be used to
create 1.5VSB, 1.8VSB or 3.3VSB as required.
Gates At A Glance
This table shows which gate drive pin controls which MOSꢀET:
Gate Number:
Pin Number:
Drives the FET between:
5V Dual
FET mode:
pass device
pass device
pass device
linear regulator
1
2
3
4
5
6
7
8
18
19(1)
19(1)
22
1
5VSB
5V
5V Dual
3.3V Dual
3.3V Dual
3.3V
5VSB
3.3V
5VSB
3.3V
3.3V
and
3.3V/2.5V Dual Memory pass device/linear regulator(2)
3
3.3V/2.5V Dual Memory
linear regulator
linear regulator
linear regulator
4
AGP
1.8V
24
Notes:
(1) Note common pin for Gate 2 and Gate 3 - both ꢀETs are operating as pass devices only in S0.
(2) ꢀET is acting as a pass device for 3.3V Dual Memory and as a linear regulator for 2.5V Dual Memory.
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2002 Semtech Corp.
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SC1544
POWER MANAGEMENT
PRELIMINARY
Pin Configuration
Ordering Information
Part Number
SC1544TS-X.XTR(1)(2)
SC1544EVB(3)
Package
TSSOP-24
N/A
Top View
Notes:
(1) Where -X.X denotes voltage options. Available
voltages are: 2.5V and 3.3V (2.5V Dual Memory or 3.3V
Dual Memory).
(2) Only available in tape and reel packaging. A reel
contains 2500 devices.
(3) Evaluation board for SC1544 - specify voltage
option when ordering.
TSSOP-24
Block Diagram
Marking Information
Top View
x.x = voltage option (Example: 3.3)
yyww = Date code (Example: 0012
xxxxxx = Lot number (Example: P94A01)
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2002 Semtech Corp.
9
SC1544
POWER MANAGEMENT
PRELIMINARY
Pin Descriptions
Pin #
Pin Name Pin Function
1
2
3
4
G5
3.3VDM
G6
Gate drive for MOSFET between VCC3 and 2.5V/3.3V Dual Memory.
Sense pin for 3.3V Dual Memory. Sense pin for 2.5V Dual Memory for 2.5V option.
Gate drive for MOSFET between 5VSB and 2.5V/3.3V Dual Memory.
G7
Gate drive for MOSFET between VCC3 and 1.5V/3.3V AGP. High when 5VSB is present and
greater than UVLO.
5
6
7
8
AGP
Sense pin for 1.5V/3.3V AGP.
TYPEDET Select 1.5V or 3.3V for AGP, high = 3.3V.
PWR_OK
EN
Power_OK signal from silver box.
Enable signal active high. Connect to 5VSB if not being used. Cycling the enable pin will reset
the over current latches.
9
/S3
Pulling this pin low (with /S5 high) causes the device to enter the S3 sleep state. Pulling both /S3
and /S5 low will cause the device to enter the S5 sleep state.
10
11
12
13
/S5
USB
PCI
Pulling this pin low along with /S3 causes the device to enter the S5 sleep state.
Enable pin for 5V Dual during S5 sleep state, high = ON.
Enable pin for 3.3V Dual during S5 sleep state, high = ON.
-CAP
Negative end of charge pump capacitor. Connect a 10nF ceramic capacitor between this pin
and pin 14 (+CAP).
14
15
16
17
18
19
20
21
22
23
24
+CAP
FC
Positive end of charge pump capacitor.
Charge pump output (9V nominal). Decouple this pin with a 0.1µF ceramic capacitor.
5V standby supply from silver box. Decouple this pin with a 1µF ceramic capacitor.
Sense pin for 5V Dual.
5VSB
5VD
G1
Gate drive for MOSFET between 5VSB and 5V Dual.
Gate drive for MOSFETs between VCC5 and 5V Dual and VCC3 and 3.3V Dual.
Reference ground.
G2/3
GND
3.3VD
G4
Sense pin for 3.3V Dual.
Gate drive for MOSFET between 5VSB and 3.3V Dual.
Sense pin for 1.8V LDO.
1.8V
G8
Gate drive for MOSFET between VCC3 (or 5VSB) and 1.8V. High when 5VSB is present and
greater than UVLO.
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SC1544
POWER MANAGEMENT
PRELIMINARY
Typical Applications Circuits
5V
C1
100uF/6.3V
GND
3.3V
C2
100uF/6.3V
GND
5VSB
C3
100uF/6.3V
GND
Q1
Q2
IRLR3103
IRLR3103
5V DUAL
C4
100uF/6.3V
GND
Q3
Q4
IRLR3103
IRLR3103
3.3V DUAL
C5
100uF/6.3V
GND
Q5
Q6
IRLR3103
IRLR3103
3.3V DUAL MEM
C6
100uF/6.3V
GND
Q7
IRLR3103
AGP
C7
100uF/6.3V
GND
Q8
IRLR3103
1.8V
U1
SC1544-3.3
G8
C8
1
24
23
22
21
20
19
18
17
16
15
14
13
100uF/6.3V
GND
G5
2
3.3VDM
1.8V
G4
3
4
G6
G7
3.3VD
GND
G2/3
G1
5
AGP
TYPEDET
PWR_OK
EN
6
TYPEDET
PWR_OK
EN
7
8
5VD
9
/SLP_S3
/SLP_S5
USB
/S3
5VSB
FC
10
11
12
/S5
USB
PCI
+CAP
-CAP
C10
0.1uF
C11
1uF
PCI
C9 0.01uF
Notes:
(1) 3.3V option shown - see below for Q5 configuration for 2.5V option.
(2) 1.8V output shown powered from 3.3V. If powered from 5VSB, this becomes 1.8VSB.
(3) See Applications Information.
3.3V
C2
D1
100uF/6.3V
GND
5VSB
C3
100uF/6.3V
GND
Q5
Q6
2.5V DUAL MEM
GND
U1
G5
SC1544-2.5
G8
1
2
24
23
22
21
20
19
18
17
16
15
14
13
C6
100uF/6.3V
2.5VDM
G6
1.8V
G4
3
4
Q5 body diode in series with D1 to pre-charge 2.5V Dual Memory
D1 to ensure that the linear regulator will still regulate
G7
3.3VD
GND
G2/3
G1
5
AGP
6
TYPEDET
PWR_OK
EN
7
8
5VD
9
/S3
5VSB
FC
10
11
12
/S5
USB
+CAP
-CAP
PCI
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2002 Semtech Corp.
11
SC1544
POWER MANAGEMENT
Applications Information
Theory Of Operation
PRELIMINARY
To prevent false latching due to capacitor inrush currents,
low supply rails or momentary overloads, the current limit
The SC1544 provides a simple way to power five seperate latch has a timer. If V is above the OCP threshold (V
)
TH(OC)
OUT
voltage buses while controlling them correctly using the before the timer times out, then the outputs do not
ACPI control interface (PWR_OK, /SLP_S3 and /SLP_S5). latch.
It requires only a single supply rail (5VSB from the system Reducing Commutation Noise
silver box) to operate. An internal charge pump generates
the gate voltages required to enable the use of n-channel The slew rate of the linears is slow enough to provide
ꢀETs throughout the design. The external ꢀETs are soft commutation. The non-linear switch outputs (5V and
operated in two discrete modes:
3.3V Duals) have fast slew rates. It may be necessary to
put a resistor in series with the gate to reduce transients
(3.3V Dual Memory shown):
1) as pass devices where V = V - (I * R )
DS(ON)
OUT
IN
OUT
2) as linear regulators.
Please refer to the Gates At A Glance section on page
8 and the Typical Applications Circuits on page 11 to
determine which ꢀETs operate in which mode.
3.3V
U1
G5
SC1544-3.3
G8
R1
1
2
24
23
22
21
20
19
18
17
16
15
14
13
Q5
IRLR3103
10k (typ.)
3.3VDM
G6
1.8V
G4
Linear Mode: the SC1544 contains a bandgap reference
trimmed for optimal temperature coefficient which is fed
into the inverting input of an error amplifier. The output
voltage of each linear regulator (monitored by the sense
pin for that output) is divided down internally using a
resistor divider and compared to the bandgap voltage.
The error amplifier drives the gate of the appropriate
external ꢀET to maintain the voltage at the non inverting
input, and hence the output voltage.
3
4
G7
3.3VD
GND
G2/3
G1
3.3V DUAL MEM
5
AGP
6
TYPEDET
PWR_OK
EN
7
8
5VD
9
/S3
5VSB
FC
10
11
12
/S5
USB
+CAP
-CAP
PCI
Pass Device Mode: when a particular output is enabled
(please refer to the Power Matrix section on page 8) in
pass mode (i.e. 5VSB to 5V Dual), the appropriate gate
drive will be driven high to turn the ꢀET hard on, minimizing
Another possible source of commutation noise occurs at
startup on 3.3V Dual Memory, when the standby ꢀET, Q6
and the pass-through ꢀET, Q5 are both off. 3.3V Dual
Memory will charge to 3.3V minus 0.7V (the drop across
the Q5 body diode). When PWR_OK asserts, Q6 turns on
shorting 3.3V to 3.3V Dual Memory, pulling it down locally
momentarily. This should not be an issue as long as there
is sufficient capacitance on 3.3V locally. Another way to
reduce this drop is to place a schottky diode across Q5
with the cathode towards 3.3V Dual Memory so this rail
charges to 3.3V minus 0.4V, thus reducing the drop when
Q5 turns on:
the voltage drop due to I *R
.
DS(ON)
OUT
The sense pins serve two functions:
1) to sense the output voltage for the linear regulators
2) to sense the output voltage for over current protection
Over Current Protection is provided for all dual outputs.
OCP is implemented by utilizing the R
of the ꢀETs. As
DS(ON)
the output current increases, the regulation loop
maintains the output voltage (linear mode only) by turning
3.3V
on the ꢀET more and more. Eventually, as the R
low
DS(ON)
+
C1
TO PIN
1
limit is reached (pass devices are already operating at
this point) the ꢀET will be unable to turn on any further
and the output voltage will start to fall. When the output
voltage falls to approximately 50% of nominal, all outputs
are latched off. Toggling the enable pin or cycling 5VSB
will reset the latch.
Increase bulk capacitance (preferred)
Q5
IRLR3103
D1 (optional)
TO PIN
2
3.3V DUAL MEM
www.semtech.com
2002 Semtech Corp.
12
SC1544
POWER MANAGEMENT
Applications Information (Cont.)
Linear Regulator Stability
PRELIMINARY
ꢀor the 2.5V Dual Memory linear regulator:
2.5
R2 ≤
≤ 71Ω
When extremely low ESR capacitors (Oscons, Polymers,
high value ceramics) are used on outputs requiring fast
transients (3.3V/2.5V memory), the linear regulators may
exhibit some overshoot and/or transient instability.
External compensation may be necessary (5VSB to 3.3V
Dual Memory shown):
350µA • 100
2.5V
<
VOUT (AJUSTED)
< 3.3V
C6
100uF/6.3V
I SENSE
R1
R2
GND
U1
G5
SC1544-2.5
G8
1
2
24
23
22
21
20
19
18
17
16
15
14
13
2.5VDM
G6
1.8V
G4
VOUT (FIXED)
U1
G5
SC1544-3.3
G8
3
3.3V DUAL MEM
1
2
24
23
22
21
20
19
18
17
16
15
14
13
R1 1k
4
G7
3.3VD
GND
G2/3
G1
3.3VDM
G6
1.8V
G4
5
3
C1
22nF
AGP
6
4
Q6
IRLR3103
TYPEDET
PWR_OK
EN
G7
3.3VD
GND
G2/3
G1
7
5
AGP
8
6
5VD
TYPEDET
PWR_OK
EN
9
7
5VSB
/S3
5VSB
FC
10
11
12
8
/S5
5VD
9
USB
+CAP
-CAP
/S3
5VSB
FC
10
11
12
PCI
/S5
USB
+CAP
-CAP
PCI
Another possibility is to use dual capacitor types for the
load capacitor - a ceramic capacitor will provide high
frequency decoupling for the load while an electrolytic
capacitor (high ESR) will tame the Q to prevent instability:
The output voltage can only be adjusted upwards from
the fixed output voltage, and can be calculated using the
following equation:
R1
3.3V DUAL MEM
VOUT(ADJUSTED) = VOUT(FIXED) • 1+
+ R1• ISENSE Volts
R2
Therefore to set the 2.5V Dual Memory linear regulator
to 2.6V, for example, R1 = 2.8Ω and R2 = 69.8Ω. The
maximum voltage to which an output can be set using
this method is limited by the input voltage to the ꢀET(s)
and the RDS(ON) of the ꢀET(s).
+
C1
bulk
C2
Electrolytic
-
Ceramic - high frequency decoupling
Adjusting the Output Voltage of the Linear Regulators
Please note that this technique cannot be used for the
3.3V Dual Memory, 3.3V Dual and 5V Dual outputs since
the output is switched via a pass device (i.e. not
regulated) when not in S0.
It is possible to adjust the output voltage of the linear
regulators (1.8V, 2.5V Dual Memory and AGP) by
applying an external resistor divider to the sense pin (see
below). Since the sense pins sink a nominal 100µA (1.8V
LDO, 150µA for the 1.5V AGP LDO, 325µA for the 3.3V
AGP LDO and 350µA for the 2.5V Dual Memory LDO),
the resistor values should be selected to allow 100x that
current to flow through the divider. This will ensure that
variations in the sense current will have negligible affect
on the output voltage regulation. Thus a target value for
R2 (maximum) can be calculated:
(ault Protection Hints
Loss of AC Power: if it is possible during brownouts or
momentary loss of AC power to the computer silver box
that PWR_OK can assert low while S3 and S5 remain
high then the over current protection may trigger. This is
because the state machine will ignore this illegal
transition and monitor all outputs as if they are still in
S0, despite the fact that the inputs are going away. If
5VSB decays slowly, S3 and S5 remain high, and one
output drops below the OCP threshold for long enough
VOUT(FIXED)
R2 ≤
Ω
ISENSE • 100
www.semtech.com
2002 Semtech Corp.
13
SC1544
POWER MANAGEMENT
PRELIMINARY
Applications Information (Cont.)
(ault Protection Hints ꢀCont.)
that the OCP times out then the outputs will latch off.
Then if the AC power returns after the OCP latches off,
but before the 5VSB supply drops below UVLO, then the
device will not start up again until EN or 5VSB is cycled.
One way to avoid this happening is to force the device
into S3 if PWR_OK goes low but S3 and S5 remain high
using the circuit shown below. This will supply the
outputs from 5VSB which will either cause 5VSB to drop
below UVLO and reset the part when the AC power comes
back up, or it may prevent OCP occuring at all. Either way
correct functionality will be guaranteed once AC power
returns.
U1
G5
SC1544-2.5
G8
1
2
24
23
22
21
20
19
18
17
16
15
14
13
2.5VDM
G6
1.8V
G4
3
4
G7
3.3VD
GND
G2/3
G1
5
AGP
6
TYPEDET
PWR_OK
EN
7
PWR_OK
/SLP_S3
8
D1
1N4148
5VD
9
/S3
5VSB
FC
10
11
12
/S5
R1 4.7k
USB
+CAP
-CAP
PCI
Incorrect Signals (rom Silver Box: Some silver boxes
have been found that produce incorrect voltages on the
PWR_OK line, producing dangerous negative voltage
spikes up to -1V or greater. Such spikes exceed the
absolute maximum ratings for this device and can cause
the device to malfunction. If a supply produces such
spikes they can be clamped to GND using a small schottky
diode as shown below, completely removing any threat.
U1
G5
SC1544-2.5
G8
1
2
24
23
22
21
20
19
18
17
16
15
14
13
2.5VDM
G6
1.8V
G4
3
4
G7
3.3VD
GND
G2/3
G1
5
AGP
6
TYPEDET
PWR_OK
EN
7
PWR_OK
8
5VD
9
D1
/S3
5VSB
FC
10
11
12
/S5
USB
+CAP
-CAP
PCI
www.semtech.com
2002 Semtech Corp.
14
SC1544
POWER MANAGEMENT
PRELIMINARY
Outline Drawing - TSSOP-24
Land Pattern - TSSOP-24
Contact Information
Semtech Corporation
Power Management Products Division
200 ꢀlynn Road, Camarillo, CA 93012
Phone: (805)498-2111 ꢀAX (805)498-3804
www.semtech.com
2002 Semtech Corp.
15
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