SC1549TSTR [SEMTECH]
Power Supply Support Circuit, Fixed, 3 Channel, PDSO20, TSSOP-20;
| 型号： | SC1549TSTR |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Power Supply Support Circuit, Fixed, 3 Channel, PDSO20, TSSOP-20 光电二极管 |
| 文件： | 总12页 (文件大小：259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC1549
Instantly Available ACPI Controller
for Advanced Motherboards
PRELIMINARY
POWER MANAGEMENT
Description
Features
The new ACPI specification extends the computers use
by reducing boot time, enabling remote access and
reducing power consumption.
Complete programmable supply for instantly available
PC systems
5V dual and 3.3V dual supplies are programmable to
be active or inactive in S5
Integrated AGP voltage supply with “TYPEDET” signal
for 3.3V or 1.5V operation can be used to generate
a 1.5V standby supply
Integrated charge pump removes the need for PMOS
FETs, enables single supply operation
Over current protection on dual outputs
TSSOP-20 package
Semtech’s SC1549, SC243x, SC112A with SC1175 or
SC1114 with SC1110 provide all the voltages necessary
for a Pentium 4 Brookdale-G ACPI system.
The SC1549 offers three independant supplies: a 5V
dual supply for USB, a 3.3V dual supply for PCI or 3.3VSB
and a 1.5V or 3.3V supply for AGP or 1.5VSB. The AGP
supply is programmable using the system TYPEDET signal.
An on-board internal charge pump eliminates the need
for P-channel MOSFETs and enables function from a single Applications
5V supply (system 5VSB). Both dual outputs are over
current protected.
Instantly available motherboards
Typical Application Circuit
5V
C1
100uF/6.3V
GND
3.3V
C2
100uF/6.3V
GND
5VSB
C3
100uF/6.3V
GND
Q1
Q2
IRLR3103
IRLR3103
5V DUAL
C4
100uF/6.3V
GND
Q3
Q4
IRLR3103
IRLR3103
3.3V DUAL
C5
100uF/6.3V
GND
Q5
IRLR3103
U1
1
2
20
19
18
17
16
15
14
13
12
11
AGP
GND
5VSB
G5
G4
C6
3.3VD
GND
G2/3
G1
100uF/6.3V
3
AGP
4
TYPEDET
PWR_OK
EN
TYPEDET
PWR_OK
EN
5
6
5VD
7
/SLP_S3
/SLP_S5
USB
/S3
5VSB
FC
8
/S5
9
USB
+CAP
-CAP
C7
C8
10
0.1uF
1uF
PCI
PCI
C9 0.01uF
SC1549
Revision 2, November 2002
1
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SC1549
POWER MANAGEMENT
PRELIMINARY
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied.
Parameter
Symbol
Maximum
Units
Input Supply Voltage
V5VSB
-0.3 to 7
-0.3 to V5VSB
-0.3 to 13.2
17
V
V
Logic Input Pins
Charge Pump Output Voltage
Thermal Impedance Junction to Case
Thermal Resistance Junction to Ambient
Operating Ambient Temperature Range
Operating Junction Temperature Range
Storage Temperature Range
VFC
θJC
V
°C/W
°C/W
°C
90.2
θJA
TA
0 to 70
TJ
0 to 125
-65 to +150
300
°C
TSTG
TLEAD
°C
Lead Temperature (Soldering) 10 Sec.
°C
Electrical Characteristics(1)
Unless specified: all applicable silver box supplies (3.3V, 5V, 5VSB) ± 5%, GND = 0V, VSENSE PINS = VOUT(NOM), TA = 25°C. Values in bold apply over full
operating ambient temperature range.
Parameter
Symbol
Test Conditions
Min
4.5
Typ
Max
Units
IN
Supply Voltage
Quiescent Current
V5VSB
IQ
5.0
10
5.5
15
20
V
All states (S0, S3, S5, disabled)
V5VSB Rising
mA
Undervoltage Lockout
Threshold Voltage
VUVLO
3.5
4.0
4.4
V
Logic Inputs (EN, PCI, PWR_OK, /S3, /S5, TYPEDET, USB)
Logic Pin Sink Current(2)
ISINK
VBIAS = 5V, all logic pins
EN, VEN = 0V
0.1
0.5
50
1
µA
µA
Logic Pin Source Current
ISOURCE
3
PCI, TYPEDET, USB, VPIN = 0V
/S3, PWR_OK, VPIN = 0V
/S5, V/S5 = 0V
200
400
600
100
150
Threshold Voltage
VIH
VIL
2.4
V
V
0.8
3.3V Dual Output
Output Voltage(3)
V3.3VD
1mA ≤ IOUT ≤ 720mA
3.250
3.300
3.350
V
3.217
3.383
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2002 Semtech Corp.
2
SC1549
POWER MANAGEMENT
PRELIMINARY
Electrical Characteristics (Cont.)(1)
Unless specified: all applicable silver box supplies (3.3V, 5V, 5VSB) ± 5%, GND = 0V, VSENSE PINS = VOUT(NOM), TA = 25°C. Values in bold apply over full
operating ambient temperature range.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
3.3V Dual Output (Cont.)
Line Regulation(3)
REGLINE
REGLOAD
VG3(HI)
V5VSB = 4.75V to 5.25V, IOUT = 0A
V5VSB = 5V, IOUT = 0A to 720mA
IG3 = 10µA
0.01
0.01
8.75
40
0.10
0.20
%
%
Load Regulation(3)
Gate 3 Drive Voltage(4)
8.00
V
VG3(LO)
IG3 = -10µA
100
mV
mA
Gate 3 Drive Current(4)
Gate 4 Drive Voltage(5)
Gate 4 Drive Current(5)
IG3(SOURCE)
IG3(SINK)
VG4(HI)
VG3 = 5V
0.5
-10
0.7
-14
8.75
0.8
4
VG3 = 3V
V3.3VD = 3.2V, IG4 = 10µA
V3.3VD = 3.4V, IG4 = -10µA
V3.3VD = VOUT(NOM) - 100mV, VG4 = 5V
V3.3VD = VOUT(NOM) + 100mV, VG4 = 3V
Sinking, V3.3VD = 3.3V
8.00
V
VG4(LO)
1.0
-130
100
IG4(SOURCE)
IG4(SINK)
I3.3VD
2
mA
µA
-3.5
-70
5
Sense Pin Bias Current
5V Dual Output
Gate 2 Drive Voltage(6)
-100
VG2(HI)
VG2(LO)
IG2(SOURCE)
IG2(SINK)
VG1(HI)
IG2 = 10µA
IG2 = -10µA
VG2 = 5V
8.00
8.75
40
V
mV
mA
Gate 2 Drive Current(6)
Gate 1 Drive Voltage(7)
Gate 1 Drive Current(7)
0.5
-10
0.7
-14
8.75
40
VG2 = 3V
IG1 = 10µA
IG1 = -10µA
VG1 = 5V
8.00
V
VG1(LO)
IG1(SOURCE)
IG1(SINK)
I5VD
100
16
mV
mA
0.5
-10
0.7
-14
VG1 = 3V
Sense Pin Bias Current(2)
AGP Output
Output Voltage(8)
V5VD = 5V
µA
%
VAGP
1mA ≤ IOUT ≤ 720mA
-2.0
VOUT(NOM) +2.0
-3.0
+3.0
Line Regulation(8)
REGLINE
REGLOAD
VG5(HI)
V5VSB = 4.75V to 5.25V, IOUT = 0A
V5VSB = 5V, IOUT = 0A to 720mA
VAGP = VOUT(NOM) - 100mV, IG5 = 10µA
VAGP = VOUT(NOM) + 100mV, IG5 = -10µA
3
0.01
0.01
8.75
0.8
0.10
0.20
%
%
V
Load Regulation(8)
Gate 5 Drive Voltage(9)
8.00
VG5(LO)
1.0
V
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2002 Semtech Corp.
SC1549
POWER MANAGEMENT
PRELIMINARY
Electrical Characteristics (Cont.)(1)
Unless specified: all applicable silver box supplies (3.3V, 5V, 5VSB) ± 5%, GND = 0V, VSENSE PINS = VOUT(NOM), TA = 25°C. Values in bold apply over full
operating ambient temperature range.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
mA
AGP Output (Cont.)
Gate 5 Drive Current(9)
IG5(SOURCE)
IG5(SINK)
IAGP
VAGP = VOUT(NOM) - 100mV, VG5 = 5V
VAGP = VOUT(NOM) + 100mV, VG5 = 3V
VAGP = 3.3V, TYPEDET = High
VAGP = 1.5V, TYPEDET = Low
2
4
-3.5
-235
-110
-5
Sense Pin Bias Current
-340
-160
-445
-210
µA
FC (Charge Pump)
Output Voltage
VFC
V5VSB = 5V
9.0
9.5
50
10.0
V
Overcurrent Protection(10)
Trip Threshold
VTH(OC)
30
70
%VOUT
ms
(11)
Short Circuit Immunity
1
75
Notes:
(1) This device is ESD sensitive. Use of standard ESD handling precautions is required.
(2) Guaranteed by design.
(3) Applies to S3 sleep state and S5 sleep state when the PCI pin is high.
(4) Gate 3 is high in S0 and low in the S3 and S5 sleep states.
(5) Gate 4 is high in the S3 sleep state and the S5 sleep state when the PCI pin is high. Gate 4 is low in S0, and
in the S5 sleep state when the PCI pin is low.
(6) Gate 2 is high in S0 and low in the S3 and S5 sleep states.
(7) Gate 1 is high in the S3 sleep state and the S5 sleep state when the USB pin is high. Gate 1 is low in S0,
and in the S5 sleep state when the USB pin is low.
(8) Applies to S0 only. VAGP = 3.3V when TYPEDET is high and 1.5V when the TYPEDET pin is low.
(9) Gate 5 is high whenever 5VSB is present and > UVLO, unless OCP has been tripped.
(10) Applies to 3.3V Dual and 5V Dual outputs when enabled only. When an output is disabled, that output is not
monitored for OCP. The AGP output does not have over current protection.
(11) Minimum and maximum time limits for over current protection to trip when powered up (or enabled) into a
shorted output and when a short is applied to an enabled, OCP protected output.
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4
SC1549
POWER MANAGEMENT
PRELIMINARY
State Diagram Showing Gate Drive Status
Note:
(1) State machine will not allow illegal transitions such as S3 to S5. In order to get to S5 from S3, it is first
necessary to enter S0.
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2002 Semtech Corp.
5
SC1549
POWER MANAGEMENT
PRELIMINARY
Timing Diagrams
Startup
Normal
Operation
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2002 Semtech Corp.
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SC1549
POWER MANAGEMENT
PRELIMINARY
Power Matrix
This table shows which output is powered from which supply under each system state.
System State USB PCI
/S3
/S5 PWR_OK 3.3V Dual 5V Dual
3.3V/1.5V
AGP(2)
Comments
S0
S3
S5
X(1)
X(1)
0
X(1)
X(1)
0
1
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
3.3V
5VSB
OFF
5V
3.3V
ON
ON
ON
ON
ON
5VSB
OFF
All outputs off
PCI enabled
0
1
5VSB
OFF
OFF
1
0
5VSB
5VSB
USB enabled
1
1
5VSB
PCI & USB enabled
Notes:
(1) X = “don’t care”. In S0 and S3, the 3.3V dual and 5V dual outputs are not affected by the state of the PCI and
USB pins. These outputs are only controlled by the state of the PCI and USB pins in S5.
(2) Gate 5 is high in all states with 5VSB > UVLO and OCP not tripped. If powered from 3.3V as shown in the table,
the AGP output is only present in S0, and will ramp with the 3.3V supply as it comes up. This avoids dips in the 3.3V
supply which would otherwise occur if Gate 5 went high after the 3.3V supply came up, demanding high currents to
charge output capacitors. If powered from 5VSB this output can be used to create 1.5VSB or 3.3VSB as required.
Gates At A Glance
This table shows which gate drive pin controls which MOSFET:
Gate Number:
Pin Number:
Drives the FET between:
5V Dual
FET mode:
pass device
pass device
pass device
linear regulator
linear regulator
1
2
3
4
5
16
17(1)
17(1)
20
5VSB
5V
5V Dual
3.3V Dual
3.3V Dual
AGP
3.3V
5VSB
3.3V
and
2
Notes:
(1) Note common pin for Gate 2 and Gate 3 - both FETs are operating as pass devices only in S0.
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2002 Semtech Corp.
7
SC1549
POWER MANAGEMENT
PRELIMINARY
Pin Configuration
Ordering Information
Part Number
SC1549TSTR(1)
Note:
Package
Top View
TSSOP-20
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
TSSOP-20
Block Diagram
Marking Information
Top View
yyww = Date code (Example: 0012)
xxxxxx = Lot number (Example: P94A01)
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2002 Semtech Corp.
8
SC1549
POWER MANAGEMENT
PRELIMINARY
Pin Descriptions
Pin #
Pin Name Pin Function
1
2
5VSB
G5
5V standby supply from silver box. Connect this pin to pin 14.
Gate drive for MOSFET between 3.3V and 1.5V/3.3V AGP. High when 5VSB is present and
greater than UVLO.
3
4
5
6
AGP
Sense pin for 1.5V/3.3V AGP.
TYPEDET Select 1.5V or 3.3V for AGP, high = 3.3V.
PWR_OK
EN
Power_OK signal from silver box.
Enable signal active high. Connect to 5VSB if not being used. Cycling the enable pin will reset
the over current latches.
7
/S3
Pulling this pin low (with /S5 high) causes the device to enter the S3 sleep state. Pulling both /S3
and /S5 low will cause the device to enter the S5 sleep state.
8
9
/S5
USB
PCI
Pulling this pin low along with /S3 causes the device to enter the S5 sleep state.
Enable pin for 5V Dual during S5 sleep state, high = ON.
10
11
Enable pin for 3.3V Dual during S5 sleep state, high = ON.
-CAP
Negative end of charge pump capacitor. Connect a 10nF ceramic capacitor between this pin
and pin 12 (+CAP).
12
13
14
15
16
17
18
19
20
+CAP
FC
Positive end of charge pump capacitor.
Charge pump output (9V nominal). Decouple this pin with a 0.1µF ceramic capacitor.
5V standby supply from silver box. Decouple this pin with a 1µF ceramic capacitor.
Sense pin for 5V Dual.
5VSB
5VD
G1
Gate drive for MOSFET between 5VSB and 5V Dual.
Gate drive for MOSFETs between 5V and 5V Dual and 3.3V and 3.3V Dual.
Reference ground.
G2/3
GND
3.3VD
G4
Sense pin for 3.3V Dual.
Gate drive for MOSFET between 5VSB and 3.3V Dual.
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2002 Semtech Corp.
9
SC1549
POWER MANAGEMENT
Applications Information
Theory Of Operation
PRELIMINARY
will reset the latch.
To prevent false latching due to capacitor inrush currents,
The SC1549 provides a simple way to power three low supply rails or momentary overloads, the current limit
seperate voltage buses while controlling them correctly latch has a timer. If VOUT is above the OCP threshold (VTH(OC)
using the ACPI control interface (PWR_OK, /SLP_S3 and before the timer “times out”, then the outputs do not
/SLP_S5). latch.
)
It requires only a single supply rail (5VSB from the system Reducing Commutation Noise
silver box) to operate. An internal charge pump generates The slew rate of the linears is slow enough to provide
the gate voltages required to enable the use of n-channel soft commutation. The non-linear switch outputs (5V and
MOSFETs throughout the design. The external FETs are 3.3V Duals) have fast slew rates. It may be necessary to
operated in two discrete modes:
1) as pass devices where VOUT = VIN - (IOUT * RDS(ON)
2) as linear regulators.
put a resistor in series with the gate to reduce transients
(3.3V Dual shown):
)
Q3
Please refer to the “Gates At A Glance” section on page
7 and the Typical Applications Circuit on page 1 to
determine which FETs operate in which mode.
IRLR3103
3.3V DUAL
3.3V
U1
SC1549
Linear Mode: the SC1549 contains a bandgap reference
trimmed for optimal temperature coefficient which is fed
into the inverting input of an error amplifier. The output
voltage of each linear regulator (monitored by the sense
pin for that output) is divided down internally using a
resistor divider and compared to the bandgap voltage.
The error amplifier drives the gate of the appropriate
external FET to maintain the voltage at the non inverting
input, and hence the output voltage.
1
20
19
18
17
16
15
14
13
12
11
5VSB
G4
3.3VD
GND
G2/3
G1
2
G7
R1
3
10k (typ.)
AGP
4
TYPEDET
5
6
PWR_OK
EN
5VD
7
/S3
5VSB
FC
8
/S5
9
USB
PCI
+CAP
-CAP
10
Pass Device Mode: when a particular output is enabled
(please refer to the “Power Matrix” section on page 7) in
pass mode (i.e. 5VSB to 5V Dual), the appropriate gate
drive will be driven high to turn the FET hard on, minimizing
Another possible source of commutation noise occurs at
startup on 3.3V Dual and 5V Dual, when the standby
FET and the pass-through FET are both off. Each output
will charge to 3.3V (or 5V as applicable) minus 0.7V (the
drop across the body diode). When PWR_OK asserts, the
main pass FET turns on shorting the supply to the output,
0.7V below it, pulling it down locally momentarily. This
should not be an issue as long as there is sufficient
capacitance on the supplies locally. Another way to reduce
this drop is to place a schottky diode across the FET with
the cathode towards the output so it charges to the supply
voltage minus 0.4V, thus reducing the drop when the
FET turns on (3.3V Dual shown):
the voltage drop due to IOUT*RDS(ON)
.
The sense pins serve two functions:
1) to sense the output voltage for the linear regulators
2) to sense the output voltage for over current protection
Over Current Protection is provided for both dual outputs.
OCP is implemented by utilizing the RDS(ON) of the FETs. As
the output current increases, the regulation loop
maintains the output voltage (linear mode only) by turning
on the FET more and more. Eventually, as the RDS(ON) low
limit is reached (pass devices are already operating at
this point) the FET will be unable to turn on any further
and the output voltage will start to fall. When the output
voltage falls to approximately 50% of nominal, all outputs
are latched off. Toggling the enable pin or cycling 5VSB
3.3V
C1
Increase bulk capacitance (preferred)
+
TO PIN 17, G2/3
Q5
IRLR3103
D1 (optional)
TO PIN 19, 3.3VD
3.3V DUAL
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2002 Semtech Corp.
10
SC1549
POWER MANAGEMENT
PRELIMINARY
Applications Information (Cont.)
Adjusting the Output Voltage of the Linear Regulator
momentary loss of AC power to the computer “silver box”
that PWR_OK can assert low while S3 and S5 remain
It is possible to adjust the output voltage of the linear high then the over current protection may trigger. This is
regulator (1.5V/3.3V/AGP) by applying an external because the state machine will ignore this illegal
resistor divider to the sense pin (see below). Since the transition and monitor all outputs as if they are still in
sense pin sinks a nominal 160µA (TYPEDET = low, 340µA S0, despite the fact that the inputs are going away. If
for TYPEDET = high), the resistor values should be 5VSB decays slowly, S3 and S5 remain high, and one
selected to allow 100x that current to flow through the output drops below the OCP threshold for long enough
divider. This will ensure that variations in the sense that the OCP “times out” then the outputs will latch off.
current will have negligible affect on the output voltage Then if the AC power returns after the OCP latches off,
regulation. Thus a target value for R2 (maximum) can be but before the 5VSB supply drops below UVLO, then the
calculated:
device will not start up again until EN or 5VSB is cycled.
One way to avoid this happening is to force the device
into S3 if PWR_OK goes low but S3 and S5 remain high
using the circuit shown below. This will supply the
outputs from 5VSB which will either cause 5VSB to drop
below UVLO and reset the part when the AC power comes
back up, or it may prevent OCP occuring at all. Either way
correct functionality will be guaranteed once AC power
returns.
VOUT(FIXED)
ISENSE • 100
R2 ≤
Ω
1.5
160µA • 100
R2 ≤
≤ 94 Ω
For TYPEDET = low:
1.5V < VOUT (ADJUSTED) < VIN
AGP
I SENSE
U1
SC1549
C6
1
20
19
18
17
16
15
14
13
12
11
100uF/6.3V
GND
R1
5VSB
G4
U1
SC1549
2
G7
3.3VD
GND
G2/3
G1
1
2
20
19
18
17
16
15
14
13
12
11
5VSB
G4
3.3VD
GND
G2/3
G1
3
VOUT (FIXED = 1.5V)
AGP
G7
4
TYPEDET
3
R2
AGP
TYPEDET
PWR_OK
EN
5
PWR_OK
4
6
EN
5VD
5
PWR_OK
/SLP_S3
7
/S3
5VSB
FC
6
D1
5VD
8
/S5
7
R1 4.7k
1N4148
/S3
5VSB
FC
9
USB
+CAP
-CAP
8
/S5
10
PCI
9
USB
+CAP
-CAP
10
PCI
The output voltage can only be adjusted upwards from
the fixed output voltage, and can be calculated using the
following equation:
Incorrect Signals From Silver Box: Some silver boxes
have been found that produce incorrect voltages on the
PWR_OK line, producing dangerous negative voltage
spikes up to -1V or greater. Such spikes exceed the
absolute maximum ratings for this device and can cause
the device to malfunction. If a supply produces such
spikes they can be clamped to GND using a small schottky
diode as shown below, completely removing any threat.
R1
R2
VOUT(ADJUSTED) = VOUT(FIXED) • 1+
+ R1• ISENSE Volts
Therefore to set the linear regulator with TYPEDET = low
to 1.8V, for example, R1 = 17.8Ω and R2 = 90.9Ω. The
maximum voltage to which an output can be set using
this method is limited by the input voltage to the FET(s)
and the RDS(ON) of the FET(s).
U1
SC1549
1
2
20
19
18
17
16
15
14
13
12
11
5VSB
G4
3.3VD
GND
G2/3
G1
G7
3
Please note that this technique cannot be used for the
3.3V Dual and 5V Dual outputs since the output is
switched via a pass device (i.e. not regulated) when not
in S0.
AGP
TYPEDET
PWR_OK
EN
4
5
PWR_OK
6
D1
5VD
7
/S3
5VSB
FC
8
/S5
Fault Protection Hints
9
USB
+CAP
-CAP
10
PCI
Loss of AC Power: if it is possible during brownouts or
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2002 Semtech Corp.
11
SC1549
POWER MANAGEMENT
PRELIMINARY
Outline Drawing - TSSOP-20
Land Pattern - TSSOP-20
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
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2002 Semtech Corp.
12
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SEMTECH
SC1563IMS-1.8TRT
Fixed/Adjustable Positive LDO Regulator, 1.2V Min, 4.8V Max, 0.7V Dropout, CMOS, PDSO8, LEAD FREE, MSOP-8
SEMTECH
SC1563IMS-2.5TR
Fixed/Adjustable Positive LDO Regulator, 1.2V Min, 4.8V Max, 0.7V Dropout, CMOS, PDSO8, MSOP-8
SEMTECH
SC1563IMS-2.5TRT
Fixed/Adjustable Positive LDO Regulator, 1.2V Min, 4.8V Max, 0.7V Dropout, CMOS, PDSO8, LEAD FREE, MSOP-8
SEMTECH
SC1563IMS-2.8TR
Fixed/Adjustable Positive LDO Regulator, 1.2V Min, 4.8V Max, 0.7V Dropout, CMOS, PDSO8, MSOP-8
SEMTECH
SC1563IMS-2.8TRT
Fixed/Adjustable Positive LDO Regulator, 1.2V Min, 4.8V Max, 0.7V Dropout, CMOS, PDSO8, LEAD FREE, MSOP-8
SEMTECH
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