SC2447TSTRT [SEMTECH]
Dual-Phase, Single or Dual Output Synchronous Step-Down Controller; 双相，单或双输出同步降压型控制器
| 型号： | SC2447TSTRT |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Dual-Phase, Single or Dual Output Synchronous Step-Down Controller |
| 文件： | 总26页 (文件大小：756K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC2447
Dual-Phase, Single or Dual Output
Synchronous Step-Down Controller
POWER MANAGEMENT
Features
Description
ꢀ2-Phase Step-down Controller optimized for Philips
The SC2447 is a versatile high-frequency dual phase PWM
step-down controller optimized for Philips and Renesas
DrMOSTM. Both phases are capable of sourcing or sink-
ing load currents, making the SC2447 suitable for net-
working system power and DDR applications.
or Renesas DrMOSTM
ꢀOut of Phase Operation for Low Input Current Ripple
ꢀOutputs Source and Sink Current
ꢀFixed Frequency Peak Current-Mode Control
ꢀLossless Inductor DCR Current Sensing
ꢀOptional Resistor Current-Sensing for Precise Cur-
rent-Limit
The SC2447 employs fixed frequency, continuous-con-
duction peak current-mode control for easy compensa-
tion and fast transient response.
ꢀDual 30A Outputs or 2-Phase 60A Single Output
Operation
ꢀWide Input Voltage Range: 4.65V to 15V
ꢀIndividual Closed-Loop Soft-Start, Overload Shut-
down Timer and Enable
The SC2447 can be used to generate two independent
outputs (up to 30A per output) or a single 60A output
with shared phase current. The PWM signals are 180°
out of phase to minimize input/output ripple.
ꢀOutput Voltage as Low as 0.5V
ꢀStarts into Pre-Bias Output
ꢀTri-State PWM Output during Shutdown
ꢀProgrammable Frequency Up to 1MHz Per Phase
ꢀExternal Synchronization
Either inductor DC resistance or precision sense resistor
can be used for current-mode control. Inductor DC resis-
tance sensing has the advantage of being lossless.
ꢀTSSOP-28 Lead-free Package. Fully WEEE and RoHS
Compliant
Each phase has individual closed-loop soft-start and over-
load shutdown timer. The SC2447 powers up neatly with
pre-biased output. It has tri-state shutdown and hiccup
overload protection. In two-phase single-output configu-
ration, the master timer controls the soft-start and over-
load shutdown functions. The SC2447 is in a lead-free,
WEEE and RoHS compliant, TSSOP-28 package.
Applications
ꢀTelecommunication Power Supplies
ꢀDDR Memory Power Supplies
ꢀGraphic Power Supplies
ꢀServers and Base Stations
Typical Application Circuit
VIN
12V
RVCC
10Ω
R2
10Ω
R1
10Ω
CIN2
22µF
x 4
CIN1
22µF
x 4
VDDO
CBP
VDDC
VDDG
VDDC
VDDG
VDDO
CBP
C3
1µF
C4
1µF
C5
1µF
C6
1µF
CB2
100nF
CB1
100nF
AVCC
L1
CBN
VO
CBN
VO
L2
CVCC
4.7µF
1µH/1.8mΩ
REG5V
VI
REG5V
VI
0.4µH/1mΩ
VOUT1
2.5V/20A
VOUT2
1.2V/25A
GDH1
GDL1
GDH2
GDL2
RS1B
RS2B
200KΩ
DISABLE
DISABLE
22.1KΩ
CO1
100µF
x 3
CO2
100µF
x 3
VSSO
VSSO
VSSC
VSSC
RS1A
22.1KΩ
RS2A
SC2447
22.1KΩ
PIP212-12M
PIP212-12M
CCS2
68nF
CS1+
CS1-
CCS1
100nF
CS2+
CS2-
RFB1A
10KΩ
RFB2A
10KΩ
RS2C , 20KΩ
RS1C , 11KΩ
IN1-
IN2-
COMP2
ROSC
AGND
RFB1B
2.49KΩ
RFB2B
7.15KΩ
COMP1
ROSC , 51.1KΩ
RA1
RA2
REFOUT
REF
24.9KΩ
16.9KΩ
CCMP1
10pF
CCMP2
10pF
CA1
CREF
CA2
3.3nF
0.1uF
3.3nF
REFIN
SYNC
SS1/EN1
SS2/EN2
CSS1
0.1µF
CSS2
0.1µF
Figure 1
1
www.semtech.com
Revision: December 15, 2006
SC2447
POWER MANAGEMENT
Ordering Information
Pin Configurations
Device
Top Mark
SC2447
Package
TOP VIEW
SC2447TSTRT(1)(2)
TSSOP-28
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CS1+
CS1-
SS1/EN1
NC
SC2447EVB
Evaluation Board
3
ROSC
IN1-
NC
Notes:
4
GDH1
GDL1
NC
(1) Only available in tape and reel packaging. A reel contains 2500 devices
for TSSOP package.
(2) Lead free product. This product is fully WEEE and RoHS compliant.
5
COMP1
SYNC
AGND
REF
6
7
NC
8
GDL2
GDH2
NC
9
REFOUT
REFIN
COMP2
IN2-
10
11
12
13
14
NC
NC
CS2-
AVCC
SS2/EN2
CS2+
(28 Pin TSSOP)
θJA= 84°C/W; θJC= 13°C/W.
Figure 2
Absolute Maximum Rating
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device
reliability.
Parameter
Symbol
AVCC
Maximum Ratings
-0.3 to 16
Units
V
Supply Voltage
Gate Outputs GDH1, GDH2, GDL1, GDL2 voltages
IN1-, IN2- Voltages
VGDH1, VGDH2,VGDL1, VGDL2
VIN1-,VIN2-
VREF ,VREFOUT
VREFIN
COMP1,VCOMP2
-0.3 to 6
V
-0.3 to AVCC+0.3
-0.3 to 6
V
REFOUT Voltages
V
REF, REFIN Voltage
-0.3 to AVCC+0.3
-0.3 to AVCC+0.3
-0.3 to AVCC+0.3
-0.3 to AVCC+0.3
-0.3 to 6
V
COMP1, COMP2 Voltages
CS1+, CS1-, CS2+ and CS2- Voltages
SYNC Voltage
V
V
VCS1+,VCS1-,VCS2+,VCS2-
V
VSYNC
VSS1,VSS2
TSTG
V
SS1/EN1 AND SS2/EN2 Voltages
Storage Temperature Range
Lead Temperature (Soldering) 10 sec
Junction Temperature
V
-60 to 150
°C
°C
°C
kV
TLEAD
TJ
260
150
ESD Rating (Human Body Model)
ESD
2
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© 2006 Semtech Corp.
2
SC2447
POWER MANAGEMENT
Recommended Operating Conditions
The performance is not guarantied if exceeding the specifications below.
Parameter
Symbol
AVCC
TA
Conditions
Min
4.65
-40
Typ
Max
15
Units
V
AVCC Operating Voltage
Ambient temperature Range
Junction Temperature Range
85
°C
TJ
-40
125
°C
Electrical Characteristics
Unless specified: AVCC = 12V, SYNC = 0, ROSC = 51.1kΩ, -40°C < TA = TJ < 125°C
Parameter
Symbol
Conditions
Min
Typ
Max
4.65
15
Units
Undervoltage Lockout
AVCC Start Threshold
AVCCTH
AVCCHYST
ICC
AVCC Increasing
4.50
0.2
8
V
V
AVCC Start Hysteresis
AVCC Operating Current
AVCC Quiescent Current in UVLO
Channel 1 Error Amplifier
Input Common-Mode Voltage Range(1)
Inverting Input Voltage Range(1)
Input Offset Voltage
AVCC= 12V
mA
mA
AVCC = AVCCTH - 0.2V
2.5
0
0
3
V
V
AVCC
±3
0 ~ 70°C
±1
-100
-100
170
65
mV
nA
Non-Inverting Input Bias Current
Inverting Input Bias Current
Amplifier Transconductance
Amplifier Open-Loop Gain
Amplifier Unity Gain Bandwidth(1)
IREF
-250
-250
I
nA
IN1-
GM1
aOL1
µΩ−1
dB
5
MHz
V
= VCS1- = 0
VCSSS11+ Increasing
Minimum COMP1 Switching Threshold
1.7
V
Amplifier Output Sink Current
Amplifier Output Source Current
Channel 2 Error Amplifier
V
IN1- = 1V, VCOMP1 = 2.5V
11
µA
µA
V
IN1- = 0, VCOMP1 = 2.5V
8.5
Input Common-mode Voltage Range(1)
Inverting Input Voltage Range(1)
0
0
3
AVCC
±3
V
V
Input Offset Voltage
0 ~ 70°C
±1
mV
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© 2006 Semtech Corp.
3
SC2447
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: AVCC = 12V, SYNC = 0, ROSC = 51.1kΩ, -40°C < TA = TJ < 125°C
Parameter
Symbol
Conditions
Min
Typ
-100
-150
Max
Units
nA
Non-inverting Input Bias Current
Inverting Input Bias Current
IREFIN
-250
-380
I
nA
IN2-
Inverting Input Voltage for 2-Phase Single
Output Operation
2.5
V
Amplifier Transconductance
Amplifier Open-Loop Gain
Amplifier Unity Gain Bandwidth(1)
GM2
aOL2
170
65
5
µΩ−1
dB
MHz
VCS2+ = VCS2- = 0
Minimum COMP2 Switching Threshold
1.7
V
V
SS2 Increasing
Amplifier Output Sink Current
Amplifier Output Source Current
Oscillator
VCOMP2 = 2.5V
VCOMP2 = 2.5V
11
µA
µA
8.5
Channel Frequency
fCH1, fCH2
0 ~ 70°C
450
2.1fCH
1.5
500
550
0.5
kHz
kHz
V
(1)
Synchronizing Frequency
SYNC Input High Voltage
SYNC Input Low Voltage
V
VSYNC = 0.2V
VSYNC = 2V
1
50
SYNC Input Current
ISYNC
µA
DMAX1,
DMAX2
Channel Maximum Duty Cycle
88
%
%
Channel Minimum Duty Cycle
Current-limit Comparators
Input Common-Mode Range
DMIN1, DMIN2
0
0
AVCC - 1.5
57.5
V
VILIM1+,
VILIM2+
VCS1- = VCS2- = 0.5V,
Sourcing Mode, 0 ~ 70°C
Cycle-by-cycle Peak Current Limit
42.5
50
mV
V
=VCS1- = 0
VCCSS12+- =VCS2- = 0
Positive Current-Sense Input Bias Current
I
CS1+, ICS2+
-0.7
-0.7
-2
-2
µA
µA
Negative Current-Sense Input Bias
Current
VCS1+ =VCS1- = 0
VCS2+ =VCS2- = 0
ICS1-, ICS2-
PWM Outputs
GDL1, GDL2,
GDH1, GDH2
Peak Source Current
AVCC = 12V
AVCC = 12V
10
8
mA
mA
GDL1, GDL2,
GDH1, GDH2
Peak Sink Current
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© 2006 Semtech Corp.
4
SC2447
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: AVCC = 12V, SYNC = 0, ROSC = 51.1kΩ, -40°C < TA = TJ < 125°C
Parameter
Symbol
Conditions
Min Typ
Max
Units
Output High Voltage
Source IO = 1.2mA, 0 ~ 70°C
4.1
5
V
Output Low Voltage
Sink IO = 1mA
0
0.4
V
Maximum Tri-State Leakage
Current
GDH in High Impedance State
2
µA
Propagation delay time from
current sense inputs to PWM
output(1)
TDLPWM
TA =25°C
85
ns
Soft-Start, Overload Hiccup and Enable
Soft-Start Charging Current
ISS1, ISS2
VSS1 = VSS2 = 1.5V
9.5
3.2
µA
Overload Hiccup Enabling
Voltage
VSS1 and VSS2 Increasing
V
VIN1-= 0.5VREF,VIN2-=0.5V
SS1 = VSS2 > 2.85VREFIN
,
,
37
7.5
µA
µA
V
V
Soft-Start Discharging Current
at Over Current Condition
ISS1(DIS),
ISS2(DIS)
VIN1-= 0.5VREF,VIN2-=0.5V
SS1 = VSS2 < 2.85VREFIN
V
Overload Hiccup Threshold
Voltage
VSS1 and VSS2 Decreasing
VSS1 and VSS2 Decreasing
2.85
0.5
Overload Hiccup Recovery
Soft-Start Voltage
VSSRCV1,
VSSRCV2
V
PWM Output Disable SS/EN
Voltage
0.6
1.5
V
PWM Output Enable SS/EN
Voltage
1.2
V
Internal 0.5V Reference Buffer
Output Voltage
VREFOUT
IREFOUT = -1mA, 0°C < TA = TJ < 70°C 495 500
505
mV
%/mA
%V
Load Regulation
0 < IREFOUT < -5mA
0.05
Line Regulation
AVCCTH < AVCC < 15V, IREFOUT = -1mA
0.02%
Notes:
(1) Guaranteed by design, not tested in production.
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© 2006 Semtech Corp.
5
SC2447
POWER MANAGEMENT
Typical Performance Characteristics
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© 2006 Semtech Corp.
6
SC2447
POWER MANAGEMENT
Typical Application Circuit Performance
Circuit Conditions: 2-Output Configuration as in Figure 16. VIN = 12V, VOUT1 = 2.5V, VOUT2 = 1.2V, ROSC = 51.1kΩ, SYNC = 0, and TA = 25°C.
Pre-biased Start Up (VOUT1
)
Shutdown (VOUT1)
Soft-Start Up (VOUT1
)
VOUT1
1V/div
VOUT1
1V/div
VOUT1
1V/div
IOUT1
2A/div
VSS1/EN1
2V/div
VSS1/EN1
2V/div
VSS1/EN1
5V/div
IOUT1
10A/div
VGDL1
5V/div
IOUT1=0A
ROUT1=1Ω
10ms/div
200µs/div
10ms/div
Output Voltage Ripple (VOUT1
)
Load Transient Response (VOUT1
)
Overload Hiccup (VOUT1)
VOUT1
20mV/div
VOUT1
VOUT1
1V/div
0.1V/div
VSS1/EN1
2V/div
IOUT1
10A/div
VSW1
10V/div
IOUT1
5A/div
IOUT1
20A/div
IOUT1=20A
IOUT1=15A to 20A
2µs/DIV
200µs/div
50ms/div
Pre-biased Start Up (VOUT2
)
Shutdown (VOUT2)
Soft-Start Up (VOUT2
)
VOUT2
0.5V/div
VOUT2
0.5V/div
VOUT2
0.5V/div
IOUT2
1A/div
VSS2/EN2
2V/div
VSS2/EN2
2V/div
VSS2/EN2
5V/div
IOUT2
IOUT2
20A/div
20A/div
VGDL2
5V/div
IOUT2=0A
ROUT2=1Ω
10ms/div
200µs/div
10ms/div
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© 2006 Semtech Corp.
7
SC2447
POWER MANAGEMENT
Typical Application Circuit Performance
Circuit Conditions: 2-Output Configuration as in Figure 16. VIN = 12V, VOUT1 = 2.5V, VOUT2 = 1.2V, ROSC = 51.1kΩ, SYNC = 0, and TA = 25°C.
Output Voltage Ripple (VOUT2
)
Load Transient Response (VOUT2
)
Overload Hiccup (VOUT2)
VOUT2
0.1V/div
VOUT2
20mV/div
VOUT2
0.5V/div
VSS2/EN2
2V/div
IOUT2
10A/div
IOUT2
5A/div
VSW2
10V/div
IOUT2
20A/div
IOUT2=25A
IOUT2=20A to 25A
2µs/DIV
200µs/div
50ms/div
ꢀꢉꢉꢈꢘꢈꢊꢌꢘꢜꢃ'ꢃꢚꢐꢗ(ꢃ)**+,-
1.)ꢑꢃ2ꢃ3.1ꢑ
ꢞꢂꢐꢐꢃ'ꢃꢚꢐꢗ(ꢃ)**+,-
1.)ꢑꢃ2ꢃ3.1ꢑ
Output Voltage Ripple
V
OUT1 & VOUT2
1ꢂ
1ꢀ
0ꢂ
0ꢀ
ꢇꢂ
ꢇꢀ
ꢃꢀ
ꢝꢘ7"ꢐꢃꢄꢝ
ꢝꢘ7"ꢐꢃꢄꢝ
ꢝꢚ5ꢈꢃ"ꢐꢄꢁꢂꢝ
VOUT1
20mV/div
0
ꢝꢚ5ꢈꢃ"ꢐꢄꢁꢂꢝ
VOUT2
20mV/div
4
ꢝꢚ5ꢈꢄ"ꢐꢃꢁꢄꢝ
#
VSW2
10V/div
ꢝꢚ5ꢈꢄ"ꢐꢃꢁꢄꢝ
ꢄ
VSW1
10V/div
ꢀ
ꢀ
ꢂ
ꢃꢀ
ꢃꢂ
ꢄꢀ
ꢄꢂ
ꢅꢀ
ꢀ
ꢂ
ꢃꢀ
ꢃꢂ
ꢄꢀ
ꢄꢂ
ꢅꢀ
IOUT1=20A
IOUT2=25A
1µs/DIV
ꢚꢏꢎꢋꢏꢎꢐꢓꢏꢌꢌꢉꢙꢎꢐꢑꢗꢔ
ꢚꢏꢎꢋꢏꢎꢐꢓꢏꢌꢌꢉꢙꢎꢐꢑꢗꢔ
Circuit Conditions: 2-Ouput Configuration, VIN = 12V, LOUT=0.4uH for VOUT= 1.2V, LOUT=1uH for VOUT= 2.5V, 3.3V, and 5.0V, ROSC = 51.1kΩ, and TA = 25°C.
ꢀꢉꢉꢈꢘꢈꢊꢌꢘꢜꢃ'ꢃꢚꢐꢗ(ꢃ)**+,-
ꢞꢂꢐꢐꢃ'ꢃꢚꢐꢗ(ꢃ)**+,-
).*ꢑ/ꢃ0.0ꢑ/ꢃ1.)ꢑꢃ2ꢃ3.1ꢑ
).*ꢑ/ꢃ0.0ꢑ/ꢃ1.)ꢑꢃ2ꢃ3.1ꢑ
ꢃꢀꢀ
1ꢂ
1ꢀ
0ꢂ
0ꢀ
ꢇꢂ
ꢃꢄ
ꢃꢀ
0
ꢝꢘ7"ꢐꢃꢄꢝ
ꢝꢘ7"ꢐꢃꢄꢝ
ꢝꢚ5ꢈ"ꢐꢂꢁꢀꢝ
ꢝꢚ5ꢈ"ꢐꢂꢁꢀꢝ
ꢝꢚ5ꢈ"ꢐꢅꢁꢅꢝ
ꢝꢚ5ꢈ"ꢐꢄꢁꢂꢝ
ꢝꢚ5ꢈ"ꢐꢅꢁꢅꢝ
4
ꢝꢚ5ꢈ"ꢐꢃꢁꢄꢝ
#
ꢝꢚ5ꢈꢃ"ꢐꢄꢁꢂꢝ
ꢄ
ꢝꢚ5ꢈꢄ"ꢐꢃꢁꢄꢝ
ꢀ
ꢀ
ꢂ
ꢃꢀ
ꢃꢂ
ꢄꢀ
ꢄꢂ
ꢅꢀ
ꢀ
ꢂ
ꢃꢀ
ꢃꢂ
ꢄꢀ
ꢄꢂ
ꢅꢀ
ꢚꢏꢎꢋꢏꢎꢐꢓꢏꢌꢌꢉꢙꢎꢐꢑꢗꢔ
ꢚꢏꢎꢋꢏꢎꢐꢓꢏꢌꢌꢉꢙꢎꢐꢑꢗꢔ
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8
SC2447
POWER MANAGEMENT
Typical Application Circuit Performance
Circuit Conditions: 2-Phase Configuration as in Figure 17, VIN = 12V, VOUT = 1.2V, ROSC = 51.1kΩ, SYNC = 0, and TA = 25°C.
Pre-biased Start Up (VOUT
)
Shutdown (VOUT)
Soft-Start Up
VOUT
0.5V/div
VOUT
0.5V/div
VOUT
0.5V/div
IOUT
1A/div
VSS1/EN1
2V/div
VSS1/EN1
2V/div
VSS1/EN1
5V/div
IOUT
20A/div
IOUT
20A/div
VGDL1
5V/div
IOUT=0A
ROUT2=1Ω
10ms/div
200µs/div
10ms/div
Output Voltage Ripple (VOUT
)
Load Transient Response (VOUT
)
Overload Hiccup (VOUT)
VOUT
20mV/div
VOUT
0.5V/div
VOUT
0.1V/div
VSS1/EN1
2V/div
IOUT
50A/div
VSW1
10V/div
IOUT
IOUT
50A/div
10A/div
VSW2
10V/div
IOUT2=50A
IOUT2=40A to 50A
1µs/DIV
200µs/div
50ms/div
ꢀꢉꢉꢈꢘꢈꢊꢌꢘꢜꢃ'ꢃꢚꢐꢗ(ꢃ)**+,-
1!4ꢙꢒꢐꢊ/ꢃ3.1ꢑ
ꢞꢂꢐꢐꢃ'ꢃꢚꢐꢗ(ꢃ)**+,-
1!4ꢙꢒꢐꢊ/ꢃ3.1ꢑ
ꢝꢍꢁꢁꢊꢌꢎꢃꢖꢙꢒꢁꢊ
1!4ꢙꢒꢐꢊ/ꢃ3.1ꢑ
1ꢀ
0ꢂ
0ꢀ
ꢇꢂ
ꢇꢀ
4ꢂ
ꢃꢂꢁꢀ
ꢃꢄꢁꢂ
ꢃꢀꢁꢀ
ꢇꢁꢂ
ꢅꢀ
ꢄꢂ
ꢄꢀ
ꢃꢂ
ꢃꢀ
ꢂ
ꢝꢘ7"ꢐꢃꢄꢝ
ꢝꢘ7"ꢐꢃꢄꢝ
ꢝꢘ7"ꢐꢃꢄꢝ
ꢘ9:ꢗ$ꢕꢃ
ꢘ9:ꢗ$ꢕꢄ
ꢂꢁꢀ
ꢄꢁꢂ
ꢀꢁꢀ
ꢀ
ꢀ
ꢃꢀ
ꢄꢀ
ꢅꢀ
#ꢀ
ꢂꢀ
4ꢀ
ꢀ
ꢃꢀ
ꢄꢀ
ꢅꢀ
#ꢀ
ꢂꢀ
4ꢀ
ꢀ
ꢃꢀ
ꢄꢀ
ꢅꢀ
#ꢀ
ꢂꢀ
4ꢀ
ꢚꢏꢎꢋꢏꢎꢐꢓꢏꢌꢌꢉꢙꢎꢐꢑꢗꢔ
ꢚꢏꢎꢋꢏꢎꢐꢓꢏꢌꢌꢉꢙꢎꢐꢑꢗꢔ
ꢈꢞꢎꢍ ꢐꢚꢏꢎꢋꢏꢎꢐꢓꢏꢌꢌꢉꢙꢎꢐꢑꢗꢔ
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© 2006 Semtech Corp.
9
SC2447
POWER MANAGEMENT
Pin Descriptions
Pin
Pin Name Pin Function
1
CS1+
CS1-
ROSC
IN1-
The Non-inverting Input of Channel 1 Current-sense Amplifier/Comparator
The Inverting Input of Channel 1 Current-sense Amplifier/Comparator. Normally tied to the
output of the converter.
2
3
4
5
An external resistor connected from this pin to AGND sets the oscillator frequency.
Inverting Input of Channel 1 Error Amplifier. Tie an external resistive divider between output
1 and ground for output voltage sensing.
COMP1 The Channel 1 Error Amplifier Output. This pin is used for loop compensation.
Edge-triggered Synchronization Input. When not synchronized, tie this pin to a voltage above
1.5V or ground. An external clock (frequency > frequency set with ROSC) at this pin
synchronizes the controllers.
6
SYNC
7
8
9
AGND
REF
Analog Signal Ground.
The Non-inverting Input of Channel 1 Error Amplifier.
REFOUT Buffered 0.5V internal reference.
An external reference voltage is applied to this pin. This is also the non-inverting input of
Channel 2 Error amplifier.
10
11
REFIN
COMP2 The Channel 2 Error Amplifier Output. This pin is used for loop compensation.
The Inverting Input of Channel 2 Error Amplifier. Tie an external resistive divider between
12
IN2-
output 2 and ground for output voltage sensing. Tie to AVCC for two-phase single output
applications.
The Inverting Input of Channel 2 Current-sense Amplifier/Comparator. Normally tied to the
output of the converter.
13
14
CS2-
CS2+
The Non-inverting Input of Channel 2 Current-sense Amplifier/Comparator.
An external capacitor tied to this pin sets (1) the soft-start time (2) output overload shutdown
SS2/EN2 time for Channel 2. Pulling this pin below 0.6V tri-states GHD2 and forces GDL2 low. Leave
open for two-phase single output applications.
15
16
20
21
24
25
AVCC
GDH2
GDL2
GDL1
GDH1
Power Supply Voltage for the Analog Portion of the Controllers.
PWM Output 2.
Logic Enable Signal for Channel 2.
Logic Enable Signal for Channel 1.
PWM Output 1.
An external capacitor tied to this pin sets (1) the soft-start time (2) output overload shutdown
time for Channel 1. Pulling this pin below 0.6V tri-states GDH1 and forces GDL1 low.
28
SS1/EN1
NC
17,18,19
22,23,26,27
No Connection.
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© 2006 Semtech Corp.
10
SC2447
POWER MANAGEMENT
Block Diagram
SYNC
CLK2
CLK1
AVCC
16
6
FREQUENCY
DIVIDER
CLK
1.25V
REFERENCE
0.5V
OSCILLATOR
ROSC
3
SLOPE COMP.
COMP1
5
GDH1
25
IN1
4
SLOPE2
-
R
S
TRI-STATE1
EA1
REF
8
+
-
+
Q
PWM1
+
REFSS1
TGON1
UV
SLOPE1
GDL1
24
CS1+
1
+
+
+
ISEN1
Σ
CS1-
2
-
CLK1
OC1
PRE-BIAS
OL1
DSBL1
SOFT-START
&
+
ILIM1+
OVERLOAD
HICCUP
CONTROL 1
-
SS1/EN1
28
SS1/EN1
1.25V
2R
50mV
SSL1
0.5V
+
REFOUT
9
-
R
UVLO
4.3/4.5V
AGND
7
COMP2
11
B
A
SEL
2.5V
MUX
-
Y
CLK2
+
GDH2
20
ANALOG
SWITCH
IN2
12
-
R
REFIN
10
EA2
TRI-STATE2
+
+
-
Q
PWM2
S
+
REFSS2
TGON2
UV
SLOPE2
CS2+
14
GDL2
21
+
+
+
CS2-
13
ISEN2
Σ
CLK2
-
PRE-BIAS
SOFT-START
&
OL2
DSBL2
+
OC2
ILIM2+
OVERLOAD
HICCUP
CONTROL 2
SS2/EN2
15
-
SSL2
SS2/EN2
50mV
1.25V
R
2R
REFSS2
Figure 3. SC2447 Block Diagram
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© 2006 Semtech Corp.
11
SC2447
POWER MANAGEMENT
Block Diagram
2.85V
-
+
S
R
OL
0.5V/3.2V
Q
9.5uA
SS/EN
COMP
SSL
-
+
S
R
DSBL
Q
0.8V
(0.6V min.)
R
S
TGON
CLK
OC
17.0uA
UV
Q
46.5uA
Figure 4. Soft-Start and Overload Hiccup Control Circuit
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12
SC2447
POWER MANAGEMENT
Timing Chart
AVCC
AVCC
4.5V
4.5V
VSS/EN
VSS/EN
3.2V
3.2V
Enable Hiccup
VCOMP
Enable Hiccup
VCOMP
1.5V
1.5V
1.25V
1.25V
0
0
VREFSS
VIN-
VREFSS
VIN-
0.5V (VREF
)
0.5V (VREF)
0
0
0
0
GDH
GDL
GDH
GDL
GDH in high impedance state
GDH in high impedance state
0
0
t0
t6
t7
t1
t2
t4
t3
t5
t2 t4
t5 t6 t7
t0
t1
(a) Normal Start Up
(b) Pre-Biased Start Up
Figure 5. SC2447 Start-up Timing Diagram
AVCC
4.3V
VSS/EN
VCOMP
VREFSS
VIN-
0.5V (VREF
)
GDH
GDL
GDH in high impedance state
t17
t16
Figure 6. SC2447 UVLO Shutdown Timing Diagram
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SC2447
POWER MANAGEMENT
Timing Chart
VSS/EN
3.2V
Enable Hiccup
Enable Hiccup
2.85V
VCOMP
1.50V
1.25V
0.8V
0.5V
0V
VIN-
0.5V
Reference Voltage
Min.(VREF, VREFSS
)
0V
GDH in high impedance state
GDH
GDL
0V
0V
t14
t15
t7
t8 t9
t10 t11 t12
t13
Figure 7. SC2447 Overload Hiccup Operation Timing Diagram
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14
SC2447
POWER MANAGEMENT
Application Information
The SC2447 consists of two current-mode synchronous For a given output power, the size of the passive
buck controllers with many integrated functions. The components are inversely proportional to the switching
SC2447 can be used to generate:
frequency, whereas MOSFET/Diode switching losses are
proportional to the operating frequency. Other issues such
1) two independent outputs from a common input or as heat dissipation, packaging and the cost issues are
two different inputs or,
2) dual-phase output with current sharing,
also considered. The frequency bands for signal
transmission should be avoided because of EM
3) current sourcing/sinking from common or separate interference.
inputs as in DDR (I and II) memory application.
Minimum Switch On Time Consideration
Step-Down Converter
In the SC2447, the falling edge of the clock turns on the
Starting from the following step-down converter top MOSFET. The inductor current and the sensed voltage
specifications,
ramp up. After the sensed voltage crosses a threshold
determined by the error amplifier output, the top MOSFET
is turned off. The propagation delay time from the turn-
on of the controlling FET to its turn-off is the minimum
switch on time. This propagation delay time consists of
the propagation delay time (TDLPWM) from the current sense
inputs to the PWM output and the propagation delay time
(TDLTG) from the trailing edge of the PWM input to the
trailing edge of the phase voltage.
Input voltage range: Vin ∈ [Vin,min,Vin,max
]
Input voltage ripple (peak-to-peak): ∆Vin
Output voltage: Vo
Output voltage accuracy: ε
Output voltage ripple (peak-to-peak): ∆Vo
Nominal output (load) current: Io
Maximum output current limit: Io,max
Output (load) current transient slew rate: dIo (A/s)
Circuit efficiency: η
The SC2447 has a typical propagation delay time from
the current sense inputs to the PWM output of about
85ns at room temperature. The shortest on interval
(TMINON) of the controlling FET is then 85ns+TDLTG. Assuming
that TDLTG is 45ns, the controller either does not turn on
the top MOSFET at all or turns it on for at least 130ns.
TDLTG can be found in the MOSFET driver datasheet.
Selection criteria and design procedures for the following
are described.
1) output inductor (L) type and value
2) output capacitor (Co) type and value
3) input capacitor (Cin) type and value
4) power MOSFETs
For a synchronous step-down converter, the operating duty
cycle is VO/VIN. The required on time for the top MOSFET
is VO/(VIN*fs). If the frequency is set such that the required
pulse width is less than 130ns, assuming TDLTG is 45ns,
then the converter will start skipping cycles. Due to
minimum on-time limitation, simultaneously operating at
very high switching frequency and very short duty cycle is
not practical. If the voltage conversion ratio VO/VIN and
hence the required duty cycle is higher, the switching
frequency can be increased to reduce the size of passive
components.
5) current sensing and limiting circuit
6) voltage sensing circuit
7) loop compensation network
Operating Frequency (fs)
The switching frequency in the SC2447 is user-
programmable. The advantages of using constant
frequency operation are simple passive component
selection and ease of feedback compensation. Before
setting the operating frequency, the following trade-offs
should be considered:
There will not be enough modulating headroom if the on
time is made equal to the minimum on time (TMINON). For
ease of control, set the switching frequency so that the
pulse width is at least 1.5 times the minimum on time.
1) Passive component size
2) Efficiency
3) EMI condition
4) Minimum switch on time
5) Maximum duty ratio
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15
SC2447
POWER MANAGEMENT
Application Information (Cont.)
Consider the following when choosing inductors:
Setting the Switching Frequency
a) Inductor core material: For high efficiency applications
above 350kHz, ferrite, Kool-Mu and polypermalloy
materials should be used. Low-cost powdered iron cores
can be used for cost sensitive-applications below 350kHz
but with attendant higher core losses.
The switching frequency is set with an external resistor
connected from Pin 3 to the ground. The set frequency is
inversely proportional to the resistor value (Figure 8).
800
700
600
500
400
300
200
100
0
b) Select inductance value: Sometimes the calculated
inductance value is not available off-the-shelf. The designer
can choose the next larger standard inductance value.
The inductance varies with temperature and DC current.
It is a good engineering practice to re-evaluate the
resulting current ripple at the rated DC output current.
c) Current rating: The saturation current of the inductor
should be at least 1.5 times of the peak inductor current
under all conditions.
0
50
100
150
200
250
Rosc (k Ohm)
Output Capacitor (Co) and Vout Ripple
Figure 8. Free Running Frequency vs. ROSC
Inductor (L) and Ripple Current
The output capacitor filters the inductor current in the
steady state and serves as a reservoir during load transient.
The output capacitor can be modeled as an ideal capacitor
in series with its parasitic ESR (Resr) and ESL (Lesl) (Figure
9 ).
Both step-down controllers in the SC2447 operate in
synchronous continuous-conduction mode (CCM)
regardless of the output load. The output inductor
selection/design is based on the output DC and transient
requirements. Both output current and voltage ripples
are reduced with larger inductors but it takes longer to
change the inductor current during load transients.
Conversely, smaller inductors results in lower DC copper
losses but the AC core losses (flux swing) and the winding
AC resistance losses are higher. A compromise is to
choose the inductance such that peak-to-peak inductor
ripple-current is 20% to 30% of the rated output load
current.
Co
Lesl
Resr
Figure 9. An Equivalent Circuit of Co
If the current through the branch is ib(t), the voltage across
the terminals will then be
Assuming that the inductor current ripple (peak-to-peak)
value is δ*Io, the inductance value will then be
t
1
dib (t)
Vo (1− D)
δIo fs
vo (t) =Vo +
ib (t)dt + Lesl
+ Resrib (t).
L =
.
∫
Co
dt
0
This basic equation illustrates the effect of ESR, ESL
and Co on the output voltage.
The peak current in the inductor becomes (1+δ/2)*Io
and the RMS current is
δ 2
12
The first term is the DC voltage across Co at time t=0.
The second term is the voltage variation caused by the
IL,rms = Io 1+
.
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SC2447
POWER MANAGEMENT
Application Information (Cont.)
The voltage rating of aluminum capacitors should be at
least 1.5Vo. The RMS current ripple rating should also
be greater than
charge balance between the load and the converter
output. The third term is voltage ripple due to ESL and
the fourth term is the voltage ripple due to ESR. The
total output voltage ripple is then the vector sum of the
last three terms.
δIo
.
2 3
Since the inductor current waveform is a triangular with
peak-to-peak value δ*Io, the ripple-voltage caused by
inductor current ripple is
Usually it is necessary to have several capacitors of the
same type in parallel to satisfy the ESR requirement. The
voltage ripple cause by the capacitor charge/discharge
should be an order of magnitude smaller than the voltage
ripple caused by the ESR. To guarantee this, the
capacitance should satisfy
δIo
8Cofs
∆vC
≈
,
the ripple-voltage due to ESL is
δIo
D
∆vESL = Leslfs
,
10
Co >
.
2πfsResr
and the ESR ripple-voltage is
In many applications, several low ESR ceramic capacitors
are added in parallel with the aluminum capacitors in
order to further reduce ESR and improve high frequency
decoupling. Because the values of capacitance and ESR
are usually different in ceramic and aluminum capacitors,
the following remarks are made to clarify some practical
issues.
∆vESR = Resr δIo.
Aluminum capacitors (e.g. electrolytic, solid OS-CON,
POSCAP, tantalum) have high capacitances and low ESLs.
The ESR has the dominant effect on the output ripple
voltage. It is therefore very important to minimize the
ESR.
Remark 1: High frequency ceramic capacitors may not
carry most of the ripple current. It also depends on the
capacitor value. Only when the capacitor value is set
properly, the effect of ceramic capacitor low ESR starts
to be significant.
When determining the ESR value, both the steady state
ripple-voltage and the dynamic load transient need to be
considered. To keep the steady state output ripple-
voltage < ∆Vo, the ESR should satisfy
For example, if a 10µF, 4mΩ ceramic capacitor is
connected in parallel with 2x1500µF, 90mΩ electrolytic
capacitors, the ripple current in the ceramic capacitor is
only about 42% of the current in the electrolytic
capacitors at the ripple frequency. If a 100µF, 2mΩ
ceramic capacitor is used, the ripple current in the
ceramic capacitor will be about 4.2 times of that in the
electrolytic capacitors. When two 100µF, 2mΩ ceramic
capacitors are used, the current ratio increases to 8.3.
In this case most of the ripple current flows in the
ceramic decoupling capacitor. The ESR of the ceramic
capacitors will then determine the output ripple-voltage.
∆Vo
δIo
Resr1
<
.
To limit the dynamic output voltage overshoot/
undershoot to within α (say 3%) of the steady state
output voltage) from no load to full load, the ESR value
should satisfy
αVo
Io
Resr2
<
.
Then, the required ESR value of the output capacitors
should be
Remark 2: The total equivalent capacitance of the filter
bank is not simply the sum of all the paralleled capacitors.
The total equivalent ESR is not simply the parallel
combination of all the individual ESRs either. Instead
Resr = min{Resr1,Resr2 }.
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SC2447
POWER MANAGEMENT
Application Information (Cont.)
they should be calculated using the following formulae.
2
2
(R1a + R1b )2 ω2C1a C1b + (C1a + C1b )2
Ceq(ω) :=
2
2
(R1a C1a + R1b C1b )ω2C1aC1b + (C1a + C1b )
2
2
2
2
R1aR1b(R1a + R1b )ω2C1a C1b + (R1bC1b + R1aC1a
)
Req(ω) :=
2
2
(R1a + R1b )2 ω2C1a C1b + (C1a + C1b )2
where R1a and C1a are the ESR and capacitance of
electrolytic capacitors, and R1b and C1b are the ESR and
capacitance of the ceramic capacitors respectively.
(Figure 10)
Figure 11. A Simple Model for the Converter Input
C1a
C1b
Ceq
R1a
R1b
Req
Figure 10. Equivalent RC Branch
Req and Ceq are both functions of frequency. For rigorous
design, the equivalent ESR should be evaluated at the
ripple frequency for voltage ripple calculation when both
ceramic and electrolytic capacitors are used. If R1a = R1b =
R1 and C1a = C1b = C1, then Req and Ceq will be frequency-
independent and
Req = 1/2 R1 and Ceq = 2C1.
Figure 12. Typical Waveforms at Converter Input
It can be seen that high di/dt pulse current flows in the
input capacitor. Capacitors with low ESL should be used.
It is also important to place the input capacitor close to
the MOSFETs on the PC board to reduce trace inductance
around the pulse current loop.
Input Capacitor (Cin)
The input supply to the converter usually comes from a
pre-regulator. Since the input supply is not ideal, input
capacitors are needed to filter the current pulses at the
switching frequency. A simple buck converter is shown in
Figure 11.
The RMS value of the capacitor current is approximately
δ2
ICin = Io D[(1+ )(1− )2 + (1−D)].
12
η2
D
D
η
In Figure 11 the DC input power supply has an internal
impedance Rin and the input capacitor Cin has an ESR of
Resr. The MOSFET and the input capacitor current
waveforms, the ESR voltage ripple and the input voltage
ripple are shown in Figure 12.
The power dissipated in the input capacitor is then
2
PCin = ICin Resr.
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SC2447
POWER MANAGEMENT
Application Information (Cont.)
If D1<0.5 and D2<0.5, then
For reliable operation, the maximum power dissipation
in the capacitors should not result in more than 10oC of
temperature rise. Many manufacturers specify the
maximum allowable ripple current (ARMS), rating of the
capacitor at a given ripple frequency and ambient
temperature. The input capacitance should be large
enough to handle the ripple current. For higher power
applications, multiple capacitors are placed in parallel to
increase the ripple current handling capability.
ICin ≈ D Io12 + D2Io2
.
2
1
Choosing Power MOSFETs
Power MOSFETs with integrated gate drivers such as
PIP212, R2J20601NP, PIP202, PIP201 and IP2001,
IP2002 are suitable for SC2447 application.
Sometimes meeting tight input voltage ripple
specifications may require the use of larger input
capacitance. At full load, the peak-to-peak input voltage
ripple due to the ESR is
Current Sensing
Inductor current sensing is required for the current-mode
control. Although the inductor current can be sensed
with a precision resistor in series with the inductor, the
lossless inductive current sense technique can be used
in the SC2447. This technique has the advantages of,
δ
∆vESR = Resr (1+ )Io.
2
The peak-to-peak input voltage ripple due to the capacitor
is
DIo
∆vC ≈
,
1) lossless current sensing
Cin fs
2) lower cost compared to resistive sensing
3) more accurate compared to RDS(ON) sensing
From these two expressions, CIN can be found to meet
the input voltage ripple specification. In a multi-phase
converter, interleaved switching reduces ripple. The two
step-down channels of the SC2447 operate at 180 degrees
from each other. If both step-down channels in the SC2447
are connected in parallel, both the input and the output
RMS currents will be reduced.
The basic arrangement of the inductive current sense is
shown in Figure 13.
RL is the equivalent series resistance of the output inductor.
Rs and Cs form a RC network for inductor current sensing.
Ripple cancellation effect of interleaving allows the use
of smaller input capacitors. When converter outputs are
connected in parallel and interleaved, a smaller inductor
and capacitor can be used for each channel. The total
output ripple-voltage remains unchanged. The use of a
smaller inductor helps speed up the output load
transient.
Vin
Q1
iL(t)
L
RL
Cs
Cin
Rs
Vo
Q2
Cout
Rload
vC(t)
When two channels with a common input are interleaved,
the combined input current waveform depends on the duty
ratios and the output currents of both channels. Assuming
that the output current ripple is small, the following formula
can be used to estimate the RMS ripple current in the
input capacitor.
Figure 13. The Basic Structure of Inductive Current
Sense
In steady state, the DC voltage across RL is
VCS = RL IO .
Let the duty ratio and output current of Channel 1 and
Channel 2 be D1, D2 and Io1, Io2, respectively.
Notice that the DC value of VCs is independent of the
values of L, Rs and Cs. This means that, if only the
average load current information is needed (such as in
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SC2447
POWER MANAGEMENT
Application Information (Cont.)
average current mode control), this current sensing of 22nF ~ 330nF.
method is sufficient without time constant matching
requirement.
a) When the required current limit ILM is higher than ILMcp
,
Rs3 is not needed and solve the following three equations
In the current mode control as implemented in SC2447, for Rs, Rs1, and Rs2:
voltage ripple on Cs is required for PWM operation. In
fact, the VCs AC peak-to-peak voltage ripple (denoted as
∆VCs) directly affects the signal-to-noise ratio of the PWM
operation. In general, smaller ∆VCs leads to lower signal-
to-noise ratio and more noise sensitive operation. Larger
L
(Rs // Rs1) Cs =
,
RL
Rs1
ILM RL
= 50mV,
∆VCs leads to more circuit (power stage) parameter
sensitive operation. A good engineering compromise is:
Rs + Rs1
and
Rs2 = Rs // Rs1 .
∆VCs~ RL δIo.
Note that RS2 is made equal to RS//RS1 to reduce effect
of the bias current of the current amplifier in SC2447.
It is necessary to match the following time constants to
equalize the ripple.
L
b) When the required current limit ILM is less than ILMcp
remove Rs1 and solve the following two equations for Rs
and Rs3:
,
≈ RsCs .
RL
For example, L = 1µH and RL = 1.8mΩ, the time constant
RsCs should be set to 555.6µs. If one selects Cs = 33nF,
then Rs = 16.9 kΩ.
L
RsCs =
,
RL
Rs
Scaling the Current Limit
ILM RL +
VO = 50mV ,
Rs3
Over-current is handled differently in the SC2447
depending on the direction of the inductor current. If
the differential sense voltage between CS+ and CS-
exceeds +50mV, the PWM signal (GDH) will go low. The
MOSFET driver will turn off the top MOSFET and turn on
the bottom MOSFET, to limit the inductor current. This
+50mV is the cycle-by-cycle peak current limit when the
load is drawing current from the converter. There is no
cycle-by-cycle current limit when the inductor current flows
in the reverse direction.
Rs2 is then calculated from
Rs3Rs
.
Rs2 =
Rs3 − Rs
Vin
Q1
Vgs1
iL(t)
L
RL
PN
Cin
Rs
Rs1
In the circuit of Figure 13, the equivalent inductor current
limit is set according to
Vo
Q2
Cs
Cout
Rload
Vgs2
vC(t)
50mV
ILMcp
=
,
RL
when the load is sourcing current from the converter. If
RL = 1.8mΩ, then ILMcp = 27.8A. The circuit in Figure 14
allows the user to scale the equivalent current limit with
the same RL.
1
+
Rs2
2
-
ISEN
Rs3
CS in the current sensing network is usually in the range
Figure 14. Scaling the Equivalent Current Limit
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SC2447
POWER MANAGEMENT
Application Information (Cont.)
Overload Protection and Hiccup
When C32 = 0.1µF, tssr is calculated as 28.4ms. Note
that during soft start, the converter only starts switching
During start-up, the capacitor from the SS/EN pin to when the voltage at SS/EN exceeds 1.25V.
ground functions as a soft-start capacitor. After the
converter starts and enters regulation, the same d) The effective start-up time is
capacitor operates as an overload shutoff timing
(3.2 −1.25)V
tsso = C32
capacitor. There is an internal net 9.5µA current source
charging the soft start capacitor C32(C33), connected to
the SS/EN pin. The soft-start voltage VSS/EN will reach its
final value if no current limit occurs. As the load current
increases, the cycle-by-cycle current-limit comparator will
first limit the inductor current. If VSS/EN is higher than
3.2V, an internal net 37µA current source will discharge
the soft-start capacitor C32(C33) during the off time after
tripping the over-current comparator. If VSS/EN falls to
2.85V, the controller will shut off both the top and the
bottom MOSFETs by pulling down the GDL and tri-stating
the GDH output (PWM). An internal net 7.5µA current
source discharges C32(C33) .
.
9.5µA
The average inductor current is then
tsso
ILeff = ILMcp
.
tssf 1 +tssf 2 + tssr
ILeff ≈ 0.34 ILMcp and is independent of the soft start
capacitor value. The converter will not overheat in
hiccup.
Setting the Output Voltage
The non-inverting inputs of channel 1 and channel 2 error
amplifiers are brought out as device pins (Pin 10 and Pin
8). These pins can be tied to the precision 0.5V reference
output (Pin 9) of the SC2447. A simple voltage divider
(Ro1 at top and Ro2 at bottom) sets the converter output
voltage. The voltage feedback gain h=0.5/Vo is related
to the divider resistors as follows:
When the capacitor is discharged below 0.5V, the overload
hiccup latch is reset, the 9.5µA current source recharges
the SS/EN capacitor and converter restarts. The overload
hiccup function is enabled when the soft start capacitor
voltage exceeds 3.2V. The converter will repeatedly start
and shut off until it is no longer overloaded when the
soft-start voltage exceeds 3.2V. This hiccup mode of
overload protection is a form of foldback current limiting.
The following calculations estimate the average inductor
current when the converter output is shorted to the
ground:
h
Ro2 =
Ro1
.
1− h
Once either Ro1 or Ro2 is chosen, the other can be
calculated for the desired output voltage Vo. Since the
number of standard resistance values is limited, the
calculated resistance may not be available as a standard
value resistor. As a result, there will be a set error in the
converter output voltage. This non-random error is
caused by the feedback voltage divider ratio. It cannot
be corrected by the feedback loop.
a) The time taken to discharge the capacitor from 3.2V
to 2.85V is
(3.2 − 2.85)V
tssf 1 = C32
.
37µA
If C32 = 0.1µF, tssf1 is calculated as 0.945ms.
b) The time taken to discharge the capacitor from 2.85V
to 0.5V is
The following table lists a few standard resistor
combinations for realizing some commonly used output
voltages.
(2.85− 0.5)V
tssf 2 = C32
.
7.5µA
Vo (V)
(1-h)/h
0.6
0.2
0.9
0.8
1.2
1.4
1.5
2
1.8
2.6
2.5
4
3.3
5.6
If C32 = 0.1µF, tssf2 is calculated as 31.3ms.
c) The soft start time from 0.5V to 3.2V is
Ro1 (Ohm) 200 806 1.4K 2.0K 2.61K 4.02K 5.62K
Ro2 (Ohm) 1K 1K 1K 1K 1K 1K 1K
(3.2 −0.5)V
tssr = C32
.
9.5µA
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SC2447
POWER MANAGEMENT
Application Information (Cont.)
Only the voltages in boldface can be precisely set with
standard 1% resistors.
The slope of the compensation ramp is then
Se=0.4*fs.
From this table, one may also observe that when the
value
The slope of the internal compensation ramp is well above
the minimal slope requirement for current loop stability
and is sufficient for all the applications.
1− h Vo − 0.5
=
.
h
0.5
With the inner current loop stable, the output voltage is
then regulated with the outer voltage feedback loop. A
simplified equivalent circuit model of the synchronous
Buck converter with current mode control is shown in
Figure 15.
and its multiples fall into the standard resistor value
chart (1%, 5% or so), it is possible to use standard value
resistors to set up the exact and required output voltage
value.
The input bias current of the error amplifier also causes
an error in setting the output voltage. The maximum
inverting input bias current of the error amplifiers is -
380nA. Assuming the non-inverting input is tied to the
0.5V reference output, the percentage error in the
second output voltage will be –100% · (0.38µA)
·
R
R
/[0.5 · (R +R ) ]. To keep this error below
o1 o2
0.2%, R
o1 o2
< 2.6kΩ.
o2
k
Loop Compensation
SC2447 uses current-mode control for both step-down
channels. Current-mode control is a dual-loop control
system in which the inductor peak current is loosely
controlled by the inner current-loop. The higher gain outer
loop regulates the output voltage. Since the current loop
makes the inductor appear as a current source, the complex
high-Q poles of the output LC network are split into a
dominant pole determined by the output capacitor and
the load resistance and a high frequency pole. This pole-
splitting property of current-mode control greatly simplifies
loop compensation.
Figure 15. A Simple Model of Synchronous Buck
Converter with Current Mode Control
The transconductance error amplifier (in the SC2447)
has a gain gm of 170µA/V. The target of the compensation
design is to select the compensation network consisting
of C2, C3 and R2, along with the feedback resistors Ro1,
Ro2 and the current sensing gain, such that the converter
output voltage is regulated with satisfactory dynamic
performance.
The inner current-loop is unstable (sub-harmonic
oscillation) unless the inductor current up-slope is steeper
than the inductor current down-slope. For stable
operation above 50% duty-cycle, a compensation ramp
is added to the sensed-current. In the SC2447 the
compensation ramp is approximately
Vramp=D*0.4V.
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SC2447
POWER MANAGEMENT
Application Information (Cont.)
PC Board Layout Issues
Circuit board layout is very important for the proper
operation of high frequency switching power converters.
A power ground plane is required to reduce ground
bounces. The followings are suggested for proper layout.
Power Stage
1) Separate the power ground from the signal ground. In
the SC2447, the power ground PGND should be tied to
the source terminal of lower MOSFETs. The signal ground
AGND should be tied to the negative terminal of the
output capacitor.
2) Minimize the size of high pulse current loop. Place
the top MOSFET, bottom MOSFET and the input
capacitors close to each other with short and wide traces.
In addition to the aluminum energy storage capacitors,
add multi-layer ceramic (MLC) capacitors from the input
to the power ground to improve high frequency bypass.
Control Section
1) The frequency-setting resistor ROSC should be placed
close to Pin 3. Trace length from this resistor to the
analog ground should be minimized.
2) Solder the bias decoupling capacitor right across the
AVCC and analog ground AGND.
3) Place the current sensing network away from the
power circuit and close to the corresponding CS+ and
CS- pins. Use X7R ceramic capacitor for the sensing
capacitor because of its temperature stability.
4) Use an isolated local ground plane for the controller
and tie it to the negative side of output capacitor bank.
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SC2447
POWER MANAGEMENT
Typical Application Schematic
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SC2447
POWER MANAGEMENT
Typical Application Schematic
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25
SC2447
POWER MANAGEMENT
Outline Drawing - TSSOP-28
DIMENSIONS
INCHES MILLIMETERS
MIN NOM MAX MIN NOM MAX
A
DIM
A
D
E
e
N
-
-
-
-
-
-
-
-
-
-
-
-
.047
1.20
0.15
1.05
0.30
0.20
A1 .002
A2 .031
.006 0.05
.042 0.80
.012 0.19
.007 0.09
2X E/2
b
c
D
.007
.003
E1
.378 .382 .386 9.60 9.70 9.80
PIN 1
INDICATOR
E1 .169 .173 .177 4.30 4.40 4.50
E
e
.252 BSC
.026 BSC
6.40 BSC
0.65 BSC
L
L1
N
01
aaa
.018 .024 .030 0.45 0.60 0.75
ccc
2X N/2 TIPS
C
1 2 3
(.039)
(1.0)
e/2
28
-
28
-
0
8
0
8
B
.004
.004
.008
0.10
0.10
0.20
bbb
ccc
D
aaa C
A2
A
SEATING
PLANE
H
C
A1
A-B D
bxN
bbb
C
c
GAGE
PLANE
0.25
L
01
(L1)
DETAIL A
SEE DETAIL A
SIDE VIEW
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MO-153, VARIATION AE.
Land Pattern - TSSOP-28
X
DIMENSIONS
DIM
INCHES
(.222)
.161
.026
.016
MILLIMETERS
(5.65)
4.10
0.65
0.40
1.55
7.20
C
G
P
X
Y
Z
(C)
G
Y
Z
.061
.283
P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
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© 2006 Semtech Corp.
26
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