SC2599EVB_技术文档

SC2599

Low Voltage DDR

Termination Regulator

POWER MANAGEMENT

Features

Description

The SC2599 is designed to meet the latest JEDEC speciﬁ-

cation for low power DDR3 and DDR4, while also support-

ing DDR and DDR2. The SC2599 regulates up to + 3A for

VTT and up to + 40mA for VREF.



Input to linear regulator (VIN): 1.0V to 3.6V

Output (VTT): 0.5V to 1.8V

Bias Voltage (VDD): 2.35V to 3.6V

Up to 3A sink or source from VTT for DDR through

DDR4

+ 1% over temperature (with respect to VDDQ/2, in-

cluding internal resistor divider variation) VREF and

VTT

Logic-level enable input

Built in soft-start

Thermal shutdown with auto-restart

Over current protection

Minimal output capacitance

The SC2599 also provides an accuracy of +1% over tem-

perature (which takes into account the internal resistor

divider) for VREF and VTT for the memory controller and

DRAM.



SC2599 protection features include thermal shutdown

with auto-restart for VTT and over-current limit for both

VTT and VREF.

Under-Voltage-Lock-Out circuits are included to ensure

that the output is oﬀ when the bias voltage falls below its

threshold, and that the part behaves elegantly in power-

up or power-down.

Package: MLPD8 - 2mm x 2mm x 0.6mm

Applications

The low external parts count combined with industry

leading speciﬁcations make SC2599 an attractive solution

for DDR through DDR4 termination.



DDR Memory Termination

Typical Application Circuit

C_IN

C_VDD

1μF

2x10μF

VDDQ

VDD VIN

VDDQ

VTT

VTTS

VREF

C_VTT

3x10μF

(1)

C_VREF

EN

GND

PAD

0.1μF

Note:

(1) This component is optional.

Rev. 2.0

1

SC2599

Pin Conﬁguration

Ordering Information

Device

Package

SC2599ULTRC⁽¹⁾⁽²⁾

SC2599EVB

MLPD8

Evaluation Board

Notes:

(1) Available in tape and reel only. A reel contains 3000 devices.

(2) Lead-free packaging only. Device is WEEE and RoHS compliant

and halogen-free.

VDD

VIN

1

2

3

4

8

7

6

5

VDDQ

VREF

VTTS

EN

Therm al

PAD

VTT

G ND

MLPD8 - 2mm x 2mm x 0.6mm

Marking Information

C99

Yw

nnn = Part Number (Example: C99)

Yw = Datecode

2

SC2599

Absolute Maximum Ratings

Thermal Information

Thermal Resistance, Junction to Ambient⁽²⁾(°C/W) . . . 57

Thermal Resistance, Junction to Ambient⁽³⁾(°C/W) . . . 45

Maximum Junction Temperature (°C) . . . . . . . . . . . . . . +150

Storage Temperature Range (°C). . . . . . . . . . . . -65 to +150

Peak IR Reflow Temperature (10s to 30s) (°C) . . . . . . . +260

VIN (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.3

VDD to GND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.3

VTT to GND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to VDD

EN (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.0

Other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.3

ESD Protection Level (HBM)⁽¹⁾(kV). . . . . . . . . . .

ESD Protection Level (CDM)⁽¹⁾(kV). . . . . . . . . . .

2.5

1

Exceeding the above speciﬁcations may result in permanent damage to the device or device malfunction. Operation outside of the parameters

speciﬁed in the Electrical Characteristics section is not recommended.

Notes:

(1) HBM: tested according to ANSI/ESDA/JEDEC JS-001. CDM: tested according to JESD-C101E.

(2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.

(3) Based upon lab measurement on EVB board: 3 x 2 (in), 4 layer FR4 PCB with thermal vias under the exposed pad.

Electrical Characteristics

Unless otherwise noted T_J= -40 to +125°C, V_IN= 1.2V, V_DD= 3.3V . Typical values are at T_A= 25°C.

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Input Supplies

LDO Supply Voltage

VDD Supply Voltage

V_IN

1

3.6

V

V_DD

2.35

2.0

Measured at VDD pin, rising edge

Measured at VDD pin, falling edge

2.25

2.15

VDD UVLO Threshold

V

1.95

VDD UVLO Hysteresis

0.1

415

160

100

3

V

Quiescent Current for VDD

I_Q

Load =0A, EN = High, V_VDDQ> 1V

Load =0A, EN = Low, V_VDDQ> 1V, I_REF= 0A

Load =0A, EN = Low, V_VDDQ= 0V, I_REF= 0A

Load =0A, EN = High

700

400

160

30

μA

Shutdown Current for VDD

I_QSD

Quiescent Current for V_IN

Shutdown Current for V_IN

VTT Output

I_IN

I_INSD

Load =0A, EN = Low

3

20

Output Voltage Range

VTT

0.5

-1

1.8

+1

V

Output Voltage Tolerance with

respect to VDDQ/2

Load = 0A, VTT = 0.5V to 1.8V

%

3

SC2599

Electrical Characteristics (continued)

Parameter

Symbol

Conditions

-2A < Load < 2A

Min

-25

40

Typ

Max

Units

Load Regulation

+25

150

300

mV

High-Side MOSFET (source), Load = 0.1A

Low-Side MOSFET (sink), Load = 0.1A

EN = Low

100

140

8

On-Resistance

mΩ

Ω

50

Discharge MOSFET On-Resistance

Reference Input/Output

VDDQ Voltage Range

VDDQ Input Bias Current

Tolerance with respect to VDDQ/2

VREF Source Current Limit

VREF Sink Current Limit

Protection

1

0

3.6

10

1

V

ꢀA

%

Load = 0A, VREF = 0.5V to 1.8V

-1

40

- 40

mA

Thermal Shutdown Threshold

Thermal Restart Hysteresis

Output Current Limit Threshold

Soft-Start

160

20

⁰C

A

Ambient Temperature: 25 ⁰C

3.7

4.3

VTT Soft-Start Time

From EN = High to V_TT= 90% VREF

40

ꢀs

Logic

EN = High

EN = Low

1.7

-1

EN Logic Threshold

EN Input Current

V

0.3

1

ꢀA

4

SC2599

Block Diagram

Therm al

Shutdown

VDD

1

2

VIN

UVLO

EN

5

Soft-Start

DRIVER

LOGIC

R

3

VTT

VDDQ

8

+

-

R

4

GND

EN\

VREF

7

6

VTTS

Pin Descriptions

Pin #

Pin Name

Pin Function

1

VDD

Input bias voltage — 2.35V to 3.6V . Connect a ceramic capacitor from this pin to GND.

LDO input range — 1V to 3.6V. Connect ceramic capacitors from this pin to GND.

2

VIN

3

4

5

6

7

VTT

GND

EN

Output of the linear regulator. Connect ceramic capacitors from this pin to GND.

Ground reference for the IC.

Logic input to enable or disable the VTT output. If EN pin is grounded to shut down the linear regulator,

VREF remains active.

VTTS

VREF

VTT output sense input. Connect VTTS to the output at the output capacitor to implement remote sense.

The reference output, equal to one half of VDDQ. Connect a 100nF capacitor from this pin to GND.

8

VDDQ

GND

External reference input; range 1V to 3.6V.

Thermal pad. This pad must be connected to GND. For optimal heat sinking, connect to the GND plane us-

ing multiple vias.

PAD

5

SC2599

Detailed Application Circuit

C₁

C₂

C₃

PAD

VTT

VIN

G ND

VTT 3

VIN 2

4

5 EN

EN

C₄

C₅

6 VTTS

7 VREF

VDD

1

8

3.3V

C₆

R₁

VDDQ

VREF

100 O hm

C₇

C₈

Bill Of Materials

Reference Designator

Description

Value

Part Number

Manufacture

C₁, C₂, C₃, C₄, C₅,

Ceramic Capacitor

10uF/0805/X7R

1uF/0603/X7R

0.1uF/0603/X7R

GRM21BR71A106KE51

Murata

C₆

GRM188R71A105KA61D

GRM188R71H104KA93D

C₇, C₈

6

SC2599

Typical Characteristics

Characteristics in this section are based upon the detailed application circuit on page 6.

0.6V VREF Regulation Sink/Source

0.6V VTT Regulation Sink/Source

VIN = 1.2V, VDDQ = 1.2V, VDD = 3.3V

0.620

0.610

0.600

Sink

Source

Sink

Source

25⁰C

85⁰C

-40⁰C

25⁰C

85⁰C

-40⁰C

0.610

0.600

0.590

0.580

0.590

0.580

-0.05 -0.04 -0.03 -0.02 -0.01

0

0.01 0.02 0.03 0.04 0.05

-3

-2

-1

0

1

2

3

VTT Current (A)

VREF Current (A)

0.75V VREF Regulation Sink/Source

0.75V VTT Regulation Sink/Source

VIN = 1.5V, VDDQ = 1.5V, VDD = 3.3V

0.770

0.760

0.750

0.770

Sink

Source

Sink

Source

25⁰C

85⁰C

-40⁰C

25⁰C

85⁰C

-40⁰C

0.760

0.750

0.740

0.730

0.740

0.730

-0.05 -0.04 -0.03 -0.02 -0.01

0

0.01 0.02 0.03 0.04 0.05

-3

-2

-1

0

1

2

3

VREF Current (A)

VTT Current (A)

0.9V VREF Regulation Sink/Source

0.9V VTT Regulation Sink/Source

VIN = 1.8V, VDDQ = 1.8V, VDD = 3.3V

0.920

0.910

0.900

0.920

Sink

Source

Sink

Source

25⁰C

85⁰C

-40⁰C

25⁰C

85⁰C

-40⁰C

0.910

0.900

0.890

0.880

0.890

0.880

-0.05 -0.04 -0.03 -0.02 -0.01

0

0.01 0.02 0.03 0.04 0.05

-3

-2

-1

0

1

2

3

VTT Current (A)

VREF Current (A)

7

SC2599

Typical Characteristics

Characteristics in this section are based upon the detailed application circuit on page 6.

Start-Up and Shutdown Using EN

Shutdown Using VDD

VREF = 40mA, VTT = 1A

VIN = 1.2V, VDD = 3.3V, VREF = 0A, VTT = 0A

EN (2V/div)

VIN = VDDQ (200mV/div)

VDDQ (200mV/div)

VTT (200mV/div)

VREF (200mV/div)

VDD (1V/div)

VTT (200mV/div)

VREF (200mV/div)

500us/div

5ms/div

Start-Up Using VDDQ

VREF = 0A, VTT = 0A, VIN = 1.2V

Start-Up Using VDD

VREF = 40mA, VTT = 1A

VDDQ (200mV/div)

VIN = VDDQ (200mV/div)

VDD (1V/div)

VTT (200mV/div)

VREF (200mV/div)

2ms/div

1ms/div

Load Transient Source and Sink: -1A to +1A

VDDQ = 1.2V, VIN = 1.2V, VDD = 3.3V

Current Limit with VTT Shorted

VDDQ = 1.2V, VIN = 1.2V, VDD = 3.3V

Input Current (1A/div)

7mV

VTT (20mV/div)

VTT (100mV/div)

Source Current Load (1A/div)

Sink Current Load (1A/div)

200us/div

10ms/div

8

SC2599

Applications Information

theory tells us that the input capacitance can be chosen to

be half of the output capacitance.

VTT Output

VTT starts to ramp up when EN and VDD meet their startup

thresholds. SC2599 regulates VTT to the voltage at VREF

and can support up to 3A for sourcing or sinking

capability.

Ceramic capacitors have a capacitance value that degrades

with temperature, DC and AC bias, and their chemistry.

Usually, ceramic capacitors need to be derated by 50%

when operated at their rated DC voltage. Therefore, it is

recommended to use capacitors with a voltage rating of

6.3V or higher for 3.3V or lower applications.

To achieve tight regulation and fast dynamic response at

VTT, it is recommended to connect the VTTS sense signal

to VTT at the ceramic output capacitors.

Stability and VTT Capacitor

VREF Output

Figure 1 shows the small signal model for the sourcing

current loop stability. The low frequency pole is formed

by C_OUTand R_L. Since this pole depends on those variables,

it is recommended to have a minimum of 10uF C_OUTfor

stable condition. SC2599 has an internal compensation

network to ensure the stability as the load changes. Figure

2 shows the bode plot with the crossover frequency at

around 0.8MHz and 36 degree phase margin. Another

parameter eﬀecting to the loop stability is parasitic induc-

tance in PCB layout and output capacitor ESL. The gain

plot shows that a peaking rising after the crossing fre-

quency is due to ESL eﬀect. Minimizing the ESL reduces

this peaking.

VREF starts to ramp up when VDD meets the UVLO thresh-

old. SC2599 regulates VREF to one-half of VDDQ. To

reduce the component count and provide a good accu-

racy reference for VTT, SC2599 includes an internal resistor

divider network. SC2599 is capable of sinking or sourcing

up to 60mA at VREF. To reduce the component count

further, SC2599 does not require the user to have a local

ceramic capacitor at the VREF pin - but it is recommended

to layout with a capacitor place holder.

EN Input

The EN pin is used to enable and disable VTT only; it does

not control VREF. When EN is pulled low, the VTT output is

discharged internally to ground through an 8Ω FET.

VIN

VTT

Protection

gm *V_{G S}

-

SC2599 has thermal protection with auto-restart. When

the junction temperature is above the thermal shutdown

threshold (160^OC), SC2599 disables VTT, while VREF

remains present. When the junction temperature drops

below the hysteretic window, typically at 140^OC, SC2599

will be enabled again.

+

C_IN

V_{G S}

-

+

R_L

C_{O UT}

VREF

Z_C

SC2599 has a built-in current limit feature to prevent

damage to the sink and source FETs. If VTT is shorted to

VDD or ground, SC2599 will sink or source current up to

the current limit threshold.

Figure 1 — Small Signal Model

PCB Layout

The SC2599 requires minimal external components to

provide a VTT solution. Figure 3 shows the component

placement and layout for the application circuit on page

6. The thermal pad should be connected to the GND plane

using multiple vias.

Input Capacitor

The primary purpose of input capacitance is to provide the

charge to the VTT output capacitor when there is a load

transient at VTT. In the typical application circuit, VDDQ

equals VIN, and VTT equals one-half of VDDQ. As a result,

9

SC2599

PG ND on top and bottom layers

C3

C2

VTT copper pour on top

and bottom layers

C1

C4

C5

Route VTT sense

trace on inner layer

VIN copper pour on top

and/or bottom layer

C 4,C5 shown located

on bottom side

C6

R1 shown located on

bottom side

Thermal pad must connect to the

GND plane using multiple vias.

Figure 2 — Gain and Phase Bode Plot

Fc = 810KHz, PM = 36 degree at 1A Source

Figure 3 — Component Placement and Layout

Critical Layout Guidelines

C_VTT

Bias and Reference Capacitors:

Sinking Current Loop

A 1ꢀF capacitor must be placed as close as possible to the

IC and connected between pin 6 (VDD) and the ground

plane.

VTT

G ND

VIN

C_VIN

Q _B

A 0.1ꢀF capacitor must be placed as close as possible to

the IC and connected between pin 4 (VREF) and the

ground plane. The user has an option to add this capaci-

tor to the circuit but it is recommended to layout with a

capacitor place holder.

C_VTT

VDDQ Reference Capacitor:

VTT

VIN

G ND

An R-C ﬁlter from the supply used for VDDQ consisting of

a 100 Ω resistor and a 0.1ꢀF capacitor should be placed as

close as possible to the IC and connected between pin 5

(VDDQ) and the ground plane, as shown on page 6.

Q _T

Sourcing Current

Loop

C_VIN

VTT and VIN Capacitors:

Since SC2599 provides both sink and source capabilities,

the loop impedance through the input and VTT capacitors

plays an important role in circuit stability. Figure 4 shows

both sink and source current loops. Close attention to

board layout is needed to reduce ESL in these loops.

During a bode plot measurement for the sourcing current

loop, an injected small AC signal ﬂows around the loop

from C_INto Q_Tthrough C_VTTand then returns to C_VINthrough

the ground plane. Therefore, it is recommended to keep

the C_INand C_VTTcapacitors as close as possible to reduce

Figure 4 — Small AC Signal Current Loops

the ESL impedance between them. Similarly in the sinking

current loop, an injected small AC signal ﬂows from C_VTT

through Q_Band then returns to C_VTTthrough the GND

plane. Therefore, it is recommended to keep ESL small for

this loop. Balancing the ESL of those loops gives the best

case for stability.

10

SC2599

Outline Drawing — MLPD8

11

SC2599

Land Pattern — MLPD8

12

SC2599

owner. The information presented in this document does not form part of any quotation or contract, is believed to be

accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any conse-

quence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellec-

tual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation

resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress

including, but not limited to, exposure to parameters beyond the speciﬁed maximum ratings or operation outside the

speciﬁed range.

SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-

SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS

IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer

purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold

Semtech and its oﬃcers, employees, subsidiaries, aﬃliates, and distributors harmless against all claims, costs damages

and attorney fees which could arise.

Notice: All referenced brands, product names, service names and trademarks are the property of their respective

owners.

Contact Information

Semtech Corporation

Power Mangement Products Division

200 Flynn Road, Camarillo, CA 93012

Phone: (805) 498-2111 Fax: (805) 498-3804

www.semtech.com

13


型号：	SC2599EVB
厂家：	SEMTECH CORPORATION
描述：	Low Voltage DDR Termination Regulator 双倍数据速率
文件：	总13页 (文件大小：1026K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SC2599EVB [SEMTECH]

相关型号：

SC2599ULTRC

SC25A

SC25B

SC25D

SC25G

SC25J

SC25K

SC25M

SC25M1000A3S81030

SC25M1000A5FW1030

SC25M1000A5SQ1030

SC25M1000APSV1025