SC284PEVB_技术文档

SC284P

Dual Channel 2.5MHz, 2.0A Synchronous

Buck with Automatic Power Save

POWER MANAGEMENT

Features

Description



V_INRange — 2.75 – 5.5V

The SC284P is a dual channel 2A synchronous step-down

regulator designed to operate with an input voltage

range of 2.75 to 5.5 Volts. Each channel oﬀers seven

pre-determined output voltages via three control pins

programmable from ꢀ.0 to 3.3 Volts. The control pins

allow for on-the-ﬂy voltage changes, enabling system

designers to implement dynamic power savings. The

SC284P is also capable of adjusting the output voltage

via an external resistor divider.

V_OUTSelectable — ꢀ.0 - 3.3V

Up to 2A Output Current for Each Channel

Package with Ultra-Small Footprint : 3 x 3 x 0.6(mm)

Switching Frequency — 2.5MHz

Eﬃciency Up to 94%

High Light-load Eﬃciency via Automatic PSAVE

Mode



Low Output Noise in CCM

The SC284P is optimized for maximum eﬃciency over a

wide range of load currents. During full load operation,

the device operates in PWM mode with ﬁxed 2.5MHz

oscillator frequency, allowing the use of small surface

mount external components. As the load decreases,

the regulator will transition into Power Save mode

maintaining high eﬃciency.

Excellent Transient Response

Start Up into Pre-Biased Output

ꢀ00% Duty-Cycle Low Dropout Operation

Shutdown Current — <ꢀµA

Internal Soft-Start

Input Under-Voltage Lockout

Output Over-Voltage, Current Limit Protection

Over-Temperature Protection

V_OUTFurther Adjustable Using External Resistors

Connecting CTL0 — CTL2 to logic low forces the device

into shutdown mode reducing the supply current to less

than ꢀµA. Connecting any of the control pins to logic

high enables the converter and sets the output voltage

according to Table ꢀ. Other features include under-

voltage lockout, soft-start to limit inrush current, and

over-temperature protection.



PGOOD Feature

Lead-free, Halogen-free, and RoHS/WEEE Compliant

Applications



Wireless Access Point/Router/Modem

Femtocell

Set-Top Box

Point-Of-Sale

Projector

Typical Application Circuit

L_A2.2µH

PVINA

V_INA

V_OUTA

LXA

VOUTA

R_AVINA1Ω

C_OUTA

22µF

C_INA

10µF

AVINA

L_B2.2µH

C_AVINA10nF

V_OUTB

LXB

VOUTB

AGNDA

C_OUTB

22µF

SC284P

PVINB

AVINB

V_INB

R_AVINB1Ω

PGNDA

C_INB

10µF

C_AVINB10nF

PGNDB

CTL0B

AGNDB

CTL0A

CTL1A

CTL2A

CTL0B

CTL1B

CTL1A

CTL2A

CTL1B

CTL2B

PGOODA

PGOODB

PGOODA

PGOODB

Revision 2.ꢀ

ꢀ

SC284P

Pin Conﬁguration

Ordering Information

Device

Package

SC284PULTRC^(ꢀ)(2)

SC284PEVB

3 x 3 x 0.6(mm) MLPQ-UT20

Evaluation Board

20 19

18

17

16

Notes:

(ꢀ) Available in tape and reel only. A reel contains 3,000 devices.

(2) Available in lead-free package only. Device is fully WEEE and RoHS

compliant and halogen-free.

1

2

3

15

14

13

12

11

PVINA

AGNDA

AVINA

CTL0B

PGOODB

AVINB

TOP VIEW

AGNDB

PVINB

PGOODA

CTL0A

4

5

T

6

7

8

9

10

Table 1 – Output Voltage Settings

3 x 3 x 0.6(mm) MLPQ-UT20

θ_JA= 40°C/W

CTL2[A/B] CTL1[A/B] CTL0[A/B]

Output Voltage

Disabled

ꢀ.0V

0

ꢀ

0

ꢀ

0

ꢀ

0

ꢀ

0

ꢀ.ꢀV

Marking Information

ꢀ.2V

ꢀ.5V

ꢀ

0

ꢀ

0

ꢀ

ꢀ.8V

2.5V

3.3V

284P = Part Number Code

yyww = Date Code

xxxx = Semtech Lot Number

2

SC284P

Absolute Maximum Ratings

Recommended Operating Conditions

AVINA, AVINB, PVINA, PVINBSupply (V) . . . . . -0.3 to +6.0

LXA and LXB (V) . . . . . . . . . -ꢀ toV_IN+ꢀ, -3 (20ns Max), 6 Max

VOUTA and VOUTB (V) . . . . . . . . . . . . . . . . . . -0.3 to (V_IN+0.3)

CTLXA/Bpins (V) . . . . . . . . . . . . . . . . . . . -0.3 to (V_IN+ 0.3)

Peak IR Reflow Temperature (°C) . . . . . . . . . . . . . . . . . . . . . 260

ESD Protection Level⁽²⁾(kV) . . . . . . . . . . . . . . . . . . . . . . . . . 3kV

Output Short Circuit to GND. . . . . . . . . . . . . . . .Continuous

V_INAand V_INBSupply (V) . . . . . . . . . . . . . . . . . . . . . . . 2.75 to 5.5

Maximum Output Current Each Channel (A) . . . . . . . . . 2.0

Thermal Information

Thermal Resistance, Junction to Ambient ^(ꢀ)(°C/W) . . . . 40

Maximum Junction Temperature (°C) . . . . . . . . . . . . . . +ꢀ50

Storage Temperature Range(°C) . . . . . . . . . . . . . . -65to+ꢀ50

Exceeding the absolute maximum ratings may result in permanent damage to the device and/or device malfunction. Operation outside of the

parameters speciﬁed in the Electrical Characteristics section is not recommended.

Notes:

(ꢀ) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD5ꢀ standards.

(2) Tested according to JEDEC standard JESD22-Aꢀꢀ4-B.

Electrical Characteristics

Unless speciﬁed: V_INA= V_INB= 5.0V, V_OUTA= V_OUTB= ꢀ.5V, C_INA= C_INB=ꢀ0µF, C_OUTA=C_OUTB= 22µF, L= 2.2µH, -40°C ≤ (T_A= T_J)≤ +ꢀ25 °C. Unless otherwise

noted typical values are T_A= +25 °C.

Parameter

Symbol

Conditions

Min

2.75

2.55

Typ

Max Units

Input Voltage Range

V_INA/B

5.5

V

2.65

200

2.75

Rising V_{INA ,}V_INB

Hysteresis

Under-Voltage Lockout

Quiescent Current

UVLO

I_Q

mV

Channel A & B, PWM mode excluding I_OUT

,

6

mA

per channel

60

ꢀ

µA

µs

V

I_OUT= 0mA, CTL_X= V_IN

CTL_0-2= GND, Per channel

Shutdown Current

Soft-Start Time

I_SHDN

t_SS

ꢀ0

Channel A & B; I_OUT= 2A, V_OUT=90% of ﬁnal value

ꢀ700

Output Voltage Range

V_OUT

ꢀ.0

3.3

Channel A & B; I_OUT=400mA, PWM Mode

PSAVE Mode

-2.0

+2.0

Output Voltage Tolerance^(ꢀ)

CTL Settings Regulation

ΔV_OUT

%

ꢀ.75

ꢀ

Channel A & B; Relative to V_OUTat CTL=ꢀ00,

I_OUTA=400mA; I_OUTB=400mA; PWM Mode

ΔV_CTL-REG

Line Regulation

Load Regulation

ΔV_LINE-REG

ΔV_LOAD-REG

Channel A & B; V_IN= 2.75 – 5.5V; PWM Mode

Channel A & B; V_IN= 5.0V; I_OUT=ꢀmA – 2A

0.2

0.3

%/V

%/A

3

SC284P

Electrical Characteristics (continued)

Parameter

Symbol

Conditions

Channel A & B; Peak LX current

Channel A & B

Min

2.25

2.0

Typ

3.0

2.5

-ꢀ

Max Units

Current Limit Threshold

Oscillator Frequency

I_LIMIT

3.75

3.0

A

f_OSC

MHz

Channel A & B; V_IN= 5.5V; LX = 0V; CTL_0-2= GND

Channel A & B; V_IN= 5.5V; LX= 5.0V; CTL_0-2= GND

Average LX Current, V_OUT=ꢀ.5V

Channel A & B; I_LX= ꢀ00mA, T_J= 25 °C

Channel A & B; I_LX= -ꢀ00mA, T_J= 25 °C

Channel A & B; CTL_0-2=VIN or GND

Channel A & B

-ꢀ0

LX Leakage Current⁽²⁾

I_LK(LX)

µA

mA

mΩ

ꢀ

ꢀ0

Foldback Holding Current

High Side Switch Resistance⁽³⁾

Low Side Switch Resistance

CTLx Input Current⁽²⁾

I_{CL_HOLD}

R_{DSON_P}

R_{DSON_N}

I_{CTL_}

600

95

65

-2.0

ꢀ.6

2.0

0.4

µA

V

CTLx Input High Threshold

CTLx Input Low Threshold

Impedence of PGOOD Low

PGOOD Threshold

V_{CTLx_HI}

V_{CTLx_LO}

R_{PGOOD_LO}

V_{PG_TH}

Channel A & B

V

8

90

2

Ω

VOUT rising

Asserted

%

ms

μs

%

°C

PGOOD Delay

V_{PG_DLY}

PGOOD= Low

Channel A & B

20

ꢀꢀ5

ꢀ60

ꢀ0

V_OUTOver Voltage Protection

V_OVP

T_SD

Thermal Shutdown Temperature⁽⁴⁾

Thermal Shutdown Hysteresis⁽⁴⁾

T_{SD_HYS}

Notes:

(ꢀ) The “Output Voltage Tolerance”includes output voltage accuracy, voltage drift over temperature.

(2) A negative current means the current ﬂows from the pin and a positive current means the current ﬂows into the pin.

(3) Measured from VIN_A/Bto LX_A/B

(4) Thermal shutdown protection is independent for each channel.

.

4

SC284P

Typical Characteristics

Circuit Conditions: C_IN= ꢀ0uF/6.3V; C_OUT= 22uF/6.3V, Unless otherwise noted, L= 2.2uH (TOKO: ꢀꢀ27AS-2R2M).

Eﬃciency vs. Load Current

Total Loss (Per Channel) vs. Load Current

100

90

80

70

60

50

1000

800

600

400

200

0

TA=25℃

V_IN= 5V, V_OUT= 3.3V

Vin=3.3V,Vo=1.5V

V_IN= 3.3V, V_OUT= 1.5V

V_IN= 5V, V_OUT= 1.5V

Vin=5V,Vo=3.3V

Vin=5V,Vo=1.5V

0

0.5

1.0

1.5

2.0

0.001

0.01

0.1

1

10

Load Current (A)

Steady State (PSAVE) Operation (I_OUT=200mA)

Steady State (PWM) Operation (I_OUT=2A)

I_OUT

2A/div

I_OUT

200mA/div

I_LX

500mA/div

ꢀA/div

V_LX

2V/div

V_IN= 5V

500ns/div

V_IN= 5V

V_OUT= ꢀ.5V

UVLO Hysteresis

UVLO Rising Threshold

2.70

2.68

2.66

2.64

2.62

2.60

200

195

190

185

180

175

170

-50

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

Ambient Temperature (⁰C)

5

SC284P

Typical Characteristics

Circuit Conditions: C_IN= ꢀ0uF/6.3V; C_OUT= 22uF/6.3V, Unless otherwise noted, L= 2.2uH (TOKO: ꢀꢀ27AS-2R2M).

Load Regulation, Vout=1.0V

Load Regulation, Vout=1.2V

1.27

1.25

1.22

1.20

1.17

1.15

1.12

1.10

1.05

1.00

0.95

0.90

125⁰C

25⁰C

-40⁰C

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

Load Current (A)

Load Regulation, Vout=1.8V

Load Regulation, Vout=1.5V

1.60

1.90

1.85

1.80

1.75

1.70

1.55

1.50

1.45

1.40

125⁰C

25⁰C

-40⁰C

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

Load Current (A)

Load Regulation, Vout=2.5V

Load Regulation, Vout=3.3V

3.45

3.40

3.35

3.30

3.25

3.20

3.15

2.65

2.60

2.55

2.50

2.45

2.40

2.35

125⁰C

25⁰C

-40⁰C

25⁰C

-40⁰C

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

Load Current (A)

6

SC284P

Typical Characteristics

Circuit Conditions: C_IN= ꢀ0uF/6.3V; C_OUT= 22uF/6.3V, Unless otherwise noted, L= 2.2uH (TOKO: ꢀꢀ27AS-2R2M).

Line Regulation, Vout=1.0V, Iout=500mA

1.05

Line Regulation, Vout=1.2V, Iout=500mA

1.26

1.24

1.22

1.20

1.18

1.16

1.14

1.04

1.03

1.02

125⁰C

25⁰C

1.01

25⁰C

1.00

-40⁰C

0.99

0.98

0.97

0.96

0.95

2.5

3.0

3.5

4.0

4.5

5.0

5.5

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Input Voltage (V)

Inout Voltage (V)

Line Regulation, Vout=1.8V, Iout=500mA

Line Regulation, Vout=1.5V, Iout=500mA

1.58

1.89

1.87

1.85

1.83

1.81

1.79

1.77

1.75

1.73

1.71

1.56

1.54

1.52

1.50

1.48

1.46

1.44

125⁰C

25⁰C

125⁰C

25⁰C

-40⁰C

2.5

3.0

3.5

4.0

4.5

5.0

5.5

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Input Voltage (V)

Line Regulation, Vout=2.5V, Iout=500mA

Line Regulation, Vout=3.3V, Iout = 500mA

3.46

2.62

3.42

3.38

3.34

3.30

3.26

3.22

3.18

3.14

2.58

2.54

2.50

2.46

2.42

2.38

125⁰C

25⁰C

-40⁰C

25⁰C

-40⁰C

2.5

3.0

3.5

4.0

4.5

5.0

5.5

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Input Voltage (V)

7

SC284P

Typical Waveforms

Circuit Conditions: C_IN= ꢀ0uF/6.3V; C_OUT= 22uF/6.3V, L= 2.2uH (TOKO: ꢀꢀ27AS-2R2M).

Start Up (Enable) (V_OUT=1.5V)

Start Up (Power up V_IN=V_CTLx) (V_OUT=1.5V)

V_IN

5V/div

V_IN

2V/div

V_CTL

2V/div

V_OUT

ꢀV/div

V_OUT

ꢀV/div

V_IN= 5V

I_OUT= 0.4A to 2A

50us/div

V_IN= 5V

I_OUT= 0.4A to 2A

50us/div

Start Up (Enable) (V_OUT=3.3V)

Start Up (Power up V_IN=V_CTLx) (V_OUT=3.3V)

V_IN

5V/div

V_IN

2V/div

V_CTL

2V/div

V_OUT

ꢀV/div

V_OUT

ꢀV/div

V_IN= 5V

I_OUT= 2A

200us/div

V_IN= 5V

I_OUT= 2A

200us/div

Shutdown (Disable)(V_OUT=1.5V)

Shutdown (Disable)(V_OUT=3.3V)

V_IN

5V/div

V_IN

5V/div

V_CTL

2V/div

V_OUT

V_CTL

2V/div

ꢀV/div

V_OUT

ꢀV/div

V_IN= 5V

R_OUT= ꢀ.65Ω(2A)

50us/div

8

SC284P

Typical Characteristics

Circuit Conditions: C_IN= ꢀ0uF/6.3V; C_OUT= 22uF/6.3V, Unless otherwise noted, L= 2.2uH (TOKO: ꢀꢀ27AS-2R2M).

Switching Frequency Vs Temperature, Vout=1.0V

Switching Frequency Vs Temperature, Vout=1.2V

2.575

2.57

2.565

2.56

2.57

2.565

2.56

2.555

2.55

2.555

2.55

2.545

2.54

2.545

2.54

2.535

-40

-15

10

35

60

85

110

135

-40

-15

10

35

60

85

110

135

Ambient Temperature (⁰C)

Switching Frequency Vs Temperature, Vout=1.8V

Switching Frequency Vs Temperature, Vout=1.5V

2.575

2.57

2.565

2.56

2.57

2.565

2.56

2.555

2.55

2.555

2.55

2.545

2.54

2.545

2.54

2.535

-40

-15

10

35

60

85

110

135

-40

-15

10

35

60

85

110

135

Ambient Temperature (⁰C)

Switching Frequency Vs Temperature, Vout=2.5V

2.575

Switching Frequency vs Temperature, Vout=3.3V

2.575

2.57

2.565

2.56

2.57

2.565

2.56

2.555

2.55

2.555

2.55

2.545

2.54

2.545

2.54

2.535

-40

-15

10

35

60

85

110

135

-40

-15

10

35

60

85

110

135

Ambient Temperature (⁰C)

9

SC284P

Typical Characteristics

Circuit Conditions: C_IN= ꢀ0uF/6.3V; C_OUT= 22uF/6.3V, Unless otherwise noted, L= 2.2uH (TOKO: ꢀꢀ27AS-2R2M).

Switching Frequency Vs Input Voltage, Vout=1.0V

Switching Frequency Vs Input Voltage, Vout=1.2V

2.65

2.6

2.55

2.5

2.6

2.55

2.5

2.45

2.5

3

3.5

4

4.5

5

5.5

2.5

3

3.5

4

4.5

5

5.5

Input Voltage (V)

Switching Frequency Vs Input Voltage, Vout=1.8V

Switching Frequency Vs Input Voltage, Vout=1.5V

2.65

2.6

2.55

2.5

2.6

2.55

2.5

2.45

2.5

3

3.5

4

4.5

5

5.5

2.5

3

3.5

4

4.5

5

5.5

Input Voltage (V)

Switching Frequency Vs Input Voltage, Vout=2.5V

2.65

Switching Frequency vs Input Voltage, Vout=3.3V

2.65

2.6

2.55

2.5

2.6

2.55

2.5

2.45

2.5

3

3.5

4

4.5

5

5.5

2.5

3

3.5

4

4.5

5

5.5

Input Voltage (V)

ꢀ0

SC284P

Typical Waveforms

Circuit Conditions: C_IN= ꢀ0uF/6.3V; C_OUT= 22uF/6.3V, L= 2.2uH (TOKO: ꢀꢀ27AS-2R2M).

Transient Response (Vout=1.5V, Iout=0.1A to 0.4A)

Transient Response (Vout=1.5V, Iout=0.4A to 2A)

V_OUT

ꢀ00mV/div

50mV/div

I_LX

ꢀA/div

200mA/div

I_OUT

200mA/div

I_OUT

ꢀA/div

V_IN= 5V

I_OUT= 0.4A to 2A

V_IN= 5V

I_OUT= 0.ꢀA to 0.4A

20us/div

Transient Response (Vout=1.5V, Iout=0.01A to 0.1A)

Transient Response (Vout=3.3V, Iout=0.4A to 2A)

V_OUT

50mV/div

V_OUT

ꢀ00mV/div

I_LX

ꢀA/div

I_LX

500mA/div

I_OUT

50mA/div

I_OUT

200mA/div

V_IN= 5V

I_OUT= 2A

200us/div

V_IN= 5V

I_OUT= 2A

200us/div

Output Hard Short (V_OUT=1.5V)

Output Voltage Ripple (V_OUT=1.5V)

V_OUT

ꢀV/div

V_OUT

20mV/div

I_LX

ꢀA/div

V_IN= 5V

I_OUT= 500mA

ꢀus/div

V_IN= 5V

I_OUT= 500mA

50us/div

ꢀꢀ

SC284P

Pin Descriptions

Pin #

Pin Name Pin Function

ꢀ

2

3

PVINA

AGNDA

AVINA

Channel A — Input supply voltage for the converter power stage and internal circuitry.

Ground connection for internal circuitry — connect directly to PGNDA.

Power supply for internal circuitry — must be connected to PVINA using an R-C ﬁlter of ꢀΩ and ꢀ0nF.

Power Good indicator for channel A. When the output voltage reaches the PGOODA threshold, this pin will be

open drain (after the PGOOD delay), otherwise it is pulled low internally.

4

5

PGOODA

CTL0A

Channel A — Control bit 0, see Table ꢀ for decoding. This pin has a ꢀ MΩ internal pull-down resistor. This resis-

tor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in

under-voltage lockout.

Channel A — Control bit ꢀ, see Table ꢀ for decoding. This pin has a ꢀ MΩ internal pull-down resistor. This resis-

tor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in

under-voltage lockout.

6

7

CTLꢀA

CTL2A

Channel A — Control bit 2, see Table ꢀ for decoding. This pin has a ꢀ MΩ internal pull-down resistor. This resis-

tor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in

under-voltage lockout.

8

VOUTB

PGNDB

LXB

Output voltage sense pin of Channel B

9

Channel B — Ground connection for converter power stage and internal circuitry.

Switching node of Channel B — connect an inductor between this pin and the output capacitor.

Channel B — Input supply voltage for the converter power stage and internal circuitry.

Ground connection for internal circuitry — connect directly to PGNDB.

ꢀ0

ꢀꢀ

ꢀ2

ꢀ3

PVINB

AGNDB

AVINB

Power supply for internal circuitry — must be connected to PVINB using an R-C ﬁlter of ꢀΩ and ꢀ0nF.

Power Good indicator for channel B. When the output voltage reaches the PGOODB threshold, this pin will be

open drain (after the PGOOD delay), otherwise it is pulled low internally.

ꢀ4

ꢀ5

PGOODB

CTL0B

Channel B — Control bit 0, see Table ꢀ for decoding. This pin has a ꢀ MΩ internal pulld-own resistor. This resis-

tor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in

under-voltage lockout.

Channel B — Control bit ꢀ - see Table ꢀ for decoding. This pin has a ꢀ MΩ internal pull-down resistor. This

resistor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is

in under-voltage lockout.

ꢀ6

ꢀ7

CTLꢀB

CTL2B

Channel B — Control bit 2, see Table ꢀ for decoding. This pin has a ꢀ MΩ internal pull-down resistor. This resis-

tor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in

under-voltage lockout.

ꢀ8

ꢀ9

20

VOUTA

PGNDA

LXA

Output voltage sense pin of Channel A

Channel A — Ground connection for converter power stage and internal circuitry.

Switching node of Channel A — connect an inductor between this pin and the output capacitor.

Thermal pad for heatsinking purposes.

PAD

ꢀ2

SC284P

Block Diagram

1

PVINA

Current Amp

AVINA

3

Plimit Amp

Oscillator and

Slope Generator

Control

Logic

20

LXA

18

VOUTA

CTL0A

CTL1A

CTL2A

PWM

Comp

Error Amp

5

6

7

500mV

Ref

Voltage

Select

19

PGNDA

PSAVE

Comp

2

AGNDA

PGOOD

Detector

Delay

4

PGOODA

AVINB

11

PVINB

Current Amp

13

Plimit Amp

Oscillator and

Slope Generator

Control

Logic

10

LXB

8

VOUTB

CTL0B

PWM

Comp

15

Error Amp

500mV

Ref

Voltage

Select

CTL1B 16

9

PGNDB

17

12

CTL2B

PSAVE

Comp

AGNDB

PGOOD

Detector

Delay

PGOODB

14

ꢀ3

SC284P

Applications Information

enough in value for the current through the resistor chain

to be at least 20µA in order to ignore the V_OUTpin current.

Detailed Description

The SC284P is a two channel synchronous step-down

converter. Both channels of this device are designed

to operate at a ﬁxed-frequency of 2.5MHz in CCM and

provide the same current capacity of up to 2A. The

switching frequency is chosen to minimize the size of the

external inductor and capacitors while maintaining high

eﬃciency. Both channels of SC284P are independent.

where V_OSTDis the pre-determined output voltage via the

CTL pins.

Operation

C_FFis needed to maintain good transient response

performance. The correct value of C_FFcan be found using

the following equation.

During normal operation, the PMOS FET is activated on

each rising edge of the internal oscillator. The voltage

feedback loop uses an internal feedback resistor divider.

The period is set by the internal oscillator. The device has

an internal synchronous NMOS rectiﬁer and does not

require a Schottky diode on the LXpin.

To simplify the design, it is recommended to program the

desired output voltage from a standard ꢀ.0V as shown in

Figure ꢀ with the correct C_FFcalculated from Equation 2.

For programming the output voltage from other standard

voltages, R_FBꢀ, R_FB2and C_FFneed to be adjusted to meet

Equations ꢀ and 2.

Programmable Output Voltage

Both channels on SC284P have seven pre-determined

output voltage values which can be individually selected

by programming the CTL input pins (see Table ꢀ — Output

Voltage Settings). Each CTL pin has an active ꢀ MΩ internal

pull-down resistor. The ꢀMΩ resistor is switched in circuit

whenever the CTL input voltage is below the input

threshold, or when the part is in under-voltage lockout. It is

recommended to tie all high CTL pins together and use an

V_INA

L

V_OUTA

PVINA

LXA

R_AVINA1Ω

C_INA

10µF

SC284P

C_FFA

C_OUTA

AVINA

AGNDA

PVINB

R_FB1A

C_AVINA

0.1µF

external pull-up resistor to V_INif there is no enable signal, or

if the enable input is an open drain/collector signal.The CTL

pins may be driven by a microprocessor to allow dynamic

voltage adjustment for systems that reduce the supply

voltage when entering sleep states. Avoid all zeros being

present on the CTL pins when changing programmable

output voltages as this would momentarily disable the

device.

VOUTA

R_FB2A

10kΩ

V_INB

R_FB1A= (V_OUTA-1)

x R_FB2A

for CTLA_X= 0010

(1.0V)

R_AVINB1Ω

C_INB

10µF

AVINB

L

V_OUTB

C_AVINB

0.1µF

LXB

AGNDB

C_FFB

C_OUTB

PGOODA

R_FB1B

PGOODA

CTL3A

Enable A

VOUTB

CTL2A

CTL1A

R_FB2B

10kΩ

R_FB1B= (V_OUTB-1)

x R_FB2B

SC284P is also capable of regulating a diﬀerent (higher)

output voltage, which is not shown in the Table ꢀ, via an

external resistor divider.There will be a typical 2µA current

for CTLB_X= 0010

(1.0V)

PGOODB

Enable B

PGNDA

PGNDB

PGOODB

CTL3B

CTL2B

CTL1B

ﬂowing into the V_OUTpin. The typical schematic for an ad-

justableoutputvoltageoptionfromthestandardꢀ.0Vwith

CTL_X=[00ꢀ], is shown in Figure ꢀ. R_FBꢀA/Band R_FB2A/Bare used

to adjust the desired output voltage. If the R_FB2A/Bcurrent

Figure 1 — Output Voltage Programming

is such that the 2µAV_OUTpin current can be ignored, then R_FBꢀA/B

can be found by the next equation. R_FB2A/Bneed to be low

ꢀ4

SC284P

Applications Information (continued)

Power Save Mode Operation

Power Good

PGOOD is an open-drain output.When the output volt-

age drops below nominal voltage, the PGOOD pin is

pulled low after a 20μs delay. During start-up, PGOOD

will be asserted ꢀ.7ms (typ.) after the output voltage

reaches 90% of the final regulation voltage.Over volt-

age, fold-back current limit and thermal shutdown will

force PGOOD low after a 20μs delay. When recovering

from a fault, PGOOD will be asserted ꢀ.7ms (typ.) af-

ter Vout reaches 90% of the final regulation voltage.

WhentheloadcurrentdecreasesbelowthePSAVEthreshold,

PWM switching stops and the device automatically enters

PSAVE mode.This threshold varies depending upon the in-

putvoltageandtheoutputvoltagesetting,optimizingeﬃ-

ciencyforallpossibleloadcurrentsinPWMorPSAVEmode.

While in PSAVE mode, output voltage regulation is

controlled by a series of switching bursts. During a

burst, the inductor current is limited to a peak value

which controls the on-time of the PMOS switch. Af-

ter reaching this peak, the PMOS switch is disabled

and the inductor current decreases to near 0mA.

Switching bursts continue until the output voltage climbs

to VOUT +2.5% or until the PSAVE current limit is reached.

Switching is then stopped to eliminate switching losses,

enhancing overall eﬃciency. Switching resumes when

the output voltage reaches the lower threshold of VOUT

and continues until the upper threshold again is reached.

Maximum Power Dissipation

Each channel of SC284P has its own Θ_JAof 40°C/W when

only one channel is in operation. Since both channels are

within the same package, please make sure to use both

channelsforpowercalculations. Toguaranteeanoperating

junction temperature of less than ꢀ25°C, Figure 3 shows

the maximum allowable power loss for each channel. The

curve is based upon the junction temperature of either

channel reaching a maximum of ꢀ25°C. Each channel of

SC284P can support up to 2A load current.

Note that the output voltage is regulated hysteretically

while in PSAVE mode between VOUT and VOUT + 2.5%.

The period and duty cycle while in PSAVE mode are

solely determined by VIN and VOUT until PWM mode

resumes. This can result in the switching frequency be-

ing much lower than the PWM mode frequency. If the

output load current increases enough to cause VOUT to

decrease below the PSAVE exit threshold (VOUT-4%),

the device automatically exits PSAVE and operates in

continuous PWM mode. Note that the PSAVE high and

low threshold levels are both set at or above

VOUT to minimize undershoot when the SC284P

2.8

2.6

2.4

2.2

T_A= 25°C

2

1.8

1.6

1.4

1.2

1

0.8

0.6

T_A= 55°C

T_A= 85°C

0.4

0.2

0

exits PSAVE mode and returns to PWM mode.

2.8

2.2 2.4 2.6

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

Load

Loss of Channel A (W)

(I_OUT

)

O FF

V_{OU T}+2.5%

Figure 3 — Maximum allowable loss for each channel

for a maximum junction temperature of 125°C

V_OUT

V_{OU T}- 4%

BURST

V_LX

PSAVE

EXIT

PW M M ode at

M edium/High

Load

PSAVE M ode at

Light Load

PW M M ode at

M edium/High

Load

Tim e

Figure 2 - Transitions Between PWM and PSAVE Modes

ꢀ5

SC284P

Applications Information (continued)

Protection Features

Soft-Start

The SC284P provides the following protection features:

• Current Limit

Soft-start is activated once VIN reaches the UVLO and one

or more CTL pins are set high to enable the part. A thermal

shutdown event will also activate the soft-start sequence.

Soft-start controls the maximum current during startup

thus limiting inrush current. The PMOS current limit is

stepped through four soft-start levels of approximately

20%, 25%, 40%, & ꢀ00%. Each step is maintained for 400μs

following an internal reference start up duration of ꢀ00μs

giving a total nominal startup period of ꢀ700μs. During

startup, the chip operates by controlling the inductor

current swings between 0A and current limit. If at any time

V_OUTreaches 86% of the target or at the end of the soft-

start period, the SC284P will switch to PWM mode

operation.

• Over-Voltage Protection

• Soft-Start

• Thermal Shutdown

Current Limit

The internal PMOS power device in the switching stage

is protected by a current limit feature. If the inductor

current is above the PMOS current limit for ꢀ6 consecutive

cycles, the part enters foldback current limit mode and

the output current is limited to the current limit holding

current (I_{CL_HOLD}) of a few hundred milliampere. Under

this condition, the output voltage will be the product of

I_{CL_HOLD}and the load resistance. The current limit holding

current will decrease when the output voltage increases.

The load presented must fall below the current limit

holding current for the part to exit foldback current

limit mode. Figure 4 shows how the typical current limit

holding current varies with output voltage. The SC284P

is capable of sustaining an indeﬁnite short circuit without

damage and will resume normal operation when the fault

is removed. The foldback current limit mode is disabled

during soft-start.

The SC284P is capable of starting up into a pre-biased

output.

Shut Down

When all CTL pins of a channel are low, the corresponding

channel will be disabled, drawing less than ꢀμA from that

input power supply. The internal switches and bandgap

voltage will be immediately turned oﬀ.

Thermal Shutdown

300

The device has a thermal shutdown feature to protect

the SC284P if the junction temperature exceeds ꢀ60°C.

During thermal shutdown, the on-chip power devices are

disabled, tri-stating the LX output. When the temperature

drops by ꢀ0°C, it will initiate a soft-start cycle to resume

normal operation.

T_A= 25°C

250

200

150

100

50

V_IN= 3.6V

V_IN= 5.0V

Inductor Selection

V_IN= 3.3V

The SC284P converter has internal loop compensation.

The compensation is designed to work with an output

ﬁlter corner frequency of less than 40kHz for a V_INof 5V

and 50KHz for a V_INof 3.3V over any operating condition.

The corner frequency of the output ﬁlter is shown in the

following equation.

0

1.0

1.5

2.0

2.5

3.0

3.5

Output Voltage (V)

Figure 4— Typical Current Limit Holding Current

vs. Output Voltage

1

f_C

2S

LuC_OUT

Over-Voltage Protection

In the event of a ꢀ5% over-voltage on the output, the

PWM drive is disabled leaving the LX pin ﬂoating.

Values outside this range may lead to instability, malfunc-

tion, or out-of-speciﬁcation performance.

ꢀ6

SC284P

Applications Information (continued)

L at

Dimen-

sions

LxWxH

(mm)

In general, the inductance is chosen by making the

inductor ripple current to be less than 30% of maximum

load current. When choosing an inductor, it is important

to consider the change in inductance with DC bias

current. The inductor saturation current is speciﬁed as

the current at which the inductance drops a speciﬁc

percentage from the nominal value. This is approximately

30%. Except for short-circuit or other fault conditions,

the peak current must always be less than the saturation

current speciﬁed by the manufacturer. The peak current is

the maximum load current plus one half of the inductor

ripple current at the maximum input voltage. Load and/or

line transients can cause the peak current to exceed this

level for short durations. Maintaining the peak current

below the inductor saturation speciﬁcation keeps the

inductor ripple current and the output voltage ripple at

acceptable levels. Manufacturers often provide graphs of

actual inductance and saturation characteristics versus

applied inductor current. The saturation characteristics of

the inductor can vary signiﬁcantly with core temperature.

Core and ambient temperatures should be considered

when examining the core saturation characteristics.

DCR

Max

(Ω)

Rated

Current

(A)

Manufacturer

Part Number

L

(μH)

Rated

Current

(μH)

TOKO

1071AS-1R0N

ꢀ.00 30% 0.040

2.20 20% 0.048

ꢀ.00 23% 0.062

2.70

2.50

2.20

0.70

ꢀ.54

0.70

2.8x3.0xꢀ.5

3.5x3.7xꢀ.8

3.2x3.2xꢀ.5

TOKO

1127AS-2R2M

Panasonic

ELLVGG1R0N

Table 2 – Recommended Inductors

C_OUTSelection

The internal voltage loop compensation in the SC284P

limits the minimum output capacitor value to 22µF if using

a 2.2µH inductor or 44µF if using a ꢀµH inductor.This is due

to its inﬂuence on the the loop crossover frequency, phase

margin, and gain margin. The total output capacitance

should not exceed 50µF to avoid any start-up problems.

For most typical applications it is recommended to use an

output capacitance of 22µF to 44µF. When choosing the

output capacitor’s capacitance, verify the voltage derating

eﬀect from the capacitor vendor’s data sheet.

When the inductance has been determined, the DC

resistance (DCR) must be examined. The eﬃciency that

can be achieved is dependent upon the DCR of the

inductor. Lower values give higher eﬃciency. The RMS DC

current rating of the inductor is associated with losses in

the copper windings and the resulting temperature rise of

the inductor. This is usually speciﬁed as the current which

produces a 40˚C temperature rise. Most copper windings

are rated to accommodate this temperature rise above

maximum ambient.

Capacitors with X7R or X5R ceramic dielectric are

recommended for their low ESR and superior temperature

and voltage characteristics. Y5V capacitors should not

be used as their temperature coeﬃcients make them

unsuitable for this application.

The output voltage droop due to a load transient is

determined by the capacitance of the ceramic output

capacitor. The ceramic capacitor supplies the load current

initially until the loop responds. Within a few switching

cycles the loop will respond and the inductor current will

increase to match the required load. The output voltage

droop during the period prior to the loop responding

can be related to the choice of output capacitor by the

relationship from the following equation.

Magnetic ﬁelds associated with the output inductor can

interfere with nearby circuitry. This can be minimized by

the use of low noise shielded inductors which use the

minimum gap possible to limit the distance that magnetic

ﬁelds can radiate from the inductor. However shielded

inductors typically have a higher DCR and are thus less

eﬃcient than a similarly sized non-shielded inductor.

Final inductor selection depends upon various design

considerations such as eﬃciency, EMI, size, and cost. Table

2 lists the manufacturers of recommended inductor

options. The saturation characteristics and DC current

ratings are also shown.

ꢀu ',_/2$'

9_'5223u I_26&

&

287

The outputcapacitorRMSripplecurrentmaybecalculated

ꢀ7

SC284P

Applications Information (continued)

from the following equation.

§

·

9₂₈₇

9

9₂₈₇

9

¨

¸

,

ꢂꢀ

&,1ꢁ506ꢀ

,1

©

,1

¹

9

₂₈₇u

ꢀ

9

ꢂ 9₂₈₇

ꢁ

§

·

The input voltage ripple and RMS current ripple are at

a maximum when the input voltage is twice the output

voltage or 50% duty cycle.

ꢄ

,1ꢁ0$;ꢀ

¨

¸

,

&287ꢁ506ꢀ

/ u I_26&u 9

ꢃ ꢂ

©

,1

¹

Table 3 lists the manufac turers of recommended capacitor

options.

The input capacitor provides a low impedance loop for

the edges of pulsed current drawn by the PMOS switch.

Low ESR/ESL X5R ceramic capacitors are recommended

for this function. To minimize stray inductance, the capaci-

tor should be placed as close as possible to the VIN and

GND pins of the SC284P.

Value

Rated

Type Voltage

(VDC)

Dimensions

LxWxH

Manufacturer

Part Nunber

Value

(μF)

at

3.3V

(μF)

(mm)

Murataꢀ

2.0xꢀ.25xꢀ.25

(EIA:0805)

ꢀ0 ꢀ0%

22 20%

47 20%

X5R

6.3

4.74

4.05

6.57

20.3

GRM21BR60J106K

Murataꢀ

2.0xꢀ.25x0.85

(EIA:0805)

GRM219R60J106K

Murataꢀ

2.0xꢀ.25xꢀ.25

(EIA:0805)

GRM21BR60J226M

Murataꢀ

3.2xꢀ.6xꢀ.6

(EIA:ꢀ206)

GRM31CR60J476M

Table 3 – Recommended Capacitors

C_INSelection

The SC284P source input current is a DC supply current

with a triangular ripple imposed on it. To prevent large

input voltage ripple, a low ESR ceramic capacitor is

required. A minimum value of ꢀ0μF should be used. It is

important to consider the DC voltage coeﬃcient charac-

teristics when determining the actual required value. It

should be noted a ꢀ0µF, 6.3V, X5R ceramic capacitor with

5V DC applied may exhibit a capacitance as low as 4.05µF.

To estimate the required input capacitor, determine the

acceptable input ripple voltage and calculate the

minimum value required for C_INas shown by the following

equation.

§

·

9₂₈₇

9

9₂₈₇

9

¨

¸

ꢀꢀ

,1

©

,1

¹

&

,1

§

·

'9

¨

¸

ꢀ (65 u I_26&

¸

,

©

287

¹

The input capacitor RMS ripple current varies with the

input and output voltage. The maximum input capacitor

RMS current is found from the next equation .

ꢀ8

SC284P

Applications Information (continued)

Stages

Operation description

K

Normal PWM operation

Overload protection is enabled and peak current limit at 100% level

J

6

7

6WDJH

ꢁ

6WDJH

ꢂ

Cycle by cycle peak current limit

OCP protection is activated.

Foldback peak current limit.

6WDJH

ꢀ

8

PWM "ON" when inductor current of 0A

PWM "OFF" when inductor current hits peak current limit of foldback

mode.

M

Conditions

Operation description

Inductor current hits peak current limit

Peak current limit for 16 consecutive cycles

Vout ≥ 100% target

J

K

L

M

Inductor current doesn't hit peak current limit

Figure 5 — Current Limit Protection

Stages

Operation description

Chip is OFF.

0

Peak current limit at 20% level

PWM "ON" when inductor current of 0A

PWM "OFF" when inductor current hits peak current limit

Stage duration of 400µs

1

Peak current limit at 25% level

PWM "ON" when inductor current of 0A

PWM "OFF" when inductor current hits peak current limit

Stage duration of 400µs

2

3

4

%

Peak current limit at 40% level

6WDJH

ꢁ

6WDJH

ꢂ

PWM "ON" when inductor current of 500mA

PWM "OFF" when inductor current hits peak current limit

Stage duration of 400µs

$

&

6WDJH

ꢀ

Peak current limit at 100% level

PWM "ON" when inductor current of 500mA

PWM "OFF" when inductor current hits peak current limit

Stage duration of 400µs

Peak current limit at 100% level

Switch to closed-loop PWM operation.

Soft Start ends.

*

)

6WDJH

ꢃ

+

(

5

6

'

Normal PWM operation

Overload protection is enabled

6WDJH

ꢅ

6WDJH

ꢄ

Conditions

Operation description

VIN > UVLO Threshold

AND

One or more CTL pin is high.

AND

A

,

Internal reference is ready.

End of stage 1 AND Vout<86% of target

End of stage 2 AND Vout<86% of target

End of stage 3 AND Vout<86% of target

End of stage 4 AND Vout<86% of target

Vout>86% of target

End of soft start time of 1700µs

B

C

D

E

F

G

H

I

6WDJH

ꢆ

Figure 6 — Soft Start Operation

ꢀ9

SC284P

Applications Information (continued)

PCB Layout Considerations

The layout diagram in Figure 7 shows a recommended

PCB top layer for the SC284P and supporting components.

Figure 8 shows the bottom layer for this PCB. Fundamental

layout rules must be followed since the layout is critical for

achieving the performance specified in the Electrical

Characteristics table. Poor layout can degrade the perfor-

mance of the DC-DC converter and can contribute to EMI

problems, ground bounce, and resistive voltage losses.

Poor regulation and instability can result.

The following guidelines are recommended when devel-

oping a PCB layout:

Figure 7 — Recommended PCB Layout (Top Layer)

ꢀ. The input capacitor, C_IN, should be placed as close

to the VIN and PGND pins as possible. This capacitor

provides a low impedance loop for the pulsed currents

present at the buck converter’s input. Use short wide

traces to connect as closely to the IC as possible.

This will minimize EMI and input voltage ripple by

localizing the high frequency current pulses.

2. Keep the LX pin traces as short as possible to minimize

pickup of high frequency switching edges to other

parts of the circuit. C_OUTand L should be connected as

close as possible between the LX and PGND pins, with

a direct return to the PGND pin from C_OUT

.

3. Route the output voltage feedback/sense path away

from the inductor and LX node to minimize noise and

magnetic interference.

Figure 8 — PCB Bottom Layer

4. Use a ground plane referenced to the SC284P PGND

pin. Use several vias to connect to the component

side ground to further reduce noise and interference

on sensitive circuit nodes.

5. If possible, minimize the resistance from the output

and PGND pin to the load. This will reduce the voltage

drop on the ground plane and improve the load

regulation. It will also improve the overall eﬃciency

by reducing the copper losses on the output and

ground planes.

C5

L2

R1 C1

C3

U1

6. Connect the AGND pins to the thermal pad.

C4

C2 R2

L1

C6

Figure 9 — Recommended PCB Layout

(Top Layer Details)

20

SC284P

Outline Drawing – 3x3 MLPQ-UT20

Land Pattern – 3x3 MLPQ-UT20

2ꢀ

SC284P

The information presented in this document does not form part of any quotation or contract, is believed to be accurate

and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its

use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property

rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from

misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but

not limited to, exposure to parameters beyond the speciﬁed maximum ratings or operation outside the speciﬁed range.

SEMTECHPRODUCTSARENOTDESIGNED,INTENDED,AUTHORIZEDORWARRANTEDTOBESUITABLEFORUSEINLIFE-SUPPORT

APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH AP-

PLICATIONSISUNDERSTOODTOBEUNDERTAKENSOLELYATTHECUSTOMER’SOWNRISK.Shouldacustomerpurchaseoruse

Semtechproductsforanysuchunauthorizedapplication,thecustomershallindemnifyandholdSemtechanditsoﬃcers,em-

ployees,subsidiaries,aﬃliates,anddistributorsharmlessagainstallclaims,costsdamagesandattorneyfeeswhichcouldarise.

Contact Information

Semtech Corporation

Power Management Products Division

200 Flynn Road, Camarillo, CA 930ꢀ2

Phone: (805) 498-2ꢀꢀꢀ Fax: (805) 498-3804

www.semtech.com

22


型号：	SC284PEVB
厂家：	SEMTECH CORPORATION
描述：	Dual Channel 2.5MHz, 2.0A Synchronous Buck with Automatic Power Save
文件：	总22页 (文件大小：2696K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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