SC3203SETRC [SEMTECH]
3A EcoSpeed® Step-Down Regulator with Power Save;
| 型号： | SC3203SETRC |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | 3A EcoSpeed® Step-Down Regulator with Power Save |
| 文件： | 总20页 (文件大小：1294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC3203
3A EcoSpeed® Step-Down Regulator
with Power Save
POWER MANAGEMENT
Features
Description
®
Input voltage — 9V to 16V
Programmable VIN UVLO
The SC3203 is an integrated, synchronous 3A EcoSpeed
•
step-down regulator. It incorporates Semtech’s advanced,
patented adaptive on-time architecture to achieve best-
in-class dynamic performance using point-of-load appli-
cations. The input voltage range is 9V to 16V, and the
output voltage is adjustable from 0.75V to 7.5V. The device
features an internal LDO and automatic PSAVE mode for
high efficiency across the output load range.
Output voltage adjustable from 0.75V to 7.5V
Output current — Up to 3A
Internal reference — + 2%
Supports ceramic capacitors
Low component count
Power good output (open-drain)
Low RDSON mosfets
•
65mΩ low-side/100mΩ high-side
ENABLE input
Switching frequency is internally programmed to 500kHz.
Semtech’s adaptive on-time control provides pseudo-fixed
frequency operation in continuous conduction combined
with excellent transient performance.
•
Programmable VIN UVLO and hysteresis
VIN Under-Voltage Lock Out
500kHz switching frequency
Adaptive on-time control:
Additional features include cycle-by-cycle current limit,
soft start, output over voltage and over temperature pro-
tection, and automatic fault recovery. The open-drain
PGOOD pin provides output status.
•
Excellent transient response
Pseudo-fixed frequency during CCM
•
Fault protection features:
•
•
•
Over-current/Over-voltage/Under-voltage
Over-temperature
Automatic Restart (Hiccup)
The device is available in a lead-free SOIC8-EP5 package.
Internal soft-start
Applications
Start-up into pre-bias output
Power Save and Smart Power Save
Internal LDO for bias voltage
SOIC8-EP5 lead-free package
WEEE and RoHS compliant and halogen-free
Consumer Electronics, DTV and Set-top Boxes
Networking Equipment, Embedded Systems
Medical Equipment, Office Automation
Instrumentation, Portable Systems
Point of Load Converters
Typical Application Circuit
3.3V
RPG O O D
SC3203
10n
PG O O D
PG O O D
BST
LX
L
VO UT
Enable
VIN
EN
CTO P
VIN
49.9
Ω
BYP
VFB
CIN
RTO P
RBO T
CO U T
PAD
AG ND
1µ
Rev 2.1
1
© 2015 Semtech Corporation
SC3203
Pin Configuration
Ordering Information
(1)(2)
Device
Package
TOP VIEW
SC3203SETRC
SC3203EVB
SOIC8-EP5
1
2
3
4
8
7
6
5
VFB
EN
BST
LX
Evaluation Board
Notes:
PG O O D
BYP
(1) Available in tape and reel only. A reel contains 3,000 devices.
(2) Lead-free packaging only. Device is WEEE and RoHS compliant
and halogen-free.
VIN
AG ND
PG ND PAD
SOIC8-EP5
Marking Information
Top M ark
SC3203
yyww
xxxxx
yyww = Date code
xxxxx = Lot code
2
SC3203
Absolute Maximum Ratings
Recommended Operating Conditions
LX to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +18
EN to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +18
VIN to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +18
BST to LX (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0
BST to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +23
BYP to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3to+6.0
PGOOD to AGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3to+6.0
VFB to AGND (V) . . . . . . . . . . . . . . . . . . . . . . . -0.3 to BYP +0.3
AGND to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 0.3
Maximum Peak Inductor Current (A) . . . . . . . . . . . . . . . . . 5.0
Peak IR Reflow Temperature (°C ). . . . . . . . . . . . . . . . . . . . . 260
BST to LX Capacitance (nF) . . . . . . . . . . . . . . . . . . . . . . . . . . ..15
ESD Protection Level (kV)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . 5kV
Supply Input Voltage (V) . . . . . . . . . . . . . . . . . . . . . . . 9 to 16
Maximum Continuous Output Current (A). . . . . . . . . . . . 3.0
Maximum Peak Inductor Current (A) . . . . . . . . . . . . . . . 4.0
Thermal Information
Storage Temperature (°C ) . . . . . . . . . . . . . . . . . . -60 to +150
Maximum Junction Temperature (°C ). . . . . . . . . . . . . . . . 150
Operating Junction Temperature (°C ). . . . . . . -40 to +125
Thermal Resistance Junction to Ambient(2) (°C/W ). . . . .36
Thermal Resistance Junction to Case(2) (°C/W ). . . . . . . .5.5
Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not recommended.
NOTES:
(1) Tested according to JEDEC standard JESD22-A114-B.
(2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
Electrical Characteristics
Unless specified: VIN =12V, TA=+25°C for Typ, -40°C to +85°C for Min and Max, TJ < 125°C, per detailed application circuit
Min
Typ
Max
4.55
10
Parameter
Conditions
Units
Input Supply
VIN rising edge, EN = VIN
Hysteresis, EN = VIN
VEN = 0V
4.40
0.30
V
V
VIN UVLO Threshold
VIN Supply Current
μA
No switching, IOUT = 0A, VFB 5% higher than
the VFB On-time Threshold
0.35
mA
Controller
VFB On-Time Threshold Accuracy
VFB Input Bias Current
736
750
0.2
766
mV
μA
3
SC3203
Electrical Characteristics (continued)
Min
Typ
Max
Parameter
Timing
Conditions
Units
On-time accuracy
VIN = 12V, VOUT = 3.3V
476
560
260
32
644
ns
ns
Minimum Off-Time
Automatic Restart Cycle Time
Soft start
ms
Soft start Time
From PWM Switching to Output Regulation
LX - PGND
1.8
0
ms
Current Sense
Zero-Crossing Detector Threshold
Fault Protection
-10
+10
mV
VFB with respect to nominal,
8 Consecutive Switching Cycles
Output Under-Voltage Threshold
75
%VREF
Output Over-Voltage Threshold
Smart PowerSave Protection Threshold
OV, UV Fault Noise Immunity Delay
Over-Temperature Shutdown
PGOOD Output
VFB with respect to nominal
VFB with respect to nominal
120
110
2.5
%VREF
%VREF
μs
160
°C
PGOOD Startup Delay Time
From EN rising edge to PGOOD high
FB rising edge
3.3
90
ms
%
PGOOD Under-voltage Threshold
FB falling edge
85
%
PGOOD Over-voltage Threshold
FB rising edge
120
%
Enable Input(1)
EN Input Logic High Threshold (VEN_BYP
)
VIN = 12V; EN rising edge; BYP on; Switcher off
VIN = 12V; EN rising edge; BYP on, Switcher on
Hysteresis at VEN_ON threshold
1.0
1.5
V
V
EN Input Logic High Threshold (VEN_ON
EN Input Voltage Hysteresis
EN Input Current Hysteresis
EN Input Bias Current
)
100
1.75
mV
μA
μA
kΩ
Hysteresis at VEN_ON threshold
VEN = 12V
-1
10
EN Input Resistance
EN < VEN_ON Threshold; EN rising edge
810
4
SC3203
Electrical Characteristics (continued)
Min
Typ
Max
Parameter
Conditions
Units
Boost Switch
BST Switch On-Resistance
Internal Power mosfets
BYP = 5V
12
Ω
Current Limit
Inductor Valley Current Limit, LDO=5V
VIN=16V, LX=0V, High Side mosfet off
High Side
3.0
3.75
1
4.5
5
A
µA
High Side LX Leakage Current
100
65
mΩ
Switch Resistance
Low Side
Note:
(1) See Applications Information for a description of the EN input operation.
5
SC3203
Detailed Application Circuit
Vext
RPG O O D
SC3203
10nF
PG O O D
PG O O D
VO UT @ 3A
BST
LX
L
VO UT
Enable
VIN
EN
RTO P
VIN
49.9
Ω
BYP
VFB
CIN
CTO P
PAD
AG ND
CO UT
1µ
RBO T
Component Selection
VOUT (V)
L (µH)
0.9V
1.0V
1.1V
1.2V
1.5V
1.8V
2.5V
3.3V
5.0V
2.2
2x22uF X5R, 0805 case, 10V
4.7
2x10uF X5R, 0805 case, 10V
COUT (µF)
RTOP (kΩ)
RBOT (kΩ)
CTOP (pF)
39.2
200
22
66.5
200
18
31.6
69.8
27
30.1
51.1
33
24.3
24.9
39
20.5
15
19.6
16.5
4.99
82
26.1
8.66
68
4.75
82
47
6
SC3203
Typical Characteristics
Efficiency vs Load — 1V, 1.5V, 1.8V output
Efficiency vs Load — 2.5V, 3.3V, 5V output
VIN = 12V
VIN = 12V
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
1V
1.5V
1.8V
2.5V
3.3V
5V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Load (A)
Load (A)
Load Regulation - 2.5V, 3.3V, 5V output
Load Regulation - 1V, 1.5V, 1.8V output
VIN = 12V
VIN = 12V
2.0%
1.5%
1.0%
0.5%
0.0%
-0.5%
-1.0%
-1.5%
-2.0%
2.0%
1.5%
1.0%
0.5%
0.0%
-0.5%
-1.0%
-1.5%
-2.0%
2.5V
3.3V
5V
1V
1.5V
1.8V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Load (A)
Load (A)
Switching Frequency vs Load - 1V, 1.5V, 1.8V
Switching Frequency vs Load - 2.5V, 3.3V, 5V
VIN = 12V
VIN = 12V
600
550
500
450
400
350
300
250
200
150
100
50
600
550
500
450
400
350
300
250
200
150
100
50
1V
2.5V
3.3V
5V
1.5V
1.8V
0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Load (A)
Load (A)
7
SC3203
Typical Characteristics (continued)
Load Transient, 0A to 3A to 0A - 3.3VOUT
Load Transient, 1.5A to 3A to 1.5A - 3.3VOUT
VOUT = 3.3V, VIN = 12V
VOUT = 3.3V, VIN = 12V
VOUT (100mV/div)
LOAD (2A/div)
VOUT (100mV/div)
LOAD (2A/div)
LX (20V/div)
LX (20V/div)
Time (200µs/div)
Time (200µs/div)
Load Transient, 0A to 3A to 0A - 1.5VOUT
VOUT = 1.2V, VIN = 12V
Load Transient, 1.5A to 3A to 1.5A - 1.5VOUT
VOUT = 1.2V, VIN = 12V
VOUT (50mV/div)
VOUT (50mV/div)
LOAD (2A/div)
LX (20V/div)
LOAD (2A/div)
LX (20V/div)
Time (1ms/div)
Time (200µs/div)
Startup - EN controlled
VOUT = 3.3V, VIN = 12V
Startup - VIN ramp
VOUT = 3.3V, VIN ramp-up to 12V, EN connected to VIN
EN(5V/div)
VIN, EN(10V/div)
VOUT (2V/div)
VOUT (2V/div)
PGOOD(5V/div)
PGOOD(5V/div)
LX (20V/div)
LX (20V/div)
Time (1ms/div)
Time (1ms/div)
8
SC3203
Typical Characteristics (continued)
Power Save Switching - No Load
Power Save Switching - 100mA Load
VOUT = 3.3V, VIN = 12V, no load
VOUT = 3.3V, VIN = 12V, 100mA load
VOUT (100mV/div)
VOUT (100mV/div)
LX (10V/div)
LX (10V/div)
Time (1ms/div)
Time (4µs/div)
Continuous Mode Switching - 3A Load
VOUT = 3.3V, VIN = 12V, 3A Load
Hiccup Recovery from Over-Current
VOUT = 1.2V, VIN = 12V
VOUT (50mV/div)
LOAD (2A/div)
VOUT (100mV/div)
LX (10V/div)
LX (10V/div)
Time (1µs/div)
Time (20ms/div)
Pre-bias Startup
VOUT = 1.2V, VIN = 12V, Load = 10mA
Shutdown via EN control
VOUT = 1.2V, VIN = 12V, Load = 1A
EN(5V/div)
EN(5V/div)
VOUT (500mV/div)
VOUT (1V/div)
PGOOD(5V/div)
LX (20V/div)
PGOOD(5V/div)
LX (20V/div)
Time (1ms/div)
Time (400µs/div)
9
SC3203
Pin Descriptions
Pin #
Pin Name
Pin Function
Enable input for switching regulator —Pull EN high to enable the LDO and PWM. Connect to PGND to disable
the PWM. Connect a resistor divider from VIN to program the external VIN Under-voltage threshold.
1
EN
Boost Supply pin — Connect a 10nF capacitor between BST and LX to develop the floating voltage for the
high-side gate drive.
2
3
4
5
6
7
8
BST
LX
Switching (phase) node. LX is also the sense point for the Zero Current Detector.
Power input for the High Side Mosfet and for the input to the LDO. VIN is the also sense point for the internal
VIN Under-voltage Lockout and the VIN input for the On-time Generator.
VIN
AGND
BYP
Ground for the internal analog circuitry. Connect this directly to the PAD for the PGND connection.
Bypass pin for the internal 5V LDO which supplies bias voltage for the analog and gate drive circuits— A 1uF
decoupling capacitor is required — The LDO is enabled when the EN pin exceeds typically 1V.
PGOOD
VFB
Open-drain Power Good output.
Feedback input — Connect this pin to a resistor/capacitor divider between the output voltage and AGND.
See the Table on the Typical Application Circuit for recommended values.
Power ground connection. PAD is ground for the power circuits of the IC. The PGND pad should connect
directly to the AGND pin, see Layout Guidelines.
PAD
PGND
10
SC3203
Block Diagram
EN
1
PG O O D
7
BST
2
VIN
LDO
FB
VIN UVLO
5V LDO
LDO
4
VIN
6
BYP
PW M Control and Status
Fault Detect and Hiccup
Reference
Soft Start
3
LX
G ate Drive
Control
LX
LDO
REF
FB
O n-Tim e
G enerator
VFB
8
Com parator
VIN
PG ND
AG ND
PAD
5
Zero Cross Detector
Valley Current Lim it
RILIM
ILIM
11
SC3203
Applications Information
The on-time pulse width is determined by the DC voltage
of LX and by VIN. The pulse width is proportional to the
DC voltage of LX and inversely proportional to the input
voltage. With this adaptive on-time design, the device
automatically anticipates the on-time needed to regulate
VOUT for the present VIN condition. The on-time is approxi-
mated by the following equation:
Synchronous Buck Converter
The SC3203 is a step down synchronous buck DC-DC regu-
lator. The device supports 3A operation at high efficiency
in an SOIC-8 package.The buck regulator employs pseudo-
fixed frequency adaptive on-time control. The 500kHz
operating frequency enables the user to optimize the
design for minimal board space and optimum efficiency.
The adaptive on-time control provides fast transient
response and allows reduced size for the power filter.
9/;
W21
9,1uꢀꢁꢁN+]
Input Voltage Range
The SC3203 operates over the input range of 9V to 16V. The
internal LDO generates a fixed 5V output that provides bias
power for the device.
When the on-time completes, the low-side mosfet Q2
(Figure 1) is turned on. Q2 must stay on for the minimum
off-time of 260nsec, and remains on until one of the fol-
lowing occurs:
Adaptive On-time Control
The pseudo-fixed frequency, adaptive on-time control is
shown in Figure 1. The ripple voltage generated at the
output capacitor is divided down by the feedback resistor
network and used as a PWM ramp signal. When the FB pin
falls to the FB threshold a single on-time pulse for the
high-side mosfet Q1 is triggered.
• VFB falls below the 750mV reference. If this
occurs, Q2 turns off and Q1 turns on for another
high-side on-time.
• If operating in PSAVE mode, Q2 turns off if the
inductor current falls to zero. If the FB pin is
above the 750mV reference, both Q2 and Q1
remain off, and the output current is supplied
by the output capacitor.
VIN
TO N
VLX
VOUT Voltage Selection
VIN
CIN
The output voltage is regulated by comparing the voltage
at the FB pin to the internal 750mV reference voltage, see
Figure 2.
VFB
FB Threshold
Q1
VLX
LX
VOUT
L
Q2
RTOP
VO UT
C TOP
FB
COUT
Rtop
Rbot
CTO P
PG ND
SC3203
RBOT
To FB pin
49.9Ω
Figure 1 — Adaptive On-time Control
Figure 2 — Output Voltage Selection
One-Shot Timer and Operating Frequency
When the FB pin falls to the FB Threshold (750mV), the
device sends a single on-time pulse to the high-side
mosfet.
12
SC3203
Applications Information (continued)
The output voltage is approximated by the following
equation:
Power-save Operation
At light loads the SC3203 enters power-save mode to
improve efficiency. During the low-side on-time, the
internal zero-cross comparator monitors inductor current
via the LX voltage across the low-side mosfet. If the
inductor current falls to zero for 8 consecutive switching
cycles, the controller enters power-save (PSave) mode.
§
·
5723
5%27
¨
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¸
9287 ꢁꢂꢃꢄu ꢀꢀ
¨
©
¹
Note that the Adaptive On-time control regulates the
valley of the FB ripple voltage, not the DC value. In
practice the DC value of FB and VOUT can be slightly
higher than the value predicted by DC equations; this is
easily corrected by reducing the value of RTOP slightly. For
recommended values of the FB components for different
VOUTs, see the Table in the Detailed Application Circuit.
In PSave mode, after the high-side on-time has completed
and the low-side mosfet is on, the low-side is turned off
when the inductor current reaches zero. At this time both
mosfets remain off until VFB drops to the 750mV threshold.
While the mosfets are off, the load is supplied by the
output capacitor. Figure 4 shows power-save operation
at light loads.
Continuous Mode Operation
The SC3203 operates in CCM (Continuous Conduction
Mode) when the load current exceeds 50% of the induc-
tor ripple current (Figure 3). In this mode one of the
power mosfets is always on, with no intentional dead
time other than to avoid cross-conduction. This mode of
operation results in typically 500kHz operation.
Dead tim e varies
according to load
FB Ripple
Voltage
FB threshold
(750m V)
(VFB
)
Inductor
Current
Zero (0A)
FB Ripple
Voltage (VFB
FB threshold
(750m V)
LX ringing
(parasitic LC)
O n-tim e (TO N
)
)
LX = VO UT
LX
LX tri-states when inductor
current reaches zero.
DC Load Current
Inductor
Current
LX on-tim e is triggered when
VFB reaches the FB Threshold.
LX drives to PG ND when
on-tim e is com pleted.
Figure 4 — Power-save Operation
LX on-tim e is triggered when VFB
reaches the FB Threshold.
O n-tim e
(TO N
)
While operating in power-save mode, after each high-side
on-time, the low-side turns on for at least the minimum
260nsec off-time. After this, if the inductor current has
not reached zero and the FB pin falls below the FB thresh-
old, power-save operation is terminated. The controller
immediately generates a high-side on-time and returns
to Continuous Mode Operation, resulting in a rapid
response to large step load increases.
LX
LX drives to PG ND when on-tim e is com pleted.
LX rem ains low (PG ND) until VFB falls to the FB threshold.
Figure 3 — Continuous Mode Operation
13
SC3203
Applications Information (continued)
Smart Power Save Protection
IPEAK
ILO AD
ILIM
Loads or circuits which are connected to more than one
DC source may leak current from a higher voltage into a
lower voltage. If the SC3203 provides the lower voltage
and is operating in PSave mode, this leakage can cause
VOUT to slowly rise during the dead-time when both
mosfets are off. If the leakage is high it can drive VOUT up
to the over-voltage threshold, resulting in a shutdown.
Time
Figure 6 — Valley Current Limit
Smart power save prevents this condition. When the FB
pin exceeds 10% above nominal (exceeds 825mV), the
device immediately disables power-save and turns on the
low-side mosfet. This draws current from VOUT through the
inductor and causes VOUT to fall. When VFB drops back to
the 750mV trip point, a normal on-time switching cycle
begins. Typically the device will return to normal power-
save operation.
Enable Input and VIN UVLO
The EN input is used to enable or disable the switch-
ing regulator. The EN pin has two thresholds. The first
threshold at typically 1V activates the internal LDO. The
second threshold at 1.5V turns on the switcher.
This method prevents a hard OVP shutdown and also
cycles energy from VOUT back to VIN. Figure 5 shows typical
Smart PSave operation.
The EN input also features a programmable input Under-
Voltage Lockout (VIN UVLO). A resistor divider to the
EN pin allows the user to select a VIN point at which the
switcher will turn off. The EN circuit is shown in Figure 7.
VO UT and VFB rise due to leakage
VO UT discharges via inductor
through LX to PG ND.
current flowing into CO UT
Sm art Power Save
Threshold (825m V)
FB threshold
Norm al VO UT ripple
1.5VREF
LX tri-stated
VIN
Hysteresis
100m V
LX
LX drives low (PG ND)
when Sm art PSAVE
threshold is reached
R1
LX drives low (PG ND)
after LX on-tim e and
returns to Power Save
Single LX on-tim e pulse
when FB reaches FB
threshold
EN
EN
Com parator
R2
R EN
Figure 5 — Smart Power Save
O n/O ff
Current Limit Protection
Current limiting is accomplished by sensing the low-side
mosfet current. If this mosfet current exceeds the Current
Limit value (typically 3.75A), the mosfet is kept on. The
controller will not allow another high-side on-time until the
current in the low-side mosfet falls to 3.75A. This method
controls the inductor valley current as shown by ILIM in
Figure 6.
Figure 7 — Enable Input Circuit
14
SC3203
Applications Information (continued)
When the EN input is below 1.5V, the switcher is off.
mosfet Q1 is on and resistor REN is connected to the EN
pin. When the EN pin reaches 1.5V, the comparator out-
put drives high and the switcher is enabled. mosfet Q1
is then switched off, removing REN from the circuit which
immediately raises the voltage at the EN pin and pro-
vides VIN hysteresis. An additional hysteresis of 100mV is
provided internally at the comparator input.
ramps up. If the output reaches normal levels, the PGood
output will switch to high (open circuit) typically 3.3msec
after the EN pin drives high to begin a soft start cycle.
On startup, the FB rising edge threshold for PGood is
750mV -10% (675mV). Once PGood drives high, the FB
pin must fall to 750mV -15% (638mV) before the PGood
output will drive low.
Output Over-Voltage Protection
The equations for selecting the VIN_ON and VIN_OFF
thresholds are shown below. Note that REN has a typical
value of 810kΩ and tolerance of +/- 20%.
OVP (Over-Voltage Protection) becomes active as soon as
the switcher is enabled. The OVP threshold is set at 750mV
+ 20% (900mV). When the FB pin exceeds the 900mV the
low-side mosfet turns on. It will remain on while the low-
side current is negative (remain on while current flows out
of the LX pin). When the low-side current reaches zero or
becomes positive (current into the LX pin), the low-side
mosfet turns off and the LX pin is tri-stated. LX remains
tri-stated until the FB pin falls below the 750mV +15%
(863mV), which starts the Hiccup Mode timer and forces a
32msec delay before a new soft start cycle begins.
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The PGOOD output also drives low when the FB pin
exceeds the OVP threshold.
Soft Start of PWM Regulator
Output Under-Voltage Protection
Soft start is achieved in the PWM regulator by ramping
the internal FB Comparator reference from zero to 750mV.
When the ramp voltage reaches 750mV, the ramp is
ignored and the FB comparator switches over to a fixed
750mV threshold. During soft start the FB pin follows the
internal ramp, which limits the start-up inrush current
and provides a controlled soft start profile for a wide
range of applications. Typical soft start ramp time is
1.8msec.
When the FB pin falls to 75% of its nominal voltage (falls
to 563mV) for eight consecutive clock cycles, the mosfets
are turned off and the controller enters Hiccup Mode
operation. Under-Voltage faults are normally caused by
an output overload; the controller will automatically
recover on the next soft start cycle after the overload is
removed.
Over-Temperature Protection
If the internal temperature rises to 160°C the device will
shut down. The device remains off until the temperature
drops to 150°C, which starts the Hiccup Mode timer and
forces a 32msec delay before a new soft start cycle
begins.
During soft start the regulator turns off the low-side
mosfet during any cycle if the inductor current falls to
zero. This prevents negative inductor current, allowing the
device to start into a pre-biased output with negligible
drooping on the output.
Hiccup Mode (Automatic Fault Recovery)
Power Good Output
The SC3203 includes Hiccup Mode fault protection. If the
switcher output shuts down due to a fault condition, the
device remains off until the fault condition is removed,
which begins the 32ms Hiccup Mode timer. After 32msec
The Power Good (PGood) output is an open-drain indica-
tor. The output is open (high impedance) when the
output is within normal regulation. During startup the
PGood output is held low at AGND while the output
15
SC3203
Applications Information (continued)
has passed a new soft start cycle is attempted. After soft
start, if the output is still in a fault condition the switcher
will again shut down and wait another 32msec before
attempting the next soft-start. The 32msec delay between
soft start cycles reduces power loss and heating in the
power components.
BYP UVLO and POR
The BYP UVLO (Under-Voltage Lock-Out) circuitry inhibits
switching and tri-states the power mosfets until the BYP
voltage rises above 4.0V. An internal POR (Power-On Re-
set) occurs when BYP exceeds 4.0V, which resets the fault
latch and enables the soft start ramp. The SC3203 then
begins a soft start cycle. The PWM will shut off if BYP falls
below 3.7V.
Note that an external VIN UVLO event is treated internally
as a fault condition and triggers the Hiccup Mode feature.
This will lead to a delay on restart when VIN has recovered
to a normal level. The EN pin can rise above the VIN UVLO
threshold but the controller must complete a 32msec
time-out before the switcher will start up. The same delay
also occurs for OVP and Over-Temperature shut down.
Boost Supply
The Boost supply provides bias for the high-side mosfet
driver. Connect a 10nF between Boost and LX. Larger
values of Boost capacitance should not be used, the
Boost driver circuit is designed for 10nF.
BYP Regulator
The SC3203 has an internal regulator that supplies the
bias voltage for the PWM controller. Although this voltage
is available externally, the BYP regulator is designed for
internal use only. The BYP pin requires a 1μF bypass
capacitor. When the EN pin exceeds typically 1V, the BYP
regulator is enabled and goes through a start-up
sequence.
During start-up while the BYP output voltage remains
below 4V, the BYP short-circuit protection is active and
limits the current to typically 35mA. After BYP exceeds
4.0V the LDO operates in voltage regulation mode with
output current limited to typically 100mA (see Figure 9).
BYP Voltage (V)
5V
Voltage regulating with
100m A current lim it
4V
Short-circuit Protection 35m A
Figure 9 — LDO Start-Up
16
SC3203
PCB Layout Guidelines
The optimum layout for the SC3203 is shown in Figure 12.
This layout shows an integrated mosfet buck regulator
with a maximum current of 3A. The total PCB area is
approximately 19.1mm x 11.3mm.
• TheVIN capacitor should be located immediately
next to the VIN and PGND pins, and mounted on
the same side of the pcb. Use wide traces or
copper areas to connect between the capacitor
and the IC pins.
• Connect the AGND pin directly to the PGND pad.
For the RBOT connection to ground, route this to
the AGND pin while avoiding the high-noise
current path between CIN, the PGND PAD, and
COUT.
• Place the inductor near the LX pin and route
directly to the pin using wide, short traces.
• A 1μF BYP capacitor should be located at and
directly connected to the BYP and AGND pins,
and mounted on the same side of the pcb.
• A 0.01 μF Boost capacitor should be located at
and directly connected to the BST and LX pins,
and mounted on the same side of the pcb.
• Using the placement shown below, the power
Ground plane can be a solid area that directly
connects the ground points for CIN, COUT, the
PGND PAD, and AGND pin.
• The FB trace and FB components should not be
placed or routed near the high-noise switching
nodes (LX, BST, VIN). Do not route FB traces
under or near the inductor: magnetic fields from
the inductor can induce switching noise into the
FB signal and cause erratic operation.
EN trace, 2nd layer
FB trace for VOUT sense
2nd layer
PGOOD trace, 2nd layer
Figure 12 — PCB Layout
17
SC3203
Outline Drawing — SOIC8-EP5
DIM ENSIO NS
M ILLIM ETERS
M IN NO M M AX
A
D
E
e
DIM
A
1.25
1.75
0.15
1.65
0.51
0.25
-
-
-
-
-
N
A1 0.00
A2 1.25
E/2
b
c
0.31
0.17
E1
D
E
4.80 4.90 5.00
6.00 BSC
E1 3.80 3.90 4.00
1
2
ccc C
2X N/2 TIPS
e
F
H
1.27 BSC
e/2
B
2.95
3.85
2.70
0.50
-
-
-
2.15
0.25
h
L
L1
N
01
aaa
bbb
ccc
0.40 0.72 1.27
(1.05)
D
aaa C
8
A2
A
0°
8°
-
SEATING
PLANE
0.10
0.25
0.25
A1
bxN
C
bbb
C
A-B D
F
h
1
EXPO SED PAD
h
H
H
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G AUG E
PLANE
L
0.25
01
(L1)
SEE DETAIL A
DETAIL A
SIDE VIEW
NO TES:
1. CO NTRO LLING DIM ENSIO NS ARE IN M ILLIM ETERS (ANG LES IN DEG REES).
-A-
-B-
-H-
TO BE DETERM INED AT DATUM PLANE .
2. DATUM S
AND
3. DIM ENSIO NS "E1" AND "D" DO NO T INCLUDE M O LD FLASH, PRO TRUSIO NS O R G ATE BURRS.
4. THE M EASUREM ENT O F DIM ENSIO N "F" DO ES NO T INCLUDE EXPO SED TIE BAR.
18
SC3203
Land Pattern — SOIC8-EP5
E
D
SO LDER
M ASK
DIM ENSIO NS
DIM M ILLIM ETERS
(5.30)
3.50
5.10
2.60
3.20
1.27
0.60
2.10
7.40
C
D
E
F
G
P
X
Y
Z
(C)
F
G
Y
Z
THERM AL VIA
P
Ø 0.36m m
X
NO TES:
1. CO NTRO LLING DIM ENSIO NS ARE IN M ILLIM ETERS (ANG LES IN DEG REES).
2. THIS LAND PATTERN IS FO R REFERENCE PURPO SE O NLY.
CO NSULT YO UR M ANUFACTURING G RO UP TO ENSURE YO UR
CO M PANY'S M ANUFACTURING G UIDELINES ARE M ET.
3. THERM AL VIAS IN THE LAND PATTERN O F THE EXPO SED PAD SHALL BE
CO NNECTED TO A SYSTEM G RO UND PLANE. FAILURE TO DO SO M AY
CO M PRO M ISE THE THERM AL AND/O R FUNCTIO NAL PERFO RM ANCE O F
THE DEVICE.
4. REFERENCE IPC-SM -782A, SECTIO N 9.1, RLP NO . 300A.
19
SC3203
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20
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