SC4524AEVB [SEMTECH]

28V 2A Step-Down Switching Regulator; 28V 2A降压型开关稳压器
SC4524AEVB
型号: SC4524AEVB
厂家: SEMTECH CORPORATION    SEMTECH CORPORATION
描述:

28V 2A Step-Down Switching Regulator
28V 2A降压型开关稳压器

稳压器 开关
文件: 总18页 (文件大小:741K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
SC4524A  
28V 2A Step-Down Switching Regulator  
POWER MANAGEMENT  
Features  
Description  
Wide input range: 3V to 28V  
2A Output Current  
200kHz to 2MHz Programmable Frequency  
Precision ꢀV Feedback Voltage  
Peak Current-Mode Control  
Cycle-by-Cycle Current Limiting  
Hiccup Overload Protection with Frequency Foldback  
Soft-Start and Enable  
Thermal Shutdown  
The SC4524A is a constant frequency peak current-mode  
step-down switching regulator capable of producing 2A  
output current from an input ranging from 3V to 28V. The  
switching frequency of the SC4524A is programmable  
up to 2MHz, allowing the use of small inductors and  
ceramic capacitors for miniaturization, and high input/  
output conversion ratio. The SC4524A is suitable for  
next generation XDSL modems, high-definition TVs and  
various point of load applications.  
Thermally Enhanced 8-pin SOIC Package  
Fully RoHS and WEEE compliant  
Peak current-mode PWM control employed in the  
SC4524Aachievesfasttransientresponsewithsimpleloop  
compensation. Cycle-by-cycle current limiting and hiccup  
overload protection reduces power dissipation during  
output overload. Soft-start function reduces input start-  
up current and prevents the output from overshooting  
during power-up.  
Applications  
XDSL and Cable Modems  
Set Top Boxes  
Point of Load Applications  
CPE Equipment  
DSP Power Supplies  
LCD and Plasma TVs  
The SC4524A is available in SOIC-8 EDP package.  
Typical Application Circuit  
Efficiency  
D1  
90  
85  
80  
10V – 28V  
V
IN  
1N4148  
C4  
2.2mF  
C1  
0.1mF  
BST  
SW  
IN  
L1  
OUT  
5V/2A  
75  
70  
65  
60  
55  
50  
45  
40  
VIN = 12V  
VIN =24V  
8.2mH  
R4  
SC4524A  
SS/EN  
42.2k  
FB  
GND  
COMP  
ROSC  
D2  
20BQ030  
R6  
10.5k  
C2  
22mF  
C7  
R7  
28.0k  
R5  
18.2k  
10nF  
C8  
10pF  
C5  
2.2nF  
0
0.5  
1
1.5  
2
L1: Coiltronics DR73-8R2  
C2: Murata GRM31CR60J226K  
C4: Murata GRM31CR71H225K  
Load Current (A)  
Figure 1. 1MHz 10V-28V to 5V/2A Step-down Converter  
November 2, 2007  
SC4524A  
Pin Configuration  
Ordering Information  
Device  
Package  
SC4524ASETRT(ꢀ)(2)  
SC4524AEVB  
SOIC-8 EDP  
SW  
IN  
1
2
3
4
8
7
6
5
BST  
Evaluation Board  
FB  
Notes:  
9
ROSC  
GND  
COMP  
SS/EN  
(ꢀ) Available in tape and reel only. A reel contains 2,500 devices.  
(2) Available in lead-free package only. Device is fully WEEE and RoHS  
compliant.  
(8 - Pin SOIC - EDP)  
Marking Information  
yyww=Date code (Example: 0752)  
xxxxx=Semtech Lot No. (Example: E90ꢀ0)  
2
SC4524A  
Absolute Maximum Ratings  
Thermal Information  
Junction to Ambient (ꢀ) ……………………………… 36°C/W  
Junction to Case (ꢀ) ………………………………… 5.5°C/W  
Maximum Junction Temperature……………………… ꢀ50°C  
Storage Temperature ………………………… -65 to +ꢀ50°C  
VIN Supply Voltage ……………………………… -0.3 to 32V  
BST Voltage ……………………………………………… 42V  
BST Voltage above SW …………………………………… 36V  
SS Voltage ……………………………………………-0.3 to 3V  
Lead Temperature (Soldering) ꢀ0 sec ………………… 300°C  
FB Voltage …………………………………………… -0.3 to VIN  
SW Voltage ………………………………………… -0.6 to VIN  
SW Transient Spikes (ꢀ0ns Duration)……… -2.5V to VIN +ꢀ.5V  
Peak IR Reflow Temperature …………………………. 260°C  
ESD Protection Level(2) ………………………………… 2000V  
Recommended Operating Conditions  
Input Voltage Range ……………………………… 3V to 28V  
Maximum Output Current ……………………………… 2A  
Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the  
Electrical Characteristics section is not recommended.  
NOTES-  
(ꢀ) Calculated from package in still air, mounted to 3x 4.5, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD5ꢀ standards.  
(2) Tested according to JEDEC standard JESD22-Aꢀꢀ4-B.  
Electrical Characteristics  
Unless otherwise noted, VIN = ꢀ2V, VBST = ꢀ5V, VSS = 2.2V, -40°C < TA = TJ < ꢀ25°C, ROSC = ꢀ2.ꢀkΩ.  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
Input Supply  
Input Voltage Range  
3
28  
V
VIN Start Voltage  
VIN Rising  
2.70  
2.82  
225  
2
2.95  
V
VIN Start Hysteresis  
mV  
mA  
µA  
VIN Quiescent Current  
VIN Quiescent Current in Shutdown  
Error Amplifier  
VCOMP = 0 (Not Switching)  
VSS/EN = 0, VIN = ꢀ2V  
2.6  
50  
40  
Feedback Voltage  
0.980  
ꢀ.000  
0.005  
-ꢀ70  
280  
60  
ꢀ.020  
-340  
V
%/V  
nA  
µΩ-ꢀ  
dB  
Feedback Voltage Line Regulation  
FB Pin Input Bias Current  
Error Amplifier Transconductance  
Error Amplifier Open-loop Gain  
COMP Pin to Switch Current Gain  
COMP Maximum Voltage  
COMP Source Current  
COMP Sink Current  
VIN = 3V to 28V  
VFB = ꢀV, VCOMP = 0.8V  
8
A/V  
V
2.4  
VFB = 0.9V  
ꢀ7  
VFB = 0.8V, VCOMP = 0.8V  
VFB = ꢀ.2V, VCOMP = 0.8V  
µA  
25  
Internal Power Switch  
Switch Current Limit  
(Note ꢀ)  
2.6  
3.3  
4.3  
A
Switch Saturation Voltage  
ISW = -2.6A  
250  
400  
mV  
3
SC4524A  
Electrical Characteristics (Cont.)  
Unless otherwise noted, VIN = ꢀ2V, VBST = ꢀ5V, VSS = 2.2V, -40°C < TA = TJ < ꢀ25°C, ROSC = ꢀ2.ꢀkΩ.  
Parameter  
Conditions  
Min  
Typ  
ꢀ35  
ꢀ00  
Max  
Units  
ns  
Minimum Switch On-time  
Minimum Switch Off-time  
Switch Leakage Current  
Minimum Bootstrap Voltage  
BST Pin Current  
ꢀ50  
ꢀ0  
ns  
µA  
V
ISW = -2.6A  
ISW = -2.6A  
ꢀ.8  
60  
2.3  
95  
mA  
Oscillator  
ROSC = ꢀ2.ꢀkΩ  
ROSC = 93.ꢀkΩ  
ꢀ.04  
240  
ꢀꢀ0  
50  
ꢀ.3  
300  
230  
ꢀ00  
ꢀ.56  
360  
350  
ꢀ70  
MHz  
kHz  
Switching Frequency  
Foldback Frequency  
ROSC = ꢀ2.ꢀkΩ, VFB = 0  
ROSC = 93.ꢀkΩ, VFB = 0  
kHz  
Soft Start and Overload Protection  
SS/EN Shutdown Threshold  
0.2  
ꢀ.0  
0.3  
ꢀ.ꢀ3  
ꢀ.7  
0.4  
ꢀ.3  
V
V
SS/EN Switching Threshold  
VFB = 0 V  
VSS/EN = 0 V  
VSS/EN = ꢀ.5 V  
Soft-start Charging Current  
µA  
ꢀ.2  
2.0  
2.8  
Soft-start Discharging Current  
Hiccup Arming SS/EN Voltage  
Hiccup SS/EN Overload Threshold  
Hiccup Retry SS/EN Voltage  
ꢀ.5  
µA  
V
2.ꢀ5  
ꢀ.9  
VSS/EN Rising  
VSS/EN Falling  
VSS/EN Falling  
V
0.6  
ꢀ.0  
ꢀ.2  
V
Over Temperature Protection  
Thermal Shutdown Temperature  
Thermal Shutdown Hysteresis  
ꢀ65  
ꢀ0  
°C  
°C  
Note ꢀ: Switch current limit does not vary with duty cycle.  
4
SC4524A  
Pin Descriptions  
SO-8  
Pin Name  
Pin Function  
Emitter of the internal NPN power transistor. Connect this pin to the inductor, the freewheeling diode and the  
bootstrap capacitor.  
SW  
Power supply to the regulator. It is also the collector of the internal NPN power transistor. It must be closely by-  
passed to the ground plane.  
2
IN  
3
4
ROSC  
GND  
An external resistor from this pin to ground sets the oscillator frequency.  
Ground pin  
Soft-start and regulator enable pin. A capacitor from this pin to ground provides soft-start and overload hiccup  
functions. Hiccup can be disabled by overcoming the internal soft-start discharging current with an external pull-  
up resistor connected between the SS/EN and the IN pins. Pulling the SS/EN pin below 0.2V completely shuts off  
the regulator to low current state.  
5
SS/EN  
The output of the internal error amplifier. The voltage at this pin controls the peak switch current. A RC compensa-  
tion network at this pin stabilizes the regulator.  
6
7
8
9
COMP  
FB  
The inverting input of the error amplifier. If VFB falls below 0.8V, then the switching frequency will be reduced to  
improve short-circuit robustness (see Applications Information for details).  
Supply pin to the power transistor driver. Tie to an external diode-capacitor bootstrap circuit to generate drive  
voltage higher than VIN in order to fully enhance the internal NPN power transistor.  
BST  
The exposed pad serves as a thermal contact to the circuit board. It is to be soldered to the ground plane of the  
PC board.  
Exposed Pad  
5
SC4524A  
Block Diagram  
IN  
2
SLOPE  
COMP  
COMP  
6
+
+
S
ISEN  
-
+
6.1mW  
FB  
7
-
+
+
+
ILIM  
OC  
20mV  
EA  
-
BST  
8
V1  
+
S
R
PWM  
-
Q
POWER  
TRANSISTOR  
FREQUENCY  
FOLDBACK  
CLK  
ROSC  
3
OSCILLATOR  
1.23V  
+
1
A1  
SW  
-
R
R
SS/EN  
5
SOFT-START  
AND  
OVERLOAD  
HICCUP  
GND  
4
1V  
1.9V  
REFERENCE  
& THERMAL  
SHUTDOWN  
FAULT  
CONTROL  
Figure 2. SC4524A Block Diagram  
-
1.9V  
B4  
+
S
R
I
C
2mA  
Q
OVERLOAD  
B1  
SS/EN  
B2  
1V/2.15V  
FAULT  
S
R
OC  
I
_
Q
D
3.5mA  
PWM  
B3  
Figure 3. Soft-start and Overload Hiccup Control Circuit  
6
SC4524A  
Typical Characteristics  
Feedback Voltage vs Temperature  
Efficiency  
Efficiency  
90  
85  
80  
75  
70  
65  
60  
55  
50  
45  
40  
90  
1.02  
1.01  
1.00  
0.99  
0.98  
0.97  
VO=5V  
VIN =12V  
85  
VO=3.3V  
VO=5V  
80  
VO=2.5V  
VO=3.3V  
VO=2.5V  
75  
70  
VO=1.5V  
65  
60  
55  
1MHz, VIN =12V  
1MHz, VIN =24V  
D2 =20BQ030  
50  
D2=20BQ030  
45  
40  
0
0.5  
1
1.5  
2
-50 -25  
0
25  
50 75 100 125  
0
0.5  
1
1.5  
2
Temperature (oC)  
Load Current (A)  
Load Current (A)  
Frequency Setting Resistor  
vs Frequency  
Foldback Frequency vs VFB  
Frequency vs Temperature  
1000  
100  
10  
1.25  
1
1.2  
1.1  
1.0  
0.9  
0.8  
VIN =12V  
ROSC=93.1k  
ROSC=93.1k  
0.75  
0.5  
0.25  
0
ROSC=12.1k  
TA =25oC  
ROSC=12.1k  
1
0
0.5  
1
1.5  
2
2.5  
0.0  
0.2  
0.4  
0.6  
0.8  
1.0  
-50 -25  
0
25 50  
75 100 125  
Temperature (oC)  
VFB (V)  
Frequency (MHz)  
Switch Saturation Voltage  
vs Switch Current  
Switch Current Limit vs Temperature  
BST Pin Current vs Switch Current  
100.0  
75.0  
50.0  
25.0  
0.0  
4.5  
300  
250  
200  
150  
100  
50  
VIN =12V  
VBST =15V  
4.0  
3.5  
3.0  
2.5  
-40oC  
-40oC  
125oC  
125oC  
25oC  
-50 -25  
0
25 50  
75 100 125  
0
0.5  
1
1.5  
2
2.5  
3
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
Temperature (oC)  
Switch Current (A)  
Switch Current (A)  
7
SC4524A  
Typical Characteristics (Cont.)  
VIN Supply Current  
VIN Thresholds vs Temperature  
VIN Shutdown Current vs VIN  
vs Soft-Start Voltage  
100  
80  
60  
40  
20  
0
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
VSS = 0  
125oC  
-40oC  
Start  
2.9  
2.8  
2.7  
2.6  
2.5  
2.4  
-40oC  
125oC  
UVLO  
25  
0
5
10  
15  
VIN (V)  
20  
25  
30  
0
0.5  
1
1.5  
2
-50 -25  
0
50  
75 100 125  
Temperature (oC)  
VSS (V)  
Soft-Start Charging Current  
vs Soft-Start Voltage  
SS Shutdown Threshold  
vs Temperature  
VIN Quiescent Current vs VIN  
0.0  
-0.5  
-1.0  
-1.5  
-2.0  
-2.5  
-3.0  
0.40  
0.35  
0.30  
0.25  
0.20  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
125oC  
-40oC  
125oC  
-40oC  
VCOMP = 0  
-50 -25  
0
25  
50  
75 100 125  
0
0.5  
1
1.5  
2
0
5
10  
15  
20  
25  
30  
Temperature (oC)  
VSS (V)  
VIN (V)  
8
SC4524A  
Applications Information  
Operation  
When the SS/EN pin is released, the soft-start capacitor  
is charged with an internal ꢀ.6µA current source (not  
shown in Figure 3). As the SS/EN voltage exceeds 0.4V,  
the internal bias circuit of the SC4524A turns on and the  
SC4524A draws 2mA from VIN. The ꢀ.6µA charging current  
turns off and the 2µA current source IC in Figure 3 slowly  
charges the soft-start capacitor.  
The SC4524A is a constant-frequency, peak current-  
mode, step-down switching regulator with an integrated  
28V, 2.6A power NPN transistor. Programmable switching  
frequency makes the regulator design more flexible. With  
the peak current-mode control, the double reactive poles  
of the output LC filter are reduced to a single real pole by  
the inner current loop. This simplifies loop compensation  
and achieves fast transient response with a simple Type-2  
compensation network.  
The error amplifier EA in Figure 2 has two non-inverting  
inputs. The non-inverting input with the lower voltage  
predominates. One of the non-inverting inputs is biased  
to a precision ꢀV reference and the other non-inverting  
input is tied to the output of the amplifier A. Amplifier Aꢀ  
producesanoutputV=2(VSS/EN -ꢀ.23V).ViszeroandCOMP  
is forced low when VSS/EN is below ꢀ.23V. During start up,  
the effective non-inverting input of EA stays at zero until  
the soft-start capacitor is charged above ꢀ.23V. Once VSS/EN  
exceeds ꢀ.23V, COMP is released. The regulator starts to  
switch whenVCOMP rises above 0.4V. If the soft-start interval  
is made sufficiently long, then the FB voltage (hence the  
output voltage) will track Vduring start up. VSS/EN must be  
at least ꢀ.83V for the output to achieve regulation. Proper  
soft-start prevents output overshoot. Current drawn from  
the input supply is also well controlled.  
As shown in Figure 2, the switch collector current is  
sensed with an integrated 6.ꢀmW sense resistor. The  
sensed current is summed with a slope-compensating  
ramp before it is compared with the transconductance  
error amplifier (EA) output. The PWM comparator trip  
point determines the switch turn-on pulse width. The  
current-limit comparator ILIM turns off the power switch  
when the sensed signal exceeds the 20mV current-limit  
threshold.  
Driving the base of the power transistor above the  
input power supply rail minimizes the power transistor  
saturation voltage and maximizes efficiency. An external  
bootstrap circuit (formed by the capacitor Cand the  
diode Din Figure ꢀ) generates such a voltage at the BST  
pin for driving the power transistor.  
Overload / Short-Circuit Protection  
Table  
2 lists various fault conditions and their  
corresponding protection schemes in the SC4524A.  
Shutdown and Soft-Start  
Table 2: Fault conditions and protections  
The SS/EN pin is a multiple-function pin. An external  
capacitor (4.7nF to 22nF) connected from the SS pin to  
ground sets the soft-start and overload shutoff times of  
the regulator (Figure 3). The effect of VSS/EN on the SC4524A  
is summarized in Table ꢀ.  
Condition  
Fault  
Protective Action  
Cycle-by-cycle limit at  
IL>ILimit, VFB>0.8V  
Over current  
programmed frequency  
Cycle-by-cycle limit with  
IL>ILimit, VFB<0.8V  
Over current  
frequency foldback  
Shutdown, then retry  
VSS/EN Falling  
SS/EN<1.9V  
Persistent over current  
or short circuit  
(Hiccup)  
Table 1: SS/EN operation modes  
Tj>160C  
Over temperature  
Shutdown  
SS/EN  
<0.2V  
Mode  
Supply Current  
18uA @ 5Vin  
2mA  
Shutdown  
As summarized in Table ꢀ, overload shutdown is disabled  
during soft-start (VSS/EN<2.ꢀV). In Figure 3, the reset input of  
the overload latch B2 will remain high if the SS/EN voltage  
is below 2.ꢀV. Once the soft-start capacitor is charged  
above 2.ꢀV, the output of the Schmitt trigger Bgoes high,  
the reset input of B2 goes low and hiccup becomes armed.  
0.4V to 1.23V  
1.23V to 2.1V  
>2.1V  
Not switching  
Switching & hiccup disabled  
Switching & hiccup armed  
Load dependent  
Pulling the SS/EN pin below 0.2V shuts off the regulator  
and reduces the input supply current to ꢀ8µA (VIN = 5V).  
9
SC4524A  
Applications Information (Cont.)  
As the load draws more current from the regulator, the  
current-limit comparator ILIM (Figure 2) will eventually  
limit the switch current on a cycle-by-cycle basis. The  
over-current signal OC goes high, setting the latch B3. The  
soft-start capacitor is discharged with (ID - IC) (Figure 3). If  
the inductor current falls below the current limit and the  
PWM comparator instead turns off the switch, then latch  
B3 will be reset and IC will recharge the soft-start capacitor.  
If over-current condition persists or OC becomes asserted  
more often than PWM over a period of time, then the  
soft-start capacitor will be discharged below ꢀ.9V. At this  
juncture, comparator B4 sets the overload latch B2. The  
soft-start capacitor will be continuously discharged with  
(ID - IC). The COMP pin is immediately pulled to ground. The  
switching regulator is shut off until the soft-start capacitor  
is discharged below ꢀ.0V. At this moment, the overload  
latch is reset. The soft-start capacitor is recharged and  
the converter again undergoes soft-start. The regulator  
will go through soft-start, overload shutdown and restart  
until it is no longer overloaded.  
down switching regulator in continuous-conduction  
mode (CCM) is given by  
VO + VD  
V + VD VCESAT  
D =  
(2)  
IN  
where VCESAT is the switch saturation voltage and VD is  
voltage drop across the rectifying diode.  
In peak current-mode control, the PWM modulating  
ramp is the sensed current ramp of the power switch.  
This current ramp is absent unless the switch is turned  
on. The intersection of this ramp with the output of the  
voltage feedback error amplifier determines the switch  
pulse width. The propagation delay time required to  
immediately turn off the switch after it is turned on is the  
minimum controllable switch on time (TON(MIN)).  
Closed-loop measurement shows that the SC4524A  
minimum on time is about ꢀ35ns at room temperature  
(Figure 4). If the required switch on time is shorter than  
the minimum on time, the regulator will either skip cycles  
or it will jitter.  
If the FB voltage falls below 0.8V because of output  
overload, then the switching frequency will be reduced.  
Frequency foldback helps to limit the inductor current  
when the output is hard shorted to ground.  
Minimum On Time vs Temperature  
200  
190  
180  
170  
160  
150  
140  
130  
120  
110  
100  
VO =1.5V  
1MHz  
During normal operation, the soft-start capacitor is  
charged to 2.4V.  
Setting the Output Voltage  
The regulator output voltage is set with an external  
resistive divider (Figure ꢀ) with its center tap tied to the  
FB pin. For a given R6 value, R4 can be found by  
VO  
6   
-50 -25  
0
25  
50  
75 100 125  
R4 = R  
1  
(ꢀ)  
1.0V  
Temperature (OC)  
Setting the Switching Frequency  
Figure 4. Variation of Minimum On Time  
with Ambient Temperature  
The switching frequency of the SC4524A is set with an  
external resistor from the ROSC pin to ground.  
To allow for transient headroom, the minimum operating  
switch on time should be at least 20% to 30% higher than  
the worst-case minimum on time.  
Minimum On Time Consideration  
The operating duty cycle of a non-synchronous step-  
ꢀ0  
SC4524A  
Applications Information (Cont.)  
Minimum Off Time Limitation  
The input capacitance must also be high enough to keep  
input ripple voltage within specification. This is important  
in reducing the conductive EMI from the regulator. The  
input capacitance can be estimated from  
The PWM latch in Figure 2 is reset every cycle by the  
clock. The clock also turns off the power transistor to  
refresh the bootstrap capacitor. This minimum off time  
limits the attainable duty cycle of the regulator at a given  
switching frequency. The measured minimum off time is  
ꢀ00ns typically. If the required duty cycle is higher than  
the attainable maximum, then the output voltage will not  
be able to reach its set value in continuous-conduction  
mode.  
IO  
CIN  
>
(6)  
4 ⋅ DV FSW  
IN  
where DVIN is the allowable input ripple voltage.  
Multi-layer ceramic capacitors, which have very low ESR  
(a few mW) and can easily handle high RMS ripple current,  
are the ideal choice for input filtering. A single 4.7µF  
X5R ceramic capacitor is adequate for 500kHz or higher  
switching frequency applications, and ꢀ0µF is adequate  
for 200kHz to 500kHz switching frequency. For high  
voltage applications, a small ceramic (ꢀµF or 2.2µF) can be  
placed in parallel with a low ESR electrolytic capacitor to  
satisfy both the ESR and bulk capacitance requirements.  
Inductor Selection  
The inductor ripple current for a non-synchronous step-  
down converter in continuous-conduction mode is  
(VO + VD ) (1 D)  
DIL =  
(3)  
FSW L1  
where FSW is the switching frequency and Lis the  
inductance.  
Output Capacitor  
The output ripple voltage DVO of a buck converter can be  
An inductor ripple current between 20% to 50% of the  
maximum load current gives a good compromise among  
efficiency, cost and size. Re-arranging Equation (3) and  
assuming 35% inductor ripple current, the inductor is  
given by  
expressed as  
1
DVO = DIL ESR +  
(7)  
8 FSW CO  
where CO is the output capacitance.  
(VO + VD ) (1 D)  
35% IO FSW  
L1 =  
(4)  
Since the inductor ripple current DIL increases as D  
decreases (Equation (3)), the output ripple voltage is  
therefore the highest when VIN is at its maximum.  
If the input voltage varies over a wide range, then choose  
Lbased on the nominal input voltage. Always verify  
converter operation at the input voltage extremes.  
A ꢀ0µF to 47µF X5R ceramic capacitor is found adequate  
for output filtering in most applications. Ripple current  
in the output capacitor is not a concern because the  
inductor current of a buck converter directly feeds CO,  
resulting in very low ripple current. Avoid using Z5U  
and Y5V ceramic capacitors for output filtering because  
these types of capacitors have high temperature and high  
voltage coefficients.  
The peak current limit of SC4524A power transistor is at  
least 2.6A. The maximum deliverable load current for the  
SC4524A is 2.6A minus one half of the inductor ripple  
current.  
Input Decoupling Capacitor  
The input capacitor should be chosen to handle the RMS  
ripple current of a buck converter. This value is given by  
Freewheeling Diode  
Use of Schottky barrier diodes as freewheeling rectifiers  
reduces diode reverse recovery input current spikes,  
easing high-side current sensing in the SC4524A. These  
IRMS _ CIN = IO D (1 D)  
(5)  
ꢀꢀ  
SC4524A  
Applications Information (Cont.)  
diodes should have an average forward current rating  
at least 2A and a reverse blocking voltage of at least a  
few volts higher than the input voltage. For switching  
regulators operating at low duty cycles (i.e. low output  
voltage to input voltage conversion ratios), it is beneficial  
to use freewheeling diodes with somewhat higher  
average current ratings (thus lower forward voltages). This  
is because the diode conduction interval is much longer  
than that of the transistor. Converter efficiency will be  
improved if the voltage drop across the diode is lower.  
Minimum Bootstrap Voltage  
vs Temperature  
2.2  
2.1  
2.0  
1.9  
1.8  
1.7  
1.6  
I
SW = -2.6A  
The freewheeling diode should be placed close to the  
SW pin of the SC4524A to minimize ringing due to trace  
inductance. 20BQ030 (International Rectifier), B230A  
(Diodes Inc.), SSꢀ3, SS23 (Vishay), CMSHꢀ-40M, CMSHꢀ-  
40ML and CMSH2-40M (Central-Semi.) are all suitable.  
-50 -25  
0
25 50  
75 100 125  
Temperature (oC)  
Figure 5. Typical Minimum Bootstrap Voltage required  
to Saturate Transistor (ISW= -2.6A).  
The freewheeling diode should be placed close to the SW  
pin of the SC4524A on the PCB to minimize ringing due to  
trace inductance.  
D1  
BST  
C1  
VIN  
VOUT  
Bootstrapping the Power Transistor  
SW  
IN  
SC4524A  
D
2
The typical minimum BST-SW voltage required to fully  
saturate the power transistor is shown in Figure 5, which  
is about ꢀ.96V at room temperature.  
GND  
(a)  
D3  
D1  
The BST-SW voltage is supplied by a bootstrap circuit  
powered from either the input or the output of the  
converter (Figure 6). To maximize efficiency, tie the  
bootstrap diode to the converter output if VO>2.5V.  
Since the bootstrap supply current is proportional to the  
converter load current, using a lower voltage to power  
the bootstrap circuit reduces driving loss and improves  
efficiency.  
BST  
C1  
VIN  
VOUT  
SW  
IN  
SC4524A  
D
2
GND  
(b)  
Figure 6. Methods of Bootstrapping the SC4524A  
For the bootstrap circuit, a fast switching PN diode (such  
as ꢀN4ꢀ48 or ꢀN9ꢀ4) and a small (0.ꢀµF – 0.47µF) ceramic  
capacitor is sufficient for most applications. When  
bootstrapping from 2.5V to 3.0V output voltages, use a  
low forward drop Schottky diode (BAT-54 or similar) for  
D. When bootstrapping from high input voltages (>20V),  
reduce the maximum BST voltage by connecting a Zener  
diode (D3) in series with D.  
Loop Compensation  
The goal of compensation is to shape the frequency  
response of the converter so as to achieve high DC  
accuracy and fast transient response while maintaining  
loop stability.  
ꢀ2  
SC4524A  
Applications Information (Cont.)  
CONTROLLER AND SCHOTTKY DIODE  
Including the voltage divider (R4 and R6), the control to  
feedback transfer function is found and plotted in Figure  
8 as the converter gain.  
Io  
Rs  
CA  
REF  
+
Vc  
PWM  
MODULATOR  
EA  
FB  
-
L1  
Vo  
Since the converter gain has only one dominant pole at  
low frequency, a simple Type-2 compensation network  
is sufficient for voltage loop compensation. As shown in  
Figure 8, the voltage compensator has a low frequency  
integrator pole, a zero at FZꢀ, and a high frequency pole  
at FPꢀ. The integrator is used to boost the gain at low  
frequency. The zero is introduced to compensate the  
excessive phase lag at the loop gain crossover due to the  
integrator pole (-90deg) and the dominant pole (-90deg).  
The high frequency pole nulls the ESR zero and attenuates  
high frequency noise.  
Vramp  
SW  
COMP  
R4  
R6  
Co  
C5  
C8  
R7  
Resr  
Figure 7. Block diagram of control loops  
The block diagram in Figure 7 shows the control loops of a  
buck converter with the SC4524A. The inner loop (current  
loop) consists of a current sensing resistor (Rs=6.ꢀmW)  
and a current amplifier (CA) with gain (GCA=28). The outer  
loop (voltage loop) consists of an error amplifier (EA), a  
PWM modulator, and a LC filter.  
Since the current loop is internally closed, the remaining  
task for the loop compensation is to design the voltage  
compensator (C5, R7, and C8).  
For a converter with switching frequency FSW, output  
inductance L, output capacitance CO and loading R, the  
control (VC) to output (VO) transfer function in Figure 7 is  
given by:  
GPWM (1 + sRESRCO )  
Vo  
=
(8)  
Figure 8. Bode plots for voltage loop design  
Vc (1 + s /ωp )(1 + s /ωn Q + s2 /ωn2 )  
This transfer function has a finite DC gain  
Therefore, the procedure of the voltage loop design for  
the SC4524A can be summarized as:  
R
GPWM  
,
GCA RS  
(ꢀ) Plot the converter gain, i.e. control to feedback transfer  
function.  
an ESR zero FZ at  
(2) Select the open loop crossover frequency, FC, between  
ꢀ0% and 20% of the switching frequency. At FC, find the  
required compensator gain, AC. In typical applications with  
ceramic output capacitors, the ESR zero is neglected and  
the required compensator gain at FC can be estimated by  
1
ωZ =  
,
RESRCO  
a dominant low-frequency pole FP at  
1
ωp ≈  
,
RCO  
VFB  
1
1
(9)  
AC = − 20 log  
GCARS 2πFCCO VO  
and double poles at half the switching frequency.  
ꢀ3  
SC4524A  
Applications Information (Cont.)  
capacitor, the main power switch and the freewheeling  
diode carry pulse current (Figure 9). For jitter-free  
operation,thesizeoftheloopformedbythesecomponents  
should be minimized. Since the power switch is already  
integrated within the SC4524A, connecting the anode of  
the freewheeling diode close to the negative terminal of  
the input bypass capacitor minimizes size of the switched  
current loop. The input bypass capacitor should be placed  
close to the IN pin. Shortening the traces of the SW and  
BST nodes reduces the parasitic trace inductance at these  
nodes. This not only reduces EMI but also decreases  
switching voltage spikes at these nodes.  
(3) Place the compensator zero, FZꢀ, between ꢀ0% and  
20% of the crossover frequency, FC.  
(4) Use the compensator pole, FPꢀ, to cancel the ESR zero,  
FZ.  
(5) Then, the parameters of the compensation network  
can be calculated by  
A
C
20  
10  
R7 =  
C5 =  
C8 =  
gm  
1
2πFZ1 R7  
1
The exposed pad should be soldered to a large ground  
plane as the ground copper acts as a heat sink for the  
device. To ensure proper adhesion to the ground plane,  
avoid using vias directly under the device.  
2πFP1 R7  
where gm=0.28mA/V is the EA gain of the SC4524A.  
Example: Determine the voltage compensator for an  
800kHz, ꢀ2V to 3.3V/2A converter with 22uF ceramic  
output capacitor.  
V
IN  
Choose a loop gain crossover frequency of 80kHz, and  
place voltage compensator zero and pole at FZꢀ=ꢀ6kHz  
(20% of FC), and FPꢀ=600kHz. From Equation (9), the  
required compensator gain at FC is  
V
OUT  
1
1
1.0  
3.3  
AC = − 20 log  
=15.9dB  
28 6.1 103 2π ⋅ 80 103 22 106  
Z
L
Then the compensator parameters are  
1015.9  
20  
R7 =  
C5 =  
= 22.3k  
0.28 103  
1
Figure 9. Heavy lines indicate the critical pulse  
current loop. The inductance of this  
loop should be minimized.  
= 0.45nF  
=12pF  
2π 16 103 22.1 103  
1
C8 =  
2π600 103 22.1 103  
Select R7=22.ꢀk, C5=0.47nF, and C8=ꢀ0pF for the design.  
Compensator parameters for various typical applications  
are listed in Table 4. A MathCAD program is also available  
upon request for detailed calculation of the compensator  
parameters.  
PCB Layout Considerations  
In a step-down switching regulator, the input bypass  
ꢀ4  
SC4524A  
Recommended Component Parameters in Typical Applications  
Table 4 lists the recommended inductance (L) and compensation network (R7, C5, C8) for common input and output  
voltages. The inductance is determined by assuming that the ripple current is 35% of load current IO. The compensator  
parameters are calculated by assuming a 22mF low ESR ceramic output capacitor and a loop gain crossover frequency  
of FSW/ꢀ0.  
Table 4. Recommended inductance (L1) and compensator (R7, C5, C8)  
Typical Applications  
Recommended Parameters  
Vin(V)  
Vo(V)  
Io(A)  
Fsw(kHz)  
C2(uF)  
L1(uH)  
15  
8.2  
15  
8.2  
22  
10  
R7(k)  
C5(nF)  
C8(pF)  
1
2
1
2
1
2
1.5  
2.5  
3.3  
300  
500  
4.32  
2.2  
12.4  
15  
1.0  
0.82  
500  
1000  
500  
1000  
500  
1000  
500  
1000  
500  
22  
15  
15  
6.8  
33  
15  
15  
8.2  
33  
22  
20  
43.2  
20  
0.68  
0.47  
0.68  
0.47  
0.68  
0.47  
0.68  
0.47  
0.68  
0.47  
0.68  
0.47  
1
2
1
2
1
2
5
24  
22  
10  
43.2  
35.7  
63.4  
35.7  
63.4  
43.2  
84.5  
43.2  
84.5  
7.5  
10  
1000  
500  
1000  
15  
10  
ꢀ5  
SC4524A  
Typical Application Schematics  
D1  
D3  
24V  
V
IN  
18V Zener  
1N4148  
C4  
4.7mF  
C1  
0.33mF  
BST  
SW  
IN  
L1  
OUT  
8.2mH  
1.5V/2A  
R4  
SC4524A  
SS/EN  
33.2k  
FB  
GND  
COMP  
ROSC  
D2  
20BQ030  
R6  
66.5k  
C2  
22mF  
C7  
10nF  
R7  
4.32k  
R5  
90.9k  
C8  
22pF  
C5  
2.2nF  
L1: Coiltronics DR73-8R2  
C2: Murata GRM31CR60J226K  
C4: Murata GRM32ER71H475K  
Figure 10. 300kHz 24V to 1.5V/2A Step-down Converter  
D1  
10V – 26V  
V
IN  
1N4148  
C1  
0.1mF  
C4  
4.7mF  
BST  
SW  
IN  
L1  
OUT  
8.2mH  
3.3V/2A  
R4  
3.65k  
SC4524A  
SS/EN  
FB  
GND  
COMP  
ROSC  
D2  
SS23  
R6  
1.58k  
C2  
22mF  
C7  
10nF  
R7  
R5  
23.7k  
C8  
22pF  
13.0k  
C5  
2.2nF  
L1: Coiltronics DR73-8R2  
C2: Murata GRM31CR60J226M  
C4: Murata GRM32ER71H475K  
Figure 11. 800kHz 10V-26V to 3.3V/2A Step-down Converter  
ꢀ6  
SC4524A  
Typical Performance Characteristics  
(For A 24V to 5V/2A Step-down Converter with 1MHz Switching Frequency)  
6
5
24V Input (10V/DIV)  
4
3
2
1
0
5V Output (2V/DIV)  
SS Voltage (1V/DIV)  
0
0.5  
1
1.5  
2
2.5  
3
10ms/DIV  
Load Current (A)  
Figure 12(b). VIN Start up Transient (IO=2A)  
Figure 12(a). Load Characteristic  
5V Output Short (5V/DIV)  
5V Output Response (500mV/DIV, AC Coupling)  
Inductor Current (1A/DIV)  
Retry Inductor Current (2A/DIV)  
SS Voltage (2V/DIV)  
40us/DIV  
20ms/DIV  
Figure 12(c). Load Transient Response  
(IO= 0.3A to 2A)  
Figure 12(d). Output Short Circuit (Hiccup)  
ꢀ7  
SC4524A  
Outline Drawing - SOIC-8 EDP  
A
D
E
e
DIMENSIONS  
INCHES MILLIMETERS  
N
DIM  
A
MIN  
MAX MIN  
.069 1.35  
.005 0.00  
.065 1.25  
.020 0.31  
.010 0.17  
MAX  
1.75  
0.13  
1.65  
0.51  
0.25  
NOM  
NOM  
-
-
-
-
-
-
-
-
-
-
.053  
A1 .000  
2X E/2  
A2 .049  
E1  
b
c
.012  
.007  
D
.189 .193 .197 4.80 4.90 5.00  
1
2
E1 .150 .154 .157 3.80 3.90 4.00  
E
e
F
H
.236 BSC  
.050 BSC  
6.00 BSC  
1.27 BSC  
ccc  
2X N/2 TIPS  
C
e/2  
.116 .120 .130 2.95 3.05 3.30  
.085 .095 .099 2.15 2.41 2.51  
B
-
-
h
.010  
.020 0.25  
0.50  
L
L1  
N
01  
aaa  
bbb  
ccc  
.016 .028 .041 0.40 0.72 1.04  
D
(.041)  
(1.05)  
8
-
8
-
aaa  
C
0°  
8°  
0°  
8°  
A2  
A
.004  
.010  
.008  
0.10  
0.25  
0.20  
SEATING  
PLANE  
C
A1  
bxN  
bbb  
C
A-B D  
h
F
EXPOSED PAD  
h
H
H
c
GAGE  
PLANE  
0.25  
L
01  
(L1)  
DETAIL  
A
SEE DETAIL  
A
SIDE VIEW  
NOTES:  
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).  
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-  
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS  
OR GATE BURRS.  
REFERENCE JEDEC STD MS-012, VARIATION BA.  
4.  
Land Pattern - SOIC-8 EDP  
E
SOLDER MASK  
D
DIMENSIONS  
DIM  
C
INCHES  
(.205)  
MILLIMETERS  
(5.20)  
Z
(C)  
D
E
F
G
P
X
Y
Z
.134  
.201  
.101  
.118  
.050  
.024  
.087  
.291  
3.40  
5.10  
2.56  
3.00  
1.27  
0.60  
2.20  
7.40  
G
Y
F
THERMAL VIA  
Ø 0.36mm  
P
X
NOTES:  
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.  
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR  
COMPANY'S MANUFACTURING GUIDELINES ARE MET.  
2. REFERENCE IPC-SM-782A, RLP NO. 300A.  
3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD  
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.  
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR  
FUNCTIONAL PERFORMANCE OF THE DEVICE.  
Contact Information  
Semtech Corporation  
Power Mangement Products Division  
200 Flynn Road, Camarillo, CA 930ꢀ2  
Phone: (805) 498-2ꢀꢀꢀ Fax: (805) 498-3804  
ꢀ8  

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