SC4609 [SEMTECH]
Low Input, MHz Operation, High Efficiency Synchronous Buck; 低投入，兆赫操作，高效率同步降压
| 型号： | SC4609 |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Low Input, MHz Operation, High Efficiency Synchronous Buck |
| 文件： | 总18页 (文件大小：329K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC4609
Low Input, MHz Operation,
High Efficiency Synchronous Buck
POWER MANAGEMENT
Description
Features
The SC4609 is a voltage mode step down (buck) regula-
tor controller that provides accurate high efficiency power
conversion from an input supply range of 2.7V to 5.5V. A
high level of integration reduces external component
count, and makes it suitable for low voltage applications
where cost, size and efficiency are critical. The SC4609
is capable of producing an output voltage as low as 0.5V.
Asynchronous start up
Programmable switching frequency up to 1MHz
BiCMOS voltage mode PWM controller
2.7V to 5.5V input voltage range
Output voltage as low as 0.5V
+/-1% reference accuracy
Sleep mode (Icc = 10µA typ)
Adjustable lossless short circuit current limiting
Combination pulse by pulse & hiccup mode
current limit
High efficiency synchronous switching
1A peak current driver
External soft start
12-pin MLP Lead-free package, fully WEEE and RoHS
compliant
The SC4609 drives external, N-channel MOSFETs with a
peak gate current of 1A. A non-overlap protection is pro-
vided for the gate drive signals to prevent shoot through
of the MOSFET pair. The SC4609 features lossless cur-
rent sensing of the voltage drop across the drain to
source resistance of the high side MOSFET during its
conduction period. Its switching frequency can be pro-
grammed up to 1MHz.
Applications
Distributed power architecture
Servers/workstations
The quiescent supply current in sleep mode is typically
lower than 10µA. A external soft start is provided to pre-
vent output voltage overshoot during start-up.
Local microprocessor core power supplies
DSP and I/O power supplies
Battery-powered applications
Telecommunications equipment
Data processing applications
The SC4609 is an ideal choice for converting 3.3V, 5V or
other low input supply voltages. It’s available in 12 pin
MLP package.
Typical Application Circuit
Vin=2.7V - 5.5V
C10
C13
C14
22u
22u
220u
D2
1u
C17
M11
R13
1
R3
U1
R6
1
12
1
11
10
9
BST
DRVH
L1
C3
4.7u
Vout=1.5V (as low as 0.5V*) / 12A
VCC
PHASE
DRVL
PGND
AGND
SS
1.8u
R5
2
ISET
C9
1
C6
C5
C4
3
8
COMP
FSET
VSENSE
M2
4.7n
C16
560pF
2.2n
330u
22u
C2
4
7
22u
R7
10k
C1
5
6
R8
200
180p
Css
22u
R1
SC4609
14.3k
R9
*External components can be modified to provide a Vout as low as 0.5V
4.99k
Revision: February 8, 2006
1
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SC4609
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied.
Parameter
Symbol
Maximum
Units
Supply Voltage (VCC)
PGND
6
V
V
A
±0.3
±0.25
Output Drivers (DRVH, DRVL) Currents
Continuous
Peak
±1.00
A
Inputs (VSENSE, COMP, FSET, ISET, SS)
BST
-0.3 to 6
12
V
V
PHASE
-0.3 to 6
-2 to 7
-40 to +85
-65 to +150
+150
V
PHASE Pulse tpulse < 50ns
Operating Ambient Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Peak IR Reflow Temperature, 10 - 40s
ESD Rating (Human Body Model)
V
TA
TSTG
TJ
°C
°C
°C
°C
kV
TPKG
ESD
260
4
All voltages with respect to AGND. Currents are positive into, negative out of the specified terminal.
Electrical Characteristics
Unless otherwise specified, VCC = 3.3V, CT = 270pF, TA = -40°C to 85°C, TA=TJ
Note: (1). Guaranteed by design.
Parameter
Test Conditions
Min
Typ
Max
Unit
Overall
Supply Voltage
5.5
15
V
Supply Current, Sleep
Supply Current, Operating
VCC Turn-on Threshold
VCC Turn-off Hysteresis
Error Amplifier
FSET = 0V
VCC = 5.5V
10
2
µA
mA
V
3.75
2.7
TA = -40°C to 85°C
350
mV
Input Voltage
TA = 25°C
0.495
0.5
0.5
0.505
(Internal Reference)
V
VCC = 2.7V - 5.5V, TA = 25°C
TA = -40°C to 85°C
VSENSE = 0.5V
0.4925
0.4925
0.5075
0.5075
VSENSE Bias Current
Open Loop Gain (1)
Unity Gain Bandwidth (1)
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90
8
nA
dB
VCOMP = 0.5 to 2.5V
MHz
2
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SC4609
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless otherwise specified, VCC = 3.3V, CT = 270pF, TA = -40°C to 85°C, TA=TJ
Parameter
Test Conditions
Min
Typ
Max
Unit
Error Amplifier (Cont.)
Slew Rate (1)
2.4
VCC - 0.3
0.3
V/µs
V
VOUT High
ICOMP = -5.5mA
ICOMP = 5.5mA
VCC - 0.5
525
VOUT Low
0.45
625
Oscillator
Initial Accuracy
TA = 25°C
575
0.05
0.02
kHz
%/V
%/°C
kHz
Hz
Voltage Stability
TA = 25°C, VCC = 2.7V to 5.5V
TA = -40°C to 85°C
Temperature Coefficient
Minimum Operation Frequency (1)
Maximum Operation Frequency (1)
Ramp Peak to Valley
Ramp Peak Voltage
Ramp Valley Voltage
Sleep, Soft Start, Current Limit
Sleep Threshold
50
1M
1
V
1.3
0.3
V
V
Measured at FSET
VSYNC = 0V
75
-55
200
mV
µA
Sleep Input Bias Current
Programmable Soft Start Time (1)
Soft Start Charge Current
ISET Bias Current
-1
C = 20nF
1.75
-5.75
-50
ms
µA
TA = 25°C
TJ = 25°C
-45
µA
Temperature Coefficient of ISET
Current Limit Blank Time (1)
Gate Drive
0.28
130
%/°C
ns
DRVH Minimum OFF Time
Peak Source (DRVH)
Peak Sink (DRVH)
TA = 25°C, VSENSE = 0
Vgs = 3.3V, ISOURCE = 100mA
Vgs = 3.3V, ISINK = 100mA
Vgs = 3.3V, ISOURCE = 100mA
Vgs = 3.3V, ISINK = 100mA
Vgs = 3.3V, COUT = 4.7nF
Vgs = 3.3V, COUT = 4.7nF
160
2.7
1.8
2.2
1.5
35
ns
Ω
Ω
(1)
Peak Source (DRVL)
Ω
Peak Sink (DRVL)
Output Rise Time
Ω
ns
ns
ns
Output Fall Time
27
Minimum Non-Overlap (1)
40
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SC4609
POWER MANAGEMENT
Pin Configuration
Ordering Information
Part Number(1)
SC4609MLTRT(2)
SC4609EVB
Device
TOP VIEW
MLP-12
BST DRVH PHASE
Evaluation Board
12
11
10
Notes:
VCC
ISET
1
2
3
9
8
7
DRVL
PGND
AGND
(1) Only available in tape and reel packaging. A reel
contains 3000 devices.
(2) Lead free product. This product is fully WEEE and
RoHS compliant.
COMP
4
5
6
FSET VSENSE SS
(MLP12, 4x4)
Pin Descriptions
Pin #
Pin Name
Pin Function
1
VCC
Positive supply rail for the IC. Bypass this pin to GND with a 0.1 to 4.7µF low ESL/ESR
ceramic capacitor.
2
ISET
The ISET pin is used to limit current in the high side MOSFET. The SC4609 uses the
voltage across the VIN and ISET pins in order to set the current limit. The current limit
threshold is set by the value of an external resistor (R3 in the Typical Application Circuit
Diagram). Current limiting is performed by comparing the voltage drop across the sense
resistor with the voltage drop across the drain to source resistance of the high side
MOSFET during the MOSFET’s conduction period. The voltage drop across the drain to
source resistance of the high side MOSFET is obtained from the VIN and PHASE pin.
3
4
COMP
FSET
This is the output of the voltage error amplifier. The voltage at this output is inverted
internally and connected to the non-inverting input of the PWM comparator. A lead-lag
network from the COMP pin to the VSENSE pin compensates for the two pole LC filter
characteristics inherent to voltage mode control. The lead-lag network is required in order
to optimize the dynamic performance of the voltage mode control loop.
The FSET pin is used to sets the PWM oscillator frequency through an external timing
capacitor that is connected from the FSET pin to the GND pin. When the FSET is pulled
and held below 75mV, its sleep mode operation is invoked. Sleep mode operation is
invoked by clamping the FSET pin to a voltage below 75mV. The typical supply current
during sleep mode is 10µA. The SC4609 can be operated in synchronous mode by placing
a resistor in series between the timing capacitor and ground. The other terminal of the
timing capacitor will remain connected to the FSET pin.
5
6
VSENSE
SS
This pin is the inverting input of the voltage amplifier and serves as the output voltage
feedback point for the Buck converter. VSENSE is compared to an internal reference value
of 0.5V. VSENSE is hardwired to the output voltage when an output of 0.5V is desired.
For higher output voltages, a resistor divider network is necessary (R7 and R9 in the Typical
Application Circuit Diagram).
Soft start. A capacitor to ground sets the soft start time. The soft start time is independent
SS = 87.5 • 103 • C.
of switching frequency and is defined as
Where C is the external
capacitor in nF and soft start time in second.
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SC4609
POWER MANAGEMENT
Pin Descriptions (Cont.)
Pin #
Pin Name
Pin Function
7
8
9
AGND
PGND
DRVL
Analog ground.
Power ground.
DRVL drives the gate of the low side (synchronous rectifier) MOSFET. The output drivers
are rated for 1A peak currents. The PWM circuitry provides complementary drive signals to
the output stages. The cross conduction of the external MOSFETs is prevented by
monitoring the voltage on the driver pins of the MOSFET pair in conjunction with a time
delay optimized for FET turn-off characteristics.
10
PHASE
The PHASE pin is used to limit current in the high side MOSFET. The SC4609 uses the
voltage across the VIN and ISET pin in order to set the current limit. The current limit
threshold is set by the value of an external resistor (R3 in the Typical Application Circuit
Diagram). Current limiting is performed by comparing the voltage drop across the sense
resistor with the voltage drop across the drain to source resistance of the high side
MOSFET during the MOSFET’s conduction period. The voltage drop across the drain to
source resistance of the high side MOSFET is obtained from the VIN and PHASE pin.
11
12
DRVH
BST
DRVH drives the gate of the high side (main switch) MOSFET. The output drivers are rated
for 1A peak currents. The PWM circuitry provides complementary drive signals to the
output stages. The cross conduction of the external MOSFETs is prevented by monitoring
the voltage on the driver pins of the MOSFET pair in conjunction with a time delay
optimized for FET turn-off characteristics.
This pin enables the converter to drive an N-Channel high side MOSFET. BST connects to
the external charge pump circuit. The charge pump circuit boosts the BST pin voltage to a
sufficient gate-to-source voltage level for driving the gate of the high side MOSFET.
THERMAL PAD Pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected
internally.
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SC4609
POWER MANAGEMENT
Block Diagram
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SC4609
POWER MANAGEMENT
Application Information
Enable
The maximum frequency of the external clock signal can
be higher than the natural switching frequency by about
10%.
The SC4609 is enabled by applying a voltage greater than
2.7 volts to the VCC pin. The SC4609 is disabled when
VCC falls below 2.35 volts or when sleep mode opera-
tion is invoked by clamping the FSET pin to a voltage
below 75mV. 10µA is the typical current drawn through
the VCC pin during sleep mode. During the sleep mode,
the high side and low side MOSFETs are turned off and
the internal soft start voltage is held low.
FSET
CFSET
C
SC4609
External
Clock
R
A
Signal
1k
56pF
RSYNC
100
D
Oscillator
Figure 1
The FSET pin is used to set the PWM oscillator frequency
through an external timing capacitor that is connected
from the FSET pin to the GND pin. The resulting ramp
waveform ion the FSET pin is a triangle at the PWM fre-
quency with a peak voltage of 1.3V and a valley voltage
of 0.3V. 200ns minimum OFF time for the top switch
allows the bootstrap capacitor to be charged during each
cycle. The capacitor tolerance adds to the accuracy of
the oscillator frequency. The approximate operating fre-
quency and soft start time are both determined by the
value of the external timing capacitor as shown in Table
1.
UVLO
When the FSET pin is not pulled and held below 75mV,
the voltage on the Vcc pin determines the operation of
the SC4609. As Vcc increases during start up, the UVLO
block senses Vcc and keeps the high side and low side
MOSFETs off and the internal soft start voltage low until
Vcc reaches 2.7V. If no faults are present, the SC4609
will initiate a soft start when Vcc exceeds 2.7V. A hyster-
esis (350mV) in the UVLO comparator provides noise
immunity during its start up.
Soft Start
External Timing
Frequency (kHz)
Capacitor Value (pF)
The soft start function is required for step down control-
lers to prevent excess inrush current through the DC bus
during start up. Generally this can be done by sourcing a
controlled current into a timing capacitor and then using
the voltage across this capacitor to slowly ramp up the
error amp reference. The closed loop creates narrow
width driver pulses while the output voltage is low and
allows these pulses to increase to their steady state duty
cycle as the output voltage reaches its regulated value.
With this, the inrush current from the input side is con-
trolled. The duration of the soft start in the SC4609 is
controlled by an external capacitor. SS, the startup time
is difined as:
120
270
470
560
1000
575
350
295
Table 1. Operating Frequency value Based on the
Value of the External Timing Capacitor Placed Across
the FSET and GND Pins
Synchronous mode operation is invoked by using a sig-
nal from an external clock. A low value resistor (100Ω
typical) must be inserted in series with the timing capaci-
tor between the timing capacitor and the GND pin. The
other terminal of the timing capacitor will remain con-
nected to the FSET pin. The transformed external clock
signal is then connected to the junction of the external
timing capacitor and the added resistor RSYNC as shown
in Figure 1.
SS = 87.5 • 103 • C
where, C is the value of the external capacitor in nF, and
SS is the startup time in second.
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SC4609
POWER MANAGEMENT
Application Information (Cont.)
Over Current Protection
A
B
VO −nom
The SC4609 detects over current conditions by sensing
the voltage across the drain-to-source of the high side
MOSFET. The SC4609 determines the high side MOS-
FET current level by sensing the drain-to-source conduc-
tion voltage across the high side MOSFET via the Vin (see
the Typical Application Circuit on page 1) and PHASE pin
during the high side MOSFET’s conduction period. This
voltage value is then compared internally to a user pro-
grammed current limit threshold. Note that user should
place Kelvin sensing connections directly from the high
side MOSFET source to the PHASE pin.
0.7
⋅VO−nom
C
VO
IMAX
D
IO
Figure 2. Over current protection characteristic of
SC4609
The current limit threshold is programmed by the user
based on the RDS(on) of the high side MOSFET and the
value of the external set resistor RSET (where RSET is
represented by R3 in the applications schematics of this
document). The SC4609 uses an internal current source
to pull a 50µA current from the input voltage to the ISET
pin through external resistor RSET.
Power MOSFET Drivers
The SC4609 has two drivers which are optimized for driv-
ing external power N-Channel MOSFETs.. The driver block
consists two 1 Amp drivers. DRVH drives the high side
N-MOSFET (main switch), and DRVL drives the low side
N-MOSFET (synchronous rectifier transistor).
The output drivers also have gate drive non-overlap
mechanism that provides a dead time between DRVH
and DRVL transitions to avoid potential shoot through
problems in the external MOSFETs. By using the proper
design and the appropriate MOSFETs, the SC4609 is
capable of driving a converter with up to 12A of output
The current limit threshold resistor (RSET) value is calcu-
lated using the following equation:
IMAX RDS(ON)
RSET
=
50µA
The RDS(ON) sensing used in the SC4609 has an addi-
tional feature that enhances the performance of the over
current protection. Because the RDS(ON) has a positive
temperature coefficient, the 50µA current source has a
positive coefficient of about 0.28%/C° providing first or-
current. As shown in Figure 3, td1 the delay from the
top MOSFET off to the bottom MOSFET on is adaptive by
,
der correction for current sensing vs temperature. This detecting the voltage of the phase node. td2, the delay
compensation depends on the high amount of thermal
transferring that typically exists between the high side N-
MOSFET and the SC4609 due to the compact layout of
the power supply.
from the bottom MOSFET off to the top MOSFET on is
fixed, is 40ns for the SC4609. This control scheme guar-
antees avoidance of cross conduction or shoot through
between the upper and lower MOSFETs and also mini-
mizes the conduction loss in the body diode of the bot-
tom MOSFET for high efficiency applications.
When the converter detects an over current condition (I
> IMAX) as shown in Figure 2, the first action the SC4609
takes is to enter the cycle by cycle protection mode (Point
B to Point C), which responds to minor over current cases.
Then the output voltage is monitored. If the over current
and low output voltage (set at 70% of nominal output
voltage) occur at the same time, the Hiccup mode op-
eration (Point C to Point D) of the SC4609 is invoked
and the internal soft start capacitor is discharged. This is
like a typical soft start cycle:
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SC4609
POWER MANAGEMENT
Application Information (Cont.)
Ip−p
2
IPEAK = IOMAX
+
TOP MOSFET Gate Drive
BOTTOM MOSFET Gate Drive
The power loss for the inductor includes its core loss and
copper loss. If possible, the winding resistance should
be minimized to reduce inductor’s copper loss. The core
loss can be found in the manufacturer’s datasheet. The
inductor’ copper loss can be estimated as follows:
Ground
Phase node
td2
td1
PCOPPER = I2
RWINDING
LRMS
Figure 3. Timing Waveforms for Gate Drives and Phase
Node
Where:
LRMS is the RMS current in the inductor. This current can
be calculated as follow is:
I
Inductor Selection
1
3
ILRMS = IOMAX 1+
∆I2
The factors for selecting the inductor include its cost,
efficiency, size and EMI. For a typical SC4609 applica-
tion, the inductor selection is mainly based on its value,
saturation current and DC resistance. Increasing the in-
ductor value will decrease the ripple level of the output
voltage while the output transient response will be de-
graded. Low value inductors offer small size and fast tran-
sient responses while they cause large ripple currents,
poor efficiencies and more output capacitance to smooth
out the large ripple currents. The inductor should be able
to handle the peak current without saturating and its
copper resistance in the winding should be as low as
possible to minimize its resistive power loss. A good trade-
off among its size, loss and cost is to set the inductor
ripple current to be within 15% to 30% of the maximum
output current.
Output Capacitor Selection
Basically there are two major factors to consider in se-
lecting the type and quantity of the output capacitors.
The first one is the required ESR (Equivalent Series Re-
sistance) which should be low enough to reduce the volt-
age deviation from its nominal one during its load changes.
The second one is the required capacitance, which should
be high enough to hold up the output voltage. Before the
SC4609 regulates the inductor current to a new value
during a load transient, the output capacitor delivers all
the additional current needed by the load. The ESR and
ESL of the output capacitor, the loop parasitic inductance
between the output capacitor and the load combined
with inductor ripple current are all major contributors to
the output voltage ripple. Surface mount speciality poly-
mer aluminum electrolytic chip capacitors in UE series
from Panasonic provide low ESR and reduce the total
capacitance required for a fast transient response.
POSCAP from Sanyo is a solid electrolytic chip capacitor
that has a low ESR and good performance for high fre-
quency with a low profile and high capacitance. Above
mentioned capacitors are recommended to use in
SC4609 application.
The inductor value can be determined according to its
operating point and the switching frequency as follows:
VOUT (V − VOUT
)
IN
L =
V
fs ∆I IOMAX
IN
Where:
fs = switching frequency and
∆I = ratio of the peak to peak inductor current to the
maximum output load current.
The peak to peak inductor current is:
Input Capacitor Selection
Ip−p = ∆I• IOMAX
The input capacitor selection is based on its ripple cur-
rent level, required capacitance and voltage rating. This
capacitor must be able to provide the ripple current by
the switching actions. For the continuous conduction
mode, the RMS value of the input capacitor can be cal-
culated from:
After the required inductor value is selected, the proper
selection of the core material is based on the peak in-
ductor current and efficiency requirements. The core
must be able to handle the peak inductor current IPEAK
without saturation and produce low core loss during the
high frequency operation is:
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SC4609
POWER MANAGEMENT
Application Information (Cont.)
Where:
VOUT (V − VOUT
)
VI2N
IB = the boost current and
VD= discharge ripple voltage.
ICIN
= IOMAX
(RMS)
IN
This current gives the capacitor’s power loss as follows:
With fs = 300kH, VD=0.3V and IB=50mA, the required
capacitance for the boost capacitor is:
PCIN = I2
RCIN(ESR)
CIN(RMS)
IB
VD fs
1
0.05
0.3 300k
1
Cboost
=
Dmax
=
0.95 = 528nF
This capacitor’s RMS loss can be a significant part of the
total loss in the converter and reduce the overall con-
verter efficiency. The input ripple voltage mainly depends
on the input capacitor’s ESR and its capacitance for a
given load, input voltage and output voltage. Assuming
that the input current of the converter is constant, the
required input capacitance for a given voltage ripple can
be calculated by:
Power MOSFET Selection
The SC4609 can drive an N-MOSFET at the high side
and an N-MOSFET synchronous rectifier at the low side.
The use of the high side N-MOSFET will significantly re-
duce its conduction loss for high current. For the top
MOSFET, its total power loss includes its conduction loss,
switching loss, gate charge loss, output capacitance loss
and the loss related to the reverse recovery of the bot-
tom diode, shown as follows:
D (1−D)
fs (∆V −IOMAX RCIN
CIN = IOMAX
)
I
(ESR)
Where:
D = VO/VI , duty ratio and
∆VI = the given input voltage ripple.
ITOP _PEAK V fs
I
PTOP _TOTAL = I2
RTOP_ON
+
TOP _RMS
V
Because the input capacitor is exposed to the large surge
current, attention is needed for the input capacitor. If
tantalum capacitors are used at the input side of the
converter, one needs to ensure that the RMS and surge
ratings are not exceeded. For generic tantalum capaci-
tors, it is wise to derate their voltage ratings at a ratio of
2 to protect these input capacitors.
GATE RG
(QGD + QGS2 ) + QGT VGATE fs + (QOSS + Qrr ) V fs
I
Where:
RG = gate drive resistor,
QGD = the gate to drain charge of the top MOSFET,
QGS2 = the gate to source charge of the top MOSFET,
QGT = the total gate charge of the top MOSFET,
QOSS = the output charge of the top MOSFET and
Qrr = the reverse recovery charge of the bottom diode.
Boost Capacitor Selection
The boost capacitor selection is based on its discharge
ripple voltage, worst case conduction time and boost
current. The worst case conduction time Tw can be esti-
mated as follows:
For the top MOSFET, it experiences high current and high
voltage overlap during each on/off transition. But for the
bottom MOSFET, its switching voltage is the bottom
diode’s forward drop during its on/off transition. So the
switching loss for the bottom MOSFET is negligible. Its
total power loss can be determined by:
1
fs
Tw =
Dmax
Where:
fs = the switching frequency and
Dmax = maximum duty ratio.
PBOT _TOTAL = I2
RBOT _ON + QGB VGATE fs +ID _AVG VF
BOT _RMS
The required minimum capacitance for boost capacitor
will be:
Where:
QGB = the total gate charge of the bottom MOSFET and
VF = the forward voltage drop of the bottom diode.
IB
VD
Cboost
=
TW
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SC4609
POWER MANAGEMENT
Application Information (Cont.)
For a low voltage and high output current application such
as the 3.3V/1.5V@12A case, the conduction loss is of-
ten dominant and selecting low RDS(ON) MOSFETs will no-
ticeably improve the efficiency of the converter even
though they give higher switching losses.
The gate charge loss portion of the top/bottom MOSFET’s
total power loss is derived from the SC4609. This gate
charge loss is based on certain operating conditions (fs,
VGATE, and IO).
The thermal estimations have to be done for both
MOSFETs to make sure that their junction temperatures
do not exceed their thermal ratings according to their
total power losses PTOTAL, ambient temperature TA and their
thermal resistance RθJA as follows:
Figure 4. Compensation network provides 3 poles and
2 zeros.
For voltage mode step down applications as shown in
Figure 4, the power stage transfer function is:
PTOTAL
TJ(max) < TA +
RθJA
s
1+
1
RC C4
1+ s + s2L1C4
GVD (s) = V
I
L1
R
Loop Compensation Design
For a DC/DC converter, it is usually required that the
converter has a loop gain of a high cross-over frequency
for fast load response, high DC and low frequency gain
for low steady state error, and enough phase margin for
its operating stability. Often one can not have all these
properties at the same time. The purpose of the loop
compensation is to arrange the poles and zeros of the
compensation network to meet the requirements for a
specific application.
Where:
R = load resistance and
RC = C4’s ESR.
The compensation network will have the characteristic
as follows:
s
ωZ1
s
s
ωZ2
s
1+
1+
1+
1+
ωI
GCOMP (s) =
s
ωP1
ωP2
The SC4609 has an internal error amplifier and requires
the compensation network to connect among the COMP
pin and VSENSE pin, GND, and the output as shown in
Figure 4. The compensation network includes C1, C2,
R1, R7, R8 and C9. R9 is used to program the output
voltage according to
Where
1
ωI =
R7 (C1 + C2 )
R7
R9
1
VO = 0.5 (1+
)
ωZ1
=
R1 C2
1
ωZ2
=
(R7 + R8 ) C9
C1 + C2
=
ωP1
R1 C1 C2
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SC4609
POWER MANAGEMENT
Application Information (Cont.)
1
Layout Guidelines
ωP2
=
R8 C9
In order to achieve optimal electrical, thermal and noise
performance for high frequency converters, special at-
tention must be paid to the PCB layouts. The goal of lay-
out optimization is to identify the high di/dt loops and
minimize them. The following guideline should be used to
ensure proper functions of the converters.
After the compensation, the converter will have the fol-
lowing loop gain:
s
1+
1
VM
s
s
ωZ2
s
1
ωI
V
1+
1+
1+
1+
I
ωZ1
s
RC C4
1+ s + s2L1C
T(s) = GPWM GCOMP(s) GVD(s) =
L1
R
s
ωP1
ωP2
1. A ground plane is recommended to minimize noises
and copper losses, and maximize heat dissipation.
2. Start the PCB layout by placing the power compo-
nents first. Arrange the power circuit to achieve a
clean power flow route. Put all the connections on
one side of the PCB with wide copper filled areas if
possible.
Where:
GPWM = PWM gain
VM = 1.0V, ramp peak to valley voltage of SC4609
The design guidelines for the SC4609 applications are
as following:
3. The Vcc bypass capacitor should be placed next to
the Vcc and GND pins.
4. The trace connecting the feedback resistors to the
output should be short, direct and far away from the
noise sources such as switching node and switching
components.
5. Minimize the traces between DRVH/DRVL and the
gates of the MOSFETs to reduce their impedance to
drive the MOSFETs.
6. Minimize the loop including input capacitors, top/bot-
tom MOSFETs. This loop passes high di/dt current.
Make sure the trace width is wide enough to reduce
copper losses in this loop.
1. Set the loop gain crossover corner frequency ω C
for given switching corner frequency ωS = 2pfs,
2. Place an integrator at the origin to increase DC
and low frequency gains.
3. Select ωZ1 and ωZ2 such that they are placed near
ωO to damp the peaking and the loop gain has a
-20dB/dec rate to go across the 0dB line for
obtaining a wide bandwidth.
4. Cancel the zero from C4’s ESR by a compensator
pole ωP1 (ωP1 = ωESR = 1/( RCC4)).
5. Place a high frequency compensator pole ωp2 (ωp2
= πfs) to get the maximum attenuation of the switch-
ing ripple and high frequency noise with the adequate
phase lag at ωC.
7. ISET and PHASE connections to the top MOSFET for
current sensing must use Kelvin connections.
8. Maximize the trace width of the loop connecting the
inductor, bottom MOSFET and the output capacitors.
The compensated loop gain will be as given in Figure 5:
T
9. Connect the ground of the feedback divider and the
compensation components directly to the GND pin
of the SC4609 by using a separate ground trace.
Then connect this pin to the ground of the output
capacitor as close as possible
ω
Z1
Loop gain
-
ω
o
ω
Z2
Gvd
0dB
c
ω
p1
ω
p2
ω
Power stage
ωESR
-
Figure 5. Asymptotic diagrams of power stage and its
loop gain
2006 Semtech Corp.
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SC4609
POWER MANAGEMENT
Application Information (Cont.)
Design Example 1. 3V to1.5V @10A application with SC4609
Vin=3V - 5.5V
C10
C13
22u
C14
22u
D2
1u
220u
C17
M1
R13
1
R3
U1
R6
12
1
11
10
9
BST
DRVH
PHASE
DRVL
PGND
AGND
SS
L1
0
C3
4.7u
Vout = 1.5V/10A
VCC
2.3u
R5
2
ISET
0
C4
22u
C5
22u
C7
3
8
C9
COMP
FSET
VSENSE
M2
C16
470pF
330u
4
7
C2
C1
R7
5.76k
8.2n
5
6
1.8n
2.2n
R8
107
SC4609
Css
22n
R1
14.3k
R9
2.87k
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SC4609
POWER MANAGEMENT
Bill of Materials
Item
1
Qty
1
Reference
Value
Part No./Manufacturer
C1
1.8nF
2
1
C2
2.2nF
3
1
C17
1uF
4
4
C4,C5, C13, C14
22uF, 1206
TDK P/N: C3225X5R0J226M
Sanyo P/N: 6TPB330ML
5
1
C7
330uF, 2870
8.2nF
6
1
C9
7
1
C16
D2
470pF
8
1
MBR0520LT1
ON Semi P/N: MBR0520LT1
Cooper Electronic
P/N: HC1-2R3
9
1
L1
2.3uH
10
11
12
13
14
15
16
17
18
19
20
2
1
1
1
1
1
1
1
1
1
1
M1, M2
R1
Powerpack, SO-8
14.3K
Vishay P/N: Si7882DP
R3
1.33K
R7
5.76K
R8
107
R9
2.87K
R13
C3
1
4.7uF, 0805
220uF, 2870
22nF
C10
Css
U1
Sanyo P/N: 6TPB220ML
SC4609
Semtech P/N: SC4609IMLTRT
Unless specified, all resistors have 1% precision with 0603 package.
Resistors are +/-1% and all capacitors are +/-20%
2006 Semtech Corp.
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SC4609
POWER MANAGEMENT
PCB Layout
COMPONENT SIDE (TOP)
COMPONENT SIDE (BOTTOM)
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SC4609
POWER MANAGEMENT
PCB Layout (Cont.)
(BOTTOM)
(TOP)
(INTER LAYER 2)
(INTER LAYER 1)
2006 Semtech Corp.
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SC4609
POWER MANAGEMENT
Outline Drawing - MLP-12
DIMENSIONS
INCHES MILLIMETERS
DIM
A
MIN NOM MAX MIN NOM MAX
A
D
B
E
-
-
-
-
.031
.040 0.80
.002 0.00
1.00
0.05
-
A1 .000
-
(.008)
-
-
(0.20)
A2
b
.010 .012 .014 0.25 0.30 0.35
.153 .157 .161 3.90 4.00 4.10
PIN 1
INDICATOR
D
D1 .074 .085 .089 1.90 2.15 2.25
(LASER MARK)
E
.153 .157 .161 3.90 4.00 4.10
E1 .074 .085 .089 1.90 2.15 2.25
e
.031 BSC
0.80 BSC
L
N
.018 .022 .026 0.45 0.55 0.65
12
12
aaa
.003
.004
0.08
0.10
bbb
A2
A
SEATING
PLANE
aaa C
A1
C
D1
LxN
E/2
2
1
E1
N
bxN
bbb
C A B
e
D/2
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
2006 Semtech Corp.
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SC4609
POWER MANAGEMENT
Land Pattern - MLP-12
K
DIMENSIONS
DIM
INCHES
MILLIMETERS
(.148)
.106
.091
.091
.031
.016
.041
.189
(3.75)
2.70
2.30
2.30
0.80
0.40
1.05
4.80
C
G
H
K
P
X
Y
Z
2x Z
H
2x G
Y
2x (C)
X
P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
2006 Semtech Corp.
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