SC4624A_技术文档

SC4624A

Low Input Voltage, High Efﬁciency, 4A Integrated

FET Synchronous Step down DC/DC Regulator

POWER MANAGEMENT

Features

Description

 VIN Range: 2.3 – 5.5V

The SC4624A is a highly integrated synchronous step-

down DC/DC regulator designed for low input voltage

range of 2.3V to 5.5 Volts. It can deliver 4A continuous

output current with the output voltage as low as 0.5 Volts.

The internal low R_DS(ON)synchronous power switches

eliminate the need for external Schottky diode while

delivering overall converter efﬁciency up to 95%.

 4A Continuous Output Current

 Adjustable Output Voltage 0.5V to Vin

 Low R_DS(ON)integrated FETs: 75mΩ and 47mΩ

 Up to 95% Efficiency

 Synchronizable and Programmable Frequency:

200kHz – 2MHz

 Power Good Monitor

 <1µA of Shutdown Current

 Programmable Soft Start

A power good pin is available to monitor the output voltage

status. Operating frequency is adjustable from 200 kHz

to 2MHz with a single resistor and it can be synchronized

to an external clock.

 Programmable Current Limit

 Over Temperature protection

 -40 to +85 °C Ambient Temperature Range

 4X4mm MLPQ-20 packages- WEEE and RoHS

compliant

The SC4624A offers adjustable current limit, soft start and

over temperature protection to safeguard the device under

extreme operating conditions. The soft start provides a

controlled output voltage ramp up at startup. When a

logic low is applied to the Enable pin, the SC4624A enters

Applications

the shutdown mode and it consumes less than 1µA of  Low Voltage Distributed DC-DC Converters

current.

 Telecommunication Power Supplies

 Portable Equipment

The SC4624A is available in 4x4 MLPQ-20 and it is rated  xDSL

over -40°C to +85°C ambient temperature range.

Typical Application Circuit

R4

C11

Vin

L1

Vout

PVIN

PH

FB

R5

R6

R2

C8

R7

R9

SYNC/EN

PGOOD

VCC

C9

R8

C4

C3

R1

C2

C1

SC4624A

SS

ISET

FS

COMP

C7

C5

R3 R11

Revision: July 10, 2008

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SC4624A

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Pin Conﬁguration

Ordering Information

Device

Top Mark

Package

Top View

SC

4624A

SC4624AMLTRT ^{(1) (2)}

MLPQ-20

SC4624AEVB-MLPQ

Evaluation Board

20

16

15

Notes:

1

PVIN

ISET

SS

PGND

AGND

VCC

(1) Available in tape and reel only. A reel contains 3,000 devices for MLPQ-20

package.

(2) Available in lead-free package only. Device is WEEE and RoHS compliant.

T

FS

FB

5

11

10

6

20Pin MLPQ

θ_JA= 29°C/W; θ_JC= 2.5°C/W.

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Absolute Maximum Ratings

Exceeding the speciﬁcations below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters speciﬁed in the

Electrical Characteristics section is not implied.

Parameter

Symbol

Maximum

-0.3 to 6

Units

V

Supply Voltage

PV_IN, V_CC

PVIN to VCC

+/- 0.3

V

FB, COMP, ISET, SYNC/EN, FS, SS, PGOOD to AGND

PGND to AGND

-0.3 to VCC+ 0.3

+/- 0.3

V

PHASE Voltage to PGND

PHASE Pulse Voltage to PGND Tpulse < 50ns

Storage Temperature Range

Junction Temperature

V_PHASE

T_STG

T_J

-0.3 to PVIN+ 0.3

-3 to PVIN+ 2

-40 to 150

150

V

°C

kV

IR Reﬂow Temperature

T_P

260

ESD Protection Level⁽¹⁾

2

V_ESD

Note:

1) Tested in accordance to JEDEC standard JESD22-A114B.

Recommended Operating Conditions

The Performance is not guarantied if exceeding the speciﬁcations below.

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Power Supply

Input Voltage Operating Range

Ambient Temperature Range

Junction Temperature

Max. Output Current

V_IN

T_A

2.3

-40

0

5.5

85

125

4

V

°C

A

T_J

I_OUTMAX

Electrical Characteristics

Unless otherwise speciﬁed, V_IN= V_CC=SYNC/EN=3.3V, R_OSC=51.1KΩ, R_ISET=27.4KΩ, T_A= -40°C to 85°C

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Power Supply

Start Threshold Voltage, UVLO

Hysteresis Voltage, UVLO

Supply Current, Shutdown

V_IUV

V_IUVHY

I_SD

V_INRising

2

120

0.2

7

2.25

V

mV

µA

mA

V_SYNC= 0V

1

10

7

I_Qswitching

I_QL

FB = COMP, No Load

Supply Current, Operating

FB = 0.6V, No Load

3.5

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SC4624A

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Electrical Characteristics (Cont.)

Unless otherwise speciﬁed, V_IN= V_CC=SYNC/EN=3.3V, R_OSC=51.1KΩ, R_ISET=27.4KΩ, T_A= -40°C to 85°C.

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Thermal Shutdown

Thermal Shutdown Trip Point

Thermal Shutdown Hysteresis

Synchronization, Enable Input

T_OTP

Temperature Rising

160

10

°C

T_{OTP_HYS}

V_ENL

V_ENH

F_SYNC

Logic Low

Logic High

0.8

V

SYNC/EN Threshold

2.0

Frequency Range, SYNC

Oscillator

20% Higher than F_OSC

200

2000

kHz

Osciilator Frequency Range

F_OSC

200

415

435

2000

585

kHz

V

R_OSC= 51.1KΩ

500

1.0

Osciilator Frequency Accuracy

R_OSC=51.1KΩ, T_A=T_J=25°C

565

Ramp Peak to Valley⁽¹⁾

Ramp Peak Voltage⁽¹⁾

Ramp Valley Voltage⁽¹⁾

Soft Start, Current Limit

Soft-Start Charge Current

ISET Bias Voltage

Over Current Trip

V_PV

V_P

1.25

0.25

V

V_V

V

I_SS

V_ISET

I_IST

4

0.55

2.55

0.3

µA

V

R_ISET= 27.4KΩ

R_ISIT= 57.6KΩ

VFB drop

0.45

1.9

0.61

3.1

A

Output UVLO

V_OUV

T_OCHP

V

Hiccup period⁽¹⁾

131072

clks

Error Ampliﬁer

Error Ampliﬁer Open Loop

100

dB

Voltage Gain ⁽¹⁾

Error Ampliﬁer Unity Gain Bandwidth⁽¹⁾

Output Voltage Slew Rate, COMP⁽¹⁾

Source Output Current, COMP

Sink Output Current, COMP

10

4

MHz

V/µs

mA

V

FB = 0.4V

FB = 0.6V

20

25

2.5

Output Voltage High, COMP

FB = 0.4V, I_COMP= -1mA

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SC4624A

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Electrical Characteristics (Cont.)

Unless otherwise speciﬁed, V_IN= V_CC=SYNC/EN=3.3V, R_OSC=51.1KΩ, R_ISET=27.4KΩ, T_A= -40°C to 85°C.

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Error Ampliﬁer (Cont.)

Output Voltage Low, COMP

FB = 0.6V, I_COMP= 1mA

0.1

0.5

+1

0.25

0.5075

+2

V

0.4925

-2

Feedback Voltage

V_FB

Vcc = 2.3V to 5.5V

%

nA

Input Bias Current⁽¹⁾

Power Switches

I_FB

FB=V_REF

300

High-Side P-MOSFET

Low Side N-MOSFET

Power Good

R_DSH(on)

R_DSL(on)

V_IN=V_CC=5V, I_SOURCE= 1A, T_A=T_J=25 °C

V_IN=V_CC=5V, I_SINK= 1A, T_A=T_J=25 °C

74

47

100

85

mΩ

PGood Voltage Low

PGood Leakage Current

PGood Delay Time⁽¹⁾

V_PGL

I_PGOOD

T_D

I_PGOOD= 1mA

PGOOD = 5V

0.2

V

1

µA

Vout rising or Vout falling

1024

+10

clks

With respect to nominal output,

PGood High Window

+8

+15

%

T_A=T_J=25 °C

Note:

(1) Guaranteed by design.

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Oper tion

Typical Performance Characteristics

Circuit condition: Application circuit#1, 5V_IN, 1V_OUT

V_IN

SS

V_IN

SS

5V/DIV

V_OUT

0.5V/DIV

5V/DIV

PGOOD

0.5V/DIV

5V/DIV

PGOOD

10ms/DIV

Figure 1. Start Up by V_IN@0A

Figure 2. Start Up by V_IN@4A

5V/DIV

V_IN

SS

0.5V/DIV

5V/DIV

0.5V/DIV

5V/DIV

V_OUT

PGOOD

5ms/DIV

1ms/DIV

Figure 4. Shutdown by V_IN@4A

Figure 3. Shutdown by V_IN@0A

Vout

V_OUT

20mV/DIV

V_OUT

50mV/DIV

Io

2.0V/DIV

l_OUT

V_PHASE

2A/DIV

1us/DIV

20us/DIV

Figure 5. Transient Response@ 0 to 4A

Figure 6. Ripple and Stability@4A

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Oper tion

Typical Performance Characteristics (Cont.)

Circuit condition: Application circuit#1, 5V_IN, 1V_OUT

0.6V/DIV

V_OUT

0.6V/DIV

5.0V/DIV

V_OUT

5.0V/DIV

SS

3V/DIV

3.0V/DIV

V_PHASE

100ms/DIV

1s/DIV

Figure 7. Over Load Hiccup

Figure 8. Thermal Shutdown Protection@0A

External clock singal=650kHz, duty=50%

˄˃˃

ˌˈ

Sync

ˌ˃

Signal

ˋˈ

5Vin

ˋ˃

ˊˈ

2.5Vin

ˊ˃

2.0V/DIV

3.3Vin

ˉˈ

ˉ˃

ˈˈ

ˈ˃

ˇˈ

ˇ˃

V_PHASE

2.0V/DIV

˃ˁ˃

˃ˁˈ

˄ˁ˃

˄ˁˈ

˅ˁ˃

˅ˁˈ

ˆˁ˃

ˆˁˈ

ˇˁ˃

1us/DIV

Output Current(A)

Figure 10. Efﬁciency(V_IN)

Figure 9. Synchronization

Internal PMOS R_DSON@ Room Temperature

Internal NMOS R_DSON@ Room Temperature

130

80

75

70

65

60

55

50

120

2.5V_IN

110

2.5V_IN

3.3V_IN

100

90

3.3V_IN

80

5V_IN

70

1

2

3

4

1

2

3

4

I_OUT(A)

Figure 12. Low-Side N-MOSFET

Figure 11. High-Side P-MOSFET

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Oper tion

Typical Performance Characteristics (Cont.)

OCP Trip

Regulation During Switching to Linear Mode

ˇˁˋ

ˇˁˇ

ˇˁ˃

ˆˁˉ

ˆˁ˅

˅ˁˋ

˅ˁˇ

˅ˁ˃

˄ˁˉ

˄ˁ˅

˃ˁˋ

2.54

3.3Vin

2.52

2.50

5Vin

VOUT

2.48

2.46

2.44

2.42

2.40

2.38

2.36

2.5Vin

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

˅˃

˅ˈ

ˆ˃

ˆˈ

ˇ˃

ˇˈ

ˈ˃

ˈˈ

ˉ˃

ˉˈ

ˊ˃

ˊˈ

ˋ˃

ˋˈ

ˌ˃

ˌˈ

˄˃˃

I_OUT(A)

R_ISET(KΩ)

Figure 14. Over Current Setting versus R_ISET

Figure 13. Loading Regulation

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SC4624A

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Pin Descriptions

Pin Name

MLPQ-20

Pin Functions

Power supply voltage for high side MOSFETs.

1,2

PVIN

Current limit setting pin. A resistor connected between ISET and AGND sets the over current

protection threshold. A ceramic decoupling between ISET pin to AGND have to be reserved to

prevent from noise inﬂuence.

3

ISET

4

5

SS

FS

Soft start time setting pin. A cap connected from this pin to GND sets the soft start up time.

Oscillator frequency setting pin. An external resistor connected from this pin to GND sets the

oscillator frequency.

Power good indicator. It is an open drain output. Low when the output is below the power good

threshold level.

6

PGOOD

7,12

VCC

NC

Power supply voltage for the analog section of the controller.

8,19,20

No connection.

The oscillator frequency of the SC4624A is set by FS when SYNC/EN is pulled and held above

9

SYNC/EN 2V. Its synchronous mode is activated as SYNC/EN is driven by an external clock. Its shutdown

mode is invoked if SYNC/EN is pulled and held below 0.8V.

This is the output of the error ampliﬁer. The voltage at this point is connected to the inverting

10

11

COMP

FB

input of the PWM comparator. A compensation network is required in order to optimize the dy-

namic performance of the voltage mode control loop.

The inverting input of the error ampliﬁer. It serves as the output voltage feedback point for the

buck controller. It senses the output voltage through an external divider.

13

AGND

PGND

PH

Analog signal ground.

Power ground.

14,15

16,17,18

Switching nodes

THERMAL Pad for heatsinking purposes only. Connect to ground plane using multiple vias. Not electrically

PAD connected internally.

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SC4624A

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Block Diagram

ASYNCHRONOUS

START UP

VCC

PVIN1

PVIN2

0.5V

THERMAL

SHUTDOWN

+

-

BANDGAP

TOP GATE

UVLO

HIGH SIDE DRIVER

AND LOGIC

ISET

AGND

VREF

I = F(R_ISET)

ERROR

OPAMP

PH1

PH2

SOFT

START

+

OVER

CURRENT

PROTECT

-

PH3

SS

FB

PWM

BLOCK

BOTTOM

GATE

COMP

PWM

SD

LOGIC

SYNC/EN

SHOOT-

THRU

PROTECTION

LOW SIDE DRIVER

AND LOGIC

OSC

FB

FS

CLOCK

PGND1

PGND2

1.1VREF

0.9VREF

PGOOD

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Application Information

Overview

During start up or restart, A typical 4µA sourcing current

charges the capacitor and then the voltage of capacitor

ramp up the error amp reference slowly. The closed

loop creates narrow width driver pulses while the output

voltage is low and allows these pulses to increase to their

steady state duty cycle as the output voltage reaches

its regulated value. The duration of the soft start in the

SC4624A is controlled by an external capacitor.

TheSC4624Aisaprogrammablehighswitchingfrequency,

integrated 4A MOSFET, synchronous step down regulator.

This reduces external component count and makes it

effective for applications which are low in cost and sized

small. A non-overlap protection is provided for the gate

drive signals to prevent shoot through of the internal

MOSFET pair.

The SC4624A is capable of producing an output voltage as

low as 0.5V and Its operation frequency is programmable

up to 2MHz by an external resistor. It features lossless

current sensing of the voltage drop across the internal

drain to source resistance of the high side MOSFET during

its conduction period.

The SC4624A starts up in asynchronous mode before SS

voltage reaches to 0.5V, and the bottom FET diode is used

for circulating current during the top FET off time. Ths SS

voltage level is clamped at V_CCﬁnally.

Oscillator

The FS pin is used to set the PWM oscillator frequency

through an external resistor that is connected from the

FS pin to the AGND. The internal ramp is a triangle at the

PWM frequency with a peak voltage of 1.25V and a valley

voltage of 0.25V. The approximate operating frequency is

determined by the value of an external resistor as shown

in Figure 15.

The quiescent supply current in shutdown mode is

typically lower than 1µA. An external soft start is provided

to prevent output voltage overshoot during start-up. Over

Temperature Protection, Power Good Indicator, External

Clock Synchronization are some of the internal added

features.

Enable

The SC4624A is enabled by applying a voltage greater

than 2V (typical) to the V_CCand SYNC/EN pin. The voltage

on the V_CCpin determines the operation of the SC4624A.

As V_CCincreases during start up, the UVLO block senses

V_CCand keeps the high side and low side MOSFETs off and

the internal soft start voltage low until V_CCreaches 2V. If

no faults are present, the SC4624A will initiate a soft start

when V_CCexceeds 2V. A typical 120mV hysteresis in the

UVLO comparator provides noise immunity during its start

up. (refer to Figures 1 & 2).

Switching Frequency Setting

145

135

125

115

105

95

85

75

65

55

45

35

25

15

5

5VIN

2.5VIN

Shutdown

200

400

600

800

1000

1200

1400

1600

1800

2000

The SC4624A is disabled when V_CCfalls below 1.88V (typi-

cal) or shutdown mode operation is invoked by clamping

the SYNC/EN pin to a voltage below 0.8V. During the shut-

down mode, A typical 0.2µA current draw through the V_CC

pin, the internal soft start voltage is held low and the inter-

nal MOSFETs are turned off. (refer to Figures 3 & 4).

F_osc(kHz)

Figure 15. Switching Frequency vs. R_FS

The operation frequency can be programmed up to 2MHz,

but there is a minimum on-time limitation which is around

110ns.Usersshouldtakecareofminimumlimitationonthe

operating duty cycle under high frequency application.

Soft Start

The soft start function is required for step down controllers

to prevent excess in-rush current through the DC bus

during start up. An external capacitor is necessary for

the soft start function and is connected from SS pin to

AGND.

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O eration

Application Information (Cont.)

Synchronization Frequency

Synchronization operation mode is invoked by using an

external clock signal and is activated when the SYNC/EN

is pulled and held above 2V and held below 0.8V. The

range of synchronization frequency is from 200kHz to

2MHz.

attention is internal high side PMOS has minimum off time

limitation and is related to duty cycle rate. This condition

makes the working duty cycle perform at randon with the

output ripple increasing and a poor transient response.

Above phenomenon can be improved by larger output

capacitor and smaller output inductor. Users need to

verify whether above application condition has opposite

inﬂuence on entire circuit.

A jitter happens when sync pulse clock edge is less than

120ns before the phase switches. It is caused by the

ground bounce of synchronization pulse coupled to PWM

comparator. Users try to avoid this application. (refer to

Figure 9).

Over Current Protection

A over current setting is programmed by an external

resistor (R_ISET). It goes through internal sense resistor and

generates a voltage.

Power Good Indicator

The PGOOD pin is an open-drain and incorporated window

comparators output. It’s is necessary that a pull-up

resistor from the PGOOD pin to the input supply for setting

the logic high level of the PGOOD signal. When FB voltage

is within +10% setting output voltages typical, the output

of power good comparator becomes high impedance after

delay time. The PGOOD signal delay time is around 1024/

F_OSC. In shutdown mode the power good output is actively

pulled low.

9ꢀ 9^FFꢀ ,u52QVHQVH

where

I : The current is generated by R_ISET, and it is ampliﬁed

by internal current ampliﬁer.

R_ONSENSE: Internal sense resistor.

Output inductor current goes through internal high side

P-MOSFET and generate a voltage.

For example, 1MHz switching frequency applications, the

PGOOD delay time is around 1ms.

9ꢂ 9^,1ꢀ ,

/

u5^'6+ꢁ21ꢀ

where

I_L: Output inductor current.

R_DSH(ON): High side P-MOSFET conduction resistance.

Thermal Shutdown

When the junction temperature rises up around 160°C,

the internal soft start voltage is held low, the internal high

side and low side MOSFETs are turned off and the output

voltage will fall to zero. Once the junction temperature

goes below hysteresis temperature around 10°C, the

regulator will restart. (refer to Figure 8).

After the high side PMOS turn on around 30ns, the OCP

comparator will compare between V2 and V1. When the

converter detects an over current condition (V2 > V1)

as shown in Figure 16, the SC4624A proceeds into the

cycle by cycle protection mode (Point B to Point C), which

responds to minor over current cases and the output

voltage is monitored.

Linear Mode Operation (100% duty)

The SC4624A can allows 100% duty cycle operation. The

Vout is,

If the over current and low output voltage (set at 60% of

nominal output voltage) occur at the same time, the SS

pin is pull low by an internal switch and the comp pin is

pulled low and the devices stops switching. Assume start

from FB = 0V, FB and SS voltage rise forward 0.5V. Once

SS voltage exceeds 0.4V, the hiccup comparator becomes

enabled. The hiccup period is around 2¹⁷/F_OSC. (Point C to

Point D).

9

287 9,1 ꢁ ꢁ5 ꢀ 5'6+ꢀ u,287

/

where

R_L: Output inductor DC resistance.

R_DSH: Internal high side P-MOSFET resistance.

(refer to Figure11).

As Vin drops gradually and close to Vout, the buck regulator

will go into 100% duty cycle ratio. A matter needing

For example, with a switching frequency application of

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Application information (Cont.)

After the required inductor value is selected, the proper

selection of the core material is based on the peak

inductor current and efﬁciency requirements. The core

must be able to handle the peak inductor current I_PEAK

without saturation and produce low core loss during the

high frequency operation and is given as follows:

550kHz, the hiccup period is around 238ms. (refer to

Figure 7).

A poor layout will make OCP trip point shift and is not

easily to calculate by R_ISET. This is because it is affected

by ground bounce, spiker voltage between Vin pin and PH

pin, and internal parameter tolerance. Users can refer to

Figure 14, it shows how to set maximum output current

,3 ꢀ 3

,3($. ,^,20$;ꢁ

ꢀ

by R_ISET

.

The power loss for the inductor includes its core loss and

copper loss. If possible, the winding resistance should be

minimized to reduce any copper loss of the inductor, (the

core loss can be found in the manufacturer’s datasheet).

A

Vout

B

0

The inductor’s copper loss can be estimated as follows:

C

0.6 * Vout

3

&223(5 ,^ꢀ/506 u5:,1',1*

Vo

D

where

I_LRMSis the RMS current in the inductor.

Imax

Iout

0

This current can be calculated as follows:

Figure 16. Over Current Protection Characteristic

ꢂ

/506 ,^20$;u ꢂ ꢀ u ',^ꢀ

Inductor Selection

,

For a typical SC4624A application, the inductor selection

ꢁ

is mainly based on its value, saturation current and DC

resistance. The inductor should be able to handle the

peak current without saturating and its copper resistance

in the winding should be as low as possible to minimize its

resistive power loss.

Output Capacitor Selection

Basically there are two major factors to consider in select-

ing the type and quantity of the output capacitors. The

ﬁrst one is the required ESR (Equivalent Series Resis-

tance) which should be low enough to reduce the voltage

deviation from its nominal one during its load changes.

The second one is the required capacitance, which should

be high enough to hold up the output voltage. Before the

SC4624A regulates the inductor current to a new value

during a load transient, the output capacitor delivers all

the additional current needed by the load.

The inductor value can be determined according to its

operating point and the switching frequency as follows:

9287 u ꢁ9,1 ꢀ 9287ꢀ

/

9

,1 u I u ',u ,20$;

6

The ESR and ESL of the output capacitor, the loop para-

sitic inductance between the output capacitor and the

load combined with inductor ripple current are all major

contributors to the output voltage ripple.

where

fs = switching frequency.

DI = ratio of the peak to peak inductor current to the

maximum output load current.

Input Capacitor Selection

The peak to peak inductor current is:

The input capacitor selection is based on its ripple cur-

rent level, required capacitance and voltage rating. This

capacitor must be able to provide the ripple current by the

,

3

ꢀ

3

',u,20$;

 2008 Semtech Corp.

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SC4624A

POWER MANAGEMENT

O eration

Application Information (Cont.)

switching actions. For the continuous conduction mode,

the RMS value of the input capacitor can be calculated

from:

5

ꢅꢄꢃ u ꢂꢁ ꢀ ^ꢇꢀ

5_ꢆ

92

9

287 u ꢁ9^,1ꢀ 9²⁸⁷ꢀ

,

&,1ꢁ506ꢀ ,^20$;u

SC4624A

C1

9^ꢂ_IN,1

R1

C2

COMP

FB

This current gives the capacitor’s power loss as follows:

Vout

L1

PH

C8

3

&,1 ,^ꢂ&,1ꢁ506ꢀ u5&,1ꢁ(65ꢀ

R7

R8

C4

R

This capacitor’s RMS loss can be a signiﬁcant part of the

total loss in the converter and reduces the overall convert-

er efﬁciency. The input ripple voltage mainly depends on

the input capacitor’s ESR and its capacitance for a given

load, input voltage and output voltage. Assuming that the

input current of the converter is constant, the required

input capacitance for a given voltage ripple can be calcu-

lated by:

R9

Figure 17. Compensation Network

Provides 3 Poles and 2 Zeros

'u ꢁꢂ ꢂ 'ꢀ

&

,1 ,20$; u

6

∆

I

u

ꢀ

'9

,

ꢂ ,20$; u5&,1ꢁ(65ꢀ

ꢁ

For voltage mode step down applications as shown in Fig-

ure 17, the power stage transfer function is:

where

D = V_O/V_I, duty ratio.

DV_I= the given input voltage ripple.

Loop Compensation Design

For a DC/DC converter, it is usually required that the con-

verter has a loop gain of a high cross-over frequency for

fast load response, high DC and low frequency gain for low

steady state error, and enough phase margin for its oper-

ating stability. Often one can not have all these properties

at the same time. The purpose of the loop compensation

is to arrange the poles and zeros of the compensation

network to meet the requirements for a speciﬁc applica-

tion.

where

R = load resistance

R_C= C4’s ESR.

The compensation network will have these characteris-

tics:

The SC4624A has an internal error ampliﬁer and requires

the compensation network to connect among the COMP

pin and FB pin, GND, and the output as shown in Figure

17. The compensation network includes C1, C2, R1, R7,

R8 and C8. R9 is used to program the output voltage ac-

cording to:

s

w_Z1

s

w_Z2

s

1+

w_I

s

G_COMP(s) =

⋅

⋅1+

w_P1

w_P2

 2008 Semtech Corp.

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SC4624A

POWER MANAGEMENT

O eration

Application Information (Cont.)

The design guidelines for the SC4624A applications are

as follows:

where

1

ω_I=

1. Set the loop gain crossover corner frequency w_Cfor

given switching corner frequency w_S= 2pfs,

2. Place an integrator at the origin to increase DC and

low frequency gains.

3. Select w_Z1and w_Z2such that they are placed near w_O

to damp the peaking and the loop gain has a -20dB/

dec rate to go across the 0dB line for obtaining a wide

bandwidth.

R₇⋅(C₁+ C₂)

1

ω_Z1=

R₁⋅C₂

1

ω_Z2=

(R₇+ R₈)⋅C₈

4. Cancel the zero from C4’s ESR by a compensator pole

w_P1(w_P1= w_ESR= 1/(R_CC₄)).

C₁+ C₂

ω_P1=

R₁⋅C₁⋅C₂

5. Place a high frequency compensator pole w_P2(w_P2

=

pfs) to get the maximum attenuation of the switch-

ing ripple and high frequency noise with the adequate

phase lag at w_C.

1

ω_P2=

R₈⋅C₉₈

The compensated loop gain will be as given as show in

Figure 18.

After the compensation, the converter will have the

following loop gain:

T(s) = G_PWM⋅G_COMP(s)⋅G_VD(s)

s

1

1+

1

s

w_Z2

s

⋅ w_I⋅ V 1+

1+

I

V_M

w_Z1

s

R_C⋅C₄

=

⋅

=

L₁

s

1+

⋅1+

1+ s + s²L₁C

w_P1

w_P2

R

where

G_PWM= PWM gain.

V_M= 1.0V, ramp peak to valley voltage of SC4624A.

Figure 18. Asymptotic Diagrams

of Power Stage and Loop Gain

 2008 Semtech Corp.

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SC4624A

POWER MANAGEMENT

O eration

Application Information (Cont.)

Layout Guidelines

the big vias to the bottom layer during the re-ﬂow

In order to achieve optimal thermal and noise immunity process.

for high frequency converters, special attention must be

paid to the PCB layout. The goal of layout optimization

is to minimize the high di/dt loops and reduce ground

bounce.

Output voltage setting, line regulation, stability , switching

frequency and OCP trip point shifted are affected by a

poor layout. The following guidelines should be used to

ensure proper functions of the converters.

1. Both Power ground (PGND) and signal ground (AGND)

are separated.

2. A ground plane is recommended to minimize noise

and copper losses, and maximize heat dissipation.

3. Start the PCB layout by placing the power components

ﬁrst. Arrange the power circuit to achieve a clean

power ﬂow route.

4. Minimize all high di/dt loops. These loops pass high

di/dt current. Make sure the trace width is wide

enough to reduce copper losses in this loop. Ground

bounce happen to magnetic ﬂux changed and it is

proportional to a magnetic ﬁled which goes through

high di/dt loops.

5. The input ceramic capacitor (C_IN) should be close to

PV_INpins and PGND pins.

6. Both input ceramic capacitor gnd and output ceramic

capacitor gnd are at same port.

7. A RC snubber circuit between PV_INand PH pins is

helpful for stability operation. Be careful with power

derating of snubber circuit.

8. The V_CCbypass capacitor should be placed next to the

V_CCand AGND pins.

9. The OCP setting resistor (R_ISET) and ﬁlter capacitor

(C_ISET) should be placed next to the ISET and AGND

pins.

10. Feedback divider connects to output connector by

Kelvin connection and far away from the noise sources

such as switching node and switching components.

11. A multilayer chip beads between AGND and PGND

will reduce the ground bounce injected to the “quiet”

circuit. It’s helpful for stability operation.

12. A large copper area underneath the SC4624 IC is

necessary for heat sinking purpose. And multiple

layers of large copper area connected through vias

can be used for better thermal performance. The size

of the vias as the connection between multiple layers

should not be too large or solder may seep through

 2008 Semtech Corp.

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SC4624A

POWER MANAGEMENT

O eration

Application Information (Cont.)

5V_IN, 1V_OUT, 4A, all ceramic capacitors ( application circuit #1 )

5Vin

R6

10k

R5

10k

R2

10R

U1

C6

C3

R10

0R

1nF

1uF

7

6

12

13

5

VCC

AGND

FS

PGOOD

SYNC/EN

NC

47.5k

47nF

R11

9

C7

2.2pF

C2

C1

8

4

SS

R1

10

11

16

17

18

19

20

3

COMP

FB

NC

opt

C5

R3

390pF

20k

ISET

30k

1Vout@4A

L1

1.8uH

1

PH

PVIN

C8

270pF

2

PH

PVIN

R7

R8

2.32k

C9

28.7k

15

14

PH

PGND

SC4624A

C4

22uF

NC

R9

28.7k

(2)

R12

MLB-160808-0600R-S2

C11

opt

R4

opt

VIN=5V; Vout=1V/4A

Switching Frequency=550kHz

L1: TOKO D104C(919AS-1R8N)

Note: (1,2) Option for stability

R12: Multilayer chip inductors; MLB-160808-0600R-S2

Input(C9)/Output Capacitors(C4): Panasonic ECJ33YBOJ226M(22uF/6.3V)

 2008 Semtech Corp.

17

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SC4624A

POWER MANAGEMENT

Operation

PCB Layout

Component Side (TOP)

(TOP layer)

(Bottom layer)

(IN1 layer)

(IN2 layer)

 2008 Semtech Corp.

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SC4624A

POWER MANAGEMENT

Outline Drawing - MLPQ - 20

B

E

DIMENSIONS

INCHES MILLIMETERS

MIN NOM MAX MIN NOM MAX

A

D

DIM

A

.031

.039

0.90 1.00

.035

.001

0.80

A1 .000

.002 0.00 0.02 0.05

-

(.008)

(0.20)

0.25 0.30

A2

b

D

D1

E

.007

.010 .012 0.18

.154 .157 .161 3.90 4.00 4.10

2.70

PIN 1

INDICATOR

.100 .106 .110 2.55

.154 .157 .161 3.90 4.00 4.10

2.70 2.80

2.80

(LASER MARK)

E1 .100

.106 .110 2.55

e

.020 BSC

0.50 BSC

L

.012 .016 .020 0.30 0.40 0.50

N

20

aaa

.004

0.10

bbb

A2

C

A

SEATING

PLANE

aaa

C

A1

D1

LxN

E/2

E1

2

1

N

bxN

bbb

C A B

e

D/2

NOTES:

1.

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).

COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

2.

Land Pattern - MLPQ - 20

K

DIMENSIONS

DIM

INCHES

(.156)

.122

.106

.020

.010

.033

.189

MILLIMETERS

(3.95)

3.10

C

G

H

K

P

X

Y

Z

2.70

0.50

0.25

0.85

4.80

G

Y

(C)

H

X

P

NOTES:

1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.

CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR

COMPANY'S MANUFACTURING GUIDELINES ARE MET.

2.

THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD

SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.

FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR

FUNCTIONAL PERFORMANCE OF THE DEVICE.

Contact Information

Semtech Corporation

Power Management Products Division

200 Flynn Road, Camarillo, CA 93012

Phone: (805) 498-2111 Fax: (805) 498-3804

www.semtech.com

 2008 Semtech Corp.

19

www.semtech.com


型号：	SC4624A
厂家：	SEMTECH CORPORATION
描述：	Low Input Voltage, High Efficiency, 4A Integrated FET Synchronous Step down DC/DC Regulator 低输入电压，高效率， 4A集成FET同步降压型DC / DC稳压器稳压器
文件：	总19页 (文件大小：1303K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SC4624A [SEMTECH]

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