SC4905A [SEMTECH]
High Performance Voltage Mode PWM Controller; 高性能电压模式PWM控制器
| 型号： | SC4905A |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | High Performance Voltage Mode PWM Controller |
| 文件： | 总24页 (文件大小：365K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC4905A/B
High Performance Voltage Mode
PWM Controller
POWER MANAGEMENT
Description
Features
The SC4905A/B is a 10 pin BICMOS primary side voltage
mode controller for use in Isolated DC-DC and off-line
switching power supplies. It is a highly integrated solution,
requiring few external components. The device features a
high speed oscillator with integrated feed forward
compensation, accurately programmable maximum duty
cycle, voltage mode of operation, line voltage monitoring,
supply UVLO, low start up current, low voltage current limit
threshold and user accessible reference.
Operation to 1MHz
Accurate programmable maximum duty cycle
Integrated oscillator/voltage feed forward
compensation
Line voltage monitoring
External frequency synchronization
Bi-phase mode of operation for ripple reduction
Under 100µA start-up current
Accessible reference voltage
VDD undervoltage lockout
The SC4905A/B device operates at a fixed frequency,
highly desirable for Telecom applications. Features a
separate SYNC pin which simplifies synchronization to
an external clock. Feeding the oscillator of one device to
the SYNC of another forces biphase operation (180
degrees apart) which reduces input ripple and filter size.
-40°C to 105°C operating temperature
10-Pin MSOP Lead-free package available.
Fully WEEE and RoHS compliant
Applications
Telecom equipment and power supplies
Networking power supplies
Power over LAN applications
Industrial power supplies
The SC4905A has a typical turn-on threshold of 4.4V
and the SC4905B has a typical turn-on threshold of
about 11.6 volts.
Isolated power supplies
These devices are available in the 10 lead MSOP
package.
Typical Application Circuit
Revision: January 4, 2006
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SC4905A/B
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the
Electrical Characteristics section is not implied.
Parameter
Symbol
Maximum
Units
V
Supply Voltage
18
Input Voltage (RC, ILIM)
Input Voltage (VFF)
Input Current (VFF)
-0.3 to VREF + 0.3
V
-0.3 to VREF + 0.7
V
2
mA
V
Input Voltage (FB)
-0.3 to VREF + 0.7
Output Current (REF) DC
OUT
5
-0.3 to VREF + 0.3
180
mA
V
Power Dissipation
mW
°C
°C
°C
KV
Storage Temperature Range
Junction Temperature
Lead Temperature (Soldering) 10 Sec.
ESD Rating (Human Body Model)
TSTG
TJ
-65 to +150
-55 to +150
+300
TLEAD
ESD
2
Electrical Characteristics
Unless otherwise specified, VDD = 12V, VIN = 48V, ROSC = 499k, COSC = 220pF, RT = 280k, RM = 2k, RB = 8.25k, CVDD = 0.1uF, Ta = Tj = -40 to 105 °C.
Parameter
Test Conditions
Min
Typ
Max
Unit
Supply Curent Section
Startup Current
VDD = UVLO Start - 1, VDD
Comparator Off
100
4.2
µA
IDD Active
VDD = Comparator On,
Oscillator Running
3.5
mA
Line Under Voltage Lockout
Start Threshold
Voltage measured at VFF pin
VFF = 1.2V +/- 3%
1.164
85
1.200
100
1.236
115
V
Hysteresis
mV
nA
I (VFF)
-300
300
IB
Oscillator Section
Maximum Frequency
CT Peak Voltage (1)
V
FF = 1.2V to 4.8V
VFF = 1.2V
0.8
1.0
1.2
3.6
200
1.2
MHz
V
VFF = 3.6V
V
CT Valley Voltage (1)
Sync/CLOCK
mV
Clock SYNC Threshold
Sync Input Detect Time (1)
.45 *VFF
.50 *VFF
50
.55 *VFF
V
FSYNC > Fosc
nS
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SC4905A/B
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless otherwise specified, VDD = 12V, VIN = 48V, ROSC = 499k, COSC = 220pF, RT = 280k, RM = 2k, RB = 8.25k, CVDD = 0.1uF, Ta = Tj = -40 to 105 °C.
Parameter
Test Conditions
Min
Typ
Max
Unit
Sync/CLOCK (Cont.)
(1)
Sync Frequency
1.2 *FOSC
Hz
Current Limit Section
Input Bias Current
0
-2
µA
mV
ns
Current Limit Threshold
Propagation Delay, ILIM to OUT (1)
VREF Section
170
200
35
230
50mV Overdrive
VREF (A version)
0 - 5mA
0 - 5mA
-3%
-3%
4
5
+3%
+3%
V
V
VREF (B version)
VDD UVLO Section (A version)
Start Threshold
4.1
11
4.4
4.6
V
Hysteresis
200
300
mV
VDD UVLO Section (B version)
Start Threshold
11.6
3.6
12
4
V
V
Hysteresis
Pulse Width Modulator Section
FB Input current
Minimum Duty Cycle (1)
Maximum Duty Cycle
PWM Gain (1)
VFB = 0V to Vref
VFB < 500mV
1
0
uA
%
V
DMAX = VFF , VFB = Vref
VFF = 3.6
95
27.5
75
%
%/V
ns
Propagation Delay, PWM to OUT (1)
Output
Output VSAT Low
Output VSAT High
Rise Time (1)
Fall Time (1)
IOUT = 1mA
500
mV
V
IOUT = 1mA
VREF - 0.5
COUT = 20pF
COUT = 20pF
10
10
ns
ns
Note 1: Guaranteed by design. Not 100% tested in production.
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SC4905A/B
POWER MANAGEMENT
Pin Configuration
Ordering Information
Part Number
SC4905AIMSTR
SC4905AIMSTRT(2)
SC4905BIMSTR
SC4905BIMSTRT(2)
Package(1) Temp. Range (TA)
(Top view)
VDD
FB
REF
MSOP-10
-40°C to 105°C
OUT
GND
ILIM
VFF
DMAX
RC
Notes:
SYNC
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
(2) Lead free product. This product is fully WEEE and
RoHS compliant.
(MSOP-10)
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SC4905A/B
POWER MANAGEMENT
Pin Descriptions
Where VFF is the voltage at the VFF pin at a given Vin,
frequency is in Hertz, resistance in ohms, and capaci-
tance in farads.
The recommended range if timing resistors is between
10 kohm and 500kohm and range of timing capacitors
is between 100pF and 1000pF. Timing resistors less
than 10 kohm should be avoided.
VDD: The supply input for the device. Once VDD has ex-
ceeded the UVLO limit, the internal reference, oscillator,
drivers and logic are powered up. This pin should be by-
passed with a low ESR capacitance right at the IC pin to
minimize noise problems, and to ensure proper opera-
tion.
Refer to layout guide lines on page 12 to achieve best
results.
FB: Input to the PWM comparator with an offset voltage
of 700mV. The feedback analog signal from the output
of an error amplifier or an Optoisolator will be connected
to this pin to provide regulation.
SYNC: SYNC is a positive edge triggered input with a
threshold precisely set to
VFF: The VFF pin provides the controller with a voltage
proportional to the power supply input voltage to achieve
feed-forward function. RM plus RB in conjunction with RT
will set the Vff level (see page 1 circuit).
0.5*VFF
In the Bi-Phase operation mode SYNC pins should be con-
nected to the Cosc (Timing Capacitors) of the other con-
troller. This will force a 180° out of phase operation.
(see page9).
In a single controller operation, SYNC could be grounded
or connected to an external synchronization clock with Fre-
quency higher than the on board oscillator Frequency (see
page 2).
(
RB + RM
)
VFF =
× VIN
(
RT + RB + RM
)
DMAX: Programmable duty cycle is achieved via resis-
tive divider from the VFF. The duty cycle percentage is
set by the ratio of the divider RM, and RB (see page 1
circuit) from the VFF signal. When RM is shorted, maxi-
mum duty cycle of 100% is achieved. RM plus RB in con-
junction with RT will also be used as the divider to set the
Vff level.
ILIM: Current sense input is provided via the ILIM pin.
The current sense input from a sense resistor provides a
pulse by pulse current limit by terminating the PWM pulse
when the input is above 180mV.
GND: Device power and analog ground. Careful atten-
tion should be paid to the layout of the ground planes
(see page 12).
VDMAX
DutyCycle% =
VFF
RC: The oscillator programming pin. The oscillator should
be referenced to Vin to achieve the line feed forward func-
tion. Only two components are required to program the
oscillator, a resistor ROSC (tied to the Vin and RC), and a
capacitor COSC (tied to the RC and GND). Since the peak
oscillator voltage is VFF, constant frequency operation is
maintained over the full power supply. When the DMAX
pin is shorted to the VFF pin, the oscillator can run at the
largest duty cycle possible.
OUT: The output is intended to drive an external FET driver
or other high impedance circuit. The output voltage swings
from GND to Vref with a typical output impedance of 500Ω.
REF: The REF pin provides a 4 or 5V user accessible
voltage reference. This pin should be decoupled with a
1µF capacitor.
Following formula can be used for a close approximation
of the Oscillator Frequency.
VFF
2
Vin−
FOSC
(R
OSC • COSC • VFF• 1.05
)
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SC4905A/B
POWER MANAGEMENT
Block Diagram
Marking Information
SC4905AIMSTR
Top Mark
SC4905BIMSTR
Top Mark
ALOA
yyww
ALOB
yyww
Bottom Mark
Bottom Mark
yyww = Date Code (Example: 0012)
xxxx
xxxx
xxxx
xxxx
xxxx = Semtech Lot No. (Example: E901
xxxx
01-1)
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SC4905A/B
POWER MANAGEMENT
Application Information
THEORY OF OPERATION
The SC4905 is a versatile 10 pin BICMOS primary side This feed forward action provides an immediate duty cycle
adjustment while maintaining a constant oscillator fre-
quency.
A maximum duty cycle can be programmed by connect-
ing a resistor divider from the VFF to the DMAX pin. The
scaling of the VFF signal will set the maximum duty cycle
percentage.
voltage mode controller optimized for applications requir-
ing minimum space such as isolated DC-DC and off-line
switching power supplies.
The device contains all of the control and drive circuity
required for isolated or non-isolated power supplies,
where an external error amplifier is used. Fixed oscillator
frequency up to 1MHz can be programmed by an exter-
nal RC network.
An external error amplifier will provide the error signal to
the FB pin of the SC4905.
The SC4905 is a voltage mode controller, utilizing a feed A current sense input is provided via the ILIM pin. The
forward scheme to accommodate for any variations in
the input supply voltage resulting in a duty cycle
adjustment. This feed forward action results in an
improved dynamic performance of the converter.
The SC4905 also provides a programmable maximum duty
cycle to prevent core saturation when a transformer is used.
As an added level of protection, SC4905 provides a cycle
current sense input from a sense resistor is used for the
peak current limit comparator.
Once VDD has exceeded the UVLO (VDD under voltage
lock out) limit, the internal reference, oscillator, drivers and
logic are powered up.
SYNC is a positive edge triggered input with a threshold
set to 0.5*VFF.
By connecting a faster external control signal to the SYNC
pin, the internal oscillator frequency will be synchronized
to the positive edge of the external control signal. In a
single controller operation, SYNC could be grounded or
connected to an external synchronization clock within the
SYNC frequency (see page 3).
In the Bi-Phase operation mode a very unique oscillator
is utilized to allow two SC4905 to be synchronized
together and work out of phase. This feature is setup by
simple connection of the SYNC input to the RC pin of the
other part. The fastest oscillator automatically becomes
the master, forcing the two PWMs to operate out of
phase. This feature minimizes the input and output
ripples, and reduces stress on the capacitors.
by cycle peak current limit during an over current condition.
SUPPLY
A single supply, VDD is used to provide the bias for the
internal reference, oscillator, drivers, and logic circuitry
of the SC4905.
PWM CONTROLLER
The SC4905 is a BICMOS primary side voltage mode
controller for use in isolated DC-DC and off-line switch-
ing power supplies. It is a highly integrated solution, re-
quiring few external components.
The device features a high speed oscillator with integrated
feed forward compensation, accurately programmable
maximum duty cycle, voltage mode of operation, line volt-
age monitoring, supply UVLO, low start-up current, low
voltage current limit threshold and user accessible refer-
ence.
Two voltage options are available for the SC4905. The
SC4905A version has a typical VDD under voltage of
4.4V, and a 4V reference, while the SC4905B version
provides a 11.6V VDD UVLO, and a 5V reference.
The Oscillator frequency is programmed by a resistor and
a capacitor network connected to the line supply voltage .
Any variations in the input supply voltage result in a duty
cycle adjustment, provided by the change of the oscillator
peak voltage via the VFF pin.
Typical
Typical
Device
Vdd UVLO
Reference Voltage
SC4905A
SC4905B
4.4V
4V
5V
11.6V
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SC4905A/B
POWER MANAGEMENT
Application Information (Cont.)
VDD UNDER VOLTAGE LOCK OUT
According to the application, and the voltages available,
the SC4905A (UVLO = 4.4V), or the SC4905B (UVLO =
11.6V) can be used to provide the VDD undervoltage
lock out function to ensure the converters controlled
start up.
Since the Rosc is referenced to the input supply voltage,
any variation in the supply is directly translated into a
variation in the duty cycle, while maintaining the fixed
frequency operation.
Following equation can be used to calculate the oscilla-
tor frequency:
Before the VDD UVLO has been reached, the internal ref-
erence, oscillator, OUT driver, and logic are disabled.
VFF
REFERENCE
Vin −
2
FOSC
A 4V (SC4905A) or a 5V(SC4905B) reference voltage is
available that can be used to source a typical current
up to 5mA to the external circuitry. The REF can be used
to provide the feed back circuitry with a regulated bias.
(
R
OSC • COSC • VFF• 1.05
)
The recommended range if timing resistors is between
10 kohm and 500kohm and range of timing capacitors
is between 100pF and 1000pF. Timing resistors less
than 10 kohm should be avoided.
OSCILLATOR
The oscillator frequency is set by connecting a RC network
as shown below.
Vin
SC4905
U1
1
2
3
4
5
10
9
VDD
FB
REF
OUT
GND
ILIM
RT
280k
Rosc
499k
8
VFF
DMAX
RC
7
RM
2k
6
SYNC
RB
Cosc
8.25k
220p, 16V
The oscillator has a ramp voltage that will track the volt-
age at the VFF pin (1.2V<VFF<3.6V). The oscillator peak
voltage is derived by charging the oscillator capacitor (Cosc)
to the VFF voltage via the oscillator resistor (Rosc). The
bias current to charge the Cosc is controlled by the Rosc.
Once the RC pin has reached the VFF voltage, the oscil-
lator ramp is discharged by an internal switch hence cre-
ating the triangle oscillator ramp.
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SC4905A/B
POWER MANAGEMENT
Application Information (Cont.)
FEED FORWARD & MAXIMUM DUTY CYCLE
The feed forward function provided by the SC4905 will
improve the dynamic performance of the converter in
response to the changes in the input supply.
In voltage mode controllers without the voltage feed for-
ward circuitry, any changes in the input supply will cause
an error in the output voltage which is sensed by the error
amplifier and eventually is translated to an adjustment in
the duty cycle by the controller. This delay in the response
will cause the slower dynamic performance of the con-
verter.
If the application does not require an upper limit on the
duty cycle, the VFF pin should be connected to the DMAX
pin. In this mode, the duty cycle will be allowed to increase
to the maximum limit of about 100%.
SYNC/Bi-Phase operation
In noise sensitive applications where synchronization of
the oscillator frequency to a reference frequency is re-
quired, the SYNC pin can accept the external clock.By
connecting an external control signal to the SYNC pin,
the Internal oscillator frequency will be synchronized to
the positive edge of the external control signal. SYNC is
a positive edge triggered input with a threshold set to
0.5*VFF.
This problem is resolved by sensing the input supply line
and making the adjustment in the duty cycle immediately
at the PWM controller.
Vin
In a single controller operation, SYNC chould be grounded
or connected to an external synchronization clock within
the SYNC frequency (see page 3).
SC4905
U1
1
2
3
4
5
10
9
VDD
FB
REF
OUT
R14
280k
R15
499k
Shut Down
VIN
8
VFF
DMAX
RC
GND
ILIM
7
R16
2k
6
U1
U2
SYNC
1
2
3
4
5
10
9
1
2
3
4
5
10
9
VDD
FB
REF
OUT
VDD
FB
REF
OUT
Rosc1
Cosc1
Rosc2
Cosc2
R18
C27
220p, 16V
8
8
VFF
DMAX
RC
GND
ILIM
VFF
DMAX
RC
GND
ILIM
8.25k
7
7
6
6
SYNC
SYNC
SC4905
SC4905
The SC4905 uses the input supply line as the bias for
the oscillator circuitry, and the VFF pin. Any changes in
the line will cause the ramp peak voltage to be adjusted
to the VFF pin voltage while maintaining the oscillator
frequency unchanged.
The VFF pin can also be used to shut down the SC4905
if it is pulled down to GND by an open collector circuitry.
This can be useful for overvoltage protection or other
control signals.
The SC4905 also provides a programmable duty cycle,
that can be set by an external voltage divider from the
VFF pin. The ratio of the divider will determine the pro-
grammed duty cycle allowed.
In the Bi-Phase operation mode a very unique oscillator
is utilized to allow two SC4905 to be synchronized
together and work out of phase. This feature is setup by
simple connection of the SYNC input to the RC pin of the
other part. The fastest oscillator automatically becomes
the master, forcing the two PWMs to operate out of
phase. This feature minimizes the input and output
ripples, and reduces stress on the capacitors.
VDMAX
DutyCycle% =
VFF
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SC4905A/B
POWER MANAGEMENT
Application Information (Cont.)
FEED BACK
GATE DRIVERS
The error signal from the output of an external Error am-
plifier such as SC431 or SC4431 is applied to the invert-
ing input of the PWM comparator at the FB pin either
directly or via an opto coupler for the Isolated applica-
tions. For best stability keep the FB trace length as short
as possible.
OUT is a CMOS gate drive output stage that is supplied
from REF and provides a peak source/sink current of
about 1mA. The output stage is capable of driving the
logic input of external MOSFET Drivers and is switched at
the oscillator frequency. When the voltage on the RC pin
is rising,, the output is high.
It should be noted that if high speed/high current drivers
such as the SC1301 are used, careful layout must be
followed in order to minimize stary inductance, which
might cause negative voltages at the output of the driv-
ers. This negative voltage can be clamped to reasonable
level by placing a small Schottky diode directly at the
output of the driver as shown below.
REF
4.7nF C36
Secondary Supply
Vout
R22
1.1k
22pF
C31
R25
100k
C33
R24
680pF
FB
6
5
3
4
C32
1nF
C30
NA
3.74k
R29
NA
R23
5.1k
R26
1
5
80.2k
MOCD207
4
C34
C35
0.1u,16V
22n, 16V
U6
SC4431
R27
9.1k
Vref
REF VDD
VDD
Mosfet Gate
2
0
R13
SC1301A
SC4905
U1
3
5
C17
C18
The signal at the FB pin is then compared to the ramp
signal from the RC pin and the OUT gate drive signal is
generated.
Voltages below 600mV at the FB pin, will produce a 0%
duty cycle at the OUT drive. Maximum duty cycle is pro-
duced when VFB-600mV>VFF. The FB signal range is from
600mv to 4V.
1
2
3
4
5
10
9
D8
VDD
REF
OUT
C22
1
FB
4
8
VFF
DMAX
RC
GND
ILIM
D11
2
7
U2
6
SYNC
SOFT START
During start up of the converter, the discharged output
capacitor, and the load current demand large supply cur-
rent requirements. To avoid this a soft start scheme is
usually implemented where the duty cycle of the regula-
tor is gradually increased from 0% until the soft start
duration is elapsed.
Programmable soft start duration can implemented ex-
ternally by utilizing a simple external circuitry shown be-
low.
OVER CURRENT
A pulse by pulse current limit is provided by the SC4905.
The current information is sensed at the ILIM pin and
compared to a peak current limit level of 180mV. If the
180mV limit is exceeded, the OUT pulse is terminated.
REF VDD
REF
SC4905
R13
0
U1
R22
1.1k
SC4905
1
2
3
4
5
VDD
FB
REF
OUT
U1
C17
C26
1
2
3
4
5
10
9
6
VDD
FB
REF
OUT
3
4
9
8
7
6
C22
C30
M1
VFF
DMAX
RC
GND
ILIM
8
5
VFF
GND
ILIM
7
R17
56.2K
DMAX
RC
MOCD207
Csoft start
6
SYNC
SYNC
R30
Rsense
D7
D15
R11
VDD
SC1301A
C18
3
5
D8
Approximate soft start duration can be calculated as be-
low:
1
4
D11
U2
2
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SC4905A/B
POWER MANAGEMENT
Application Information (Cont.)
START UP SEQUENCE
Initially during the power up, the SC4905 is in the under
voltage lock out condition. As the VDD supply exceeds
the UVLO limit of the SC4905 and the VFF pin exceeds
the line under voltage lock out of about 1.2V, the inter-
nal reference, oscillator, and logic circuitry are powered
up.
The OUT driver is not enabled until the line under voltage
lock out limit is reached. At that point, once the FB pin
has reached above 600mV, the output driver is enabled.
As the output voltage starts to increase, the error signal
from the error amplifier starts to decrease. If isolation is
required, the error amplifier output can drive the LED of
the opto isolator. The output of the opto is connected in
a common emitter configuration with a pull up resistor to
a reference voltage connected to the FB pin of the
SC4905. The voltage level at the FB pin provides the duty
cycle necessary to achieve regulation.
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SC4905A/B
POWER MANAGEMENT
Application Information (Cont.)
LAYOUT GUIDELINES
Careful attention to layout requirements are necessary for
successful implementation of the SC4905 PWM control-
ler.
High currents switching are present in the application
and their effect on ground plane voltage differentials must
be understood and minimized.
7) If an opto isolator is used for isolation, quiet primary
and secondary ground planes should be used. Same
precautions should be followed for the primary GND plane
as mentioned in item 5 mentioned above. For the sec-
ondary GND plane, the GND plane method mentioned
in item 4 should be followed.
1). The high power parts of the circuit should be laid out
first. A ground plane should be used. The number and
position of ground plane interruptions should be such as
to not unnecessarily compromise ground plane integrity.
Isolated or semi-isolated areas of the ground plane may
be deliberately introduced to constrain ground currents to
particular areas, for example the input capacitor and FET
ground.
2). The loop formed by the Input Capacitor(s) (Cin), the
FET must be kept as small as possible. This loop contains
all the high current, fast transition switching. Connections
should be as wide and as short as possible to minimize
loop inductance. Minimizing this loop area will a) reduce
EMI, b) lower ground injection currents, resulting in electri-
cally “cleaner” grounds for the rest of the system and c)
minimize source ringing, resulting in more reliable gate
switching signals.
8) All the noise sensitive components such as VFF, DMAX
resistive divider, reference by pass capacitor, VDD bypass
capacitor, current sensing circuitry, feedback circuitry, and
the oscillator resistor/capacitor network should be con-
nected as close as possible to the SC4905. The GND
return should be connected to the quiet SC4905 GND
plane.
9) The connection from the OUT of the SC4905 should be
minimized to avoid any stray inductance. If the layout
can not be optomized due to constraints, a small
Schottky diode maybe connected from the OUT pin to
the ground directly at the IC. This will clamp excessive
negative voltages at the IC. If drivers are used, the
Schottky diodes should be connected directly at the IC,
from the output of the driver to the driver ground.
10) If the SYNC function is not used, the SYNC pin should
be grounded at the SC4905 GND to avoid noise pick up.
3). The connection between FETs and the Transformer
should be a wide trace or copper region. It should be as
short as practical. Since this connection has fast voltage
transitions, keeping this connection short will minimize EMI.
4) The output capacitor(s) (Cout) should be located as
close to the load as possible. Fast transient load cur-
rents are supplied by Cout only. Connections between
Cout and the load must be short, wide copper areas to
minimize inductance and resistance.
5) The SC4905 is best placed over a quiet ground plane
area. Avoid pulse currents in the Cin FET loop flowing in
this area. GND should be returned to the ground plane
close to the package and close to the ground side of (one
of) the VDD supply capacitor(s). Under no circumstances
should GND be returned to a ground inside the Cin and
FET loop. This can be achieved by making a star connec-
tion between the quiet GND planes that the SC4905 will
be connected to and the noisy high current GND planes
connected to the FETs.
6) The feed back connection between the error amplifier
and the FB pin should be kept as short as possible, and
the GND connections should be to the quiet GND used for
the SC4905.
2006 Semtech Corp.
12
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SC4905A/B
POWER MANAGEMENT
Typical Step Load
Vout
20mV/Div
Iout
0.5A/Div
500us/Div
Cout = 6X100uF (600uF) Tantalum
Typical SC4905 Forward converter Step Load plot at Vin = 48V, Vout = 12V, Step = 50% to 75% Iout, Fosc = 245kHz
2006 Semtech Corp.
13
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SC4905A/B
POWER MANAGEMENT
SC4905A Typical Characteristics
(SC4808A)
198
197
196
195
194
193
192
191
190
78
Current limit rising
Start up Iq, Vdd = 3V
76
74
72
70
68
66
64
-40
-25
-10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
Ta (°C)
Ta (°C)
Iq (start up) vs. Temperature
Current Limit vs. Temperature
3.200
3.100
3.000
2.900
2.800
2.700
2.600
65
60
55
50
45
40
35
Idd Active, Vdd = 4V
Current limit Input current
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40
-25
-10
5
20
35
50
65
80
95
110 125
Ta (°C)
Ta (°C)
Idd (operating) vs. Temperature
Current Limit bias current vs. Temperature
4.025
4.020
4.015
4.010
4.005
4.000
3.995
4.55
Vdd UVLO (Rising)
Vdd UVLO (Falling)
Reference, Iref = 0mA, Vdd = 5V
Reference, Iref = 5mA, Vdd = 5V
4.50
4.45
4.40
4.35
4.30
4.25
4.20
4.15
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
Ta (°C)
Ta (°C)
Reference vs. Temperature
Vdd UVLO vs. Temperature
2006 Semtech Corp.
14
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SC4905A/B
POWER MANAGEMENT
SC4905A Typical Characteristics (Cont.)
0.250
220
200
180
160
140
120
100
80
Vdd UVLO (Hysteresis)
Input Bias current IFF
0.240
0.230
0.220
0.210
0.200
0.190
0.180
0.170
60
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
Ta (°C)
Ta (°C)
Vdd UVLO Hysteresis vs. Temperature
Vff pin leakage current vs. Temperature
1.240
1.220
1.200
1.180
1.160
1.140
1.120
1.100
1.080
1400
1200
1000
800
LUVLO (Rising)
LUVLO (falling)
Oscillator Frequency 1MHz
Oscillator Frequency 300kHz
600
400
200
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
Ta (°C)
Ta (°C)
Line UVLO vs. Temperature
Oscillator Frequency vs. Temperature
200
180
160
140
120
100
80
103.6
103.5
103.5
103.4
103.4
103.3
103.3
103.2
103.2
103.1
103.1
LUVLO (Hysteresis)
Input leakage current Irc
-40
-25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Ta (°C)
Ta (°C)
Line UVLO Hysteresis vs. Temperature
RC pin leakage current vs. Temperature
2006 Semtech Corp.
15
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SC4905A/B
POWER MANAGEMENT
SC4905A Typical Characteristics (Cont.)
1.792
0.075
0.070
0.065
0.060
0.055
0.050
0.045
0.040
0.035
0.030
Vout Low, Vdd = 4V
Sync. Threshold
1.790
1.788
1.786
1.784
1.782
1.780
1.778
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40
-25
-10
5
20
35
50
65
80
95
110
125
Ta (°C)
Ta (°C)
Synchronization Threshold vs. Temperature
VOUT Low vs. Temperature
280
3.942
3.940
3.938
3.936
3.934
3.932
3.930
3.928
3.926
Input leakage current IFB, Vfb = 0
Vout High, Vdd = 4V
260
240
220
200
180
160
140
120
100
-40
-25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Ta (°C)
Ta (°C)
FB pin leakage current vs. Temperature
VOUT high vs. Temperature
2006 Semtech Corp.
16
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SC4905A/B
POWER MANAGEMENT
SC4905B Typical Characteristics
209
208
207
206
205
204
203
202
201
200
199
79
78
77
76
75
74
73
72
71
70
Current limit rising
Start up Iq, Vdd = 3V
-40
-25
-10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
Ta (°C)
Ta (°C)
Iq (start up) vs. Temperature
Current Limit vs. Temperature
3.460
3.410
3.360
3.310
3.260
3.210
3.160
3.110
3.060
70
60
50
40
30
20
10
0
Idd Active, Vdd = 4V
Current limit Input current
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40
-25
-10
5
20
35
50
65
80
95
110 125
Ta (°C)
Ta (°C)
Idd (operating) vs. Temperature
Current Limit bias current vs. Temperature
5.030
5.025
5.020
5.015
5.010
5.005
5.000
13.00
Vdd UVLO (Rising)
Vdd UVLO (Falling)
Reference, Iref = 0mA, Vdd = 5V
Reference, Iref = 5mA, Vdd = 5V
12.00
11.00
10.00
9.00
8.00
7.00
6.00
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Ta (°C)
Ta (°C)
Reference vs. Temperature
Vdd UVLO vs. Temperature
2006 Semtech Corp.
17
www.semtech.com
SC4905A/B
POWER MANAGEMENT
SC4905B Typical Characteristics (Cont.)
200
180
160
140
120
100
80
3.740
Vdd UVLO (Hysteresis)
Input Bias current IFF
3.720
3.700
3.680
3.660
3.640
3.620
3.600
3.580
60
-40
-25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Ta (°C)
Ta (°C)
Vdd UVLO Hysteresis vs. Temperature
Vff pin leakage current vs. Temperature
1.240
1.220
1.200
1.180
1.160
1.140
1.120
1.100
1.080
1400
1200
1000
800
LUVLO (Rising)
LUVLO (falling)
Oscillator Frequency 1MHz
Oscillator Frequency 300kHz
600
400
200
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
Ta (°C)
Ta (°C)
Line UVLO vs. Temperature
Oscillator Frequency vs. Temperature
200
180
160
140
120
100
80
101.8
101.7
101.6
101.5
101.4
101.3
101.2
101.1
101.0
100.9
LUVLO (Hysteresis)
Input leakage current Irc
-40
-25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Ta (°C)
Ta (°C)
Line UVLO Hysteresis vs. Temperature
RC pin leakage current vs. Temperature
2006 Semtech Corp.
18
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SC4905A/B
POWER MANAGEMENT
SC4905B Typical Characteristics (Cont.)
1.796
0.060
0.055
0.050
0.045
0.040
0.035
0.030
Vout Low, Vdd = 4V
Sync. Threshold
1.794
1.792
1.790
1.788
1.786
1.784
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40
-25
-10
5
20
35
50
65
80
95
110
125
Ta (°C)
Ta (°C)
Synchronization Threshold vs. Temperature
Vout Low vs. Temperature
190
4.958
4.957
4.956
4.955
4.954
4.953
4.952
4.951
4.950
4.949
4.948
Input leakage current IFB, Vfb = 0
Vout High, Vdd = 4V
180
170
160
150
140
130
120
110
100
-40
-25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Ta (°C)
Ta (°C)
FB pin leakage current vs. Temperature
Vout high vs. Temperature
2006 Semtech Corp.
19
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SC4905A/B
POWER MANAGEMENT
Evaluation Board Schematics
2006 Semtech Corp.
20
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SC4905A/B
POWER MANAGEMENT
Evaluation Board Bill of Materials
Revised: Monday, March 8, 2003
SC4905 Single Switch Forward (RCD Reset) non Synchronous 12V 50W
Bill Of Materials
Revised: January 28,2002
Revision: 1b
Item Quantity
Reference
Part
Manufacturer #
Foot Print
1
2
3
4
5
6
7
8
1
1
2
6
5
1
2
3
CON1
5output_half_brick
3input_half_brick
470pF,100V
100u,16V
CON\5OUTPUT_HALF_BRICK
CON2
CON\3INPUT_HALF_BRICK
SM/C_0805
C11,C1
C2,C3,C4,C5,C6,C7
EEJL1CD476R
SM/C_0805
C8,C9,C14,C28,C34
0.1u,16V
C10
.47uF,100V
1u,100V
10u,16V
GHM1545X7R474K250 (Murata)
GRM44-1X7R105K250AL (Murata)
GRM42-2X5R106K16 (Murata)
SM/C_2220
C12,C13
SM/C_2220
C15,C16,C23
SM/C_1210_GRM
C17,C18,C19,C20,C21,C24,
9
7
1u, 16V
SM/C_0805
C25
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
2
1
1
1
1
1
1
2
1
2
1
1
C22
2.2u, 16V
220p, 16V
22n, 16V
NA
SM/C_0805
SM/C_0805
SM/C_0805
SM/C_0805
SM/C_0805
SM/C_0805
SM/C_0805
SM/C_0805
SM/C_2220
DIODE_DPAK
SM/DO214AA
SM/DO213AC
SMB/DO214
SOD123
C26,C27
C29,C35
C30
C31
22pF
C32
1nF
C33
680pF
C36
4.7nF
C37
.33uF,250V
MBRD660CT
MURA120T3
LS4448
C4532X7R2E334K (TDK)
D1,D2
D3
D4,D5
D6
D7
ZM4742A
1N5819HW
ZM4742A (Diodes Inc.)
D8,D9,D10,D11,D12,D13,
24
7
CMOSH-3
CMOSH-3 (Central Semiconductor)
SOD523
D15
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
1
1
1
1
1
1
1
1
1
2
3
1
1
2
2
1
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
2
2
1
D14
B140T
short
SM/DO213AC
VIA\2P
JP1
J1
REF
ED5052
J2
VDD
ED5052
L1
9uH
P1173.123T (Pulse)
LQH4N102K04 (Murata)
SUD15N15-95 (Vishay)
P1173
L2
LQH4N102K04
SUD15N15-95
OUT
SDIP0302
M1
DPAKFET
OUT
Q1
ED5052
FZT853
10
FZT853 (Zetex)
SM/SOT223_BCEC
SM/R_0805
SM/R_0805
SM/R_1206
SM/R_1210_MCR
SM/R_1210_MCR
SM/R_0805
ERJL1W
R5,R1
R2,R9,R13
R3
0
49.9k
R4
500
MRC1-100-5000-F-7
MRC1-100-5001-F-7
R6,R7
R8,R12
R10
5000
TBD
LR2512-01-R025FTR
2.2
LR2512-01-R025FTR (IRC)
R11
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
ED5052
R14
280k
R15
499k
R16
2k
R17
500
R18
8.25k
R22,R19
R20,R30
R24,R21
R23
1.1k
39.2k
3.74k
5.1k
R25
100k
R26
80.2k
R27
9.1k
R28
2.2k
R29
NA
SYNC1
T1
SYNC
PA0273
PE-68386
SC4905
SC1301A
SC4431
MOCD207
PA0273 (Pulse)
PE-68386 (Pulse)
SC4905 (Semtech)
SC1301A (Semtech)
SC4431 (Semtech)
MOCD207(Fairchild)
PA0273
T2
U1
PE-68386
MSOP10
U2,U3
U4,U6
U5
SOT23_5PIN
SOT23_5PIN
SO-8
2006 Semtech Corp.
21
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SC4905A/B
POWER MANAGEMENT
Evaluation Board Gerber Plots
Board Layout Assembly Top
Board Layout Assembly Bottom
Board Layout Top
Board Layout Bottom
2006 Semtech Corp.
22
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SC4905A/B
POWER MANAGEMENT
Evaluation Board Gerber Plots
Board Layout INNER1
Board Layout INNER2
2006 Semtech Corp.
23
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SC4905A/B
POWER MANAGEMENT
Outline Drawing - MSOP-10
DIMENSIONS
INCHES MILLIMETERS
e
DIM
A
A
MIN NOM MAX MIN NOM MAX
D
E
-
-
-
-
-
-
-
-
-
-
-
-
.043
1.10
0.15
0.95
0.27
0.23
N
A1 .000
A2 .030
.006 0.00
.037 0.75
.011 0.17
.009 0.08
b
c
D
.007
.003
2X
E/2
.114 .118 .122 2.90 3.00 3.10
E1
E1 .114 .118 .122 2.90 3.00 3.10
PIN 1
INDICATOR
E
.193 BSC
.020 BSC
4.90 BSC
0.50 BSC
e
L
L1
N
.016 .024 .032 0.40 0.60 0.80
ccc
C
1 2
(.037)
(.95)
10
10
2X N/2 TIPS
B
-
-
01
aaa
0°
8°
0°
8°
.004
.003
.010
0.10
0.08
0.25
bbb
ccc
D
aaa
C
H
A2
A
SEATING
PLANE
c
GAGE
A1
bxN
bbb
C
PLANE
C
A-B D
0.25
L
01
(L1)
DETAIL A
A
SEE DETAIL
SIDE VIEW
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MO-187, VARIATION BA.
Land Pattern - MSOP-10
X
DIMENSIONS
DIM
INCHES
(.161)
.098
MILLIMETERS
(4.10)
2.50
0.50
0.30
1.60
5.70
C
G
P
X
Y
Z
(C)
G
Y
Z
.020
.011
.063
.224
P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
2006 Semtech Corp.
24
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