SK10E151 [SEMTECH]

6-Bit D Register; 6位D注册
SK10E151
型号: SK10E151
厂家: SEMTECH CORPORATION    SEMTECH CORPORATION
描述:

6-Bit D Register
6位D注册

文件: 总5页 (文件大小:116K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
SK10/100E151  
6-Bit D Register  
HIGH-PERꢀORMANCE PRODUCTS  
ꢀeatures  
Description  
• 1100 MHz Toggle Frequency  
• Extended 100E VEE Range of –4.2V to –5.46V  
• Differential Outputs  
• Asynchronous Master Reset  
• Dual Clocks  
The SK10/100E151 offers 6 edge-triggered, high-speed,  
master-slave D-type flip-flops with differential outputs,  
designed for use in new high-performance ECL systems.  
This device is fully compatible with MC10E151 and  
MC100E151. The two external clock signals (CLK1, CLK2)  
are gated through a logical OR operation before use as  
clocking control for the flip-flops. Data is clocked into  
the flip-flops on the rising edge of either CLK1 or CLK2  
(or both). When both CLK1 and CLK2 are at a logic  
LOW, data enters the master and is transferred to the  
slave when either CLK or CLK2 (or both) go HIGH.  
• Internal 75KInput Pull-Down Resistors  
• ESD Protection of >4000V  
• Fully Compatible with MC10E/100E151  
• Specified Over Industrial Temperature Range:  
o
o
–40 C to +85 C  
• Available in 28-Pin PLCC Package  
The MR (Master Reset) signal operates asynchronously  
to make all Q outputs go to a logic LOW.  
PIN Description  
Pin  
D0–D5  
CLK1, CLK2  
MR  
ꢀunction  
ꢀunctional Block Diagram  
Data Inputs  
Clock Inputs  
Q0  
D0  
D1  
D2  
D3  
D4  
D5  
D
D
D
D
D
D
Master Reset  
True Outputs  
Q0*  
R
R
R
R
R
R
Q0–Q5  
Q0*–Q5*  
VCC0  
Q1  
Inverting Outputs  
VCC to Output  
Q1*  
Q2  
Q2*  
Q3  
Q3*  
Q4  
D5  
D4  
D3  
VEE  
D2  
D1  
D0  
26  
27  
28  
1
18  
17  
16  
15  
14  
13  
12  
Q4*  
Q4  
Q4*  
VCC  
Q3*  
Q3  
PLCC  
TOP VIEW  
Q5  
2
Q5*  
3
Q2*  
Q2  
4
CLK1  
CLK2  
MR  
www.semtech.com  
Revision 1/ꢀebruary 13, 2001  
1
SK10/100E151  
HIGH-PERꢀORMANCE PRODUCTS  
PIN Description (continued)  
Truth Tables  
Inputs  
Output  
Inputs  
CLK1  
Output  
Dn  
X
CLK1  
X
CLK2  
X
MR  
H
Qn(t+1)  
L
Dn  
L
CLK2  
MR  
L
Qn(t+1)  
u
u
L
L
H
u
L
L
L
u
u
u
H
L
L
H
H
L
L
Asynchronous Operation  
L
L
NOTES:  
H
X
L
H
1. H = HIGH Voltage Level  
2. L = LOW Voltage Level  
3. X = Dont Care  
4. t = Time Before Positive CLK Transition  
5. t+1 = Time After Positive CLK Transition  
6. u = LOW-to-HIGH Transition  
L
Qn(t)  
Qn(t)  
Qn(t)  
X
L
X
L
Synchronous Operation  
www.semtech.com  
Revision 1/ꢀebruary 13, 2001  
2
SK10/100E151  
HIGH-PERꢀORMANCE PRODUCTS  
Package Information  
28-Pin PLCC Package  
Y BRK  
S
S
N
M
M
N–  
A
R
0.007 (0.180)  
T
L – M  
Z
S
S
N
0.007 (0.180)  
T
L M  
D
PIN Descriptions  
L–  
M –  
C
E
0.004 (0.100)  
TSEATING PLANE  
G
J
G1  
D
W
VIEW S  
S
S
S
N
0.010 (0.250)  
T
L M  
V
28  
1
0.007(0.180)  
M
T
L M  
S
N
S
H
S
N
S
S
M
B
0.007 (0.180)  
T
L - M  
U
M
S
N
0.007 (0.180)  
+
T
L - M  
Z
K1  
K
+
G1  
0.010 (0.250)  
S
T L - M  
S
N
S
X
S
0.007 (0.180)  
M
T L M  
N
S
F
NOTES:  
1. Datums -L-, -M-, and -N - determined where top of  
lead shoulder exits plastic body at mold parting line.  
2. DIM G1, true position to be measured at Datum -T-,  
Seating Plane.  
3. DIM R and U do not include mold flash. Allowable  
mold flash is 0.010 (0.250) per side.  
4. Dimensioning and tolerancing per ANSI Y14.5M,  
1982.  
5. Controlling Dimension: Inch.  
6. The package top may be smaller than the package  
bottom by up to 0.012 (0.300). Dimensions R and  
U are determined at the outermost extremes of the  
plastic body exclusive of mold flash, tie bar burrs,  
gate burrs and interlead flash, but including any  
mismatch between the top and bottom of the plastic  
body.  
7. Dimension H does not include Dambar protrusion or  
intrusion. The Dambar protrusion(s) shall not cause  
the H dimension to be greater than 0.037 (0.940).  
The Dambar intrusion(s) shall not cause the H  
dimension to be smaller than 0.025 (0.635).  
INCHES  
MILLIMETERS  
DIM  
A
MIN  
MAX  
0.495  
0.495  
0.180  
0.110  
0.019  
MIN  
12.32  
12.32  
4.20  
MAX  
12.57  
12.57  
4.57  
0.485  
0.485  
0.165  
0.090  
0.013  
B
C
E
2.29  
2.79  
0.33  
0.48  
G
H
J
0.050 BSC  
0.032  
1.27 BSC  
0.026  
0.020  
0.025  
0.450  
0.450  
0.042  
0.042  
0.042  
--  
0.66  
0.51  
0.64  
11.43  
11.43  
1.07  
1.07  
1.07  
--  
0.81  
--  
--  
K
--  
--  
R
0.456  
0.456  
0.048  
0.048  
0.056  
0.020  
10o  
11.58  
11.58  
1.21  
1.21  
1.42  
0.50  
10o  
U
V
W
X
Y
Z
2o  
2o  
G1  
K1  
0.410  
0.040  
0.430  
--  
10.42  
1.02  
10.92  
--  
Revision 1/ꢀebruary 13, 2001  
3
www.semtech.com  
SK10/100E151  
HIGH-PERꢀORMANCE PRODUCTS  
DC Characteristics  
SK10/100E151 DC Electrical Characteristics (Notes 1, 2)  
(V – V = 4.2V to 5.46V; V  
loaded 50to V – 2.0V)  
CC  
CC  
EE  
OUT  
TA = –40oC  
TA = 0oC  
TA = +25oC  
TA = +85oC  
Symbol  
Characteristic  
Min  
Typ  
Max  
Min  
Typ  
Max  
Min  
Typ  
Max  
Min  
Typ  
Max  
Unit  
I
Input High Current  
150  
150  
150  
150  
µA  
IH  
Power Supply Current  
I
10EL  
44  
43  
78  
78  
44  
43  
78  
78  
44  
43  
78  
78  
44  
43  
78  
85  
mA  
mA  
EE  
100EL  
V
– V  
Power Supply Voltage  
4.2  
5.46  
4.2  
5.46  
4.2  
5.46  
4.2  
5.46  
V
CC  
EE  
AC Characteristics  
SK10/100E151 AC Electrical Characteristics  
(V  
V
= 4.2V to 5.46V ; V  
loaded 50to V 2.0V)  
CC  
CC EE  
OUT  
TA = –40oC  
TA = 0oC  
TA = +25oC  
TA = +85oC  
Symbol  
Characteristic  
Min  
Typ  
Max  
Min  
Typ  
Max  
Min  
Typ  
Max  
Min  
Typ  
Max  
Unit  
f
Maximum Toggle ꢀrequency  
1100 1400  
1100 1400  
1100 1400  
1100 1400  
MHz  
MAX  
Propagation Delay to Output  
t
t
PLH  
CLK  
MR  
436  
479  
534  
586  
471  
512  
575  
623  
494  
534  
602  
649  
553  
591  
670  
715  
ps  
ps  
PHL  
t
t
t
Setup Time, D  
0
–175  
175  
550  
0
–175  
175  
550  
0
–175  
175  
550  
0
–175  
175  
ps  
ps  
ps  
S
Hold Time, D  
350  
750  
350  
750  
350  
750  
350  
550  
H
Reset Recovery Time  
750  
RR  
Minimum Pulse Width  
CLK, MR  
t
400  
400  
400  
400  
ps  
ps  
ps  
PW  
tskew  
Within-Device Skew  
65  
65  
65  
65  
Output Rise/ꢀall Times  
(20% to 80%)  
t , t  
r
187  
561  
193  
531  
197  
494  
209  
417  
f
Notes:  
1. 10EL circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has  
been established. The circuit is in a test socket or mounted on a printed circuit board and transverse  
airflow greater than 500 lfpm is maintained. Outputs are terminated through a 50resistor to VCC 2.0V.  
2. 100K circuits are designed to meet the DC specification shown in the table where transverse airflow  
greater than 500 lfpm is maintained.  
3. For standard ECL DC specifications, refer to the ECL Logic Family Standard DC Specification Data  
Sheet.  
4. For part ordering description, see HPP Part Ordering Information Data Sheet.  
www.semtech.com  
Revision 1/ꢀebruary 13, 2001  
4
SK10/100E151  
HIGH-PERꢀORMANCE PRODUCTS  
Ordering Information  
Ordering Code  
SK10E151PJ  
Package ID  
28-PLCC  
28-PLCC  
28-PLCC  
28-PLCC  
Temperature Range  
Industrial  
Industrial  
Industrial  
Industrial  
SK10E151PJT  
SK100E151PJ  
SK100E151PJT  
Contact Information  
Semtech Corporation  
High-Performance Products Division  
Division Headquarters  
10021 Willow Creek Road  
San Diego, CA 92131  
Marketing Group  
1111 Comstock Street  
Santa Clara, CA 95054  
Phone: (408) 566-8776  
Phone: (858) 695-1808  
FAX:  
(858) 695-2633  
FAX: (408) 727-8994  
Revision 1/ꢀebruary 13, 2001  
5
www.semtech.com  

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