SK4435ATF [SEMTECH]
Line Transceiver, 4 Func, 4 Driver, 4 Rcvr, ECL, PQFP32, 5 X 5 MM, TQFP-32;
| 型号： | SK4435ATF |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Line Transceiver, 4 Func, 4 Driver, 4 Rcvr, ECL, PQFP32, 5 X 5 MM, TQFP-32 驱动 接口集成电路 驱动器 |
| 文件： | 总34页 (文件大小：1533K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SK44XX Family
Quad Buffer/Receiver
HIGH-PERFORMANCE PRODUCTS
SK44XX ꢀamily ꢀunctional Block Diagram
IN0
1
0
OUT0
IN0*
OUT0*
D
Q
D*
Q*
IN1
1
0
OUT1
OUT1*
IN1*
D
Q
Q*
D*
IN2
1
0
OUT2
IN2*
OUT2*
Q
D
Q*
D*
IN3
1
0
OUT3
IN3*
OUT3*
D
Q
Q*
D*
CLK
CLK*
SEL*
SEL
EN
EN*
Revision 1/July 10, 2002
1
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SK44XX Family
Quad Buffer/Receiver
HIGH-PERFORMANCE PRODUCTS
SK44XX ꢀamily Product Selection Guide
Quad Buffer/Receiver
3 GHz
Synch / Asynch Operation
Logic ꢀamily
Input
Termination
Output
Configuration
Power Supply
Output Swing
Avaiability
Open
50Ω
Output
Swing
Product
SK4400
SK4401
SK4404
SK4410
SK4411
SK4414
3.3V
5.2V
l
Open
l
100Ω Emitter Output
l
l
l
l
ECL / PECL
Double Swing / TTL
ECL / PECL
Now
Now
Now
Now
Now
Now
l
l
l
l
l
l
l
l
l
l
l
l
ECL / PECL
l
Double Swing / TTL
ECL / PECL
l
l
l
Logic / Translation ꢀamily
Translation
Input Termination
Output Configuration
Availability
Open
50Ω
Product
SK4425
SK4426
SK4429
SK4430
SK4435
SK4436
SK4439
SK4440
Open
l
100Ω
Emitter
Output
Anything to PECL
Anything to ECL
Anything to PECL
Anything to ECL
Anything to PECL
Anything to ECL
Anything to PECL
Anything to ECL
l
l
Now
Now
Now
Now
Now
Now
Now
Now
l
l
l
l
l
l
l
l
l
l
l
l
l
Revision 1/July 10, 2002
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2
SK44XX Family
Quad Buffer/Receiver
HIGH-PERFORMANCE PRODUCTS
SK44XX ꢀamily Package Information
5mm x 5mm TQꢀP
3
D, E
2
4
D1, E1
See
Figure 3.
b
8
Top View
e
A
A2
SEATING
PLANE
A1
b
10
Side View
Revision 1/July 10, 2002
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SK44XX Family
Quad Buffer/Receiver
HIGH-PERFORMANCE PRODUCTS
SK44XX ꢀamily Package Information (continued)
5mm x 5mm TQꢀP
02
WITH
PLATING
2
9
7
b
R1
01
e / 2
ꢁ
ꢀ
R2
S
GAGE PLANE
03
ꢁ
11
00
L
ꢀ
b
See Detail in
Figure 2
9
b1
(L1)
Figure 3.
Figure 1.
Figure 2.
1. All dimensions and tolerancing conforms to ANSI
Y14.5M-1982.
2. The top package body size may be smaller than the
bottom package body size by as much as 0.15 mm.
3. To be determined at seating plane.
4. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25 mm per side. D1 and E1
are maximum plastic body size dimensions including
mold mismatch.
5. Details of Pin 1 identifier optional, but must be located
within the zone indicated.
JEDEC Variation
All Dimensions in Millimeters
Symbol
A
MIN
1.00
0.05
0.95
NOM
1.10
0.10
1.00
7.00 BSC
5.00 BSC
7.00 BSC
5.00 BSC
32
MAX
1.20
0.15
1.05
Note Comments
Package Stand Off Height
Air Gap
A1
A2
D
Package Body Thickness
3
D1
E
4, 2 Package Body Length
3
E1
N
4, 2 Package Body Width
Lead Count
6. All dimensions are in millimeters.
e
0.50 BSC
0.22
0.20
–
Lead Pitch
7. Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall not cause the lead
width to exceed the maximum b dimension by more
b
0.17
0.17
0.08
0.08
0o
0.27
0.23
–
7
Lead Thickness
b1
R1
R2
00
01
02
03
S
than 0.08 mm. Dambar cannot be located on the lower
radius or the foot. Minimum space between protrusion
and an adjacent lead is 0.07 mm for 0.4 mm and 0.5
mm pitch packages.
–
0.20
7o
3.5o
0o
–
–
8. Exact shape of each corner is optional.
11o
12o
13o
13o
–
9. These dimensions apply to the flat section of the lead
between 0.10 mm and 0.25 mm from the lead tip.
10.A1 is defined as the distance from the seating plane to
the lowest point of the package body.
11o
12o
0.20
0.09
0.09
0.45
–
c
–
0.20
0.16
0.75
c1
L
–
0.60
1.00 REF
0.20
0.20
0.08
0.08
L1
aaa
bbb
ccc
ddd
Revision 1/July 10, 2002
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4
SK44XX Family
Quad Buffer/Receiver
HIGH-PERFORMANCE PRODUCTS
Absolute Maximum Ratings*
Symbol
Parameter
Value
Unit
V
Power Supply (V
= 0V)
= 0V)
-8.0 to 0
V
EE
CC
EE
V
V
Power Supply (V
Input Voltage
+8.0 to 0
V
V
CC
I
VCC≥VI≥VEE
Output Current
Continuous
Surge
I
50
100
mA
mA
OUT
o
T
Storage Temperature
Solder Temperature (<2 to 3 seconds: 245 C desired)
-65 to +150
265
C
stg
sol
o
o
T
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Note:
1. Device is ESD sensitive and requires protective handling.
Revision 1/July 10, 2002
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SK4400
Quad Buffer/Receiver
HIGH-PERFORMANCE PRODUCTS
Description
ꢀeatures
•
Quad Buffer/Receiver
3 GHz Fmax
3.3V / 5.2V Compatible
Available in 32 lead, 5mm X5mm, TQFP
Package
The SK4400 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input.
•
•
•
Application Notes
The SK4400 uses standard open emitter ECL outputs
optimized for:
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL /
LVECL / PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
• Standard, general purpose ECL applications
• Multiple destinations (daisy chain).
ꢀunctional Block Diagram
Input Options
IN0
1
Open
OUT0
IN0*
OUT0*
D
Q
0
IN<0 - 3>
D* Q*
IN<0 - 3>*
IN1
1
0
OUT1
OUT1*
IN1*
D
Q
Output Options
Q*
D*
Open Emitter
IN2
VCC
1
0
OUT2
IN2*
OUT2*
Q
D
Q*
D*
OUT
IN3
OUT*
1
0
OUT3
IN3*
OUT3*
D
Q
Q*
D*
Pin Description
CLK
CLK*
SEL*
SEL
EN
EN*
VCC
V
CC
OUT1*
OUT1
SEL
SEL*
Package Information
V
EE
EE
CLK*
CLK
V
OUT2
EN
OUT2*
EN*
V
CC
V
CC
32 pin, 5 mm X 5 mm
TQFP Package
Revision 1/July 10, 2002
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6
SK4400
Quad Buffer/Receiver
HIGH-PERFORMANCE PRODUCTS
DC Characteristics
(VCC - VEE = 3.0V to 5.5V; TA = 0oC to 70oC)
Parameter
Inputs
Symbol
Min
Typ
Max
Units
Input High
Input Low
VIH
VIL
VEE + 2.0
VEE
VCC
VCC - 0.2
V
V
(IN - IN*, CLK - CLK*,
EN - EN*, SEL - SEL*)
Differential Input Voltage
1
| VIH - VIL |
0.2
4.3
V
Timing Inputs (CLK / CLK*)
Input High Current
Input Low Current
IIH
IIL
-5.0
-1
+8.0
<0.5
+25
+1
µA
µA
Timing Inputs (IN / IN*)
IIH, IIL
IIH, IIL
-20
<40
80
µA
µA
Input High Current, Input Low Current
Functional Inputs (EN / EN*, SEL /
SEL*) Input Current
-500
<200
+500
Outputs
Digital Output Voltage
| OUT - OUT* |
600
780
mV
V
Output Common Mode Range
(OUT + OUT*) / 2 VCC - 1.5 VCC - 1.3
VCC - 1.1
115
Power Supply
Power Supply Current
IEE
90
mA
DC TEST CONDITIONS: Outputs terminated with 50Ω to VCC – 2V.
Note: 1. Production tested to a maximum V
= 1.8V.
diff
AC Characteristics
(VCC - VEE = 3.0V to 5.5V; TA = 0oC to 70oC)
Parameter
Symbol
Min
Typ
Max
Units
High Performance Option
Propagation Delay
IN[0:3] to OUT[0:3] (SEL = 1)
CLK to OUT[0:3] (SEL = 0)
SEL to OUT [0:3]
Tpd
Tpd
Tpd
Tpd
200
430
300
200
350
550
430
390
550
780
650
600
ps
ps
ps
ps
EN to OUT [0:3]
Channel to Channel Skew
15
40
ps
GHz
ps
1
Maximum Operating Frequency
Fmax
3.0
1
Minimum Pulse Width
PW min
250
IN to CLK
Set Up Time
Hold Time
Ts
Th
120
120
ps
ps
1
Output Rise and Fall Times (20% / 80%)
Tr / Tf
125
<1
165
ps
1
o
Temperature Coefficient
ps /
C
∆Tpd /∆T
AC TEST CONDITIONS: Outputs terminated with 50Ω to VCC – 2V
Note: 1. Guaranteed by characterization. Not production tested.
Revision 1/July 10, 2002
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SK4401
Quad Buffer/Receiver
HIGH-PERFORMANCE PRODUCTS
Description
ꢀeatures
•
Quad Buffer/Receiver
2 GHz Fmax
4.5V / 5.2V Compatible
Available in 32 lead, 5mm X5mm, TQFP
Package
The SK4401 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input.
•
•
•
Application Notes
The SK4401 uses open emitter outputs with a double
amplitude swing suitable for the following applications:
• TTL compatible destinations
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL /
LVECL / PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
• Double termination situations that require a
full swing at the destination
• Long cables
Input Options
ꢀunctional Block Diagram
Open
IN<0 - 3>
IN0
1
OUT0
IN0*
OUT0*
IN<0 - 3>*
D
Q
0
D* Q*
Output Options
IN1
1
0
OUT1
OUT1*
IN1*
D
Q
Open Emitter
Q*
D*
VCC
IN2
1
0
OUT2
IN2*
OUT2*
Q
D
Q*
D*
OUT
OUT*
IN3
1
0
OUT3
IN3*
OUT3*
D
Q
Q*
D*
Pin Description
CLK
CLK*
SEL*
SEL
EN
EN*
V
CC
V
CC
OUT1*
OUT1
SEL
SEL*
V
V
EE
EE
CLK*
CLK
Package Information
OUT2
EN
OUT2*
EN*
V
CC
VCC
32 pin, 5 mm X 5 mm
TQFP Package
Revision 1/July 10, 2002
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8
SK4401
Quad Buffer/Receiver
HIGH-PERFORMANCE PRODUCTS
DC Characteristics
(VCC - VEE = 4.2V to 5.5V; TA = 0oC to 70oC)
Parameter
Inputs
Symbol
Min
Typ
Max
Units
Input High
Input Low
VIH
VIL
VEE + 2.0
VEE
VCC
VCC -0.2
V
V
(IN - IN*, CLK - CLK*, EN - EN*, SEL -SEL*)
Differential Input Voltage
| VIH - VIL |
0.2
4.3
V
Timing Inputs (CLK / CLK*)
Input High Current
Input Low Current
IIH
IIL
-5.0
-1
+8.0
<0.5
+25
+1
µA
µA
Timing Inputs (IN / IN*)
Input High Current, Input Low Current
IIH, IIL
IIH, IIL
<40
80
µA
µA
-20
Functional Inputs (EN / EN*, SEL / SEL*)
Input Current
-500
<200
+500
Outputs
Digital Output Voltage
Output Common Mode Range
| OUT -OUT* |
(OUT + OUT*) / 2
1.2
VCC -2.2
1.5
VCC - 1.9
V
V
VCC - 1.7
115
Power Supply
Power Supply Current
IEE
90
mA
DC TEST CONDITIONS: Outputs terminated with 50Ω to VCC – 3.3V
AC Characteristics
(VCC - VEE = 4.2V to 5.5V; TA = 0oC to 70oC)
Parameter
Symbol
Min
Typ
Max
Units
High Performance Option
Propagation Delay
IN[0:3] to OUT[0:3] (SEL = 1)
CLK to OUT[0:3] (SEL = 0)
SEL to OUT [0:3]
Tpd
Tpd
Tpd
Tpd
200
400
300
250
450
650
530
500
800
950
850
850
ps
ps
ps
ps
EN to OUT [0:3]
Channel to Channel Skew
15
40
ps
GHz
ps
1
Maximum Operating Frequency
Fmax
2.0
1
Minimum Pulse Width
PW min
350
IN to CLK
Set Up Time
Hold Time
Ts
Th
120
120
ps
ps
1
Output Rise and Fall Times (20% /80%)
Tr / Tf
200
<3
350
ps
1
o
Temperature Coefficient
ps /
C
∆Tpd /∆T
AC TEST CONDITIONS: Outputs terminated with 50Ω to VCC – 3.3V
Note: 1. Guaranteed by characterization. Not production tested.
Revision 1/July 10, 2002
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SK4404
Quad Buffer/Receiver
HIGH-PERFORMANCE PRODUCTS
Description
ꢀeatures
The SK4404 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input.
•
Quad Buffer/Driver
3 GHz Fmax
3.3V / 5.2V Compatible
Available in 32 lead, 5mm X5mm, TQFP
Package
•
•
•
Application Notes
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL / LVECL
PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
The SK4404 uses 50Ω outputs with sink/source
capability, and is optimized for applications that require:
• Point to point, double terminated, timing
critical lines
• Point to point, series terminated, timing
critical lines
Input Options
ꢀunctional Block Diagram
Open
IN<0 - 3>
IN0
1
OUT0
IN0*
OUT0*
IN<0 - 3>*
D
Q
0
D* Q*
Output Options
IN1
1
0
OUT1
50Ω Source / Sink
OUT1*
IN1*
D
Q
Q*
D*
VCC
IN2
1
0
50Ω
50Ω
OUT2
IN2*
OUT
OUT
OUT2*
Q
D
Q*
D*
*
10 mA
10 mA
IN3
VEE
1
0
VEE
OUT3
IN3*
OUT3*
D
Q
Q*
D*
CLK
Pin Description
CLK*
SEL*
SEL
EN
EN*
VCC
VCC
OUT1*
OUT1
SEL
SEL*
Package Information
V
V
EE
EE
CLK*
CLK
OUT2
EN
OUT2*
EN*
32 pin, 5 mm X 5 mm
V
CC
V
CC
TQFP Package
Revision 1/July 10, 2002
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10
SK4404
Quad Buffer/Receiver
HIGH-PERFORMANCE PRODUCTS
DC Characteristics
(VCC - VEE = 3.0V to 5.5V; TA = 0oC to 70oC)
Parameter
Inputs
Symbol
Min
Typ
Max
Units
Input High
Input Low
VIH
VIL
VEE + 2.0
VEE
VCC
V
V
VCC -0.2
(IN - IN*, CLK - CLK*,
EN - EN*, SEL - SEL*)
Differential Input Voltage
| VIH - VIL |
0.2
4.3
V
Timing Inputs (CLK / CLK*)
Input High Current
IIH
IIL
-5.0
-1
+8.0
<0.5
+25
+1
µA
µA
Input Low Current
Timing Inputs (IN / IN*)
-20
IIH, IIL
<40
80
µA
Input High Current, Input Low Current
Functional Inputs (EN / EN*, SEL /
SEL*) Input Current
IIH, IIL
-500
<200
+500
µA
Outputs
Digital Output Voltage
Output Common Mode Range
Internal Current Source
Output Impedance
| OUT - OUT* |
(OUT + OUT*) / 2
ISINK
600
780
VCC -1.3
10.0
mV
V
VCC - 1.5
VCC - 1.1
13.5
8
mA
Ω
ROUT
40
50
60
Power Supply
Power Supply Current
IEE
170
225
mA
DC Test Conditions: Outputs unterminated.
AC Characteristics
(VCC - VEE = 3.0V to 5.5V; TA = 0oC to 70oC)
Parameter
Symbol
Min
Typ
Max
Units
High Performance Option
Propagation Delay
IN[0:3] to OUT[0:3] (SEL = 1)
CLK to OUT[0:3] (SEL = 0)
SEL to OUT [0:3]
Tpd
Tpd
Tpd
Tpd
200
430
300
250
350
580
450
350
550
780
650
600
ps
ps
ps
ps
EN to OUT [0:3]
Channel to Channel Skew
15
40
ps
GHz
ps
1
Maximum Operating Frequency
Fmax
3.0
1
Minimum Pulse Width
PW min
250
IN to CLK
Set Up Time
Hold Time
Ts
Th
120
120
ps
ps
1
Output Rise and Fall Times (20% / 80%)
Tr / Tf
125
<1
165
ps
1
o
Temperature Coefficient
ps /
C
∆Tpd /∆T
AC TEST CONDITIONS: Outputs terminated with 50Ω to VCC – 2V
Note:
1.
Guaranteed by characterization. Not production tested.
Revision 1/July 10, 2002
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SK4410
Quad Buffer/Receiver
HIGH-PERFORMANCE PRODUCTS
Description
ꢀeatures
The SK4410 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input.
•
•
•
•
Quad Buffer/Receiver
3 GHz Fmax
3.3V / 5.2V Compatible
Available in 32 lead, 5mm X5mm, TQFP
Package
Application Notes
The SK4410 has 100Ω input termination resistors
across each of the four inputs to help reduce system
component count and increase integration.
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL / LVECL
PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
The SK4410 uses standard open emitter ECL outputs
optimized for:
• Standard, general purpose ECL applications
• Multiple destinations (daisy chain).
Input Options
ꢀunctional Block Diagram
IN
<
0 - 3
>
>
100
IN0
1
IN<
0 - 3
*
OUT0
IN0*
OUT0*
D
Q
0
D* Q*
Output Options
IN1
Open Emitter
1
0
OUT1
OUT1*
IN1*
VCC
D
Q
Q*
D*
IN2
1
0
OUT2
IN2*
OUT2*
OUT
Q
D
Q*
D*
OUT*
IN3
1
0
OUT3
IN3*
OUT3*
Pin Description
D
Q
Q*
D*
CLK
CLK*
SEL*
SEL
EN
EN*
V
CC
VCC
OUT1*
OUT1
SEL
SEL*
V
V
EE
EE
CLK*
CLK
Package Information
OUT2
EN
OUT2*
EN*
V
CC
V
CC
32 pin, 5 mm X 5 mm
TQFP Package
Revision 1/July 10, 2002
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12
SK4410
Quad Buffer/Receiver
HIGH-PERFORMANCE PRODUCTS
DC Characteristics
(VCC - VEE = 3.0V to 5.5V; TA = 0oC to 70oC)
Parameter
Inputs
Symbol
Min
Typ
Max
Units
Input High
Input Low
VIH
VIL
VEE + 2.0
VEE
VCC
V
V
VCC - 0.2
(IN - IN*, CLK - CLK*,
EN - EN*, SEL - SEL*)
Differential Input Voltage
| VIH - VIL |
0.2
4.3
V
Timing Inputs (CLK / CLK*)
Input High Current
IIH
IIL
-5.0
-1
+8.0
<0.5
100
+25
+1
µA
µA
Ω
Input Low Current
IN / IN* Differential Input Resistance
RIN
80
120
Functional Inputs (EN / EN*, SEL /
SEL*) Input Current
IIH, IIL
-500
<200
+500
µA
Outputs
Digital Output Voltage
| OUT - OUT* |
600
780
mV
V
Output Common Mode Range
(OUT + OUT*) / 2
VCC - 1.5
VCC -1.3
VCC - 1.1
115
Power Supply
Power Supply Current
IEE
90
mA
DC Test Conditions: Outputs terminated with 50Ω to VCC – 2V.
AC Characteristics
(VCC - VEE = 3.0V to 5.5V; TA = 0oC to 70oC)
Parameter
Symbol
Min
Typ
Max
Units
High Performance Option
Propagation Delay
IN[0:3] to OUT[0:3] (SEL = 1)
CLK to OUT[0:3] (SEL = 0)
SEL to OUT [0:3]
Tpd
Tpd
Tpd
Tpd
200
430
300
250
350
550
430
360
550
780
650
600
ps
ps
ps
ps
EN to OUT [0:3]
Channel to Channel Skew
15
40
ps
GHz
ps
1
Maximum Operating Frequency
Fmax
3.0
1
Minimum Pulse Width
PW min
250
IN to CLK
Setup Time
Hold Time
Ts
Th
120
120
ps
ps
1
Output rise and Fall Times (20%/80%)
Tr/Tf
125
<1
165
ps
1
o
ps/ C
Temperature Coefficient
∆Tpd/∆T
AC Test Conditions: Outputs terminated with 50Ω to VCC – 2V
Note:
1.
Guaranteed by characterization. Not production tested.
Revision 1/July 10, 2002
13
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SK4411
Quad Buffer/Receiver
HIGH-PERFORMANCE PRODUCTS
Description
ꢀeatures
•
Quad Buffer/Receiver
3 GHz Fmax
4.2V / 5.2V Compatible
Available in 32 lead, 5mm X5mm, TQFP
Package
The SK4411 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input.
•
•
•
Application Notes
The SK4411 has 100Ω input termination resistors
across each of the four inputs to help reduce system
component count and increase integration.
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL / LVECL
PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
The SK4411 uses open emitter outputs with a double
amplitude swing suitable for the following applications:
• TTL compatible destinations
• Double termination situations that require a
full swing at the destination
Input Options
• Long cables
IN
<
0 - 3
>
>
ꢀunctional Block Diagram
100
IN<
0 - 3
*
IN0
1
OUT0
IN0*
OUT0*
Output Options
D
Q
0
D* Q*
Open Emitter
IN1
1
0
VCC
OUT1
OUT1*
IN1*
D
Q
Q*
D*
IN2
1
0
OUT
OUT2
IN2*
OUT2*
OUT*
Q
D
Q*
D*
IN3
1
0
Pin Description
OUT3
IN3*
OUT3*
D
Q
Q*
D*
CLK
CLK*
SEL*
SEL
EN
V
CC
V
CC
EN*
OUT1*
OUT1
SEL
SEL*
V
V
EE
EE
CLK*
CLK
OUT2
EN
Package Information
OUT2*
EN*
V
CC
V
CC
32 pin, 5 mm X 5 mm
TQFP Package
Revision 1/July 10, 2002
www.semtech.com
14
SK4411
Quad Buffer/Receiver
HIGH-PERFORMANCE PRODUCTS
DC Characteristics
(VCC - VEE = 4.2V to 5.5V; TA = 0oC to 70oC)
Parameter
Inputs
Symbol
Min
Typ
Max
Units
Input High
Input Low
VIH
VIL
VEE + 2.0
VEE
VCC
V
V
VCC - 0.2
(IN - IN*, CLK - CLK*,
EN - EN*, SEL - SEL*)
Differential Input Voltage
| VIH - VIL |
0.2
4.3
V
Timing Inputs (CLK / CLK*)
Input High Current
IIH
IIL
-5.0
-1
+8.0
<0.5
100
+25
+1
µA
µA
Ω
Input Low Current
IN / IN* Differential Input Resistance
RIN
80
120
Functional Inputs (EN / EN*, SEL /
SEL*)
IIH, IIL
-500
<200
+500
µA
Input Current
Outputs
Digital Output Voltage
| OUT - OUT* |
1.2
1.5
V
V
Output Common Mode Range
(OUT + OUT*) / 2 VCC - 2.2
VCC -1.9
VCC - 1.7
115
Power Supply
Power Supply Current
IEE
90
mA
DC Test Conditions: Outputs terminated with 50Ω to VCC – 3.3V.
AC Characteristics
(VCC - VEE = 4.2V to 5.5V; TA = 0oC to 70oC)
Parameter
Symbol
Min
Typ
Max
Units
High Performance Option
Propagation Delay
IN[0:3] to OUT[0:3] (SEL = 1)
CLK to OUT[0:3] (SEL = 0)
SEL to OUT [0:3]
Tpd
Tpd
Tpd
Tpd
200
400
300
250
450
650
530
500
800
950
850
850
ps
ps
ps
ps
EN to OUT [0:3]
Channel to Channel Skew
15
40
ps
GHz
ps
1
Maximum Operating Frequency
Fmax
3.0
1
Minimum Pulse Width
PW min
350
IN to CLK
Set Up Time
Hold Time
Tsu
Th
120
120
ps
ps
1
Output Rise and Fall Times (20% / 80%)
Tr / Tf
200
<3
350
ps
1
o
Temperature Coefficient
ps/ C
∆Tpd /∆T
AC Test Conditions: Outputs terminated with 50Ω to VCC – 3.3V
Note:
1.
Guaranteed by characterization. Not production tested.
Revision 1/July 10, 2002
15
www.semtech.com
SK4414
Quad Buffer/Receiver
HIGH-PERFORMANCE PRODUCTS
Description
ꢀeatures
The SK4414 is an extremely fast, stable and accurate •
low skew quad buffer or cable driver / receiver. It can •
asychronously pass four distinct signals, or it can •
resynchronize them to a common clock. In addition, •
all four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input.
Quad Buffer/Receiver
3 GHz Fmax
3.3V / 5.2V Compatible
Available in 32 lead, 5mm X5mm, TQFP
Package
Application Notes
The SK4414 has 100Ω input termination resistors
across each of the four inputs to help reduce system
component count and increase integration.
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL / LVECL
PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
The SK4414 uses 50Ω outputs with sink/source
capability, and is optimized for applications that require:
• Point to point, double terminated, timing
critical lines
• Point to point, series terminated, timing
critical lines
Input Options
IN
<
0 - 3
>
>
100
ꢀunctional Block Diagram
IN<
0 - 3
*
IN0
1
OUT0
Output Options
IN0*
OUT0*
D
Q
0
D* Q*
50Ω Source / Sink
VCC
IN1
1
0
OUT1
OUT1*
IN1*
50Ω
50Ω
D
Q
OUT
OUT
Q*
D*
*
10 mA
10 mA
IN2
1
0
OUT2
VEE
VEE
IN2*
OUT2*
Q
D
Q*
D*
IN3
1
0
Pin Description
OUT3
IN3*
OUT3*
D
Q
Q*
D*
CLK
CLK*
SEL*
SEL
EN
V
CC
V
CC
EN*
OUT1*
OUT1
SEL
SEL*
V
V
EE
EE
CLK*
CLK
OUT2
EN
Package Information
OUT2*
EN*
V
CC
V
CC
32 pin, 5 mm X 5 mm
TQFP Package
Revision 1/July 10, 2002
www.semtech.com
16
SK4414
Quad Buffer/Receiver
HIGH-PERFORMANCE PRODUCTS
DC Characteristics
(VCC - VEE = 3.0V to 5.5V; TA = 0oC to 70oC)
Parameter
Inputs
Symbol
Min
Typ
Max
Units
Input High
Input Low
VIH
VIL
VEE + 2.0
VEE
VCC
V
V
VCC - 0.2
(IN - IN*, CLK - CLK*,
EN - EN*, SEL - SEL*)
Differential Input Voltage
| VIH - VIL |
0.2
4.3
V
Timing Inputs (CLK / CLK*)
Input High Current
IIH
IIL
-5.0
-1
+8.0
<0.5
100
+25
+1
µA
µA
Ω
Input Low Current
IN / IN* Differential Input Resistance
RIN
80
120
Functional Inputs (EN / EN*, SEL / SEL*)
Input Current
IIH, IIL
-500
+500
µA
Outputs
Digital Output Voltage
Output Common Mode Range
Internal Current Source
Output Impedance
| OUT - OUT* |
600
780
VCC - 1.3
10.0
mV
V
(OUT + OUT*) / 2 VCC - 1.5
VCC - 1.1
13.5
ISINK
ROUT
8.0
40
mA
Ω
50
60
Power Supply
Power Supply Current
IEE
170
220
mA
DC Test Conditions: Outputs unterminated.
AC Characteristics
(VCC - VEE = 3.0V to 5.5V; TA = 0oC to 70oC)
Parameter
Symbol
Min
Typ
Max
Units
High Performance Option
Propagation Delay
IN[0:3] to OUT[0:3] (SEL = 1)
CLK to OUT[0:3] (SEL = 0)
SEL to OUT [0:3]
Tpd
Tpd
Tpd
Tpd
200
430
300
250
350
550
430
360
550
780
650
600
ps
ps
ps
ps
EN to OUT [0:3]
Channel to Channel Skew
15
40
ps
GHz
ps
1
Maximum Operating Frequency
Fmax
3.0
1
Minimum Pulse Width
PW min
250
IN to CLK
Set Up Time
Hold Time
Ts
Th
120
120
ps
ps
1
Output Rise and Fall Times (20% / 80%)
Tr / Tf
125
<1
165
ps
1
Temperature Coefficient
ps / oC
∆Tpd /∆T
AC Test Conditions: Outputs terminated with 50Ω to VCC – 2V
Note:
1.
Guaranteed by characterization. Not production tested.
Revision 1/July 10, 2002
17
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SK4425
Anything to PECL
HIGH-PERFORMANCE PRODUCTS
Description
ꢀeatures
The SK4425 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input. It is also capable of
receiving inputs of any technology or voltage level.
•
•
•
•
Quad Buffer / Receiver
3 GHz Fmax
Anything to PECL Translation
Available in 32 lead, 5mm X5mm, TQFP
Package
Application Notes
The SK4425 uses standard open emitter ECL outputs
optimized for:
• Standard, general purpose ECL
applications
• Multiple destinations (daisy chain).
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL / LVECL
PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
ꢀunctional Block Diagram
IN0
1
OUT0
Input Options
IN0*
OUT0*
Output Options
D
Q
0
D* Q*
Open
Open Emitter
IN1
1
0
OUT1
VCC
OUT1*
IN1*
D
Q
IN<0 - 3>
Q*
D*
IN2
1
0
OUT
IN<0 - 3>*
OUT2
IN2*
OUT2*
OUT*
Q
D
Q*
D*
IN3
1
0
OUT3
IN3*
Pin Description
OUT3*
D
Q
Q*
D*
CLK
CLK*
SEL*
SEL
EN
EN*
VCC
VCC
OUT1*
OUT1
SEL
SEL*
V
V
EE
EE
CLK*
CLK
OUT2
EN
Package Information
OUT2*
EN*
V
CC
V
CC
32 pin, 5 mm X 5 mm
TQFP Package
Revision 1/July 10, 2002
www.semtech.com
18
SK4425
Anything to PECL
HIGH-PERFORMANCE PRODUCTS
DC Characteristics
(VCC = 2.0V to 3.6V; VEE = -3.6 to -3.0V; TA = 0oC to 70oC)
Parameter
Inputs
Symbol
Min
Typ
Max
Units
Input High
Input Low
VIH
VIL
VEE + 2.0
VEE
VCC
V
V
VCC -0.2
(IN - IN*, CLK - CLK*,
EN - EN*, SEL -SEL*)
Differential Input Voltage
| VIH - VIL |
0.2
4.3
V
Timing Inputs (CLK / CLK*)
Input High Current
IIH
IIL
- 5.0
-1
+8.0
<0.5
+25
+1
µA
µA
Input Low Current
Timing Inputs (IN / IN*)
IIH, IIL
IIH, IIL
<40
80
µA
µA
-20
Input High Current, Input Low Current
Functional Inputs (EN / EN*, SEL / SEL*)
Input Current
-500
<200
+500
Outputs
Digital Output Voltage
| OUT -OUT* |
600
780
mV
V
Output Common Mode Range
(OUT + OUT*) / 2
VCC -1.5
VCC -1.3
VCC -1.1
120
Power Supply
Power Supply Current
IEE
95
mA
DC Test Conditions: Outputs terminated with 50Ω to VCC – 2V.
AC Characteristics
(VCC = 2.0V to 3.6V; VEE = -3.6 to -3.0V; TA = 0oC to 70oC)
Parameter
Symbol
Min
Typ
Max
Units
High Performance Option
Propagation Delay
IN[0:3] to OUT[0:3] (SEL = 1)
CLK to OUT[0:3] (SEL = 0)
SEL to OUT [0:3]
Tpd
Tpd
Tpd
Tpd
200
430
250
200
350
550
430
390
550
780
650
600
ps
ps
ps
ps
EN to OUT [0:3]
Channel to Channel Skew
15
40
ps
GHz
ps
1
Maximum Operating Frequency
Fmax
3.0
1
Minimum Pulse Width
PW min
250
IN to CLK
Set Up Time
Hold Time
Ts
Th
120
120
ps
ps
1
Output Rise and Fall Times (20% / 80%)
Tr / Tf
125
<1
165
ps
1
o
Temperature Coefficient
ps / C
∆Tpd /∆T
AC Test Conditions: Outputs terminated with 50Ω to VCC – 2V
Note: 1. Guaranteed by characterization. Not production tested.
Revision 1/July 10, 2002
19
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SK4426
Anything to ECL
HIGH-PERFORMANCE PRODUCTS
Description
ꢀeatures
•
Quad Buffer/Receiver
3 GHz Fmax
Anything to ECL Translation
Available in 32 lead, 5mm X5mm, TQFP
Package
The SK4426 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input. It is also capable of
receiving inputs of any technology or voltage level.
•
•
•
The SK4426 uses standard open emitter ECL outputs
optimized for:
Application Notes
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL / LVECL
PECL / LVPECL Devices
• Standard, general purpose ECL
applications
• Multiple destinations (daisy chain).
AN1004 - Interfacing Between LVDS and ECL /
PECL / LVPECL
ꢀunctional Block Diagram
IN0
1
OUT0
IN0*
OUT0*
Output Options
D
Q
Input Options
0
D* Q*
Open Emitter
Open
IN1
1
0
VGG
OUT1
OUT1*
IN1*
D
Q
IN
<
0 - 3
>
>
Q*
D*
IN2
1
0
OUT
IN<
0 - 3
*
OUT2
IN2*
OUT2*
OUT*
Q
D
Q*
D*
IN3
1
0
OUT3
IN3*
OUT3*
D
Q
Q*
D*
Pin Description
CLK
CLK*
SEL*
SEL
EN
EN*
V
GG
V
CC
OUT1*
OUT1
SEL
SEL*
V
V
EE
EE
Package Information
CLK*
CLK
OUT2
EN
OUT2*
EN*
V
GG
V
CC
32 pin, 5 mm X 5 mm
TQFP Package
Revision 1/July 10, 2002
www.semtech.com
20
SK4426
Anything to ECL
HIGH-PERFORMANCE PRODUCTS
DC Characteristics
(V = - 0.1V to 2.0V; V = 2.0V to 3.6V; VEE = -3.6V to -3.0V; T = 0oC to 70oC)
GG
CC
A
Parameter
Symbol
Min
Typ
Max
Units
Inputs
Input High
Input Low
VIH
VIL
VEE + 2.0
VEE
VCC
V
V
VCC -0.2
4.3
(IN - IN*, CLK - CLK*,
EN - EN*, SEL - SEL*)
Differential Input Voltage
| VIH - VIL |
0.2
V
Timing Inputs (CLK / CLK*)
Input High Current
IIH
IIL
-5.0
-1
+8.0
<0.5
+25
+1
µA
µA
Input Low Current
Timing Inputs (IN / IN*)
IIH, IIL
<40
80
µA
-20
-500
600
Input High Current, Input Low Current
Functional Inputs (EN / EN*, SEL / SEL*)
Input Current
IIH, IIL
<200
780
+500
µA
Outputs
Digital Output Voltage
| OUT - OUT* |
mV
V
Output Common Mode Range
(OUT + OUT*) / 2 VGG -1.5 VGG - 1.3 VGG -1.1
Power Supply
Power Supply Current
IEE
ICC
100
70
150
110
mA
mA
DC Test Conditions: Outputs terminated with 50Ω to VGG – 2V.
AC Characteristics
(V = - 0.1V to 2.0V; V = 2.0V to 3.6V; VEE = -3.6V to -3.0V; T = 0oC to 70oC)
GG
CC
A
Parameter
Symbol
Min
Typ
Max
Units
High Performance Option
Propagation Delay
IN[0:3] to OUT[0:3] (SEL = 1)
CLK to OUT[0:3] (SEL = 0)
SEL to OUT [0:3]
Tpd
Tpd
Tpd
Tpd
200
430
300
250
350
550
430
390
550
780
650
600
ps
ps
ps
ps
EN to OUT [0:3]
Channel to Channel Skew
15
40
ps
GHz
ps
1
Maximum Operating Frequency
Fmax
3
1
Minimum Pulse Width
PW min
250
IN to CLK
Set Up Time
Hold Time
Ts
Th
120
120
ps
ps
1
Output Rise and Fall Times (20% / 80%)
Tr / Tf
125
<1
165
ps
1
o
Temperature Coefficient
ps / C
∆Tpd /∆T
AC Test Conditions: Outputs terminated with 50Ω to VGG – 2V
Note:
1.
Guaranteed by characterization. Not production tested.
Revision 1/July 10, 2002
21
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SK4429
Anything to PECL
HIGH-PERFORMANCE PRODUCTS
Description
ꢀeatures
•
•
•
•
Quad Buffer/Receiver
3 GHz Fmax
Anything to PECL Translation
Available in 32 lead, 5mm X5mm, TQFP
Package
The SK4429 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input. It is also capable of
receiving inputs of any technology or voltage level.
The SK4429 uses 50Ω outputs with sink/source
capability, and is optimized for applications that require:
• Point to point, double terminated, timing
critical lines
Application Notes
• Point to point, series terminated, timing
critical lines
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL / LVECL
PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
ꢀunctional Block Diagram
IN0
1
OUT0
IN0*
OUT0*
D
Q
0
D* Q*
Input Options
Output Options
IN1
1
0
Open
50Ω Source / Sink
OUT1
OUT1*
IN1*
VCC
D
Q
Q*
D*
IN
<
0 - 3
>
>
50Ω
50Ω
IN2
1
0
OUT
OUT
OUT2
IN2*
*
OUT2*
IN<
0 - 3
*
Q
D
10 mA
10 mA
Q*
D*
VEE
VEE
IN3
1
0
OUT3
IN3*
OUT3*
D
Q
Q*
D*
Pin Description
CLK
CLK*
SEL*
SEL
EN
EN*
V
CC
V
CC
OUT1*
OUT1
SEL
SEL*
Package Information
V
EE
EE
CLK*
CLK
V
OUT2
EN
OUT2*
EN*
32 pin, 5 mm X 5 mm
V
CC
V
CC
TQFP Package
Revision 1/July 10, 2002
www.semtech.com
22
SK4429
Anything to PECL
HIGH-PERFORMANCE PRODUCTS
DC Characteristics
(V = 2.0V to 3.6V; VEE = -3.6V to -3.0V; T = 0oC to 70oC)
CC
A
Parameter
Inputs
Symbol
Min
Typ
Max
Units
Input High
Input Low
VIH
VIL
VEE + 2.0
VEE
VCC
V
V
VCC - 0.2
(IN - IN*, CLK - CLK*,
EN - EN*, SEL - SEL*)
Differential Input Voltage
| VIH - VIL |
0.2
4.3
V
Timing Inputs (CLK / CLK*)
Input High Current
IIH
IIL
-5.0
-1
+8.0
<0.5
+25
+1
µA
µA
Input Low Current
Timing Inputs (IN / IN*)
IIH, IIL
IIH, IIL
<40
80
µA
µA
-20
Input High Current, Input Low Current
Functional Inputs (EN / EN*, SEL /
SEL*) Input Current
-500
<200
+500
Outputs
Digital Output Voltage
Output Common Mode Range
Internal Current Source
Output Impedance
| OUT - OUT* |
(OUT + OUT*) / 2
ISINK
600
VCC - 1.5
8.0
780
VCC -1.3
10.5
mV
V
VCC - 1.1
13.5
mA
Ω
ROUT
40
50
60
Power Supply
Power Supply Current
IEE
170
235
mA
DC Test Conditions: Outputs unterminated.
AC Characteristics
(V = 2.0V to 3.6V; VEE = -3.6V to -3.0V; T = 0oC to 70oC)
CC
A
Parameter
Symbol
Min
Typ
Max
Units
High Performance Option
Propagation Delay
IN[0:3] to OUT[0:3] (SEL = 1)
CLK to OUT[0:3] (SEL = 0)
SEL to OUT [0:3]
Tpd
Tpd
Tpd
Tpd
200
430
300
250
350
580
450
350
550
780
650
600
ps
ps
ps
ps
EN to OUT [0:3]
Channel to Channel Skew
15
40
ps
GHz
ps
1
Maximum Operating Frequency
Fmax
3
1
Minimum Pulse Width
PW min
250
IN to CLK
Set Up Time
Hold Time
Ts
Th
120
120
ps
ps
1
Output Rise and Fall Times (20% / 80%)
Tr / Tf
125
<1
165
ps
1
o
Temperature Coefficient
ps / C
∆Tpd / ∆T
AC Test Conditions: Outputs terminated with 50Ω to VCC – 2V
Note: 1. Guaranteed by characterization. Not production tested.
Revision 1/July 10, 2002
23
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SK4430
Anything to ECL Receiver
HIGH-PERFORMANCE PRODUCTS
Description
ꢀeatures
•
Quad Buffer/Receiver
3 GHz Fmax
Anything to ECL Translation
Available in 32 lead, 5mm X5mm, TQFP
Package
The SK4430 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input. It is also capable of
receiving inputs of any technology or voltage level.
•
•
•
Application Notes
The SK4430 uses 50Ω outputs with sink/source
capability, and is optimized for applications that require:
• Point to point, double terminated, timing
critical lines
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL / LVECL
PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
• Point to point, series terminated, timing
critical lines
ꢀunctional Block Diagram
Input Options
Output Options
IN0
1
OUT0
IN0*
OUT0*
Open
50Ω Source / Sink
D
Q
0
D* Q*
VGG
IN1
1
0
IN
<
0 - 3
>
>
50Ω
50Ω
OUT1
OUT1*
IN1*
OUT
OUT
D
Q
Q*
D*
*
IN<
0 - 3
*
10 mA
VEE
10 mA
IN2
1
0
VEE
OUT2
IN2*
OUT2*
Q
D
Q*
D*
IN3
1
0
Pin Description
OUT3
IN3*
OUT3*
D
Q
Q*
D*
CLK
CLK*
SEL*
SEL
EN
EN*
VGG
V
CC
OUT1*
OUT1
SEL
SEL*
V
V
EE
EE
CLK*
CLK
OUT2
EN
OUT2*
EN*
Package Information
V
GG
V
CC
32 pin, 5 mm X 5 mm
TQFP Package
Revision 1/July 10, 2002
www.semtech.com
24
SK4430
Anything to ECL
HIGH-PERFORMANCE PRODUCTS
DC Characteristics
(V = - 0.1V to 2.0V; V = 2.0V to 3.6V; VEE = -3.6V to -3.0V; T = 0oC to 70oC)
GG
CC
A
Parameter
Inputs
Symbol
Min
Typ
Max
Units
Input High
Input Low
VIH
VIL
VEE + 2.0
VEE
VCC
V
V
VCC - 0.2
(IN - IN*, CLK - CLK*,
EN - EN*, SEL - SEL*)
Differential Input Voltage
| VIH - VIL |
0.2
4.3
V
Timing Inputs (CLK / CLK*)
Input High Current
IIH
IIL
-5.0
-1
+8.0
<0.5
+25
+1
µA
µA
Input Low Current
Timing Inputs (IN / IN*)
IIH, IIL
<40
80
µA
µA
-20
Input High Current, Input Low Current
Functional Inputs (EN / EN*, SEL / SEL*)
Input Current
IIH, IIL
-500
600
<200
+500
Outputs
Digital Output Voltage
Output Common Mode Range
Internal Current Source
Output Impedance
| OUT - OUT* |
780
VGG -1.3
10.0
mV
V
(OUT + OUT*) / 2 VGG - 1.5
VGG - 1.1
13.5
ISINK
ROUT
8.0
40
mA
Ω
50
60
Power Supply
IEE
ICC
190
70
250
110
mA
mA
Power Supply Current
DC Test Conditions: Outputs unterminated.
AC Characteristics
(V = - 0.1V to 2.0V; V = 2.0V to 3.6V; VEE = -3.6V to -3.0V; T = 0oC to 70oC)
GG
CC
A
Parameter
Symbol
Min
Typ
Max
Units
High Performance Option
Propagation Delay
IN[0:3] to OUT[0:3] (SEL = 1)
CLK to OUT[0:3] (SEL = 0)
SEL to OUT [0:3]
Tpd
Tpd
Tpd
Tpd
200
430
300
250
350
550
430
390
550
780
650
600
ps
ps
ps
ps
EN to OUT [0:3]
Channel to Channel Skew
40
80
ps
1
Maximum Operating Frequency
Fmax
3.0
GHz
1
IN to CLK
Setup Time
Hold Time
Ts
Th
120
120
ps
ps
1
Output rise and Fall Times (20%/80%)
Tr/Tf
125
<1
165
ps
1
o
Temperature Coefficient
ps/ C
∆Tpd/∆T
AC Test Conditions: Outputs terminated with 50Ω to VGG – 2V
Note:
1.
Guaranteed by characterization. Not production tested.
Revision 1/July 10, 2002
25
www.semtech.com
SK4435
Anything to PECL Receiver
HIGH-PERFORMANCE PRODUCTS
Description
ꢀeatures
The SK4435 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input. It is also capable of
receiving inputs of any technology or voltage level.
•
•
•
•
Quad Buffer/Receiver
3 GHz Fmax
Anything to PECL Translation
Available in 32 lead, 5mm X5mm, TQFP
Package
Application Notes
The SK4435 has 100Ω input termination resistors
across each of the four inputs to help reduce system AN1001 - EPIC Family Product Line
component count and increase integration.
AN1003 - Termination Techniques for ECL / LVECL
PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
The SK4435 uses standard open emitter ECL outputs
optimized for:
• Standard, general purpose applications
• Multiple destinations (daisy chain).
ꢀunctional Block Diagram
IN0
1
Input Options
Output Options
OUT0
IN0*
OUT0*
D
Q
0
Open Emitter
D* Q*
VCC
IN1
1
0
IN
<
0 - 3
>
>
OUT1
OUT1*
IN1*
100
D
Q
Q*
D*
IN<
0 - 3
*
OUT
IN2
OUT*
1
0
OUT2
IN2*
OUT2*
Q
D
Q*
D*
IN3
1
0
OUT3
IN3*
Pin Description
OUT3*
D
Q
Q*
D*
CLK
CLK*
SEL*
SEL
EN
EN*
VCC
V
CC
OUT1*
OUT1
SEL
SEL*
V
EE
EE
CLK*
CLK
V
OUT2
EN
Package Information
OUT2*
EN*
V
CC
V
CC
32 pin, 5 mm X 5 mm
TQFP Package
Revision 1/July 10, 2002
www.semtech.com
26
SK4435
Anything to PECL Receiver
HIGH-PERFORMANCE PRODUCTS
DC Characteristics
(V = 2.0V to 3.6V; VEE = -3.6V to -3.0V; T = 0oC to 70oC)
CC
A
Parameter
Inputs
Symbol
Min
Typ
Max
Units
Input High
Input Low
VIH
VIL
VEE + 2.0
VEE
VCC
V
V
VCC - 0.2
(IN - IN*, CLK - CLK*, EN - EN*, SEL - SEL*)
Differential Input Voltage
| VIH - VIL |
0.2
4.3
V
Timing Inputs (CLK / CLK*)
Input High Current
IIH
IIL
-5.0
-1
+8.0
<0.5
100
+25
+1
µA
µA
Ω
Input Low Current
IN / IN* Differential Input Resistance
RIN
80
120
Functional Inputs (EN / EN*, SEL / SEL*)
Input Current
IIH, IIL
-500
<200
+500
µA
Outputs
Digital Output Voltage
| OUT - OUT* |
600
780
mV
V
Output Common Mode Range
(OUT + OUT*) / 2
VCC - 1.5
VCC -1.3
VCC - 1.1
120
Power Supply
Power Supply Current
IEE
85
mA
DC Test Conditions: Outputs terminated with 50Ω to VCC – 2V.
AC Characteristics
(V = 2.0V to 3.6V; VEE = -3.6V to -3.0V; T = 0oC to 70oC)
CC
A
Parameter
Symbol
Min
Typ
Max
Units
High Performance Option
Propagation Delay
IN[0:3] to OUT[0:3] (SEL = 1)
CLK to OUT[0:3] (SEL = 0)
SEL to OUT [0:3]
Tpd
Tpd
Tpd
Tpd
200
430
300
250
350
550
430
360
550
780
650
600
ps
ps
ps
ps
EN to OUT [0:3]
Channel to Channel Skew
15
40
ps
GHz
ps
1
Maximum Operating Frequency
Fmax
3
1
Minimum Pulse Width
PW min
250
IN to CLK
Set Up Time
Hold Time
Ts
Th
120
120
ps
ps
1
Output Rise and Fall Times (20% / 80%)
Tr / Tf
125
<1
165
ps
1
o
Temperature Coefficient
ps / C
∆Tpd / ∆T
AC Test Conditions: Outputs terminated with 50Ω to VCC – 2V
Note:
1.
Guaranteed by characterization. Not production tested.
Revision 1/July 10, 2002
27
www.semtech.com
SK4436
Anything to ECL Receiver
HIGH-PERFORMANCE PRODUCTS
Description
ꢀeatures
The SK4436 is an extremely fast, stable and accurate •
low skew quad buffer or cable driver / receiver. It can •
asychronously pass four distinct signals, or it can •
resynchronize them to a common clock. In addition, all •
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input. It is also capable of
receiving inputs of any technology or voltage level.
Quad Buffer/Receiver
3 GHz Fmax
Anything to ECL Translation
Available in 32 lead, 5mm X5mm, TQFP
Package
Application Notes
The SK4436 has 100Ω input termination resistors
across each of the four inputs to help reduce system
component count and increase integration.
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL / LVECL
PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
The SK4436 uses standard open emitter ECL outputs
optimized for:
• Standard, general purpose applications
• Multiple destinations (daisy chain).
Input Options
Output Options
ꢀunctional Block Diagram
Open Emitter
IN0
1
VGG
OUT0
IN0*
OUT0*
D
Q
IN
<
0 - 3
>
>
0
D* Q*
100
IN1
IN<
0 - 3
*
1
0
OUT
OUT1
OUT*
OUT1*
IN1*
D
Q
Q*
D*
IN2
1
0
OUT2
IN2*
OUT2*
Q
D
Q*
D*
IN3
1
0
OUT3
IN3*
OUT3*
Pin Description
D
Q
Q*
D*
CLK
CLK*
SEL*
SEL
EN
EN*
V
GG
V
CC
OUT1*
OUT1
SEL
SEL*
Package Information
V
V
EE
EE
CLK*
CLK
OUT2
EN
OUT2*
EN*
V
GG
VCC
32 pin, 5 mm X 5 mm
TQFP Package
Revision 1/July 10, 2002
www.semtech.com
28
SK4436
Anything to ECL Receiver
HIGH-PERFORMANCE PRODUCTS
DC Characteristics
(V = - 0.1V to 2.0V; V = 2.0V to 3.6V; VEE = -3.6V to -3.0V; T = 0oC to 70oC)
GG
CC
A
Parameter
Inputs
Symbol
Min
Typ
Max
Units
Input High
Input Low
VIH
VIL
VEE + 2.0
VEE
VCC
V
V
VCC - 0.2
(IN - IN*, CLK - CLK*,
EN - EN*, SEL - SEL*)
Differential Input Voltage
| VIH - VIL |
0.2
4.3
V
Timing Inputs (CLK / CLK*)
Input High Current
IIH
IIL
-5.0
-1
+8.0
<0.5
100
+25
+1
µA
µA
Ω
Input Low Current
IN / IN* Differential Input Resistance
RIN
80
120
Functional Inputs (EN / EN*, SEL / SEL*)
Input Current
IIH, IIL
-500
<200
+500
µA
Outputs
Digital Output Voltage
| OUT - OUT* |
600
780
mV
V
Output Common Mode Range
(OUT + OUT*) / 2
VGG - 1.5 VGG -1.3 VGG - 1.1
Power Supply
IEE
ICC
100
70
150
110
mA
mA
Power Supply Current
DC Test Conditions: Outputs terminated with 50Ω to VGG – 2V.
AC Characteristics
(V = - 0.1V to 2.0V; V = 2.0V to 3.6V; VEE = -3.6V to -3.0V; T = 0oC to 70oC)
GG
CC
A
Parameter
Symbol
Min
Typ
Max
Units
High Performance Option
Propagation Delay
IN[0:3] to OUT[0:3] (SEL = 1)
CLK to OUT[0:3] (SEL = 0)
SEL to OUT [0:3]
Tpd
Tpd
Tpd
Tpd
200
430
300
250
350
550
430
390
550
780
650
600
ps
ps
ps
ps
EN to OUT [0:3]
Channel to Channel Skew
40
80
ps
GHz
ps
1
Maximum Operating Frequency
Fmax
3
1
Minimum Pulse Width
PW min
250
IN to CLK
Set Up Time
Hold Time
Ts
Th
120
120
ps
ps
1
Output Rise and Fall Times (20% / 80%)
Tr / Tf
125
<1
165
ps
1
o
Temperature Coefficient
ps / C
∆Tpd / ∆T
AC Test Conditions: Outputs terminated with 50Ω to VGG – 2V
Note:
1.
Guaranteed by characterization. Not production tested.
Revision 1/July 10, 2002
29
www.semtech.com
SK4439
Anything to PECL Receiver
HIGH-PERFORMANCE PRODUCTS
Description
ꢀeatures
•
•
•
•
Quad Buffer/Receiver
3 GHz Fmax
Anything to PECL Translation
Available in 32 lead, 5mm X5mm, TQFP
Package
The SK4439 is an extremely fast, stable and accurate
low skew quad buffer or cable driver / receiver. It can
asychronously pass four distinct signals, or it can
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input. It is also capable of
receiving inputs of any technology or voltage level.
Application Notes
The SK4439 has 100Ω input termination resistors
across each of the four inputs to help reduce system
component count and increase integration.
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL / LVECL
PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
The SK4439 uses 50Ω outputs with sink/source
capability, and is optimized for applications that require:
• Point to point, double terminated, timing
critical lines
• Point to point, series terminated, timing
critical lines
Output Options
Input Options
ꢀunctional Block Diagram
50Ω Source / Sink
VCC
IN0
1
OUT0
IN
<
0 - 3
>
>
IN0*
OUT0*
50Ω
D
Q
0
D* Q*
100
OUT
50Ω
*
OUT
IN<
0 - 3
*
IN1
10 mA
10 mA
1
0
OUT1
OUT1*
IN1*
VEE
VEE
D
Q
Q*
D*
IN2
1
0
OUT2
IN2*
OUT2*
Q
D
Pin Description
Q*
D*
IN3
1
0
OUT3
IN3*
OUT3*
D
Q
Q*
D*
CLK
CLK*
SEL*
SEL
EN
V
CC
V
CC
OUT1*
OUT1
SEL
EN*
SEL*
V
V
EE
EE
CLK*
CLK
OUT2
EN
OUT2*
EN*
Package Information
V
CC
V
CC
32 pin, 5 mm X 5 mm
TQFP Package
Revision 1/July 10, 2002
www.semtech.com
30
SK4439
Anything to PECL
HIGH-PERFORMANCE PRODUCTS
DC Characteristics
(V = 2.0V to 3.6V; VEE = -3.6V to -3.0V; T = 0oC to 70oC)
CC
A
Parameter
Inputs
Symbol
Min
Typ
Max
Units
Input High
Input Low
VIH
VIL
VEE + 2.0
VEE
VCC
V
V
VCC - 0.2
(IN - IN*, CLK - CLK*,
EN - EN*, SEL - SEL*)
Differential Input Voltage
| VIH - VIL |
0.2
4.3
V
Timing Inputs (CLK / CLK*)
Input High Current
IIH
IIL
-5.0
-1
+8.0
<0.5
100
+25
+1
µA
µA
Ω
Input Low Current
IN / IN* Differential Input Resistance
RIN
80
120
Functional Inputs (EN / EN*, SEL / SEL*)
Input Current
IIH, IIL
-500
<200
+500
µA
Outputs
Digital Output Voltage
Output Common Mode Range
Internal Current Source
Output Impedance
| OUT - OUT* |
600
780
VCC -1.3
10.0
mV
V
(OUT + OUT*) / 2 VCC - 1.5
VCC - 1.1
13.5
ISINK
ROUT
8.0
40
mA
Ω
50
60
Power Supply
Power Supply Current
IEE
170
235
mA
DC Test Conditions: Outputs unterminated.
AC Characteristics
(V = 2.0V to 3.6V; VEE = -3.6V to -3.0V; T = 0oC to 70oC)
CC
A
Parameter
Symbol
Min
Typ
Max
Units
High Performance Option
Propagation Delay
IN[0:3] to OUT[0:3] (SEL = 1)
CLK to OUT[0:3] (SEL = 0)
SEL to OUT [0:3]
Tpd
Tpd
Tpd
Tpd
200
430
300
250
350
550
430
360
550
780
650
600
ps
ps
ps
ps
EN to OUT [0:3]
Channel to Channel Skew
15
40
ps
GHz
ps
1
Maximum Operating Frequency
Fmax
3
1
Minimum Pulse Width
PW min
250
IN to CLK
Set Up Time
Hold Time
Ts
Th
120
120
ps
ps
1
Output Rise and Fall Times (20% / 80%)
Tr / Tf
125
<1
165
ps
1
o
Temperature Coefficient
ps / C
∆Tpd / ∆T
AC Test Conditions: Outputs terminated with 50Ω to VCC – 2V
Note:
1.
Guaranteed by characterization. Not production tested.
Revision 1/July 10, 2002
31
www.semtech.com
SK4440
Anything to ECL
HIGH-PERFORMANCE PRODUCTS
Description
ꢀeatures
The SK4440 is an extremely fast, stable and accurate •
low skew quad buffer or cable driver / receiver. It can •
asychronously pass four distinct signals, or it can •
resynchronize them to a common clock. In addition, all
four outputs may be asynchronously enabled or
disabled. All of the D flip-flops are triggered on the
rising edge of the CLK input. It is also capable of
receiving inputs of any technology or voltage level.
Quad Buffer/Receiver
3 GHz Fmax
Available in 32 lead, 5mm X5mm, TQFP
Package
Application Notes
AN1001 - EPIC Family Product Line
AN1003 - Termination Techniques for ECL / LVECL
PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL /
LVECL / ECL / LVPECL
The SK4440 has 100Ω input termination resistors
across each of the four inputs to help reduce system
component count and increase integration.
AN1008 - Interfacing with CML
The SK4440 uses 50Ω outputs with sink/source
capability, and is optimized for applications that require:
• Point to point, double terminated, timing
critical lines
Input Options
Output Options
• Point to point, series terminated, timing
critical lines
50Ω Source / Sink
VGG
IN
<
0 - 3
>
>
ꢀunctional Block Diagram
50Ω
50Ω
100
OUT
OUT
IN0
1
*
OUT0
IN<
0 - 3
*
IN0*
OUT0*
10 mA
VEE
10 mA
D
Q
0
D* Q*
VEE
IN1
1
0
OUT1
OUT1*
IN1*
r ECL / LVECL
and ECL /
D
Q
Q*
D*
IN2
1
0
Pin Description
OUT2
IN2*
OUT2*
Q
D
Q*
D*
IN3
1
0
OUT3
IN3*
OUT3*
D
Q
Q*
D*
CLK
CLK*
V
GG
V
CC
SEL*
SEL
EN
OUT1*
OUT1
SEL
SEL*
EN*
V
V
EE
EE
CLK*
CLK
OUT2
EN
OUT2*
EN*
V
GG
V
CC
Package Information
32 pin, 5 mm X 5 mm
TQFP Package
Revision 1/July 10, 2002
www.semtech.com
32
SK4440
Anything to ECL Receiver
HIGH-PERFORMANCE PRODUCTS
DC Characteristics
(V = - 0.1V to 2.0V; V = 2.0V to 3.6V; VEE = -3.6V to -3.0V; T = 0oC to 70oC)
GG
CC
A
Parameter
Symbol
Min
Typ
Max
Units
Inputs
Input High
Input Low
VIH
VIL
VEE + 2.0
VEE
VCC
V
V
VCC - 0.2
(IN - IN*, CLK - CLK*,
EN - EN*, SEL - SEL*)
Differential Input Voltage
| VIH - VIL |
0.2
4.3
V
Timing Inputs (CLK / CLK*)
Input High Current
IIH
IIL
-5
-1
+8.0
<0.5
100
+25
+1
µA
µA
Ω
Input Low Current
IN / IN* Differential Input Resistance
RIN
80
120
Functional Inputs (EN / EN*, SEL / SEL*)
Input Current
IIH, IIL
-500
<200
+500
µA
Outputs
Digital Output Voltage
Output Common Mode Range
Internal Current Source
Output Impedance
| OUT - OUT* |
(OUT + OUT*) / 2
ISINK
600
VGG - 1.5
8.0
780
VGG -1.3
10
mV
V
VGG - 1.1
13.5
mA
Ω
ROUT
40
50
60
Power Supply
IEE
ICC
190
70
250
110
mA
mA
Power Supply Current
DC Test Conditions: Outputs unterminated.
AC Characteristics
(V = - 0.1V to 2.0V; V = 2.0V to 3.6V; VEE = -3.6V to -3.0V; T = 0oC to 70oC)
GG
CC
A
Parameter
Symbol
Min
Typ
Max
Units
High Performance Option
Propagation Delay
IN[0:3] to OUT[0:3] (SEL = 1)
CLK to OUT[0:3] (SEL = 0)
SEL to OUT [0:3]
Tpd
Tpd
Tpd
Tpd
200
430
300
250
350
550
430
390
550
780
650
600
ps
ps
ps
ps
EN to OUT [0:3]
Channel to Channel Skew
40
80
ps
GHz
ps
1
Maximum Operating Frequency
Fmax
3
1
Minimum Pulse Width
PW min
250
IN to CLK
Set Up Time
Hold Time
Ts
Th
120
120
ps
ps
1
Output Rise and Fall Times (20% / 80%)
Tr / Tf
125
<1
165
ps
1
o
Temperature Coefficient
ps / C
∆Tpd / ∆T
AC Test Conditions: Outputs terminated with 50Ω to VGG – 2V
Note:
1.
Guaranteed by characterization. Not production tested.
Revision 1/July 10, 2002
33
www.semtech.com
SK44XX Family
Quad Buffer/Receiver
HIGH-PERFORMANCE PRODUCTS
Ordering Information
Ordering Code Package ID
32-TQFP
SK4400
5 x 5 mm
32-TQFP
SK4401
5 x 5 mm
32-TQFP
SK4404
5 x 5 mm
32-TQFP
SK4410
5 x 5 mm
32-TQFP
SK4411
5 x 5 mm
32-TQFP
SK4414
5 x 5 mm
32-TQFP
SK4425
5 x 5 mm
32-TQFP
SK4426
5 x 5 mm
32-TQFP
SK4429
5 x 5 mm
32-TQFP
SK4430
5 x 5 mm
32-TQFP
SK4435
5 x 5 mm
32-TQFP
SK4436
5 x 5 mm
32-TQFP
SK4439
5 x 5 mm
32-TQFP
SK4440
5 x 5 mm
Notes:
1.
For tape and reel, add the letter “T” at the
end of ordering code.
2.
For tape and reel information, see HPP Part
Ordering Information Data Sheet.
Contact Information
Semtech Corporation
High-Performance Products Division
Marketing Group
Division Headquarters
10021 Willow Creek Road
San Diego, CA 92131
Phone: (858) 695-1808
1111 Comstock Street
Santa Clara, CA 95054
Phone: (408) 566-8776
FAX:
(858)695-2633
FAX: (408) 566-8759
Revision 1/July 10, 2002
www.semtech.com
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