SRDA05-4_07 [SEMTECH]
Low Capacitance TVS Diode Array;
| 型号： | SRDA05-4_07 |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Low Capacitance TVS Diode Array 电视 |
| 文件： | 总11页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SRDA05-4 and SRDA12-4
RailClamp®
Low Capacitance TVS Diode Array
PROTECTION PRODUCTS - RailClamp®
Features
Description
RailClamps are surge rated diode arrays designed to
protect high speed data interfaces. The SRDA series
has been specifically designed to protect sensitive
components which are connected to data and trans-
mission lines from overvoltage caused by electrostatic
discharge (ESD), electrical fast transients (EFT), and
lightning.
Transient protection for high-speed data lines to
IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
IEC 61000-4-5 (Lightning) 24A (8/20μs)
Array of surge rated diodes with internal TVS diode
Protects four I/O lines
Low capacitance (<15pF) for high-speed interfaces
Low operating and clamping voltages
Solid-state technology
The unique design incorporates surge rated, low
capacitance steering diodes and a TVS diode in a
single package. During transient conditions, the
steering diodes direct the transient current to ground
via the internal low voltage TVS. The TVS diode clamps
the transient voltage to a safe level. The low capaci-
tance array configuration allows the user to protect up
to four high-speed data lines. The SRDA05-4 may be
used to protect lines operating up to 5 volts while the
SRDA12-4 may be used on lines operating up to 12
volts.
Mechanical Characteristics
JEDEC SOIC-8 package
Lead Finish: SnPb or Matte Sn
Molding compound flammability rating: UL 94V-0
Marking : Part number, date code, logo
Packaging : Tape and Reel per EIA 481
Applications
These devices are in a 8-pin SOIC package. They are
available with a SnPb or RoHS/WEEE compliant matte
tin lead finish. The high surge capability (Ipp=25A,
tp=8/20μs) means it can be used in high threat
environments in applications such as CO/CPE equip-
ment, telecommunication lines, and video lines.
USB Power and Data Line Protection
T1/E1 secondary IC Side Protection
T3/E3 secondary IC Side Protection
HDSL, SDSL secondary IC Side Protection
Video Line Protection
Microcontroller Input Protection
Base stations
I2C Bus Protection
Circuit Diagram
Schematic and PIN Configuration
I/O 1
REF 1
REF 1
I/O 2
1
8
REF 2
REF1
2
3
7
6
I/O 4
I/O 3
I/O 1
I/O 2
I/O 3
I/O 4
REF2
REF 2
4
5
S0-8 (Top View)
www.semtech.com
Revision 8/21/07
1
SRDA05-4 and SRDA12-4
PROTECTION PRODUCTS
Absolute Maximum Rating
Rating
Peak Pulse Power (tp = 8/20μs)
Peak Forward Voltage (IF = 1A, tp=8/20μs)
Lead Soldering Temperature
Operating Temperature
Symbol
Ppk
Value
500
Units
Watts
V
VFP
1.5
TL
260 (10 sec.)
-55 to +125
-55 to +150
°C
TJ
°C
Storage Temperature
TSTG
°C
Electrical Characteristics (T=25oC)
SRDA05-4
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage
Symbol
VRWM
VBR
IR
Conditions
Minimum
Typical
Maximum
Units
5
V
V
It = 1mA
6
VRWM = 5V, T=25°C
IPP = 1A, tp = 8/20μs
IPP = 10A, tp = 8/20μs
IPP = 25A, tp = 8/20μs
tp = 8/20μs
10
9.8
12
20
25
15
μA
V
VC
Clamping Voltage
VC
V
Clamping Voltage
VC
V
Peak Pulse Current
IPP
A
Junction Capacitance
Cj
Between I/O pins and
Ground
VR = 0V, f = 1MHz
8
4
pF
Between I/O pins
VR = 0V, f = 1MHz
pF
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© 2007 Semtech Corp.
2
SRDA05-4 and SRDA12-4
PROTECTION PRODUCTS
Electrical Characteristics (continued)
SRDA12-4
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage
Symbol
VRWM
VBR
IR
Conditions
Minimum
Typical
Maximum
Units
12
V
V
It = 1mA
13.3
VRWM = 12V, T=25°C
IPP = 1A, tp = 8/20μs
IPP = 10A, tp = 8/20μs
IPP = 20A, tp = 8/20μs
tp = 8/20μs
1
μA
V
VC
17
20
25
20
15
Clamping Voltage
VC
V
Clamping Voltage
VC
V
Peak Pulse Current
IPP
A
Junction Capacitance
Cj
Between I/O pins and
Ground
VR = 0V, f = 1MHz
8
4
pF
Between I/O pins
VR = 0V, f = 1MHz
pF
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© 2007 Semtech Corp.
3
SRDA05-4 and SRDA12-4
PROTECTION PRODUCTS
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
Power Derating Curve
10
1
110
100
90
80
70
60
50
40
30
20
10
0
0.1
0.01
0
25
50
75
100
125
150
0.1
1
10
100
1000
Ambient Temperature - TA (oC)
Pulse Duration - tp (µs)
Pulse Waveform
Clamping Voltage vs. Peak Pulse Current
110
100
90
80
70
60
50
40
30
20
10
0
22
W aveform
Parameters:
tr = 8µs
20
SRDA12-4
18
16
td = 20µs
SRDA05-4
e-t
14
12
10
SRDA3.3-4
8
td = IPP/2
6
4
2
0
Waveform
Parameters:
tr = 8µs
td = 20µs
0
5
10
15
20
25
30
0
5
10
15
20
25
30
Tim e (µs)
Peak Pulse Current - IPP (A)
Variation of Capacitance vs. Reverse Voltage
Forward Voltage vs. Forward Current
1.04
10
9
8
7
6
5
4
3
2
1
0
1.02
1
0.98
0.96
0.94
0.92
0.9
Waveform
Parameters:
μ
tr = 8 s
μ
td = 20 s
0.88
0
5
10
15
20
25
30
35
40
45
50
0
0.5
1
1.5
2
2.5
3
3.5
Forward Current - IF (A)
Reverse Voltage - VR (V)
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© 2007 Semtech Corp.
4
SRDA05-4 and SRDA12-4
PROTECTION PRODUCTS
Applications Information
Device Connection Options for Protection of Four
High-Speed Lines
Data Line and Power Supply Protection Using Vcc as
reference
The SRDA TVS is designed to protect four data lines
from transient overvoltages by clamping them to a
fixed reference. When the voltage on the protected
line exceeds the reference voltage (plus diode VF) the
steering diodes are forward biased, conducting the
transient current away from the sensitive circuitry.
Data lines are connected at pins 1, 4, 6 and 7. The
negative reference is connected at pins 5 and 8.
These pins should be connected directly to a ground
plane on the board for best results. The path length is
kept as short as possible to minimize parasitic induc-
tance.
The positive reference is connected at pins 2 and 3.
The options for connecting the positive reference are
as follows:
Data Line Protection with Bias and Power Supply
Isolation Resistor
1. To protect data lines and the power line, connect
pins 2 & 3 directly to the positive supply rail (VCC).
In this configuration the data lines are referenced
to the supply voltage. The internal TVS diode
prevents over-voltage on the supply rail.
2. The SRDA can be isolated from the power supply by
adding a series resistor between pins 2 and 3 and
VCC. A value of 10kΩ is recommended. The
internal TVS and steering diodes remain biased,
providing the advantage of lower capacitance.
3. In applications where no positive supply reference
is available, or complete supply isolation is desired,
the internal TVS may be used as the reference. In
this case, pins 2 and 3 are not connected. The
steering diodes will begin to conduct when the
voltage on the protected line exceeds the working
voltage of the TVS (plus one diode drop).
Data Line Protection Using Internal TVS Diode as
Reference
ESD Protection With RailClamps
RailClamps are optimized for ESD protection using the
rail-to-rail topology. Along with good board layout,
these devices virtually eliminate the disadvantages of
using discrete components to implement this topology.
Consider the situation shown in Figure 1 where dis-
crete diodes or diode arrays are configured for rail-to-
rail protection on a high speed line. During positive
duration ESD events, the top diode will be forward
biased when the voltage on the protected line exceeds
the reference voltage plus the V drop of the diode.
For negative events, the bottomFdiode will be biased
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© 2007 Semtech Corp.
5
SRDA05-4 and SRDA12-4
PROTECTION PRODUCTS
Applications Information (continued)
when the voltage exceeds the V of the diode. At first
F
approximation, the clamping voltage due to the charac-
teristics of the protection diodes is given by:
V = V + V
F
(for positive duration pulses)
C
CC
PIN Descriptions
V = -V
(for negative duration pulses)
C
F
However, for fast rise time transient events, the
effects of parasitic inductance must also be consid-
ered as shown in Figure 2. Therefore, the actual
clamping voltage seen by the protected circuit will be:
Figure 1 - “Rail-To-Rail” Protection Topology
(First Approximation)
V = V + V + L di /dt (for positive duration pulses)
C
CC
F
P
ESD
V = -V - L di /dt
(for negative duration pulses)
C
F
G
ESD
ESD current reaches a peak amplitude of 30A in 1ns
for a level 4 ESD contact discharge per IEC 61000-4-2.
Therefore, the voltage overshoot due to 1nH of series
inductance is:
V = L di /dt = 1X10-9 (30 / 1X10-9) = 30V
P
ESD
Example:
Consider a V = 5V, a typical V of 30V (at 30A) for the
CC
F
steering diode and a series trace inductance of 10nH.
The clamping voltage seen by the protected IC for a
positive 8kV (30A) ESD pulse will be:
Figure 2 - The Effects of Parasitic Inductance When
Using Discrete Components to Implement Rail-To-Rail
Protection
V = 5V + 30V + (10nH X 30V/nH) = 335V
C
This does not take into account that the ESD current is
directed into the supply rail, potentially damaging any
components that are attached to that rail. Also note
the high V of the discrete diode. It is not uncommon
F
for the V of discrete diodes to exceed the damage
F
threshold of the protected IC. This is due to the
relatively small junction area of typical discrete compo-
nents. It is also possible that the power dissipation
capability of the discrete diode will be exceeded, thus
destroying the device.
The RailClamp is designed to overcome the inherent
disadvantages of using discrete signal diodes for ESD
suppression. The RailClamp’s integrated TVS diode
helps to mitigate the effects of parasitic inductance in
Figure 3 - Rail-To-Rail Protection Using
RailClamp TVS Arrays
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© 2007 Semtech Corp.
6
SRDA05-4 and SRDA12-4
PROTECTION PRODUCTS
Applications Information (continued)
the power supply connection. During an ESD event,
the current will be directed through the integrated TVS
diode to ground. The total clamping voltage seen by
the protected IC due to this path will be:
V = V
+ V
TVS
C
F(RailClamp)
This is given in the data sheet as the rated clamping
voltage of the device. For an SRDA05-4 the typical
clamping voltage is <16V at I =30A. The diodes
internal to the RailClamp arePlPow capacitance, fast
switching devices that are rated to handle high tran-
sient currents and maintain excellent forward voltage
characteristics.
Using the RailClamp does not negate the need for good
board layout. All other inductive paths must be consid-
ered. The connection between the positive supply and
the SRDA and from the ground plane to the SRDA
must be kept as short as possible. The path between
the SRDA and the protected line must also be mini-
mized. The protected lines should be routed directly to
the SRDA. Placement of the SRDA on the PC board is
also critical for effective ESD protection. The device
should be placed as close as possible to the input
connector. The reason for this is twofold. First,
inductance resists change in current flow. If a signifi-
cant inductance exists between the connector and the
TVS, the ESD current will be directed elsewhere (lower
resistance path) in the system. Second, the effects of
radiated emissions and transient coupling can cause
upset to other areas of the board even if there is no
direct path to the connector. By placing the TVS close
to the connector it will divert the ESD current immedi-
ately and absorb the ESD energy before it can be
coupled into nearby traces.
www.semtech.com
© 2007 Semtech Corp.
7
SRDA05-4 and SRDA12-4
PROTECTION PRODUCTS
Typical Applications
Universal Serial Bus ESD Protection
LC01-6
8
1
5
4
SRDA05-4
LC01-6
T1/E1 Interface Protection
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© 2007 Semtech Corp.
8
SRDA05-4 and SRDA12-4
PROTECTION PRODUCTS
Applications Information - Spice Model
Pin 3
Pin 1
0.6 nH
Pin 8
SRDA05-4 & SRDA12-4 Spice Model
SRDA05-4 & SRDA12-4 Spice Parameters
SRDA05-4
D3 (TVS)
SRDA12-4
D3 (TVS)
Parameter
Unit
D1 (LCRD)
D2 (LCRD)
IS
BV
VJ
Amp
Volt
Volt
Ohm
Amp
Farad
sec
--
2.092E-11
680
2.156E-12
240
1.4E-14
6.70
1.43E-14
15
0.62
0.64
.56
.78
RS
IBV
CJO
TT
0.180
1.0 E-3
5.2E-12
2.541E-9
0.058
1.1
0.155
1.0 E-3
6.2E-12
2.541E-.9
0.058
1.1
0.56
0.40
1.0 E-3
307E-12
2.541E-9
0.247
1.1
1.0 E-3
71E-12
2.541E-9
0.246
1.1
M
N
--
EG
eV
1.11
1.11
1.11
1.11
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© 2007 Semtech Corp.
9
SRDA05-4 and SRDA12-4
PROTECTION PRODUCTS
Outline Drawing - SO-8
A
h
D
E
e
DIMENSIONS
N
INCHES
MIN NOM MAX MIN NOM MAX
MILLIMETERS
h
DIM
A
H
E/2
2X
-
-
-
-
-
-
-
-
-
-
.053
A1 .004
A2 .049
.069 1.35
.010 0.10
.065 1.25
.020 0.31
.010 0.17
1.75
0.25
1.65
0.51
0.25
E1
c
GAGE
PLANE
b
c
.012
.007
1
2
D
.189 .193 .197 4.80 4.90 5.00
0.25
L
E1 .150 .154 .157 3.80 3.90 4.00
E
e
h
L
ccc
C
01
(L1)
.236 BSC
6.00 BSC
2X N/2 TIPS
e/2
.050 BSC
-
1.27 BSC
-
0.50
DETAIL A
.010
.020 0.25
B
.016 .028 .041 0.40 0.72 1.04
(.041)
8
-
.004
.010
.008
(1.04)
8
-
0.10
0.25
0.20
L1
N
01
aaa
bbb
ccc
D
0°
8°
0°
8°
aaa C
A2
A
SEE DETAIL A
SEATING
PLANE
SIDE VIEW
C
A1
bxN
bbb
C
A-B D
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
REFERENCE JEDEC STD MS-012, VARIATION AA.
4.
Land Pattern - SO-8
X
DIMENSIONS
DIM
INCHES
MILLIMETERS
(.205)
(5.20)
3.00
1.27
0.60
2.20
7.40
C
G
P
X
Y
Z
.118
.050
.024
.087
.291
(C)
G
Y
Z
P
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2.
REFERENCE IPC-SM-782A, RLP NO. 300A.
www.semtech.com
© 2007 Semtech Corp.
10
SRDA05-4 and SRDA12-4
PROTECTION PRODUCTS
Ordering Information
Marking Diagram
Qty per
Reel
Part Number
Lead Finish
Reel Size
SC YYWW
SRDA05-4
PHIL
SC YYWW
SRDA12-4
PHIL
SRDA05-4.TB
SRDA05-4.TBT
SRDA12-4.TB
SRDA12-4.TBT
SnPb
Matte Sn
SnPb
500
500
500
500
7 Inch
7 Inch
7 Inch
7 Inch
Matte Sn
Note:
YYWW = Date Code
Note: Lead-free devices are RoHS/WEEE Compliant
Tape and Reel Specification
Pin 1 Location
User Direction of feed
Device Orientation in Tape
A0
B0
K0
6.50 +/-0.20 mm
5.40 +/-0.20 mm
2.00 +/-0.10 mm
Tape
K
(MAX)
B, (Max)
Width
D
D1
E
F
P
P0
P2
T(MAX)
W
12.0 mm
±0.3
1.5 + 0.1 mm 1.5 mm
- 0.0 mm
1.750±.10
mm
5.5±0.05
mm
4.0±0.1
mm
4.0±0.1
mm
2.0±0.05
mm
12 mm
8.2 mm
4.5 mm
0.4 mm
Contact Information
Semtech Corporation
Protection Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
www.semtech.com
© 2007 Semtech Corp.
11
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