TS30042-M015QFNR [SEMTECH]
High E! ciency 1A/2A Current-Mode Synchronous Buck Converter, 1MHz;
| 型号： | TS30042-M015QFNR |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | High E! ciency 1A/2A Current-Mode Synchronous Buck Converter, 1MHz |
| 文件： | 总18页 (文件大小：1346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TS30041/42
High E!ciency 1A/2A Current-Mode
Synchronous Buck Converter, 1MHz
TRIUNE PRODUCTS
Features
Description
•
Fixed output voltage choices: 1.5V, 1.8V, 2.5V, 3.3V, and 5V
with +/- 2% output tolerance
The TS30041 (1A) and TS30042 (2A) are DC/DC synchronous
switching regulators with fully integrated power switches,
internal compensation, and full fault protection. The switching
frequency of 1MHz enables the use of small !lter components
resulting in minimal board space and reduced BOM costs.
•
Adjustable version output voltage range: 0.9V to (VCC -
1V) with +/- 1.5% reference
•
•
•
•
•
Wide input voltage range: 4.5V to 40V (42V Abs Max)
1MHz +/- 10% !xed switching frequency
Continuous output current: 1A (TS30041), 2A (TS30042)
High e"ciency up to 95%
The TS30041/42 utilizes current mode feedback in normal
regulation PWM mode. When the regulator is placed in
standby (EN is low), the device draws less than 10uA quiescent
current.
Current mode PWM control with PFM mode for improved
light load e"ciency
•
Voltage supervisor for VOUT reported at the Power Good
(PG) pin
The TS30041/42 integrates a wide range of protection circuitry
including input supply under-voltage lockout, output voltage
soft start, current limit, and thermal shutdown.
•
•
•
Input supply under voltage lockout
Soft start for controlled startup with no overshoot
Full protection for over-current, over-temperature, and
VOUT over-voltage
The TS30041/42 includes supervisory reporting through
the PG (Power Good) open drain output to interface other
components in the system.
•
SYNC function on EN/SYNC pin to control switching fre-
quency
•
•
Less than 10uA in standby mode
Low external component count
Summary Speci"cation
•
•
•
Junction operating temperature -40 °C to 125 °C
Packaged in a 16pin QFN (3x3)
Applications
ROHS: “Product is lead-free, Halogen Free, RoHS/WEEE
compliant”
•
•
•
On-card switching regulators
Set-top box, DVD, LCD, LED supply
Industrial power supplies
Typical Application Circuit
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TS30041/42
Final Datasheet
July 27, 2016
1 of 18
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Rev 2.2
Pin Con!guration
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Figure 1: 16 Lead 3x3 QFN, Top View
Pin Description
Pin # Pin Symbol Function
Description
Switching Voltage Node Connected to 4.7uH (typical) inductor
1
2
3
4
VSW
VCC
VCC
GND
Input Voltage
Input Voltage
GND
Input voltage
Input voltage
Primary ground for the majority of the device except the low-side power FET
Regulator FB Voltage. Connects to VOUT for fixed mode and the output
resistor divider for adjustable mode
Feedback Input
5
FB
No Connect
Not Connected
Not Connected
Open-drain output
6
7
8
NC
NC
PG
No Connect
Power Good Output
Above 2.2V the device is enabled. GND the pin to put device in standby
mode. Includes internal pull-up. Also used for SYNC function
Enable & Sync Input
9
EN/SYNC
BST
Bootstrap capacitor for the high-side FET gate driver. A ceramic capacitor in
the range 15 nF - 200 nF from BST pin to VSW pin
Bootstrap Capacitor
Input Voltage
10
Input Voltage
11
12
13
14
15
16
17
VCC
Switching Voltage Node Connected to 4.7uH (typical) inductor
Switching Voltage Node Connected to 4.7uH (typical) inductor
VSW
VSW
PGND
PGND
VSW
PAD
Power GND
Power GND
GND supply for internal low-side FET/integrated diode
GND supply for internal low-side FET/integrated diode
Switching Voltage Node Connected to 4.7uH (typical) inductor
Power PAD
Power GND
TS30041/42
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Rev 2.2
Functional Block Diagrams
Figure 2: TS30041/42 Block Diagram
Figure 3: Monitor & Control Logic Functionality
TS30041/42
Final Datasheet
July 27, 2016
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Rev 2.2
Absolute Maximum Ratings
Over operating free–air temperature range unless otherwise noted(1,2,3)
Parameter
Value
-0.3 to 42
-0.3 to (VCC+6)
-1 to 42
-0.3 to 6
+/-2k
Unit
V
VCC
BST
V
VSW
V
EN, PG,FB
V
Electrostatic Discharge – Human Body Model
Electrostatic Discharge – Charge Device Model
Lead Temperature (soldering, 10 seconds)
V
+/-500
V
260
OC
Note 1: Stresses beyond those listed under “absolute maximum ratings”may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions”is not implied.
Exposure to absolute–maximum–rated conditions for extended periods may a!ect device reliability.
Note 2: All voltage values are with respect to network ground terminal.
Note 3: MOSFETs minimum breakdown voltage is 48V.
Thermal Characteristics
Over operating free–air temperature range unless otherwise noted(1,2)
Symbol
Parameter
Value
34.5
Unit
°C/W
°C/W
°C
θ
Thermal Resistance Junction to Air (Note 1)
Thermal Resistance Junction to Case (Note 1)
Storage Temperature Range
JA
θ
2.5
JC
TSTG
TJ MAX
TJ
-65 to 150
150
Maximum Junction Temperature
Operating Junction Temperature Range
°C
-40 to 125
°C
Note 1: Assumes 16LD 3x3 QFN with hi-K JEDEC board and 13.5 inch2 of 1 oz Cu and 4 thermal vias connected to PAD.
Recommended Operating Conditions
Symbol
Parameter
Input Operating Voltage
Min
Typ
Max
Units
40
VCC
4.5
12
V
CBST
Bootstrap Capacitor
15
3.76
33
2
22
4.7
200
nF
uH
uF
LOUT
Output Filter Inductor Typical Value (Note 1)
Output Filter Capacitor Typical Value(Note 2)
Output Filter Capacitor ESR
5.64
COUT
44 (2 x 22)
COUT-ESR
CBYPASS
100
mΩ
uF
Input Supply Bypass Capacitor Typical Value (Note 3)
8
10
Note 1: For best performance, an inductor with a saturation current rating higher than the maximum VOUT load requirement plus the inductor current ripple.
Note 2: For best performance, a low ESR ceramic capacitor should be used.
Note 3: For best performance, a low ESR ceramic capacitor should be used. If CBYPASS is not a low ESR ceramic capacitor, a 0.1uF ceramic capacitor should
be added in parallel to CBYPASS
TS30041/42
Final Datasheet
July 27, 2016
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Rev 2.2
Electrical Characteristics
Electrical Characteristics, TJ = -40C to 125C, VCC = 12V (unless otherwise noted)
Parameter
Symbol
Condition
Min
Typ
Max
Units
VCC Supply Voltage
Input Supply Voltage
VCC
4.5
40
V
Quiescent current Normal Mode
ICC-NORM
VCC = 12V, ILOAD = 0A
3.6
mA
VCC=12V, ILOAD=0A,
Non-switching
Quiescent current Normal Mode
– Non-switching
ICC-NOSWITCH
ICC-STBY
2.5
5
mA
uA
Quiescent current Standby Mode
VCC Under Voltage Lockout
VCC = 12V, EN = 0V
10
Input Supply Under Voltage Threshold
VCC-UV
VCC Increasing
4.3
4.5
V
Input Supply Under Voltage Threshold
Hysteresis
VCC-UV_HYST
350
mV
OSC
fOSC
Oscillator Frequency (Internal)
SYNC Frequency(1)
0.9
0.3
1
1.1
2.2
MHz
MHz
fSYNC
PG Open Drain Output
tPG
PG Release Timer
10
ms
uA
V
IOH-PG
VOL-PG
High-Level Output Leakage
Low-Level Output Voltage
VPG = 5V
0.5
IPG = -0.3mA
0.01
0.8
EN/Sync Input Voltage Thresholds
High Level Input Voltage
Low Level Input Voltage
Input Hysteresis
VIH-EN
VIL-EN
2.2
V
V
VHYST-EN
480
3.5
mV
uA
uA
VEN=5V
VEN=0V
Input Leakage
IIN-EN
-1.5
Thermal Shutdown
Thermal Shutdown Junction Temperature
TSD
Note: not tested in production
150
170
°C
°C
TSDHYST
TSD Hysteresis
Note: not tested in production
10
Note 1: SYNC frequency range is tested with a square wave. Operation with a 200ns minimum high pulse is required.
TS30041/42
Final Datasheet
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Rev 2.2
Regulator Characteristics
Electrical Characteristics, TJ = -40C to 125C (unless otherwise noted)
Parameter
Symbol
Condition
Min
Type
Max
Units
Switch Mode Regulator: L=4.7uH and C=2 x 22uF
Output Voltage Tolerance in
VOUT-PWM
ILOAD =1A
VOUT – 2%
VOUT – 1%
VOUT
VOUT + 2%
V
V
PWM Mode
Output Voltage Tolerance in
VOUT-PFM
ILOAD = 0A
VOUT + 1%
VOUT + 3.5%
PFM Mode
High Side Switch On Resistance
RDSON
Low Side Switch On Resistance
IVSW = -1A (Note 1)
IVSW = 1A (Note 1)
TS30042 (Note 4)
TS30041 (Note 4)
TS30042
180
mΩ
mΩ
A
120
2
1
Output Current
IOUT
A
2.4
1.4
2.8
1.8
3.4
A
Over Current Detect
IOCD
(High Side Switch Current)
TS30041
(Note 3)
2.4
0.914
1.5
A
V
Feedback Reference
(Adjustable Mode)
FBTH
0.886
-1.5
0.9
Feedback Reference Tolerance
Soft start Ramp Time
FBTH-TOL
TSS
(Note 3)
%
Guaranteeed by Design
4
ms
PFM Mode FB Comparator
Threshold
FBTH-PFM
VOUT + 1%
V
VOUT Under Voltage Threshold
VOUT Under Voltage Hysteresis
VOUT Over Voltage Threshold
VOUT Over Voltage Hysteresis
Max Duty Cycle
VOUT-UV
VOUT-UV_HYST
VOUT-OV
91% VOUT
93% VOUT
1.5% VOUT
103% VOUT
1% VOUT
97%
95% VOUT
VOUT-OV_HYST
DUTYMAX
T0N-MIN
(Note 2)
95%
99%
Minimum On Time
Not tested in production
100
ns
Note 1: RDSON is characterized at 1A and tested at lower current in production.
Note 2: Regulator VSW pin is forced o" for 240ns every 16 cycles to ensure the BST cap is replenished.
Note 3: For the adjustable version, the ratio of VCC/Vout cannot exceed 16.
Note 4: Based on Over Current Detect testing
TS30041/42
Final Datasheet
July 27, 2016
6 of 18
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Rev 2.2
Typical Performance Characteristics
TJ = -40C to 125C, VCC = 12V (unless otherwise noted)
Figure 4. Startup Response
Figure 5. 100mA to 1A Load Step (VCC=12V, VOUT=3.3V)
VOUT
100mV/div
VOUT
5V/div
EN
IOUT
1V/div
500mA/div
5ms/div
100us/div
Figure 6. 100mA to 2A Load (VCC=12V, VOUT=3.3V)
Figure 7. 100mA to 1A Load Step (VCC=12V, VOUT=1.8V)
VOUT
VOUT
100mV/div
100mV/div
IOUT
IOUT
500mA/div
1A/div
100us/div
100us/div
Figure 8. 100mA to 2A Load Step (VCC=12V, VOUT=1.8V)
Figure 9. Line Transient Response (VCC=12V, VOUT=3.3V)
VIN
VOUT
5V/div
100mV/div
VOUT
0.5V/div
IOUT
1A/div
100us/div
10ms/div
TS30041/42
Final Datasheet
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Rev 2.2
Typical Performance Characteristics continued
TJ = -40C to 125C, VCC = 12V (unless otherwise noted)
Figure 10. Load Regulation
Figure 11. Line Regulation (IOUT=1A)
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Figure 12. E!ciency vs. Output Current ( VOUT = 3.3V)
Figure 13. E!ciency vs. Output Current ( VOUT = 5V)
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Figure 14. E!ciency vs. Output Current ( VOUT = 1.8V)
Figure 15. E!ciency vs. Input Voltage (VOUT = 3.3V)
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TS30041/42
Final Datasheet
8 of 18
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Rev 2.2
Typical Performance Characteristics continued
TJ = -40C to 125C, VCC = 12V (unless otherwise noted)
Figure 16. Standby Current vs. Input Voltage
Figure 17. Standby Current vs. Temperature
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Figure 18. Output Voltage vs. Temperature
Figure 19. Oscillator Frequency vs. Temperature (IOUT=300mA)
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Figure 20. Quiescent Current vs. Temperature (No load)
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TS30041/42
Final Datasheet
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Rev 2.2
Functional Description
Detailed Pin Description
Unregulated input, VCC
The TS30041/42 current-mode synchronous step-down power
supply product is ideal for use in the commercial, industrial,
and automotive market segments. It includes !exibility to be
used for a wide range of output voltages and is optimized for
high e"ciency power conversion with low RDSON integrated
synchronous switches. A 1MHz internal switching frequency
facilitates low cost LC #lter combinations. Additionally, the
#xed output versions enable a minimum external component
count to provide a complete regulation solution with only 4
external components: an input bypass capacitor, an inductor,
an output capacitor, and the bootstrap capacitor. The regulator
automatically transitions between PFM and PWM mode to
maximize e"ciency for the load demand.
This terminal is the unregulated input voltage source for the
IC. It is recommended that a 10uF bypass capacitor be placed
close to the device for best performance. Since this is the main
supply for the IC, good layout practices need to be followed for
this connection.
Bootstrap control, BST
This terminal will provide the bootstrap voltage required for
the upper internal NMOS switch of the buck regulator. An
external ceramic capacitor placed between the BST input
terminal and the VSW pin will provide the necessary voltage
for the upper switch. In normal operation the capacitor is
re-charged on every low side synchronous switching action.
In the case of where the switch mode approaches 100% duty
cycle for the high side FET, the device will automatically reduce
the duty cycle switch to a minimum o$ time on every 16th
cycle to allow this capacitor to re-charge.
The TS30041/42 was designed to provide these system
bene#ts:
•
•
Reduced board real estate
Lower system cost
s
s
Lower cost inductor
Low external parts count
Sense feedback, FB
•
•
Ease of design
This is the input terminal for the output voltage feedback.
s
s
s
s
Bill of Materials and suggested board layout provided
Power Good output
For the #xed mode versions, this should be hooked directly
to VOUT. The connection on the PCB should be kept as short
as possible, and should be made as close as possible to the
capacitor. The trace should not be shared with any other
connection. (Figure 22)
Integrated compensation network
Wide input voltage range
Robust solution
Over current, over voltage and over temperature
protection
s
For adjustable mode versions, this should be connected to
the external resistor divider. To choose the resistors, use the
following equation:
VOUT = 0.9 (1 + RTOP/RBOT
)
The input to the FB pin is high impedance, and input current
should be less than 100nA. As a result, good layout practices
are required for the feedback resistors and feedback traces.
When using the adjustable version, the feedback trace should
be kept as short as possible and minimum width to reduce
stray capacitance and to reduce the injection of noise.
For the adjustable version, the ratio of VCC/Vout cannot
exceed 16.
TS30041/42
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Rev 2.2
Switching output, VSW
Under extended over current conditions (such as a short),
the device will automatically disable. Once the over current
condition is removed, the device returns to normal opera-
tion automatically. (Alternately the factory can con"gure the
device’s NVM to shutdown the regulator if an extended over
current event is detected and require a toggle of the Enable
pin to return the device to normal operation.)
This is the switching node of the regulator. It should be
connected directly to the 4.7uH inductor with a wide, short
trace and to one end of the Bootstrap capacitor. It is switching
between VCC and PGND at the switching frequency.
Ground, GND
This ground is used for the majority of the device including the
analog reference, control loop, and other circuits.
Thermal Shutdown
If the temperature of the die exceeds 170°C (typical), the VSW
outputs will tri-state to protect the device from damage. The
PG and all other protection circuitry will stay active to inform
the system of the failure mode. Once the device cools to 160°C
(typical), the device will start up again, following the normal
soft start sequence. If the device reaches 170°C, the shutdown/
restart sequence will repeat.
Power Ground, PGND
This is a separate ground connection used for the low side
synchronous switch to isolate switching noise from the rest of
the device. (Figure 22)
Enable/Synchronize, high-voltage, EN/SYNC
This is the input terminal to activate the regulator. The input
threshold is TTL/CMOS compatible. It also has an internal pull-
up to ensure a stable state if the pin is disconnected.
After a sequence of three rising edge pulses having a
frequency greater than or equal to FSync-Min, the switcher
synchronizes to the frequency of the signal provided on the
EN/SYNC pin. SYNC frequency range is tested with a square
wave and a high pulse of minimum 200ns duration is required
for proper operation. For highier frequencies of operation a
2.2uH inductor and for lower frequencies of operation a 10uH
inductor is recommended.
Reference Soft Start
The reference in this device is ramped at a rate of 4ms to
prevent the output from overshoot during startup. This ramp
restarts whenever there is a rising edge sensed on the Enable
pin. This occurs in both the "xed and adjustable versions.
During the soft start ramp, current limit is still active, and will
still protect the device in case of a short on the output.
Output Overvoltage
If the output of the regulator exceeds 103% of the regulation
voltage, the VSW outputs will tri-state to protect the device
from damage. This check occurs at the start of each switching
cycle. If it occurs during the middle of a cycle, the switching
for that cycle will complete, and the VSW outputs will tri-state
at the beginning of the next cycle.
Power Good Output, PG
This is an open drain, active low output. The switched mode
output voltage is monitored and the PG line will remain low
until the output voltage reaches the VOUT-UV threshold.
Once the internal comparator detects the output voltage
is above the desired threshold, an internal delay timer is
activated and the PG line is de-asserted to high once this
delay timer expires. In the event the output voltage decreases
below VOUT-UV, the PG line will be asserted low and remain
low until the output rises above VOUT-UV and the delay timer
times out. See Figure 3 for the circuit schematic for the PG
signal.
VCC Under-Voltage Lockout
The device is held in the o$ state until VCC reaches 4.3V
(typical). There is a 350mV hysteresis on this input, which
requires the input to fall below 4.0V (typical) before the device
will disable.
Transient Response
Internal Protection Details
TS30041/42 has been designed to work under a wide range
of input and output voltages, supporting di$erent values and
types of output capacitance. By design, TS30041/42 adjustable
output version has lower bandwidth than "xed version. For
adjustable output version designs, with a high slew rate load
requirement using a 10nF feed-forward capacitor in parallel
with the RTOP feedback resistor is recommended.
Internal Current Limit
The current through the high side FET is sensed on a cycle
by cycle basis and if current limit is reached, it will abbreviate
the cycle. In addition, the device senses the FB pin to identify
hard short conditions and will direct the VSW output to skip 4
cycles if current limit occurs when FB is low. This allows current
built up in the inductor during the minimum on time to decay
su!ciently. Current limit is always active when the regulator
is enabled. Soft start ensures current limit does not prevent
regulator startup.
TS30041/42
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Rev 2.2
Typical Application Schematic
Ç{ꢀꢁꢁꢂꢃꢄꢂꢅ
Figure 21: TS30041/42 Application Schematic
A minimal schematic suitable for most applications is shown on page 1. Figure 21 includes optional components that may be
considered to address speci!c issues as listed in the External Component Selection section.
PCB Layout
For proper operation and minimum EMI, care must be taken during PCB layout. An improper layout can lead to issues such as poor
stability and regulation, noise sensitivity and increased EMI radiation. (Figure 22) The main guidelines are the following:
•
•
•
provide low inductive and resistive paths for loops with high di/dt,
provide low capacitive paths with respect to all the other nodes for traces with high di/dt,
sensitive nodes not assigned to power transmission should be referenced to the analog signal ground (GND) and be
always separated from the power ground (PGND).
The negative ends of CBYPASS, COUT and the Schottky diode DCATCH (optional) should be placed close to each other and
connected using a wide trace. Vias must be used to connect the PGND node to the ground plane. The PGND node must be placed
as close as possible to the TS30041/42 PGND pins to avoid additional voltage drop in traces.
The bypass capacitor CBYPASS (optionally paralleled to a 0.1µF capacitor) must be placed close to the VCC pins of TS30041/42.
The inductor must be placed close to the VSW pins and connected directly to COUT in order to minimize the area between the
VSW pin, the inductor, the COUT capacitor and the PGND pins. The trace area and length of the switching nodes VSW and BST
should be minimized.
For the adjustable output voltage version of the TS30041/42, feedback resistors RBOT and RTOP are required for Vout settings
greater than 0.9V and should be placed close to the TS30041/42 in order to keep the traces of the sensitive node FB as short as
possible and away from switching signals. RBOT should be connected to the analog ground pin (GND) directly and should never
be connected to the ground plane. The analog ground trace (GND) should be connected in only one point to the power ground
(PGND). A good connection point is under the TS30041/42 package to the exposed thermal pad and vias which are connected to
PGND. RTOP will be connected to the VOUT node using a trace that ends close to the actual load.
For !xed output voltage versions of the TS30041/42, RBOT and RTOP are not required and the FB pin should be connected directly to
the Vout.
The exposed thermal pad must be soldered to the PCB for mechanical reliability and to achieve good power dissipation. Vias must
be placed under the pad to transfer the heat to the ground plane.
TS30041/42
Final Datasheet
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Rev 2.2
Figure 22: TS30041/42 PCB Layout, Top View
External Component Bill of Material
Suggested
Manufacturer
Designator
Function
Description
Manufacturer Code
Qty
CBYPASS
Input Supply Bypass Capacitor
10uF 10% 50V
1
TDK
Wurth
C2012X5R1A226K125AB
885 012 208 019
COUT
Output Filter Capacitor
22uF 10% 10V
2
SLF7045T-4R7M2R0-PF
7447745047
LOUT
LOUT
Output Filter Inductor (1A)
Output Filter Inductor (2A)
4.7uH 2A
4.7uH 3A
TDK
TDK
Wurth
VLC5045T-4R7M
744774047
1
1
TDK
Wurth
C1005X7R1C223K
885 012 205 033
CBST
Boost Capacitor
22nF 10V
Voltage Feedback Resistor
(optional)
RTOP
17.8K (Note 1)
10K (Note 1)
10K
1
1
1
1
Voltage Feedback Resistor
(optional)
RBOT
RPLP
PG Pin Pull-up Resistor (optional)
Catch Diode (optional, 1A)
30V 2A
SOD-123FL
On
Semiconductor
DCATCH
MBR230LSFT1G
40V 3A
SOD-123
NXP
Semiconductors
DCATCH
Catch Diode (optional, 2A)
PMEG4030ER,115
1
Note 1: The voltage divider resistor values are calculated for an output voltage of 2.5V. For !xed output versions, the FB pin is connected directly to VOUT
TS30041/42
Final Datasheet
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Rev 2.2
External Component Selection
The 1MHz internal switching frequency of the TS30041/42 facilitates low cost LC !lter combinations. Additionally, the !xed
output versions enable a minimum external component count to provide a complete regulation solution with only 4 external
components: an input bypass capacitor, an inductor, an output capacitor, and the bootstrap capacitor. The internal compensation
is optimized for a 44uF output capacitor and a 4.7uH inductor.
For best performance, a low ESR ceramic capacitor should be used for CBYPASS. If CBYPASS is not a low ESR ceramic capacitor, a
0.1uF ceramic capacitor should be added in parallel to CBYPASS.
The minimum allowable value for the output capacitor is 33uF. To keep the output ripple low, a low ESR (less than 35mOhm)
ceramic is recommended. Multiple capacitors can be paralleled to reduce the ESR.
The inductor range is 4.7uH +/-20%. For optimal over-current protection, the inductor should be able to handle up to the
regulator current limit without saturation. Otherwise, an inductor with a saturation current rating higher than the maximum IOUT
load requirement plus the inductor current ripple should be used.
For high current modes, the optional Schottky diode will improve the overall e"ciency and reduce the heat. It is up to the user to
determine the cost/bene!t of adding this additional component in the user’s application. The diode is typically not needed.
For the adjustable output version of the TS30041/42, the output voltage can be adjusted by sizing RTOP and RBOT feedback
resistors. The equation for the output voltage is
For the adjustable version, the ratio of VCC/Vout cannot exceed 16.
RPUP is only required when the Power Good signal (PG) is utilized.
Thermal Information
TS30041/42 is designed for a maximum operating junction temperature Tj of 125°C. The maximum output power is limited by
the power losses that can be dissipated over the thermal resistance given by the package and the PCB structures. The PCB must
provide heat sinking to keep the TS30041/42 cool. The exposed metal on the bottom of the QFN package must be soldered to a
ground plane. This ground should be tied to other copper layers below with thermal vias. Adding more copper to the top and the
bottom layers and tying this copper to the internal planes with vias can reduce thermal resistance further. For a hi-K JEDEC board
and 13.5 square inch of 1 oz Cu, the thermal resistance from junction to ambient can be reduced to θJA = 34.5°C/W. The power
dissipation of other power components (catch diode, inductor) cause additional copper heating and can further increase what the
TS30041/42 sees as ambient temperature.
TS30041/42
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Rev 2.2
Package Mechanical Drawings (all dimensions in mm)
TS30041/42
Final Datasheet
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Rev 2.2
Recommended PCB Land Pattern
TS30041/42
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Rev 2.2
Marking and Ordering Information
Tape & Reel (3300 parts/reel)
Tape & Reel (3300 parts/reel)
TS30041/42
Final Datasheet
17 of 18
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Rev 2.2
IMPORTANT NOTICE
Information relating to this product and the application or design described herein is believed to be reliable, however such information is provided as a
guide only and Semtech assumes no liability for any errors in this document, or for the application or design described herein. Semtech reserves the right
to make changes to the product or this document at any time without notice. Buyers should obtain the latest relevant information before placing orders
and should verify that such information is current and complete. Semtech warrants performance of its products to the speci!cations applicable at the time
of sale, and all sales are made in accordance with Semtech’s standard terms and conditions of sale.
SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS, OR IN NUCLEAR APPLICATIONS IN WHICH THE FAILURE COULD BE REASONABLY EXPECTED TO RESULT IN PERSONAL INJURY, LOSS OF LIFE
OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN
SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall
indemnify and hold Semtech and its o"cers, employees, subsidiaries, a"liates, and distributors harmless against all claims, costs damages and attorney
fees which could arise.
The Semtech name and logo are registered trademarks of the Semtech Corporation. All other trademarks and trade names mentioned may be marks and
names of Semtech or their respective companies. Semtech reserves the right to make changes to, or discontinue any products described in this document
without further notice. Semtech makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any
particular purpose. All rights reserved.
© Semtech 2016
Contact Information
Semtech Corporation
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111, Fax: (805) 498-3804
www.semtech.com
TS30041/42
Final Datasheet
July 27, 2016
18 of 18
Rev 2.2
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