TS51111 [SEMTECH]
High Efficiency Synchronous Rectifier and Charging IC for Wireless Power Applications;
| 型号： | TS51111 |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | High Efficiency Synchronous Rectifier and Charging IC for Wireless Power Applications 无线 |
| 文件： | 总22页 (文件大小：1093K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TS51111
High Efficiency Synchronous Rectifier and
Charging IC for Wireless Power Applications
TRIUNE PRODUCTS
Features
Description
The TS51111 is a fully-integrated synchronous rectifier for wireless
charging applications with additional integrated components to
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High efficiency synchronous rectification of AC input
Supports both Direct and Indirect Charging applications
Supports WPC Qi® compliant and non-compliant systems
Low Rds-on rectifier switches
High voltage input for higher power systems
Up to 20W+ Output
minimize system BOM.
The TS51111 includes a high efficiency synchronous rectifier to
convert the input AC power signal to a DC output level for battery
charging. The device supports both direct battery charging and
indirect power applications. Low Rds-on switches minimize power
dissipation. High voltage input capability allows for simple and
robust secondary side charger implementation. An integrated switch
provides the battery charging path and combined with the rectifier
provides back feed protection to the AC inputs. A precharge current
source is also included for low battery voltage precharge operation.
Communication capability is achieved using integrated high voltage
switches.
>98% efficiency at high currents
Integrated switches for load modulation
Integrated switch for battery disconnect
Integrated precharge current source
50mA output low Iq LDO
Analog mux for ADC sensing
Supply Under Voltage Lockout
Low external component count
Ultra-low standby quiescent current
Junction operating temperature -40C to 125C
The TS51111 includes several additional modules to allow simple
integration into wireless power systems. Integrated resistor dividers
with zero-current off-mode allow external ADC measurement of
PDC, PACKP, USB and thermistor voltages. High voltage switches are
included for communication modulation.
Applications
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Cell Phones and Smart Phones
Tablet Computers
eReaders
Power to an external controller is provided through an integrated
LDO. The ultra-low quiescent current regulator can supply high
output currents at low dropout with minimal current draw from the
battery.
Laptop Computers
Small Digital Cameras
Portable Video Recorders
Wireless charging for portable devices
Available in a 45 pin WCSP and 36 pin 6x6 QFN package.
TS51111
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Rev 2.2
Pinout (WCSP)
(Top View)
A4
A5
A1
A2
A3
MOD1
MOD2
SCL
AMUX
AGND
B4
B5
B1
B2
B3
SDA
VREF PACKN
USB EN_MOD
C4
C5
C1
C2
C3
VCORE
UART
TXD
PACKS
THERM
D4
D5
D1
D2
D3
RXD
PACKP
BST1
OVP
PACKP
E4
E5
E1
E2
E3
BST2
PDC
PDC
PDC
PDC
F4
F5
F1
F2
F3
VAC2
VAC2
VAC2
VAC1
VAC1
G4
G5
G1
G2
G3
PGND
VACDET PGND
PGND
PGND
H4
H5
H1
H2
H3
VAC2
VAC2
VAC2
VAC1
VAC1
I4
I5
I1
I2
I3
PDC
PDC
PDC
PDC
PDC
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Rev 2.2
Pin Description (WCSP)
Pin #
A1
Pin Name
SCL
Pin Function
I2C Clock
Description
I2C clock
A2
AMUX
AGND
MOD1
MOD2
SDA
Analog Sense
Analog Ground
MOD cap connection
MOD cap connection
I2C Data
Analog MUX output
A3
Quiet ground connection
Pulldown for capacitive modulation
Pulldown for capacitive modulation
I2C data
A4
A5
B1
B2
VREF
Vref Output
ADC reference output
B3
PACKN
USB
PACKN Sense
USB Supply
Battery negative terminal
USB supply and detection input
Enables modulation switches
LDO output
B4
B5
EN_MOD
VCORE
THERM
UART
TXD
Enable Modulation
VCORE LDO
C1
C2
Thermistor Drive
UART Bus
Thermistor drive
C3
UART bus
C4
UART TX
UART Tx
C5
PACKS
BST1
Output Current Sense
BST cap
Sense node for output current
Boost capacitor connection for HS FETs
Overvoltage pulldown clamp
UART Rx
D1
D2
OVP
OV Clamp
D3
RXD
UART RX
D4, D5
E1
PACKP
BST2
Battery Connection
BST cap
Battery positive terminal
Boost capacitor connection for HS FETs
Rectified input signal
E2-5
F1-F3
F4, F5
G1
PDC
Input power
Coil input
VAC2
AC power input from coil
AC power input from coil
Indicates incoming power to external micro
GND for synchronous rectifier and charging path
AC power input from coil
AC power input from coil
Filter capacitor connection for rectified voltage
VAC1
Coil input
VACDET
PGND
VAC2
VAC Detect
G2-5
H1-H3
H4, H5
I1-5
Power gnd
Coil input
VAC1
Coil input
PDC
Rectified voltage
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Rev 2.2
Pinout (QFN)
(Top View)
TS51111
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Rev 2.2
Pin Description (QFN)
Pin #
Pin Name
EN_MOD
TXD
Pin Function
Enable Modulation
UART TX
Description
Enables modulation switches
UART Tx
1
2
3
RXD
UART RX
UART Rx
4
PACKS
PACKP_K
PACKP
PDC
Output Current Sense
PACKP Kelvin
Battery Connection
Rectified voltage
Coil input
Sense node for output current
PACKP Kelvin
5
6
Battery positive terminal
Filter capacitor connection for rectified voltage
AC power input from coil
GND for synchronous rectifier and charging path
AC power input from coil
Indicates incoming power to external micro
Overvoltage pulldown clamp
Boost capacitor connection for HS FETs
Boost capacitor connection for HS FETs
LDO output
7, 13-14
8, 11-12
VAC1
9-10, 17-18
PGND
VAC2
Power gnd
15-16, 20
19
Coil input
VAC_DET
OVP
VAC Detect
21
OV Clamp
22
BST2
BST cap
23
BST1
BST cap
24
VCORE
THERM
SDA
VCORE LDO
25
Thermistor Drive
I2C Data
Thermistor drive
26
I2C data
27
SCL
I2C Clock
I2C clock
28
NC
No Connect
No Connect
29
VREF
Vref Output
ADC reference output
30
AMUX
UART
PACKN
AGND
MOD1
MOD2
USB
Analog Sense
UART Bus
Analog MUX output
31
UART bus
32
PACKN Sense
Analog Ground
MOD cap connection
MOD cap connection
USB Supply
Battery negative terminal
Quiet ground connection
Pulldown for capacitive modulation
Pulldown for capacitive modulation
USB supply and detection input
33
34
35
36
TS51111
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Rev 2.2
Functional Block Diagram
CIN
TS51111
OVP
Detect
EN_SW
VCORE
REG
BST1
CCORE
PreDrive
CB1
PACKP
VAC1
~
+
EN_PRE
COUT
MOD1
PACKPSNS
CS
Synchronous
Rectifier
CR
IOSENSE
A
A
PACKN
AGND
IBSENSE
MOD2
VCORE
A2D
PGND
~
-
EN_THERM
VAC2
Rs
CB2
VREF
THERM
BST2
UART
PreDrive
TxD
RxD
EN_MOD
PACKP_DIV
PDC_DIV
IBSENSE
IOSENSE
TEMP
PACK+
PACK-
SCL
Digital
Control
SDA
PACK-
VREF
VAC_DET
VREF
AMUX PACK-
CREF
Figure 1: TS51111 Block Diagram
TS51111
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Rev 2.2
Absolute Maximum Rating
Over operating free–air temperature range unless otherwise noted(1, 2, 3)
Parameter
Value
Unit
V
VAC1, VAC2, PDC, MOD1, MOD2, OVP
BST1, BST2
-0.3 to 22
-0.3 to (VAC + 5.5)
V
VCORE, TX, RX, UART, PACKP, SCL, SDA, VAC_DET, VREF,
AMUX, VCORE, USB
-0.3 to 5.5
V
Operating Junction Temperature Range, TJ
Storage Temperature Range, TSTG
-40 to 125
-65 to 150
2k
°C
°C
V
Electrostatic Discharge – Human Body Model
Electrostatic Discharge – Machine Model
+/-200
260
V
Lead Temperature (soldering, 10 seconds)
°C
Notes:
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating con-
ditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) ESD testing is performed according to the respective JESD22 JEDEC standard.
Recommended Operating Conditions
Symbol
Parameter
Min
Typ
Max
Unit
VACPP
FVAC
PACKP
LIN
Input Operating Voltage
Input Operating Frequency
20
210
5.5
V
kHz
V
100
2.5
Battery input when externally driven
Inductor (measured on charging mat)
Parallel resonant capacitor
14*
1.8*
183*
22
uH
nF
nF
nF
uF
uF
nF
uF
nF
nF
°C
CR
CS
Series resonant capacitor
CO
Modulation capacitors
COUT
CCORE
CB1, CB2
CIN
Output capacitor
0.8
8
1
LDO decoupling capacitor
10
Rectifier boost capacitors
200
10
1
220
20
240
Synchronous rectifier / PDC decoupling capacitor
Analog mux decoupling capacitor
VREF decoupling capacitor
CAMUX
CREF
TA
2
80
-40
-40
100
120
85
Operating Free Air Temperature
Operating Junction Temperature
TJ
125
°C
* Exact values of the resonant capacitors and inductor will depend on the specific system configuration.
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Rev 2.2
Thermal Characteristics
Symbol
Parameter
Value
Units
θ JA
36QFN Thermal Resistance Junction to Air (Note 1)
32
°C/W
Note 1: Assumes 3.917 x 3.917 in2 area of 1 oz copper, 4 layer PCB, 4 thermal vias under PAD, and 25°C ambient temperature.
Characteristics
Electrical Characteristics, TJ = -40C to 85C, PDC = PACKP = 4.2V (unless otherwise noted)
Symbol
IQ
Parameter
Condition
Min
Typ
Max
Unit
Current from PACKP, ILDO = 0, EN_
VREF = EN_SW = EN_PRE = 0
Current from PACKP, ILDO = 0, EN_
VREF = EN_SW = EN_PRE = 0
IQ,Standby,LPM
Quiescent Current in Low Power Mode
20
2
30
uA
uA
Quiescent Current in Disable (Direct
Charge, Low Power Mode disabled)
IQ,Disable
UVLO
VUVLO-PACK_P
HYSTUVLO-PACK_P
PACKP UVLO
PACKP Rising
2.1
V
PACKP UVLO Hysteresis
400
mV
PDC-PACKP Pass Device
TSW-ON
TSW-OFF
Delay from EN_SW to switch ON
200
us
ns
Delay from EN_SW to switch OFF
Precharge Current
100
INOM
Relative to set point
T = 25C; PDC = 3.5V; PACKP = 2.7V
IPRECHARGE
INOM -20%
INOM +20%
Precharge Current Temperature
Coefficient
TCPRECHARGE
25C to 85C
-0.3
3.2
%/C
A
ILIMIT
Current Limit
At 3.2 A setting
2.2
UART
TRX
Delay from UART to RX
Delay from TX to UART
UART threshold
0.7
0.6
0.8
0.8
10
us
us
V
TTX
VT,UART
VT,TX
TX threshold
V
Rdson,RX
RX Switch Resistance
Ω
SDA / SCl / EN_MOD Digital Inputs
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
RIN
VCORE = 1.5V
Voltage Rising
Voltage Falling
Voltage Rising
Voltage Falling
Voltage Rising
Voltage Falling
Voltage Rising
Voltage Falling
Resistance to GND
0.875
0.465
1.01
V
V
V
V
V
V
V
V
Ω
VCORE = 1.5V
VCORE = 1.8V
VCORE = 1.8V
VCORE = 2.5V
VCORE = 2.5V
VCORE = 3.3V
VCORE = 3.3V
Pin input impedance
0.525
1.25
0.665
1.47
0.825
1M
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Rev 2.2
Electrical Characteristics, TJ = -40C to 85C, PDC = PACKP = 4.2V (unless otherwise noted)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VAC Detect
Totem-pole configuration only.
100uA load.
VCORE-
100mV
VOH
Output high voltage
Output low voltage
Output leakage
V
mV
uA
Ω
Totem-pole or open-drain
configurations. 100uA load.
VOL
100
Output leakage in open-drain
off-state.
IOFF
0.1
Output resistance to GND in
open-drain on-state.
Rdson,VAC_DETECT
Switch Resistance
10
VREF
CVREF
VVREF
VREF decoupling capacitor
VREF voltage
80
100
2.0
120
nF
V
T = 0 to 85 C, IOUT 0mA to 2mA
T = 0 to 85 C, PDC_DIV_SEL = 0
T = 0 to 85 C, PDC_DIV_SEL = 1
T = 0 to 85 C
1.988
0.048
0.198
0.198
0.198
0.495
2.012
0.052
0.202
0.202
0.202
0.505
0.05
0.2
V/V
V/V
V/V
V/V
V/V
uA
RPDC-DIV
PDC_DIV ratio
RPACKP-DIV
RUSB-DIV
RTHERM-DIV
IQ,VREF
PACKP_DIV ratio
USB_DIV ratio
0.2
T = 0 to 85 C
0.2
THERM_DIV ratio
VREF quiescent current
T = 0 to 85 C
0.5
PACKP current if VREF enabled
300
Delay from EN_VREF to VREF
available
TEN-VREF
MOD
VREF enable time
3.2
us
EN_MOD to switches
ON delay
EN_MOD to switches
OFF delay
TMOD-ON
3
us
us
TMOD-OFF
0.7
Current from PACKP when MOD
switches closed. EN_MOD hi. EN_
VREF = EN_SE = EN_PRE = lo
IQ,MOD
MOD block quiescent current
MOD Switch Resistance
100
3
uA
Ω
Rdson,MOD
MOD1 to MOD2
Low Power LDO
VCORENOM
VDropout
VCORE voltage
Dropout voltage
PACKP = 4.2V
3.3
V
PACKP = 2.3V, IVCORE=1mA
PACKP=4.2V, VCORE = 0.9*VCORENOM
100
50
mV
mA
uF
Iout
Output current
10
1
CCORE
LDO Decoupling Capacitor
0.8
1.2
OVP
VOVP
OVP Threshold
21
2
V
Rdson,OVP
OVP Switch Resistance
Ω
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Rev 2.2
Electrical Characteristics, TJ = -40C to 85C, PDC = PACKP = 4.2V (unless otherwise noted)
Symbol
Temperature Sensing
TSHUTDOWN
Parameter
Condition
Min
Typ
Max
Unit
Over-temperature shutdown
threshold
Temperature rising
170
10
C
C
Over-temperature shutdown
hysteresis
THYST
VTSENSE
Temperature Sensor Voltage
Temperature Coefficient
25C
0.725
.75
2.4
0.775
V
TCVTSENSE
0C to 85C
mV/C
Current Sensing
PACKN - AGND 10mV to 20mV; Gain
setting = 20
IBSENSE GAIN
IOSENSE GAIN
IBSENSE VOFFSET
IOSENSE VOFFSET
Battery current sense amp gain
Output current sense amp gain
Battery current sense amp offset
Output current sense amp offset
19.6
19.6
-0.5
-0.5
20
20
0
20.4
20.4
0.5
V/V
V/V
mV
mV
PACKP - PACKS 10mV to 20mV
Gain setting = 20; PACKP = 5V
PACKN - AGND = 20mV; Gain setting
= 20; 25C
PACKP - PACKS = 20mV
Gain = 20; PACKP = 5V; 25C
0
0.5
VIB,MAX
VIO,MAX
Full range amp output
Full range amp output
750
750
mV
mV
VAC Detect
Totem-pole configuration only. 100uA
load.
VCORE-
100mV
VOH
Output high voltage
Output low voltage
Output leakage
V
mV
uA
Ω
Totem-pole or open-drain
configurations. 100uA load.
VOL
100
Output leakage in open-drain
off-state.
Output resistance to GND in
open-drain on-state.
IOFF
0.1
Rdson,VAC_DETECT
Switch Resistance
10
Functional Description
Synchronous Rectifier
The bridge rectifier in the TS51111 has a synchronous
controller which shunts the forward bias of the bridge diodes.
This allows the TS51111 to provide currents of up to 3.2A to be
efficiently transferred without significant power dissipation.
The primary side of the bridge can stand-off up to 20V. On the
secondary side, a capacitive load on the PDC pin can be used
to help attenuate the voltage signal observed on both sides
of the bridge rectifier. External boost capacitors CB1 and CB2
allow use of efficient high side nmos switches.
The bridge can be forced into asynchronous (no FET switching)
or half synchronous (LS FET only switching) operation at any
time using the CNFG register using the ASYNC or HSYNC bits
respectively. This can be used to improve efficiency at light
loads where the switching losses of the bridge would exceed
the conduction losses of the parasitic diodes.
Load Switch / Blocking FET
The integrated low impedance blocking switch provides a
direct charging path to the battery and disconnects the output
from the rectified signal until the system has been successfully
configured. Control of the switch is achieved through the I2C
interface. An integrated charge pump guarantees maximum
drive strength is available for the FET when operated as a
switch. When hard switched, gate drive is slewed slowly to
limit inrush current from the PDC cap to the battery.
The rectifier is disabled by default and will remain in an
asynchronous mode until incoming power is detected or
EN_SW or EN_PRE are asserted. In asynchronous mode, the
bridge FETs will not switch and voltage rectification will occur
through the parasitic diodes of the FETs. In this mode, current
draw in the IC is minimal.
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Functional Description (continued)
The load switch can be reconfigured to operate as a linear
regulator (see Charge Termination section below). When
enabled, the output will soft-start to limit inrush current.
In linear regulation mode, the PDC voltage must be
regulated close to the dropout voltage to limit power
dissipation in the IC.
Precharge
In low battery conditions, an integrated precharge current
source can be used to slowly charge the battery with a
controlled DC current source. The precharge current source is
controlled using the I2C interface. The precharge current has a
negative temperature coefficient to mitigate temperature rise
of the TS51111 during pre-charge. The level of the Precharge
current can be set according to the table below.
In linear regulation mode, a configurable, integrated current
limit circuit provides fault protection to the system. At the
maximum setting, current limit is disabled. If the output
current hits the current limit threshold, the device will
automatically limit the output current and set the FAULT
register ILIM bit. In this condition, the PDC voltage will
build up and must be managed through the system loop by
reducing the transmitted power. If the transmitted power
is not reduced, the TS51111 power dissipation will increase
and eventually force a thermal shutdown of the part. Current
limit in direct charge mode is not integrated but can be easily
implemented by monitoring device output current using the
integrated current sense amplifiers.
PRESET<2:0>
Precharge Current (mA)
000
001
010
011
100
101
110
111
30
40
50
60
70
80
90
100
Low Power Mode
The TS51111 supports a low-power mode when connected
directly to a battery. In this mode, the ultra-low quiescent
current LDO output is enabled to power an external
microcontroller and the power consumption of the rest of
the IC is minimized. In this mode, the TS51111 still supports
UART level translation to the microcontroller. The part will
automatically switch to normal operation when incoming
power is detected.
ILIMSET<3:0>
0000
Current Limit Typical (mA)
350
600
0001
0010
850
0011
1100
1350
1600
1850
2100
2350
2600
2850
3100
3350
3600
3850
Disable ILIM
0100
0101
0110
Current Sense Amps
0111
Two current sense amplifiers are included to allow for accurate
battery charge current and received current measurements.
The IBSENSE amplifier provides an output that is proportional
to the sense voltage on the PACKN pin when a sense resistor
is placed between PACKN and ground. The IOSENSE amplifier
will measure the differential voltage across the sense resistor
placed in series with the output current. This measurement
is an indicator of the power received by the TS51111. The
IOSENSE output is not valid when the device is in current limit.
The system should check the FAULT register periodically to
ensure the device is in a proper operating state without any
faults. Both amplifiers have a configurable gain set by the ISET
register. The gains are configurable from 10x to 80x.
1000
1001
1010
1011
1100
1101
1110
1111
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Rev 2.2
USB
VAC Detect
Functional Description (continued)
The TS51111 will automatically detect the presence of a
voltage applied to the USB pin. If the USBCTRL bit is set low
and a voltage is applied to the USB pin, the part will respond
by disabling all charging paths to the battery and switching
the LDO power input from the battery to the USB. If the
USBCTRL bit is set hi, the part will not automatically disable
charging or switch the LDO power input. The USBCTRL
bit is programmed in Non-Volatile Memory (NVM) during
manufacturing and is not user configurable. In either
condition, the USBDET bit in the FAULT register will be set.
When USB power is removed, the part will return to normal
operation.
The presence of incoming power on the coils will be indicated
by the TS51111 by asserting the VAC_DET output pin. The pin
will be de-asserted when incoming power is removed. The
VAC_DETECT output can be configured as open-drain with an
external resistor pull-up or as a totem pole with a VCORE high
level. This is set using the VAC_CNFG bit with hi for open-drain
and low for totem-pole.
UART
UART level translators are included to facilitate communication
between system components. The level shifters will translate
voltage levels from VCORE for the system microprocessor to
PACKP for a separate system.
LDO
VREF
The TS51111 LDO supports a variety of system configurations.
An on-chip ultra-low Iq LDO is provided for powering
external system components when a battery or USB supply is
available. The LDO is designed to operating with minimum
quiescent but can still deliver high output current at low
dropout voltage. Integrated current limit provides additional
protection.
An internal high-accuracy VREF circuit provides a precision
reference for external analog-to-digital converters. Integrated
voltage dividers provide sense voltages for external ADC
measurement. The VREF circuit is enabled using the EN_VREF
bit and will not draw any current when not active.
OVP
An on-board over-voltage sensor on the PDC signal is available
if additional external over-voltage protection is needed. In an
over-voltage condition, the OVP FET is active to provide a low
impedance path to ground on the OVP pin. In addition, the
OVP FET can be forced on using the register bit. This can be
used to provide an additional load on PDC if required. In an
OVP condition, the OVP bit of the FAULT register will be set hi.
If an external USB power supply is available, the LDO will draw
its input power from the USB pin instead of from the battery.
In the event that neither an external USB supply nor an
external battery is available, the LDO will automatically power-
up of the rectified voltage when incoming power is detected
and provide power to an external microcontroller.
To support multiple possible external microcontrollers, the
internal LDO has a configurable output voltage. The voltage
is set according to the following table. The LDOSET<1:0>
bits are programmed in Non-Volatile Memory (NVM) during
manufacturing and are not user configurable.
Temperature Sensing
The die temperature of the TS51111 is measured using an
onboard temperature sensor. The output of the temperature
sensor is available on the AMUX pin.
If the temperature of the TS51111 exceeds the TSD threshold,
all high current operations will be disabled until the die
temperature reaches a safe level. Temperature hysteresis
prevents rapid entering and exiting of the over-temperature
state. In thermal shutdown, the load switch, precharge
current, and synchronous rectifier are disabled. All other
functions including OVP and MOD will still be available. When
the TSD threshold is hit, the TSD bit in the FAULT register will
be set.
LDOSET<1:0>
VCORE (V)
00
01
10
11
1.5
1.8
2.5
3.3 (default)
TS51111
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Rev 2.2
Charge Termination
Thermistor Driver
Functional Description (continued)
To allow for accurate charge termination in a charging
application, the TS51111 load switch can be reconfigured
to operate as a voltage regulator. In this mode, the switch
source voltage will be regulated to the voltage set by the
VOUTSET<6:0> bits. The switch is put into this mode by
asserting the EN_TOP bit of the configuration register.
Available voltage settings and the corresponding codes are
shown. To support indirect charge applications, the EN_TOP
and IND_SET bits must both be set hi. The output voltage
will still be determined by the VOUTSET<6:0> bits. The
VOUT setpoints are 3.0V to 5.54V in 20mV steps. In addition,
VOUTSET<6:0>=0x64 will select a 5.0V setpoint.
An integrated thermistor driver allows system temperature
measurement. When enabled, the thermistor drive will drive
the VREF voltage onto the THERM pin. When disabled, the
THERM pin will be high impedance to allow external drive of
the same thermistor. In the automatic mode, the thermistor
driver is enabled whenever battery charging is enabled. This
is whenever EN_SW or EN_PRE are active. The voltage on the
THERM pin can be measured using the internal voltage divider
and will be visible on the AMUX pin.
TCTRL<1:0>
Thermistor Operation
00
01
10
11
Disable
Enable
Auto
AMUX
To reduce the number of connections required between the
microprocessor and the TS51111, all analog outputs from
the TS51111 are measured from the same analog pin and
selectable via the AMUX register. Signals on the AMUX pin
are buffered using an internal unity gain amplifier. When
unselected, the AMUX pin will be high impedance.
AMUX<2:0>
000
Analog Signal
----
001
PDC_DIV
IOSENSE
IBSENSE
TEMP
010
011
100
101
PACKP_DIV
USB_DIV
THERM_DIV
110
111
TS51111
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Rev 2.2
Control Registers
REG
R/W Description
LSON
R/W Forces on both LS FETs when hi. Allows normal synchronous rectifier operation when lo.
VAC_CONFIG
R/W Configures VAC_DET output pin behavior. Totem pole configuration when hi. Open-drain configuration
when lo.
HSYNC
ASYNC
R/W Forces half-synchronous rectifier operation (LS FET only switching) when lo. Allows synchronous rectifier
operation when hi. (ASYNC has priority when lo)
R/W Disables synchronous rectifier operation when lo. Allows synchronous rectifier operation when hi. (Has
priority over HSYNC when lo)
EN_VREF
R/W Enables VREF reference for external analog-to-digital converters when hi. Disables VREF reference when lo.
EN_TOP,
EN_SW
R/W EN_TOP = 0, EN_SW = 0
EN_TOP = 1, EN_SW = x
Load switch is disabled
Load switch is enabled as an LDO
Load switch is enabled as a switch
EN_TOP = 0, EN_SW = 1
EN_PRE
R/W Enables the precharge current source when hi. Current source is disabled when lo.
IND_SET
R/W Configures part for indirect charge operation when hi. Configures part for topoff or direct charge operation
when lo.
PACKP_LD_EN
OVP_ON
R/W Enables an internal 500 Ohm resistive load on PACKP when hi. Load is disconnected when lo.
R/W Forces the OVP FET to turn on as defined by the OVP_CS bit when hi. OVP is triggered only by high voltage
on PDC when lo.
EN_MOD
R/W Turns on the MOD FETs when hi. Turns off the MOD FETs when lo.
R/W Sets the level of the pre-charge current
PRESET <2:0>
AMUX <2:0>
PDC_DIV_SEL
ILIMSET <3:0>
TCTRL <1:0>
DIS_VREF
OVP_CS
R/W Configures measurement point for AMUX pin
R/W Changes the ratio of the PDC divider
R/W Configures the indirect charging internal current limit
R/W Configures the behavior of the Thermistor driver (THERM pin)
R/W Force the VREF output off
R/W Configures the OVP FET as 30mA current source (hi) or a switch (lo)
R/W Enable a 10K pull down load resistor on AMUX buffer
R/W Optimizes VCORE regulator for indirect charge mode.
R/W Increases the Ron for HS switches in the synchronous rectifier
R/W Configures the gain of the IBSENSE amplifier (000=10X, 001=20X,…111=80X)
R/W Configures the gain of the IOSENSE amplifier (000=10X, 001=20X,…111=80X)
R/W Configures the VOUT voltage setting for charge termination
AMUX_10K_PLDN
VCORE_indset
HI_R
IB <2:0>
IO <2:0>
VOUTSET <6:0>
PACKP_OVP
OVP
R
R
R
R
R
On-die over-voltage sensor status bit. Bit is hi during a PACKP over-voltage condition.
On-die over-voltage sensor status bit. Bit is hi during a PDC over-voltage condition.
On-die thermal sensor over-temperature status bit. Bit is hi during an over-temperature condition.
Status bit that indicates voltage applied to USB pin. Bit is hi when USB voltage is detected.
On-die current limit status bit. Bit is hi when current-limit is active.
TSD
USBDET
ILIM
TS51111
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Register Map
REG AD R/W
B7
B6
B5
B4
B3
B2
B1
B0
CNFG 0x0 R/W
0x00
0x00
0x00
0x00
0x00
0x00
VAC_CNFG
HSYNC
ASYNC
EN_VREF
EN_TOP
EN_PRE
EN_SW
PACKP_LD_
EN
CNFG2 0x1 R/W
PRESET 0x2 R/W
AMUX 0x3 R/W
0x4 R/W
IND_SET
OVP_ON
EN_MOD
PRESET<2> PRESET<1> PRESET<0>
PDC_DIV_
SEL
AMUX<2> AMUX<1> AMUX<0>
ILIMSET<3> ILIMSET<2> ILIMSET<1> ILIMSET<0>
VCORE_
indset
AMUX_10K_
PLDN
TCTRL 0x5 R/W
HI_R
EN_OVP_CS
IB<0>
DIS_VREF
IO<2>
TCTRL<1>
IO<1>
TCTRL<0>
IO<0>
ISET
0x6 R/W
0x7 R/W
0x00
0x00
--
IB<2>
IB<1>
FAULT 0x8
R
PACKP_OVP
OVP
TSD
USBDET
ILIM
Device address is 0x48
I2C Interface Timing Requirements
Standard Mode
Fast Mode(1)
Symbol
Parameter
Unit
Min
0
Max
Min
Max
fscl
tsch
tscl
I2C clock frequency
I2C clock high time
I2C clock low time
100
0
0.6
1.3
0
400
kHz
µs
µs
ns
ns
µs
ns
ns
ns
µs
µs
µs
µs
4
4.7
0
tsp(2)
tsds
tsdh
ticr(2)
ticf(2)
tocf(2)
tbuf
tsts
I2C tolerable spike time
I2C serial data setup time
I2C serial data hold time
50
50
250
0
250
0
I2C input rise time
I2C input fall time
1000
300
300
300
300
I2C output fall time; 10 pF to 400 pF bus
I2C bus free time between Stop and Start
I2C Start or repeated Start condition setup time
I2C Start or repeated Start condition hold time
I2C Stop condition setup time
300
4.7
4.7
4
1.3
0.6
0.6
0.6
tsth
tsps(2)
4
(1) The I²C interface will operate in either standard or fast mode.
(2) Parameters not tested in production.
TS51111
Final Datasheet
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Rev 2.2
Application Schematic
1
2
3
4
U1
23
36
USB
C1
BST1
USB
100nF
8
11
12
7
PDC
C2
50V
VAC1
VAC1
VAC1
PDC
PDC
PDC
VAC1
13
14
C3
C4
C5
C6
A
A
B
C
D
C7
22nF
50V
10uF
25V
10uF
25V
10uF
25V
10uF
25V
D1
NP
R4
100
47nF 50V
C10
C8
100pF
50V
C9
1.8nF
50V
34
35
MOD1
MOD2
21
4
OVP
C11
22nF
50V
68nF 50V
C12
15
16
20
VAC2
VAC2
VAC2
PACKS
VAC2
GND
J1
R1
5
6
PACKP
PACKS
1
2
C13
100nF
50V
PACKP_K
PACKP
+
-
Out
0.020
68nF 50V
22
C14
10uF
6.3V
C15
10uF
6.3V
BST2
D2
5.6V
1
2
AC
AC
COIL
31
2
3
UART
TXD
RXD
J2
GND
EN_MOD
VACDET
1
19
25
30
32
GND
GND
GND
GND
EN_MOD
VACDET
THERM
AMUX
PACKN
37
9
10
17
18
PAD
PGND
PGND
PGND
PGND
B
C
D
AMUX
VCORE
AGND
GND
GND AGND
24
29
28
VCORE
VCORE
VREF
NC
VREF
TP1
TP2
TP3
TP4
TP5
TP6
SCL
SDA
27
26
SCL
SDA
C16
10nF
10V
C17
1uF
6.3V
C18
100nF
RESET
DEBUG
SCL
33
10V
AGND
TS51111_QFN36
AGND
SDA
VCORE
U2
AGND
5
4
14 VACDET
17 EN_MOD
VDD
VACDET
EN_MOD
SCL
TP7
TP8
TP9
TP10
PDC
3
2
SCL
SDA
AMUX
USB
SDA
13 VREF
12
VSS
VREF
AMUX
AMUX
R2
10K
AGND
16
15
C19
2nF
10V
VAC1
GPIO4
GPIO5
LEDG
LEDR
18
19
7
9
10
11
LEDR
LEDG
GPIO1
GPIO2
GPIO3
GPIO6
GPIO7
GPIO8
AGND
D3
RESET
DEBUG
1
6
8
NRST
DEBUG
EN_LOAD
LED
20
TS81001-QFN
R3
150
GND
Title TS51111 EVM
WCSP package, no micro-vias
Size:
Letter
Date: 4/26/2013
Number:
Revision:
0.1
Time: 5:25:52 PM Sheet1 of
1
1
2
3
4
Figure 2: TS51111 Wireless Receiver Application
TS51111
Final Datasheet
April 17, 2015
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Rev 2.2
Package Drawing (WCSP)
Units
MILLIMETERS
Dimensions Limits
MIN
NOM
MAX
Number of Contacts
Contact Pitch
N
e
45
0.40 BSC
0.525
0.20
Overall Height
Standoff
A
0.445
0.12
-
0.625
0.30
A1
A2
E
Moldel Package Tickeness
Overall Width
-
0.325
2.200
2.195
-
Array Width
E1
D
1.60 BSC
-
Overall Length
Array Length
3.795
0.250
3.800
0.280
D1
b
3.20 BSC
0.265
Contact Diameter
TS51111
Final Datasheet
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Rev 2.2
Package Drawing (QFN)
Units
Dimensions Limits
MILLIMETERS
NOM
MIN
MAX
Number of Pins
Pitch
Overall Height
Standoff
Contact Thickness
Overall Length
Exposed Pad Width
Overall Width
N
e
A
A1
A3
D
E2
E
36
0.50 BSC
0.90
0.80
0.00
1.00
0.05
0.02
0.20 REF
6.00 BSC
4.45
4.30
4.55
6.00 BSC
4.45
0.25
0.55
-
Exposed Pad Length
Contact Width
Contact Length
Contact-to-Exposed Pad
D2
b
L
4.30
0.20
0.45
0.20
4.55
0.30
0.65
-
K
TS51111
Final Datasheet
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Rev 2.2
Package Drawing (QFN)
Units
MILLIMETERS
Dimensions Limits
MIN
NOM
MAX
Contact Pitch
E
0.50 BSC
Optional Center Pad Width
Optional tenter Pad Length
Contact Pad Spacing
Contact Pad Spacing
Contact Pad Width (X36)
Contact Pad Length (X36)
Distance Between Pads
Notes:
W2
T2
C1
C2
X1
Y1
G
-
-
-
-
-
-
-
-
4.45
4.45
-
6.00
6.00
-
-
-
-
0.35
0.65
-
0.15
Dimensions and tolerancing per ASME Y14.5M
BSC: Basic Dimension, Theorically exact value shown with tolerances.
REF: Reference Dimension, usually with tolerance, for information only.
TS51111
Final Datasheet
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Rev 2.2
Package Marking (WCSP)
Legend:
o
Pin 1 Identifier
Line 1 Marking:
Line 2 Marking:
Line 3 Marking:
TS51111
Device identification
Lot number (2 - 9 digits)
Y = last digit of year
XXXXXX
Y
M
M = month (1=Jan, 2=Feb, 3=Mar …
A=Oct, B=Nov, C=Dec)
Package Marking (QFN)
Legend:
T
S
1
Y
M
Line 1 Marking:
TS
Y
Triune Systems Logo
Y = last digit of year
M
M = month (1=Jan, 2=Feb, 3=Mar …
A=Oct, B=Nov, C=Dec)
Line 2 Marking:
Line 3 Marking:
51111
o
Device identification
Pin 1 Identifier
5
o
1
L
1
L
1
LL
S
LL = Last two whole (non-fractional)
digits of lot number
S
Assembly Site Identifier
TS51111
Final Datasheet
April 17, 2015
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Rev 2.2
Ordering Information
Part Number
Description
TS51111-M22WCSR
High Efficiency Wireless Power
Receiver, WCSP Package
TS51111-M22QFNR
High Efficiency Wireless Power
Receiver, QFN Package
RoHS and Reach Compliance
Triune Systems is fully committed to environmental quality.
All Triune Systems materials and suppliers are fully compliant
with RoHS (European Union Directive 2011/65/EU), REACH
SVHC Chemical Restrictions (EC 1907/2006), IPC-1752 Level
3 materials declarations, and their subsequent amendments.
Triune Systems maintains certified laboratory reports for
all product materials, from all suppliers, which show full
compliance to restrictions on the following:
•
•
•
•
•
•
•
•
•
•
•
•
Cadmium (Cd)
Chlorofluorocarbons (CFCs)
Chlorinate Hydrocarbons (CHCs)
Halons (Halogen free)
Hexavalent Chromium (CrVI)
Hydrobromofluorocarbons (HBFCs)
Hydrochlorofluorocarbons (HCFCs)
Lead (Pb)
Mercury (Hg)
Perfluorocarbons (PFCs)
Polybrominated biphenyls (PBB)
Polybrominated Diphenyl Ethers (PBDEs)
TS51111
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Rev 2.2
IMPORTANT NOTICE
Information relating to this product and the application or design described herein is believed to be reliable, however such information is provided as a
guide only and Semtech assumes no liability for any errors in this document, or for the application or design described herein. Semtech reserves the right
to make changes to the product or this document at any time without notice. Buyers should obtain the latest relevant information before placing orders
and should verify that such information is current and complete. Semtech warrants performance of its products to the specifications applicable at the time
of sale, and all sales are made in accordance with Semtech’s standard terms and conditions of sale.
SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS, OR IN NUCLEAR APPLICATIONS IN WHICH THE FAILURE COULD BE REASONABLY EXPECTED TO RESULT IN PERSONAL INJURY, LOSS OF LIFE
OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN
SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall
indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney
fees which could arise.
The Semtech name and logo are registered trademarks of the Semtech Corporation. Triune Systems, L.L.C. is now a wholly-owned subsidiary of Semtech
Corporation. The Triune Systems® name and logo, MPPT-lite™, and nanoSmart® are trademarks of Triune Systems, LLC. in the U.S.A. All other trademarks
and trade names mentioned may be marks and names of Semtech or their respective companies. Semtech reserves the right to make changes to, or
discontinue any products described in this document without further notice. Semtech makes no warranty, representation or guarantee, express or
implied, regarding the suitability of its products for any particular purpose. All rights reserved.
© Semtech 2015
Contact Information
Semtech Corporation
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111, Fax: (805) 498-3804
www.semtech.com
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相关型号：
TS51111-M22QFNR
High Efficiency Synchronous Rectifier and Charging IC for Wireless Power Applications
SEMTECH
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