XE3006_技术文档

XE3005/XE3006

VSSD VSSA VSSA VDD VREF

VREG11

VREG16

Power supply

management

Microphone

Bias

RESET

XE3006

VDDPA

AOUTP

PWM

DAC

Power

amplifier

AIN

Σ∆

modulator

Decimator

Amp.

AOUTN

VSSPA

Sandman

Functions

Serial Audio

Interface

Clock

mgt

SPI

MISO SS SCK MOSI SMAD SMDA BCLK SDI SDO FSYNC MCLK

XE3005 / XE3006

Low-Power Audio CODEC

GENERAL DESCRIPTION

FEATURES

•

Ultra low-power consumption, below 2 mW

Low-voltage operation down to 1.8 V

Sandman™ function to reduce system power

consumption (XE3006)

The XE3005 is an ultra low-power CODEC (Analog to

Digital and Digital to Analog Converter) for voice and

audio applications. It includes microphone supply,

preamplifier, 16-bit ADC, 16-bit DAC, serial audio

interface, power management and clock management

for the ADC and the DAC. The sampling frequency of

the ADC and of the DAC can be adjusted from 4 kHz to

48 kHz.

•

Single supply voltage

Adjustable sampling frequency: 4 – 48 kHz

Digital format: 16 bit 2s complement

Requires a minimum number of external

components

•

Easy interfacing to various DSPs

Direct connection to microphone and speaker

Various programming options

The XE3006 also includes the Sandman™ function,

which signals whether a relevant voice or audio signal is

present for the ADC or DAC.

QUICK REFERENCE DATA

• supply voltage

1.8 – 3.6 V

0.4 mA

4 – 48 kHz

78 dB

APPLICATIONS

• current (@20 kHz sampling)

• sampling frequency

•

Wireless Headsets

Bluetooth™ headset

Hands-free telephony

Digital hearing instruments

Consumer and multimedia applications

All battery-operated portable audio devices

• Typical dynamic range ADC

• Typical dynamic range DAC

78 dB

ORDERING INFORMATION

Part

Package

Ext. part no.

Temp. range

XE3005

TSSOP 20 pins

XE3005I033TRLF

-

20 to 70° C

Lead free

uCSP® 20 balls

TSSOP 24 pins

XE3005

XE3006

XE3005I064TRLF

XE3006I019

-20 to 70° C

Rev 1 August 2005

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1

XE3005/XE3006

Table of Contents

1

Device Description ...................................................................................................................................................3

1.1 Terminals Description XE3005/6................................................................................................................................4

Functional Description ............................................................................................................................................5

2

2.1 Device Functions........................................................................................................................................................5

2.2 Power-Down Functions ........................................................................................................................................... 12

3

Serial Communications......................................................................................................................................... 13

3.1 Serial Audio Interface .............................................................................................................................................. 13

3.2 Register Programming ............................................................................................................................................ 14

3.3 Serial Peripheral Interface - SPI.............................................................................................................................. 15

4

5

Sandman™ Function (XE3006) ............................................................................................................................ 17

Specifications ........................................................................................................................................................ 19

5.1 Absolute Maximum Ratings..................................................................................................................................... 19

5.2 Recommended Operating Conditions..................................................................................................................... 19

5.3 Electrical Characteristics......................................................................................................................................... 20

6

Application Information........................................................................................................................................ 27

6.1 Application Schematics – XE3006 .......................................................................................................................... 27

Register Description ............................................................................................................................................. 28

7

7.1 Register Functional Summary................................................................................................................................. 28

7.2 Register Definitions ................................................................................................................................................. 29

8

Mechanical Information ........................................................................................................................................ 33

8.1 XE3005 package size (TSSOP20).......................................................................................................................... 33

8.2 XE3005 package size (5x4 uCSP^®)........................................................................................................................ 34

8.3 XE3006 Package size (TSSOP24).......................................................................................................................... 35

9

XE3005 Land pattern recommendations (5x4 uCSP^®)....................................................................................... 36

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2

XE3005/XE3006

1

DEVICE DESCRIPTION

MOSI

SCK

1

2

20

MCLK

SS

MOSI

SS

1

2

MCLK

SMAD

SMDA

VDD

24

23

22

21

20

19

18

17

16

15

14

13

19

18

17

16

15

14

13

12

11

SDI

3

VDD

SCK

3

SDO

4

NRESET

VREG16

VREF

VSSA

VSSD

VREG11

AIN

MISO

SDI

4

BCLK

FSYNC

AOUTP

VDDPA

AOUTN

VSSPA

5

NRESET

VSSA

6

SDO

6

7

BCLK

FSYNC

AOUTP

VDDPA

AOUTN

VSSPA

VREG16

VREF

7

8

9

VSSA

9

10

VSSD

10

11

12

VREG11

AIN

Figure 1: Pin layout of the XE3006 and XE3005 in TSSOP

AOUTN

BCLK

FSYNC

VREG16

VREF

SCK

MOSI

MCLK

SDI

SDO

SS

AOUTP

VDDPA

VSSD

XEMICS

XE3005

VSSPA

VREG11

AIN

NRESET

VDD

VSSA

BOTTOM VIEW

TOP VIEW

Figure 2: Pin layout of the XE3005 in uCSP®

The XE3006 is available in a TSSOP24 package. The XE3005 is available in a TSSOP20 and uCSP® package. Detailed

information is found in chapter 8, Mechanical Information.

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XE3005/XE3006

1.1 TERMINALS DESCRIPTION XE3005/6

Terminals

Description

XE3006

XE3005

Name

Type ¹

uCSP

TSSOP24

TSSOP20

®

Master Clock. MCLK derives the internal clocks of ADC and

DAC

1

A2

MCLK

DI

2

3

4

N/A

3

N/A

A1

SMAD

SMDA

VDD

DO

AI

Sandman output ADC

Sandman output DAC

Digital power supply

Reset signal generated by the CODEC. If required, the reset

signal can be applied externally to initialize all the internal

CODEC registers

5

4

B1

NRESET

ZI/O

6

7

N/A

5

N/A

C2

VSSA

AI

Analog ground

Regulator voltage 1.6 V. Can be used to supply the

microphone

VREG16

AO

8

6

7

C1

D1

D2

E2

E1

E3

E4

D3

D4

C3

C4

B3

B4

N/A

A4

B2

A3

VREF

VSSA

VSSD

VREG11

AIN

AO

AI

Reference voltage

9

Analog ground

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

8

AI

Digital ground

9

AO

AI

ADC Regulated microphone output supply voltage 1.1 V

ADC Analog input signal

10

11

12

13

14

15

16

17

18

N/A

19

2

VSSPA

AOUTN

VDDPA

AOUTP

FSYNC

BCLK

SDO

AI

DAC Power Amplifier Ground

DAC Analog Output negative

DAC Power Amplifier Supply

DAC Analog Output positive

Serial audio interface Frame Synchronization

Serial audio interface Bit Clock

Serial audio interface Data Output

AO

AI

AO

DI/O

ZO

SDI

DI PD Serial audio interface Data Input

ZO SPI Master In Slave Out

MISO

SCK

DI PD SPI Serial Clock

SS

DI PU SPI Slave Select

DI PD SPI Master Out Slave In

20

MOSI

Note: (1)

AI = Analog Input

AO = Analog Output

DI = Digital Input

DO = Digital Output

DI/O = Digital In or Out

PU = internal Pull Up

ZO = Hi Impedance or Output

PD = internal Pull Down

ZI/O = Hi impedance In or Out

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XE3005/XE3006

2

FUNCTIONAL DESCRIPTION

A CODEC is typically used for voice and audio applications as an interface between a Digital Signal processor (DSP) or

microcontroller and the analogue interfaces like a microphone and loudspeaker.

DAC

ADC

MIC-Amplifier

CODEC

Power Amplifier

Serial Audio Interface

SPI

DSP / Microcontroller

Digital wireless transmission – Bluetooth™

Voice recognition / speech synthesis

Figure 3: Typical usage of CODEC

This chapter provides a brief description of the CODEC features relating to the CODEC configuration. The configuration

of the CODEC is defined by programming registers through a serial interface. A detailed description of the registers

defining details of the CODEC setup can be found in chapter 3 and 7. Digital voice and audio samples are passed

through the Serial Audio Interface.

2.1 DEVICE FUNCTIONS

2.1.1 ADC Signal Channel

The ADC channel is a chain of programmable amplifier, band-pass filter, sigma-delta modulator and a decimation filter.

The amplifier gain is programmable to 5x (default) and 20x. The band-pass filter has cut-off frequencies proportional to

the sampling rate. The sigma-delta modulator operates at a frequency of 64 times the sampling rate. The analog

modulator is followed by a digital decimation filter. The digital output data (16 bits, 2’s complement format) is made

available through the Serial Audio Interface. The format of the Serial Audio interface can be selected through register J.

With the default register settings the ADC can run at a sampling frequency up to 20 kHz. When used with a sampling

frequency higher than 20 kHz, then register C has to be changed.

The whole ADC chain can be powered-down through register I.

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XE3005/XE3006

2.1.2 MIC Input

The programmable pre-amplifier and the microphone bias sources VREG11 or VREG16 are optimized to operate with

electret microphones. VREG11 provides a 1.1 V reference voltage. The VREG11 can deliver up to 50 µA. VREG11 is

enabled through control register E. VREG16 is a regulated voltage of typically 1.6V and can deliver up to 1 mA.VREG16

is always enabled.

Vcc

4

5

VDD

0.1µF

NRESET

VSSA

6

7

VREG16

VREF

8

VSSA

9

VSSD

10

11

1kΩ

VREG11

AIN

12

50 pF (gain is 5)

200 pF (gain is 20)

390kΩ

1µF

GND

Figure 4: Typical microphone interface (1.1 V / 50 uA bias through VREG11)

Vcc

4

5

VDD

0.1µF

NRESET

VSSA

6

1kΩ^*

7

VREG16

VREF

8

9

VSSA

VSSD

10

11

12

VREG11

AIN

50 pF (gain is 5)

200 pF (gain is 20)

390kΩ

1µF

*

depends on microphone type

GND

Figure 5: Typical microphone interface (1.6 V / 1 mA bias through VREG16)

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XE3005/XE3006

2.1.3 DAC Signal Channel

The DAC is based on a multi bit sigma-delta modulator, which operates at a frequency of 8 times the sampling rate. The

outputs of the modulator are 2’s complement words of 6 bit. A pulse-width modulator (PWM) converts the 6 bit words into

2 single bit streams at 256 times the sampling frequency. Finally the 2 bit streams are supplied to the power amplifier.

The Power Amplifier is a Class D amplifier, which offers higher efficiency than the traditional Class AB topologies. It uses

a three-state unbalanced PWM. This means that both channels of the PA (AOUTP and AOUTN) will not switch at the

same time, therefore the outputs are not purely differential (see figure 5 and 6)

XE3005/6

VDDPA

P

s

N

AOUTP

AOUTN

P

From Serial Audio

Interface

Interpolator

&

Modulator

Pulse Width

Modulator

Power

Amplifier

N

dac_in(15:0)

@ Fsync

pwm_in(5:0)

@ 8xFsync

bit streams

@ 256xFsync

VSSPA

s = 0

s = 1

Figure 6: DAC block diagram

Figure 6 shows the relation of input and output samples of the PWM (The timing diagram is not to scale in the time-axis).

pwm_in(5:0) = 1

pwm_in(5:0) = -1

pwm_in(5:0) = 0

pwm_in(5:0) = 2

1

0

P

1

0

N

1/(256 x Fsync)

1/(8 x Fsync)

VDDPA

VSSPA

-VDDPA

OUTP-OUTN

1/(256 x Fsync)

2/(256 x Fsync)

Figure 7: Examples PWM in and out (not to scale)

The DAC receives 16-bit wide 2’s complement format through the Serial Audio Interface. The protocol can be selected

through register J. The complete DAC and PA amplifier chain can be powered-down through register I.

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XE3005/XE3006

2.1.4 Digital Loop Back

In digital loop back mode, the ADC output is routed directly to the DAC input. This allows in-circuit system level tests. The

digital loop back mode can be selected through register J.

2.1.5 Operating Frequency

A master clock (MCLK) has to be applied to the XE3005/3006. The clock frequency of the signal applied to the MCLK pin

may vary between 1.024 MHz minimum and 33.9 MHz maximum. The maximum internal clock signal frequency

(MCLK/div_factor) should not exceed 12.288 MHz.

The div_factor can be set by the user in register I to 1,2 or 4. The default value for div_factor is ‘1’.

2.1.6 Serial Audio Interface

The Serial Audio Interface is a 4-wire interface for bi-directional communication of audio data. It operates on the bit serial

clock BCLK and the frame synchronization signal FSYNC. The sampling frequency of the CODEC corresponds to the

rate at which the Audio Serial Interface will put out succeeding frames. One frame always corresponds to one sample.

One frame always contains 2 channels.

Synchronizing the Serial Audio Interface to the MCLK is recommended. FSYNC and MCLK must have a fixed ratio as

defined by the following relation:

FSYNC = Sampling frequency = frame rate = MCLK/(256 x div_factor).

The pin BCLK defines the time when the data must be presented to the serial audio interface and shifted into (pin SDI) or

out of (pin SDO) the CODEC. The number of BCLK periods in one FSYNC period is 32. The user can select to use the

first 16 clock cycles (channel 1) or the second 16 clock cycles (channel 2) of BLCK to shift in or out the data samples.

The table below shows some examples of the relationships between MCLK, BCLK and FSYNC

MCLK

2048 kHz

8192 kHz

5120 kHz

22579.2 kHz

Div_factor

BCLK

256 kHz

640 kHz

1411.2 kHz

FSYNC

8 kHz

1

4

1

2

8 kHz

20 kHz

44.1 kHz

The table below shows the possible functional configurations of the serial audio interface

CODEC

master

slave

supported protocol

LFS (Long Frame Sync)

LFS, LFS Optimization and SFS (Short Frame Sync)

By default the Serial Audio Interface operates in slave, SFS mode. In slave mode the user needs to generate the signals

BLCK, FSYNC and supply to the CODEC.

In master mode the CODEC generates the BLCK and FSYNC signals. In that case the BLCK operates at 32 times the

frequency of FSYNC. The CODEC master mode can be used with the LFS protocol only.

The register J is used for the different setups of the serial audio interface.

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XE3005/XE3006

2.1.7 Serial Peripheral Interface - SPI

The SPI interface is used to control register values. It is a serial communications interface that is independent of the rest

of the CODEC. It allows the device to communicate synchronously with a microprocessor or DSP. The CODEC interface

only implements a slave controller.

A detailed description can be found in chapter 3.3.

2.1.8

Sandman™ ADC Function

The Sandman™ function monitors the signals, which are processed in the ADC signal channel and the DAC signal

channel. The logic output signal SMAD indicates whether the ADC signal channel has processed an audio signal or only

noise, and for how long. The reference signal amplitude can be selected through register O, the time window parameters

are the off time and on time (registers L, M and N).

FSYNC

Serial Audio

BCLK

SDO

Interface

AIN

Σ∆

modulator

Decimator

Amp.

Sandman

Interface

SMAD

Figure 8: Implementation of the Sandman function for the ADC (SMAD)

The logic output SMAD can be used to power-down or reduce clock speed in other devices in the application, such as a

microcontroller, DSP or wireless link. Also, SMAD can be used as phone pick-up indicator. The Sandman™ function is

illustrated in Figure 9 and is valid for both SMAD (related to the ADC signal) and SMDA (related to the DAC signal).

Initially, SMAD is inactive (low), which means that “noise” is processed by the ADC, i.e. no audio signal amplitude above

the Reference. The Sandman™ Interface compares every output sample of the ADC signal channel to the Reference

value. If the signal is lower than the Reference value, SMAD remains inactive (low).

As soon as the signal passes the reference (time = 1), the on-time counter is started. (for the moment defined by time=’x’

see Figure 9). However, as the signal returns below the reference (time = 2) before the on-time counter has reached the

on time, the on-time counter is reset and the SMAD signal remains inactive (low).

The next time the signal gets higher than the Reference (time = 3), the on-time counter is started again and when it

reaches the on time, the SMAD signal becomes active (high), indicating that an audio signal is present (time = 4). As long

as the signal remains above the Reference, nothing happens and the SMAD signal remains active (high). When the

signal falls below the Reference (time = 5), the off-time counter is started, but as it does not reach the off time before the

signal passes again the Reference (time = 6), SMAD remains active (high). Also during the period from time = 7 to time =

8, the off time counter does not reach the off time.

When the signal falls below the Reference (time = 9) and remains below the Reference until the off-time counter has

reached the off-time, the SMAD signal is changed into the inactive (low) state (time = 10).

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XE3005/XE3006

2.1.9

Sandman™ DAC Function

The Sandman™ function monitors the signals, which are processed in the ADC signal, channel and the DAC signal

channel. The logic output signal SMDA indicates whether the DAC signal channel processes an audio signal or only

noise, and this for certain duration. The reference signal amplitude can be selected through register P, the time window

parameters are the off time and on time (registers L, M and N).

Reg I, bit 4

Sandman

SMDA

Interface

VDDPA

FSYNC

BCLK

SDI

AOUTP

Serial Audio

Interface

PWM

DAC

Power

amplifier

AOUTN

VSSPA

Figure 9: Implementation of the Sandman function for the DAC (SMDA)

The logic output SMDA can be employed to power-down other devices in the application, such as an external audio

power amplifier. By setting bit 4 in register I, the on-chip DAC signal channel can be powered-down through SMDA too.

The Sandman™ function is illustrated in Figure 9 and is valid for both SMAD (related to the ADC signal) and SMDA

(related to the DAC signal).

AIN/SDO

(AOUT/SDI)

+ reference

- reference

On-time counter

Time step = 1/fs = 1/FSYNC

Off-time counter

on-time

off-time

SMAD

(SMDA)

1

2

3

4

5

6

7

8

9

10 time

Figure 10: Illustration of the Sandman™ function.

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10

XE3005/XE3006

The above illustration is valid for either the SMAD output as a result of AIN/SDO or for the SMDA output as a

function of AOUT/SDI.

2.1.10 Start-up and Initialization

The CODEC generates its own power on reset signal after a power supply is connected to the VDD pin. The reset signal

is made available for the user at the pin NRESET. The rising edge of the NRESET indicates that the startup sequence of

the CODEC has finished. In most applications the NRESET pin can be left open.

The NRESET signal generated by the CODEC is used to initialize the various blocks in the device and guarantees a

correct start-up of the circuit. The start-up sequence that is automatically carried out upon power-up of the device is listed

below and illustrated in Figure 10.

1. NRESET is low (0V) when the device is not powered and remains low for a short time when VDD (upper curve in

Figure 10) is applied. The low state sustains while VDD, VREG16, VREF are stabilizing.

2. As soon as the MCLK signal is present, a counter is activated that counts 2²¹periods of the MCLK. After this

moment the NRESET is in the high state (VDD).

VDD = 1.8..3.3V

VREG16 = 1.6V

VREF = 1.2V

time

. . .

MCLK

977 ms (MCLK=2.048KHz)

NRESET

main reset

Figure 11: Startup sequence and NRESET signal after power-on.

The user can use the NRESET pin in 3 different ways and combinations:

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11

XE3005/XE3006

1. Leave the NRESET pin not connected. In this case the CODEC will startup as described in figure 10.

2. Use the NRESET pin as an output to indicate, to e.g. a microcontroller, that the CODEC finished its power up

sequence and that the CODEC is ready to operate.

3. Use the NRESET pin to force a re-initialization of the registers to their default values. In this case the user has to

force the NRESET to 0V for at least 32 periods of the MCLK. The circuit which forces the NRESET to 0V should

be able to sink at least 50 uA.

Figure 12 shows the block diagram of the CODEC reset.

reset to analog and

digital circuitry of codec

delay

counter

Power

On

Reset

NRESET

low drive

buffer

MCLK

XE3005/6

Figure 12: Codec reset circuitry

2.2 POWER-DOWN FUNCTIONS

2.2.1 Software Power-Down

Register I allows for the selective power down of the ADC signal channel or the DAC signal channel through SPI control.

The wake-up time, after powering down the device is typically 200µs. The maximum standby current is 96µA, depending

highly upon the Master clock (MCLK), see 5.3.5.2 Low Power Modes.

2.2.2 Hardware Power-Down

The device has no power-down pin. However, by holding down (0 V) the NRESET pin (resetting the device) as well as

the pins MCLK, BCLK and FSYNC, the power consumption will reach the standby current of typically 16µA. Use the

standard procedure for power up (see start-up and initialization procedure) after a hardware power down and apply your

registers setup procedure.

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XE3005/XE3006

3

SERIAL COMMUNICATIONS

3.1 SERIAL AUDIO INTERFACE

The Serial Audio Interface is a 4-wire interface for bi-directional communication of audio data. The 4 terminals are listed

below:

•

BCLK:

FSYNC:

Bit serial clock, one clock cycle corresponds to one data bit transmitted or received.

Frame Synchronization. This signal indicates the start of a data word. The frequency of the FSYNC

corresponds to the sample frequency of the CODEC.

•

SDI:

SDO:

Serial Data In, data received from external device and sent to DAC.

Serial Data Out, data received from ADC and sent to external device.

The same clock (BCLK) and synchronization (FSYNC) signals are used for both sending and receiving. The

synchronization signal FSYNC must have a fixed ratio with the master clock signal MCLK.

The Serial Audio Interface supports two formats that are commonly used for audio/voice CODECs and that are referred to

as SFS (Short Frame Synchronization) and LFS (Long Frame Synchronization). Data can be transmitted and received in

2 channels. Which channel is selected depends on the programmed values in the registers. The two interface protocols

are shown below.

channel 2, no data

channel 1, sample n+1

channel 1, sample n

FSYNC

BCLK

SDI

-

n+1₁₅

n₁₅n₁₄

n₀

n+1₁₅

n₁₅n₁₄

n₀

SDO

msb

lsb

Figure 13: Audio interface timing LFS mode, channel 1

channel 1, sample n+1

channel 1, sample n

channel 2, sample n

FSYNC

BCLK

SDI

-

n+1₁₅

n₁₅n₁₄

n₀

-

n+1₁₅

n₁₅n₁₄

n₀

SDO

msb

lsb

Figure 14: Audio interface timing in SFS mode, channel 1

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13

XE3005/XE3006

SDI Data should be changed on the rising edge of BCLK. The SDI data will be read by the CODEC on the falling edge of

BLCK. SDO data will change on the rising edge of the BCLK. The SDO data should be read on the falling edge of the

BLCK. Each rising edge of the FSYNC indicates the start of a new sample.

3.1.1 LFS Optimization

For transmitting and receiving, 32 clock cycles in one frame are always required (figure 12 and 13). This is even the case

when only 16 bits have to be sent or received. In most cases this can be handled easily with a DSP and microcontroller.

If the user wants to send a minimum of BLCK cycles, it is possible to shorten channel 1 (channel 2 can not be shortened).

In the LFS mode the possibility exists to shorten the number of BLCK cycles to 17 instead of 32. In this case the data is

transmitted and received in channel 2. Channel 1 is shortened to one BLCK cycle only.

Note! This optimization is possible in slave mode only.

The figure 15 shows this special LFS mode.

channel 1, no data

channel 2, sample n+1

channel 1, no data

channel 2, sample n

FSYNC

BCLK

SDI

n₁₅n₁₄

n₀

-

n₁₅n₁₄

-

n₁₅n₁₄

n₀

SDO

lsb

msb

Figure 15: Audio interface timing in LFS mode, 17 BLCK cycles, channel 2

3.2 REGISTER PROGRAMMING

The control registers define the configuration of the CODEC and define the various modes of operation. During power-up,

all registers will be configured with default values. The control register set consists of 16 registers. A detailed description

is provided chapter 7.

The control registers can be changed in the two following ways:

1. Logic values at SPI pins during power-up

There are 3 bits inside the registers which are configured depending on the logic values of the pins SS, SCK and MOSI

during the power up startup sequence as described in section 2.1.10

Value at power up

SS = 1

Influenced bits of registers

Register I(0)=0

Register I(0)=1

comments

MCLKDIV division by 1

MCLKDIV division by 2

SFS protocol

SS = 0

SCK = 0

Register J(0)=1

SCK = 1

Register J(0)=0

LFS protocol

MOSI = 0

MOSI = 1

Register E(2) = 0

Register E(2) = 1

preamplifier gain x5

preamplifier gain x20

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XE3005/XE3006

Using the SPI pins at startup the user is able to configure the CODEC in the corresponding setups without

reprogramming through the SPI interface and protocol. In best case the SPI interface can then be completely omitted and

the 3 SPI pins can be fixed to ‘0’ or ‘1’.

2. Programming through SPI interface after power-up

Once the device has been powered up, the configuration registers can be modified at all times (also when the device is

active) through the SPI interface.

The following section describes the SPI protocol which is required to change the control registers from their default

values.

3.3 SERIAL PERIPHERAL INTERFACE - SPI

The serial peripheral interface (SPI) allows the device to communicate synchronously with other devices such as a

microprocessor or a DSP. The CODEC interface only implements a slave controller. This section describes the

communication from master (e.g. DSP) to slave (CODEC pin MOSI) and from slave (CODEC pin MISO) to a master (e.g.

DSP).

Four lines are used to transmit data between the slave and master:

-

MOSI (Master Out, Slave In) data from master to slave, synchronous with the SPI clock (SCK).

MISO (Master In, Slave Out) data from slave to master, synchronous with the SPI clock (SCK).

SCK (Serial Clock) synchronizes the data bits of MOSI and MISO.

SS (Slave Select) Slave devices are selected by activating SS.

3.3.1 Protocol

During SPI communication, data is simultaneously transmitted and received.

t_recovery

1/F_sck

t_disable

SS

SCK

MOSI

MISO

14

…

15

1

0

Figure 16: SPI signal timing

The master puts data on the MOSI line on the falling edge of SCK; the slave reads the data on the rising edge of SCK.

The slave puts data on the MISO line on the falling edge of SCK; the master reads the data on the rising edge of SCK.

Transmission in either direction is by 2 bytes with MSB first.

The SS pin should be kept low during the whole transfer of data.

There are three timing constraints:

-

Recovery time (t _recovery) between the falling edge of SS and the falling edge of SCK.

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15

XE3005/XE3006

-

Disable time (t _disable) between the last rising edge of SCK and the rising edge of SS.

SCK frequency (F_SCK

)

Delay

t _recover

t _disable

F _SCK

Min

125

2 x T_master

Max

-

Unit

ns

Comments

T_master= clock period of the master clock MCLK

F_master= frequency of the master clock MCLK

0.5 x F_master

Hz

3.3.2 SPI Interface Modes

There are two SPI modes: read and write.

3.3.2.1 Read Mode

Read communication always takes place in pairs of bytes. A read request of 2 bytes is sent on the MOSI line. The

content of the addressed register, one byte, is dumped on the MISO line during the transmission of the second byte on

the MOSI. The formats of one byte are the following:

bit

mosi

7

1

6

1

5

0

4

msb

3

2

1

0

lsb

A (4:0)

bit

7

6

5

4

2

0

miso

msb

D(7:0)

lsb

ss

sck

mosi

miso

0

1

0

A4 A3 A2 A1 A0

1

request (read <address A(4:0)>)

msb

lsb

read data D(7:0) of address A(4:0)

Figure 17: SPI signal timing in read mode

3.3.2.2 Write Mode

Write communication always takes place in pairs of bytes. The format of the 2 bytes is:

Bit

mosi

7

1

6

0

5

0

4

msb

3

2

1

0

lsb

A(4:0)

Bit

7

6

5

4

2

0

mosi

msb

D(7:0)

lsb

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16

XE3005/XE3006

ss

sck

lsb

msb

mosi

A4

A3 A2

A0

1

0

A1

write data D(7:0) to address A(4:0)

request (write to address A(4:0))

Figure 18: SPI signal timing in write mode

4

SANDMAN™ FUNCTION (XE3006)

The Sandman™ function analyzes the audio signals in the ADC and DAC. Its output signals indicate whether an audio

signal is present in the ADC or DAC or if the processed signal is just noise. The threshold or reference value between

noise and audio signal as well as the minimum duration of an audio signal is user-programmable through the SPI

interface. If the XE3006 CODEC is used in a system that includes a microcontroller, a DSP or an RF link, the outputs of

the Sandman™ Interface can be used to bring these devices into standby or sleep mode whenever no audio signal is

being processed. In this way, the Sandman™ function contributes to significant additional power savings on the system

level outside the XE3006 chip.

The Sandman™ Interface consists of 2 digital outputs:

•

The SMAD detects whether the ADC processes an audio signal. The calculation is made with the digital data leaving

the ADC.

The SMDA detects whether an audio signal is processed by the DAC. The calculation is made with the digital data

entering through the Audio Interface.

The Sandman™ Interface is implemented for the ADC and for the DAC in an identical way. It works with a set of 4 user-

defined parameters: off time, on-time, ADC-reference and DAC-reference. The on time and the off time are the same for

ADC and DAC. However, the reference values for the ADC and the DAC are adjusted separately, as indicated in the

table below.

Input parameters

Off-time1(7:0)

Off-time2(15:8)

On-time(7:0)

ADC_reference(7:0)

DAC_reference(7:0)

Register

Sandman ADC

Sandman DAC

L

M

N

O

P

X

-

X

-

X

The Sandman™ Interface (for the ADC as well as for the DAC) is configured with three parameters:

• Reference (7:0): Absolute value under which the signal is considered noise and above which the signal is

considered to be an audio signal. The Sandman™ function is disabled (SMAD or SMDA at logic 1) if this parameter

is zero. The ADC and the DAC have separate Reference values.

• Off-time (15:0): Time until power down. The number of sequential samples that have to be lower than the

Reference for the power down signal to become active. The Sandman™ function is disabled (SMAD or SMDA at

logic 1) if this parameter is zero. The ADC and DAC have one common Off-time value.

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17

XE3005/XE3006

• On-time (7:0): Time until wakeup. The number of sequential samples that have to be higher than the Reference for

the power down signal to become inactive. The Sandman™ function is disabled (SMAD or SMDA at logic 1) if this

parameter is zero. The ADC and DAC have one common On-time value.

All these parameters are set in the registers L, M, N, O and P.

Reference(7:0)

0

On-time(7:0)

don’t care

0

don’t care

1.-.255

Off-time(15:0) Sandman (SMAD or SMDA) Comments

don’t care

0

logic 1 (disable function)

logic 1 (signal higher than ref)

Sandman disable

don’t care

1.-.255

1 - 65535

all registers ≠ zero

time for FSYNC =

20kHz

corresponds to

128.-.32640

corresponds to corresponds to logic 0 (signal lower than ref)

50 µs – 12 ms 50 µs - 3.2 sec

The reference (7:0) value is related to the absolute value of the 16 bits input signal. The following format is used for the

comparison:

• 16 bit inputs data (2’s-complement) : 0111’1111’1111’1111 = 0x7FFF

• 8 bit reference (unsigned) : 0111’1111’1000’0000 = 0xFF00/2

max positive value

reference max

So the reference is compared to the 8 most significant bits of the absolute value of the input signal:

reference(7:0)

Absolute reference

AIN (mV) if gain = 4

AIN (mV) if gain = 20

0

1

2

0

128

256

0.00

1.10

2.20

0.00

0.27

0.55

M

255

280

70

255 × 128 = 32640

The values in this table are amplitude values, RMS values can be derived by dividing the numbers by √2.

The working mechanism of the Sandman™ function is the following:

The incoming data is compared to the reference after each time step (1/FSYNC = 50µs if FSYNC = 20kHz).

• During the On-time phase

If the input data is higher than the reference, a counter will be incremented otherwise the counter is reset.

When the counter reaches the On-time value, then the SMAD or SMDA signal is activated (high level).

• During the Off-time phase

If the input data is lower than the reference, a counter will be incremented otherwise the counter is reset.

When the counter reaches the Off-time value, then the SMAD or SMDA signal is deactivated (low level).

In a first approximation, the following points are recommended:

• On-time at least 1ms. If the On-time is shorter than 1 ms, the Sandman™ function becomes sensitive to spikes in

the audio input signal AIN.

• Off-time at least 10ms, the Off-time should be longer than 1/f_min= 10ms, (code = 200). f_minis the minimum audio

frequency = 100Hz if FSYNC = 20kHz. The value of f_minscales proportionally with the sampling frequency FSYNC. A

high-pass filter in the ADC filters out signals below 100Hz.

• Reference should be adjusted just above the noise level.

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XE3005/XE3006

The CODEC bandwidth is around 100 Hz to 10 kHz at the nominal system frequency settings (MCLK = 5 MHz, CKDIV =

1, FSYNC = 20 kHz).

In digital loop back mode, the data entering into the Audio Interface is not transferred to the DAC. However, the

Sandman™ function (if activated) continues to output the SMDA signal based on the data entered into the Audio Interface

(input terminal SDI).

5

SPECIFICATIONS

5.1 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed in the following table may cause permanent failure. Exposure to absolute ratings for

extended periods may affect device reliability.

The values are in accordance with the Absolute Maximum Rating System (IEC 134).

All voltages are referenced to ground (VSSA and VSSD).

Analog and digital grounds are equal (VSSA = VSSD).

Symbol

VDD

Tstg

TA

Ves

Ilus

Parameter

Conditions

Min

-0.3

-65

-20

Max

3.65

150

70

500

98

Unit

V

°C

V

Supply voltage

Storage temperature

Operating free-air temperature, TA

Electrostatic discharge protection

Static latchup current

1)

2)

10

mA

V

Vlud

Dynamic latchup voltage

50

1) Tested according MIL883C Method 3015.6, class JEDEC 1B (Standardized Human Body Model: 100 pF, 1500 Ω, 3

pulses, protection related to substrate).

2) Static and dynamic latchup values are valid at 27 °C.

5.2 RECOMMENDED OPERATING CONDITIONS

All voltages referenced to ground (VSSA and VSSD).

Min

Typ

Max

Unit

Supply voltage, VDD

1.8

3.0

3.6

V

Analog signal peak input voltage, AIN (gain = 20x)

Analog signal peak input voltage, AIN (gain = 5x)

65

mV

270

Differential output load resistance

16

32

20

Ohm

Master clock frequency

1.024

33

48

70

MHz

kHz

°C

ADC or DAC conversion rate

Operating free-air temperature, TA

-20

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19

XE3005/XE3006

5.3 ELECTRICAL CHARACTERISTICS

The operating conditions in this section are: VDD = 3.0 V, T = 25°C.

5.3.1 Digital Inputs and Outputs, FSYNC = 20 kHz, output not loaded

Test

Parameter

Conditions

Min

Typ

Max

Unit

VOH High-level output voltage, DOUT

VOL Low-level output voltage, DOUT

IIH High-level input current, any digital input

IIL Low-level input current, any digital input

IO = -360uA

IO = 2mA

2.4

VDD+0.5

V

VSSD-0.5

0.4

10

V

VIH = 3.3 V

VIL = 0.6 V

uA

pF

Ci

Input capacitance

Co Output capacitance

5.3.2 ADC Dynamic Performance, FSYNC = 20 kHz

Parameter

Test Conditions

Pre-amp gain = 5x

Vin=250mV (full scale)

Min

Typ

Max

Unit

SNR Signal-to-noise ratio

72

78

0.5

70

10

dB

THD Total harmonic distortion

1 full scale

%

Hz

kHz

us

Flo Low cut-off frequency (-3 dB), See Note 1

Fhi High cut-off frequency (-3 dB), See Note 2

GD Group delay

FSYNC = 20 kHz

60

80

150

Note 1) Flo is proportional to FSYNC

Note 2) Fhi equals FSYNC/2

5.3.3 ADC Channel Characteristics, FSYNC = 20 kHz

Parameter

Test Conditions

Pre-amp gain = 5x

Min

Typ

Max

Unit

270

Vip Peak input voltage (single ended)

mV

Pre-amp gain = 20x

A-weighted, 100 Hz-10 kHz

pre-amp gain = 5x

A-weighted, 100 Hz-10 kHz

pre-amp gain = 20x

65

20

5

Vneq Equivalent input noise

µV rms

Pre-amp gain = 5x

Vin=250mV (full scale)

Dynamic range

72

1

78

dB

PSRR Power supply rejection ratio, input referred

Up to 1 kHz

Preamp-gain = 5x

Preamp gain = 20x

60

50

Cin Input capacitor

pF

200

Rin Input resistance VIN – VSSA

Eg gain error

MOhm

[%]

VDD 1.8-3.3V

+/- 0.1

-60

offset error

LSB

input noise

6.7

INL Integral non linearity

+/- 5

DNL Differential non linearity

VDD 1.8-3.3V

+/- 0.1

LSB

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XE3005/XE3006

5.3.4 DAC Dynamic Performance, load is an LC filter at 10 kHz

FSYNC = 20 kHz, MCLK = 5 MHz, for info on the LC filter see chapter 6, Application Information.

Parameter

Test Conditions

Min

Typ

Max

Unit

SNR Signal-to-noise ratio

Bandwidth 10 kHz

72

78

dB

THD Total harmonic distortion

Dynamic range

1 full scale

0.5

78

%

dB

µs

Bandwidth 10 kHz

FSYNC = 20 kHz

72

GD Group delay

150

5.3.5 Power Supply

5.3.5.1 Regulated supply characteristics @ T = 25°C

Test

Parameter

Min

Typ

Max

Unit

Conditions

1µF capacitor

390 kΩ resistor

VREF

reference Voltage

1.2

V

VREG11

I_vreg11

R_vreg11

VREG16

I_vreg16

regulated Voltage 1.1V

available current

1.1

35

1

V

µA

50

output impedance

1.5

kOhm

V

regulated Voltage 1.6V

available output current

1µF capacitor

1.5

1.6

1

mA

dB

VREF PSRR power supply rejection ratio, input referred

VREG11 PSRR power supply rejection ratio, input referred

VREG16 PSRR power supply rejection ratio, input referred

up to 1 kHz

60

40

dB

5.3.5.2 Low power mode

Stand-by mode @ VDD = 3.0V, T = 25°C

Parameter

Test Conditions

Min

Typ

Max

Unit

ADC off, DAC off

MCLK = 5 MHz,

Istb1

Istb2

Istb3

Supply current in standby mode

28

48

20

56

96

40

µA

ADC off, DAC off

MCLK = 12.2880 MHz

Supply current in standby mode

µA

NRESET mode

MCLK = 0

Stand-by mode @ VDD = 1.8V, T = 25°C

Parameter

Test Conditions

ADC off, DAC off

MCLK = 5 MHz,

ADC off, DAC off

MCLK = 12.2880 MHz

Min

Typ

25

Max

50

Unit

µA

Istb1

Istb2

Istb3

Supply current in standby mode

31

62

µA

NRESET mode

MCLK = 0

16

32

µA

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XE3005/XE3006

5.3.5.3 Normal operation, output load consumption is not included.

Normal operations @ VDD = 3.0V, FSYNC = 20 kHz, T = 25°C, Register C(7:0) = 0xF0

Parameter

Test Conditions

Min

Typ

350

240

120

Max

700

480

240

Unit

µA

ADC on, DAC on

FSYNC = 20 kHz, no load

IDD

Supply current CODEC

ADC on, DAC off

FSYNC = 20 kHz, no load

IADC Supply current ADC

IDAC Supply current DAC

µA

ADC off, DAC on

FSYNC = 20 kHz, no load

µA

Normal operations @ VDD = 3.0V, FSYNC = 48 kHz, T = 25°C, Register C(7:0) = 0xC4

Parameter

Test Conditions

Min

Typ

860

600

280

Max

1720

1200

560

Unit

µA

ADC on, DAC on

FSYNC = 48 kHz, no load

IDD

Supply current CODEC

ADC on, DAC off

FSYNC = 48 kHz, no load

IADC Supply current ADC

IDAC Supply current DAC

µA

ADC off, DAC on

FSYNC = 48 kHz, no load

µA

Normal operations @ VDD = 1.8V, FSYNC = 20 kHz, T = 25°C, Register C(7:0) = 0xF0

Parameter

Test Conditions

Min

Typ

250

200

65

Max

500

400

130

Unit

µA

ADC on, DAC on

FSYNC = 20 kHz, no load

IDD

Supply current CODEC

ADC on, DAC off

FSYNC = 20 kHz, no load

IADC Supply current ADC

IDAC Supply current DAC

µA

ADC off, DAC on

FSYNC = 20 kHz, no load

µA

Normal operations @ VDD = 1.8V, FSYNC = 48 kHz, T = 25°C, Register C(7:0) = 0xC4

Parameter

Test Conditions

Min

Typ

625

505

140

Max

1250

1010

280

Unit

µA

ADC on, DAC on

FSYNC = 48 kHz, no load

IDD

Supply current CODEC

ADC on, DAC off

FSYNC = 48 kHz, no load

IADC Supply current ADC

IDAC Supply current DAC

µA

ADC off, DAC on

FSYNC = 48 kHz, no load

µA

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XE3005/XE3006

5.3.6 Timing Requirements of serial audio interface

Ref.

Test

Conditions

Characteristics

No. *

Min

Typ

Max

Unit

1

Master Clock Frequency for MCLK = 1/ T

MCLK Duty Cycle

1024

45

5.12

33

55

10

MHz

%

Rise Time for All Digital Signals

2

ns

Fall Time for All Digital Signals

3

ns

Hold time BCLK or FSYNC high after MCLK low

Setup time BCLK or FSYNC high to MCLK low

Hold time BCLK or FSYNC low after MCLK low

Setup time BCLK or FSYNC low to MCLK low

Bit Clock Frequency for BCLK = 1 / TBCLK

Setup time data input SDI to BCLK low

Hold time data input SDI after BCLK low

Delay time SDO valid after BCLK high

Setup time data input FSYNC to BCLK low

Hold time data input FSYNC after BCLK low

4

T/4

ns

5

ns

C_Load= 10pF

6

ns

7

ns

MCLK/2

8

32xFSYNC

MHz

ns

9

T^BCLK/4

10

11

12

13

ns

T^BCLK/4

ns

T^BCLK/4

ns

*see figure 18,19 for LFS and 20, 21 for SFS

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XE3005/XE3006

5.3.6.1 Timing diagram of the serial audio interface – LFS mode

1

2

3

MCLK

5

7

BCLK

6

4

FSYNC

SDI

Figure 18: LFS, timing diagram

MCLK

8

BCLK

FSYNC

SDI

11

9

10

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SDO

D8

D7

D6

D5

D4

D3

D2

D1

D0

Figure 19: LFS, zoom timing diagram

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XE3005/XE3006

5.3.6.2 Timing diagram of the serial audio interface – SFS mode

1

2

3

MCLK

6

5

4

7

BCLK

FSYNC

SDI

Figure 20: SFS, timing diagram

MCLK

8

BCLK

FSYNC

SDI

12

9

13

11

10

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SDO

D8

D7

D6

D5

D4

D3

D2

D1

D0

Figure 21: SFS zoom timing diagram

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XE3005/XE3006

5.3.7 Timing Requirements of the Serial Peripheral Interface

Test Conditions

Ref. No.*

Characteristics

Serial Clock Frequency for SCK = 1 / TSCK

MCLK Duty Cycle

Min

Typ

Max

MCLK/2 MHz

Unit

1

2

3

4

5

6

45

125

2T

TSCK/4

55

%

ns

Recovery Time

Disable Time

C_Load= 10pF

Setup time MISO valid to SCK high

Hold time MISO valid after SCK high

Delay time MOSI valid after SCK low

* see figure 22

SS

2

3

1

4

SCK

5

6

M2

M1 M0

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

MISO

MOSI

D7

D6

D5

D4

D2

D1

D0

Figure 22: Serial Peripheral Interface timing

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XE3005/XE3006

6

APPLICATION INFORMATION

6.1 APPLICATION SCHEMATICS – XE3006

6.1.1 Typical Application schematic

Sandman output

Master Clock

MOSI

SS

1

MCLK

SMAD

SMDA

VDD

24

23

22

21

20

19

18

17

16

15

14

13

2

Vcc

SPI

SCK

3

4

MISO

SDI

0.1µF

5

NRESET

VSSA

SDO

6

Serial Audio Interface

BCLK

FSYNC

AOUTP

VDDPA

AOUTN

VSSPA

VREG16

VREF

7

8

R

L

VSSA

9

Vcc

VSSD

10

11

12

2µ2F

4µ7F

VREG11

AIN

L

R

L=680µH

R=56Ω

390kΩ

1µF

lowpass filter,

1µF

Bluetooth™ voice application

MCLK = 2.048 MHz,

div_factor =1

GND

Figure 23: Typical Application with 3^rdorder LC output Filter

6.1.2 External components required for optimal performances

The following minimum set-up of external components is required:

•

Capacitor for Vref: 1 µF

Resistor for Vref: 390 kΩ

Capacitor for VREG16: 1 µF

The low pass filter between the DAC output and the speaker depends on the CODEC settings and the speaker type.

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XE3005/XE3006

7

REGISTER DESCRIPTION

7.1 REGISTER FUNCTIONAL SUMMARY

The following registers can be programmed by the SPI to configure the operation modes. See also section 3.2 Register

Programming.

Name

Description

Register C

ADC current setting. The data in this register has the following

functions:

•

Adjust the ADC current for FSYNC > 20kHz

0xF0 for FSYNC<= 20 kHz, 0xC4 for FSYNC > 20 kHz.

Register E

Register I

Analog Input. The data in this register has the following functions:

•

Enable/disable microphone bias source of 1.1 V

Gain setting of pre-amplifier.

Function enable and clock division. The data in this register has the

following functions:

•

Enable/disable Sandman function of DAC

Enable/disable DAC channel (DAC, power amplifier)

Enable/disable ADC channel (pre-amplifier, ADC, decimation

filter)

•

Division of master clock

Register J

Audio Interface Configuration. The data in this register has the

following functions:

•

Enable/disable digital loopback

Channel select receive

Select master / slave mode

Output impedance

Channel select transmit

Select short / long frame sync

Register L

Register M

Register N

Register O

Register P

Sandman™ function, Off-time, low byte. The data in this register has

the following function:

•

Define Off-time (low byte) of the Sandman™ function

Sandman™ function, Off-time, high byte. The data in this register has

the following function:

•

Define Off-time (high byte) of the Sandman™ function

Sandman™ function, On-time. The data in this register has the

following function:

•

Define On-time of the Sandman™ function

Sandman™ function, reference for ADC. The data in this register has

the following function:

•

Define reference amplitude for ADC for Sandman™ function

Sandman™ function, reference for DAC. The data in this register has

the following function:

•

Define reference amplitude for DAC for Sandman™ function

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XE3005/XE3006

7.2 REGISTER DEFINITIONS

The complete register setup consists of 24 registers of 8 bits each, as shown in the table below. All registers are

preconfigured with the default values and do not have to be programmed by the user if no changes in the setup are

required.

The registers C, E, I and J can be used to configure the XE3005 and XE3006 differently than the default setup.

The registers L, M, N, O and P are related to the Sandman™ function available in the XE3006.

Register

Address (hex)

0x00

Name

Default value (hex)

0x48

A

B

C

D

E

F

G

H

I

Reserved

ADC current

Reserved

Analog input

Reserved

0x01

0x8F

0x02

0xF0

0x03

0x00

0x04

0x08/0x0C

0x82

0x05

0x06

0x00

0x07

0x00

0x08

Block on/off and clock division

Audio interface configuration

Reserved

0x00/0x01

0x25/0x24

0x00

J

0x09

K

L

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

Sandman™ function, off-time byte 1

Sandman™ function, off-time byte 2

Sandman™ function, on-time

Sandman™ function, reference for ADC

Sandman™ function, reference for DAC

0x00

M

N

O

P

0x00

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29

XE3005/XE3006

Register C (7:0)

address 0x02

7:0

ADC

current

ADC

Default value: Description

0xF0

0xF0 for FSYNC<= 20 kHz,

0xC4 for FSYNC > 20 kHz.

current

Register E (7:0)

address 0x04

7

ADC input

Default value

0x08/0x0C

0

Description

VMIC_EN

Generation of the microphone supply at pin VREG11:

1: enables VREG11

0: disables VREG11

6:3

2

reserved

PREAMP_

GAIN

0001

0 or 1

reserved

Gain of preamplifier:

0: 5x (270 mV peak)

1: 20x (65 mV peak)

The default is depending on the logic value of the pin MOSI during

startup (see section 3.2)

MOSI=0, default will be set to 0

MOSI=1, default will be set to 1

1:0

reserved

00

reserved

Register I (7:0)

address 0x08

block on/off and

clock division

Default value

0x00/0x01

Description

7:4

3

0000

0

reserved

0: enable

1: disable DA converter (DAC + PA)

EN_DAC

EN_ADC

2

0

0: enable

1: disable AD converter (Preamp + ADC +

decimator)

1:0

MCLKDIV

00 or 01

Division factor of the master clock:

00: 1

01: 2

10: reserved

11: 4

The default is depending on the logic value of the pin SS

during startup (see Section 3.2)

SS=0, default will be set to 1

SS=1, default will be set to 0

www.semtech.com

30

XE3005/XE3006

Register J (7:0)

address 0x09

Audio

interface

configuration

Default Description

value

0x25/

0x24

7

6

LOOPBACK

0

0: disable loopback, normal mode

1: enable loopback => The CODEC connects internally the

ADC output to DAC input

0: Receive audio data in the first 16-bit channel after the

frame synchronization.

RX_FIRST_

SECOND

0

1: Receive audio data in the second 16-bit channel after the

frame synchronization.

5

4

reserved

MASTER

1

0

reserved

1: enable audio interface in master mode (only for LFS)

0: enable audio interface in slave mode (LFS, LFS

Optimization or SFS)

3

SDO_HI_EN

0

0: SDO is continuously in output mode for both data

channels.

1: SDO is in output mode when transmitting a channel with

data (J(2) or J(1)=1).

It is switched automatically into high-impedance state

when a channel with no data is transmitted (J(2) or

J(1)=0).

2

1

0

TX_FIRST

TX_SECOND

PROTOCOL

1

0

1: transmit the audio data in the first 16-bit channel after the

frame synchronization.

0: do no transmit data in the first channel.

1: transmit the audio data in the second 16-bit channel after

the frame synchronization.

0: do no transmit data in the second channel.

1: Short Frame Synchronization mode (slave mode).

0: Long Frame Synchronization mode (master or slave

mode).

0 or 1

The default is depending on the logic value of the pin SCK during startup

(see Section 3.2)

SCK=0, default will be set to 1

SCK=1, default will be set to 0

Register L (7:0)

address 0x0B

Sandman™ function,

off-time,

Default

value 0x00

Description

least significant byte

7:0

SM_OFF_LSB

00000000 Least significant byte of the off-time of

the Sandman™ function

Register M (7:0)

address 0x0C

Sandman™ function,

off-time,

Default

value 0x00

Description

most significant byte

7:0

SM_OFF_MSB

00000000 Most significant byte of the off-time of

the Sandman™ function

Register N (7:0)

address 0x0D

7:0

Sandman™ function,

on-time

Default

value 0x00

Description

SM_ON

00000000 On-time of the Sandman™ function

www.semtech.com

31

XE3005/XE3006

Register O (7:0)

address 0x0E

7:0

Sandman™ function,

reference for ADC

SMAD_REF

Default

value 0x00

Description

00000000 Reference amplitude for ADC for

Sandman™ function

Register P (7:0)

address 0x0F

7:0

Sandman™ function,

reference for DAC

SMDA _REF

Default

value 0x00

Description

00000000 Reference amplitude for DAC for

Sandman™ function

www.semtech.com

32

XE3005/XE3006

8

MECHANICAL INFORMATION

8.1 XE3005 PACKAGE SIZE (TSSOP20)

D

E

A

X

c

H

v

M

A

y

E

Z

11

20

Q

A

2

(A )

3

A

1

pin 1 index

L

p

L

1

0

detail X

w

M

b

p

e

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

b

c

D

E

e

H

L

v

w

y

Q

1

2

3

p

E

p

Z

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

6.6

6.4

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.5

0.2

mm

1.10

0.65

0.25

1.0

0.2

0.13

0.1

Figure 24: TSSOP20

Plastic Thin Shrink Small Outline Package, 20 leads, body width: 4.4 mm

www.semtech.com

33

XE3005/XE3006

8.2 XE3005 PACKAGE SIZE (5X4 UCSP^®)

PACKAGE OUTLINE of the XE3005 uCSP^®

SIDE VIEW

XEMICS

XE3005

TOP VIEW

BOTTOM VIEW

Nominal dimensions in mm

b

D

D1

E

E1

e1

SD

SE

A

A1

A2

e2

0.325

± 0.075 ± 0.125

0

2.745

± 0.075

3.225

± 0.125

2.40

0.37

1.95

0.65

< 0.8

0.31

0.60

0.46 ^max

Figure 25: 5x4 uCSP^®

Ultra Chip Scale Package, 5 x 4 balls array.

www.semtech.com

34

XE3005/XE3006

8.3 XE3006 PACKAGE SIZE (TSSOP24)

D

E

A

X

c

H

v

M

A

y

E

Z

13

24

Q

A

2

(A )

3

A

1

pin 1 index

L

p

L

1

2

detail X

w

M

b

p

e

DIMENSIONS (mm are the originladimensions)

A

Q

y

UNIT

A

b

c

D

E

e

H

L

v

w

1

2

3

p

E

p

Z

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

7.9

7.7

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.5

0.2

mm

1.10

0.65

0.25

1.0

0.2

0.13

0.1

Figure 26: TSSOP24

Plastic Thin Shrink Small Outline Package with 24 leads and a body width of 4.4 mm.

www.semtech.com

35

XE3005/XE3006

9

XE3005 LAND PATTERN RECOMMENDATIONS (5X4 UCSP^®)

PAD

PASTE_MASK

Ø 0.25

SOLDER_MASK Ø 0.35

LAND PATTERN RECOMMENDATION

for the XE3005 uCSP^®

PLACEMENT OUTLINE

Nominal dimensions in mm

D

E

e1

SD

SE

e2

3.35

0.65

0.325

0

0.60

2.82

Figure 27: Land pattern recommendations (5x4 uCSP®)

www.semtech.com

36

XE3005/XE3006

information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and

may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof

does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech. assumes no

responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation,

repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the

specified maximum ratings or operation outside the specified range.

SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN

LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH

PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK.

Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and

hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and

attorney fees which could arise.

Contact Information

Semtech Corporation

Wireless and Sensing Products Division

200 Flynn Road, Camarillo, CA 93012

Phone (805) 498-2111 Fax : (805) 498-3804

www.semtech.com

37


型号：	XE3006
厂家：	SEMTECH CORPORATION
描述：	Low-Power Audio CODEC 低功耗音频编解码器解码器编解码器
文件：	总37页 (文件大小：374K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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