SGM41516/D_技术文档

SGM41516/SGM41516D

High Input Voltage,

3.78A Single-Cell Battery Charger

with NVDC Power Path Management

● Flexible Autonomous and I²C Operation Modes for

Optimal System Performance

FEATURES

● High Efficiency, 1.5MHz, Synchronous Buck Charger

● Fully Integrated Switches, Current Sense and

Compensation



95.5% Charge Efficiency at 1A from 5V Input

92.5% Charge Efficiency at 2A from 9V Input

Optimized for 9V/12V Input

● External Direct Charging Path Enable Output

● 9μA Ship Mode Low Battery Leakage Current

● High Accuracy

Selectable PFM Mode for Light Load Efficiency

● USB On-The-Go (OTG) Support (Boost Mode)



±0.5% Charge Voltage Regulation (8mV/Step)

±5% Charge Current Regulation at 1.5A

±10% Input Current Regulation at 0.9A



Boost Converter with up to 1.2A Output

Boost Efficiency of 93.5% at 0.5A and 92.2% at 1A

Accurate Hiccup Mode Over-Current Protection

Soft-Start Capable with up to 500μF Capacitive Load

Output Short Circuit Protection

● Safety



Battery Temperature Sensing (Charge/Boost Modes)

Thermal Regulation and Thermal Shutdown

Input Under-Voltage Lockout (UVLO)

Input Over-Voltage (ACOV) Protection

Selectable PFM Mode for Light Load Operations

● Single Input for USB or High Voltage Adaptors



3.9V to 13.5V Operating Input Voltage Range

22V Absolute Maximum Input Voltage Rating

Programmable Input Current Limit and Dynamic

Power Management (IINDPM, 100mA to 3.1A with

100mA Resolution & 3.8A) to Support USB 2.0 and

USB 3.0 Standards and High Voltage Adaptors

Maximum Power Tracking by Programmable Input

Voltage Limit (VINDPM) with Selectable Offset

VINDPM Tracking of Battery Voltage

APPLICATIONS

Smart Phones, EPOS

Portable Internet Devices and Accessory



SIMPLIFIED SCHEMATIC



Input

PMID

LS/SC

3.9V to 13.5V

USB

VBUS

DCEN

Auto Detect USB BC1.2, SDP, CDP, DCP and

Non-Standard Adaptors

OTG

5V at 1.2A

VSYS

SW

● High Battery Discharge Efficiency with 11mΩ Switch

● Narrow Voltage DC (NVDC) Power Path Management

I²C Bus

BTST

SYS

BAT

Host

I_CHG

Host Control

REGN



Instant-On with No or Highly Depleted Battery

nQON

Ideal Diode Operation in Battery Supplement Mode

TS

● Ship Mode, Wake-Up and Full System Reset Capability

SGM41516

SGM41516D

Optional

by Battery FET Control

SG Micro Corp

DECEMBER 2022 – REV. A

www.sg-micro.com

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

GENERAL DESCRIPTION

The SGM41516/SGM41516D are battery chargers and

system power path management devices with integrated

converter and power switches for using with single-cell Li-Ion

or Li-polymer batteries. This highly integrated 3.78A device is

capable of fast charging and supports a wide input voltage

range suitable for smart phones, tablets and portable systems.

I²C programming makes it a very flexible powering and

charger design solution.

power path management provides the deficit from battery by

discharging battery to the system until the system power

demand is fulfilled. This is called supplement mode, which

prevents the input source from overloading.

Starting and termination of a charging cycle can be

accomplished without software control. The sensed battery

voltage is used to decide for starting phase of charging in one

of the three phases of charging cycle: pre-conditioning,

constant current or constant voltage. When the charge

current falls below a preset limit and the battery voltage is

above recharge threshold, the charger function will

automatically terminate and end the charging cycle. If the

voltage of a charged battery falls below the recharge

threshold, the charger begins another charging cycle.

The devices include four main power switches: input reverse

blocking FET (RBFET, Q1), high-side switching FET for Buck

or Boost mode (HSFET, Q2), low-side switching FET for Buck

or Boost mode switching (LSFET, Q3) and battery FET that

controls the interconnection of the system and battery

(BATFET, Q4). The bootstrap diode for the high-side gate

driving is also integrated. The internal power path has a very

low impedance that reduces the charging time and maximizes

the battery discharge efficiency. Moreover, the input voltage

and current regulations provide maximum charging power

delivery to the battery with various types of input sources.

Several safety features are provided in the SGM41516/

SGM41516D such as over-voltage and over-current

protections, battery temperature monitoring, charging safety

timing, thermal shutdown and input UVLO. TS pin is

connected to an NTC thermistor for battery temperature

monitoring and protection in both charge and Boost modes

according to JEITA profile. This device also features thermal

regulation in which the charge current is reduced, if the

junction temperature exceeds 80℃ or 120℃ (selectable).

A wide range of input sources are supported, including

standard USB hosts, charging ports and USB compliant high

voltage adaptors. The default input current limit is

automatically selected based on the built-in USB interface.

This limit is determined by the detection circuit in the system

(e.g. USB PHY). SGM41516 is USB 2.0 and USB 3.0 power

specifications compliant with input current and voltage

regulation. It also meets USB On-The-Go (OTG) power rating

specification and is capable to boost the battery voltage to

supply 5.15V on VBUS with 1.2A (or 0.5A) current limit.

Charging status is reported by the STAT output and

fault/status bits. A negative pulse is sent to the nINT output

pin as soon as a fault occurs to notify the host. BATFET reset

control is provided by nQON pin to exit ship mode or for a full

system reset.

The devices supply a DCEN signal to control an external

P-MOSFET or load switch as a direct charging path for low

voltage PMID, or to control a 2:1 switching capacitor divider

for high voltage PMID.

The system voltage is regulated slightly above the battery

voltage by the power path management circuit and is kept

above the programmable minimum system voltage (3.5V by

default). Therefore, system power is maintained even if the

battery is completely depleted or removed. Dynamic power

management (DPM) feature is also included that

automatically reduces the charge current if the input current

or voltage limit is reached. If the system load continues to

increase after reduction of charge current down to zero, the

The SGM41516/SGM41516D are available in a Green

WLCSP-2.0×2.4-30B package.

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

2

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

PACKAGE/ORDERING INFORMATION

SPECIFIED

TEMPERATURE

PACKAGE

DESCRIPTION

ORDERING

NUMBER

PACKAGE

MARKING

PACKING

OPTION

MODEL

RANGE

SGM

41516

XXXXX

XX#XX

SGM41516 WLCSP-2.0×2.4-30B

-40℃ to +85℃

SGM41516YG/TR

Tape and Reel, 3000

SGM

41516D

XXXXX

XX#XX

SGM41516D WLCSP-2.0×2.4-30B

SGM41516DYG/TR

MARKING INFORMATION

NOTE: XXXXX = Date Code, Trace Code and Vendor Code.

Date Code - Year

Trace Code

Vendor Code

X X X X X

XX＃XX

Coordinate Information

Wafer ID Number ("A" = 01, "B" = 02, …"Y" = 25)

Coordinate Information

Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If

you have additional comments or questions, please contact your SGMICRO representative directly.

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

3

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

ABSOLUTE MAXIMUM RATINGS

Voltage Range (with Respect to GND)

RECOMMENDED OPERATING CONDITIONS

Input Voltage Range, V_VBUS..............................3.9V to 13.5V

Input Current (VBUS), I_IN..................................... 3.8A (MAX)

Output DC Current (SW), I_SWOP.............................. 5A (MAX)

Battery Voltage, V_BATOP................................... 4.624V (MAX)

Fast Charging Current, I_CHGOP........................... 3.78A (MAX)

Discharging Current (Continuous), I_BATOP............... 6A (MAX)

Ambient Temperature Range......................... -40℃ to +85℃

Junction Temperature Range....................... -40℃ to +125℃

VAC, VBUS (Converter Not Switching)............-2V to 22V ⁽¹⁾

BTST, PMID (Converter Not Switching)........... -0.3V to 22V

SW ...................................................................... -2V to 16V

SW (Peak for 10ns Duration).............................. -3V to 16V

BTST to SW....................................................... -0.3V to 6V

D+, D- ................................................................ -0.3V to 6V

REGN, TS, nCE, BAT, BATSNS, SYS (Converter Not

Switching) .......................................................... -0.3V to 6V

SDA, SCL, nINT, nQON, STAT, DCEN ............. -0.3V to 6V

Output Sink Current

OVERSTRESS CAUTION

Stresses beyond those listed in Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to

absolute maximum rating conditions for extended periods

may affect reliability. Functional operation of the device at any

conditions beyond those indicated in the Recommended

Operating Conditions section is not implied.

STAT.............................................................................6mA

nINT..............................................................................6mA

Package Thermal Resistance

WLCSP-2.0×2.4-30B, θ_JA......................................... 63℃/W

Junction Temperature.................................................+150℃

Storage Temperature Range........................-65℃ to +150℃

Lead Temperature (Soldering, 10s)............................+260℃

ESD Susceptibility

ESD SENSITIVITY CAUTION

This integrated circuit can be damaged if ESD protections are

not considered carefully. SGMICRO recommends that all

integrated circuits be handled with appropriate precautions.

Failureto observe proper handlingand installation procedures

can cause damage. ESD damage can range from subtle

performance degradation tocomplete device failure. Precision

integrated circuits may be more susceptible to damage

because even small parametric changes could cause the

device not to meet the published specifications.

HBM.............................................................................2000V

CDM ............................................................................1000V

NOTE: 1. Maximum 28V for 10 seconds.

DISCLAIMER

SG Micro Corp reserves the right to make any change in

circuit design, or specifications without prior notice.

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

4

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

PIN CONFIGURATIONS

SGM41516 (TOP VIEW)

SGM41516D (TOP VIEW)

1

2

3

4

5

1

2

3

4

5

GND

SW

PMID

VBUS

VAC

GND

SW

PMID

VBUS

VAC

A

B

C

D

E

F

A

B

C

D

E

F

GND

BAT

SW

SYS

PMID

BTST

TS

VBUS

REGN

nQON

SDA

DCEN

PSEL

nPG

GND

BAT

SW

SYS

PMID

BTST

TS

VBUS

REGN

nQON

SDA

DCEN

D+

D-

nCE

STAT

SCL

nCE

STAT

SCL

BAT

SNS

BAT

SNS

nINT

WLCSP-2.0×2.4-30B

PIN DESCRIPTION

NAME

TYPE ⁽¹⁾

FUNCTION

SGM

41516

41516D

A1, B1

GND

BAT

—

P

Ground Pin of the Device.

Battery Positive Terminal Pin. Use a 10µF capacitor between BAT and GND pins close to

the device. SYS and BAT pins are internally connected by BATFET with current sensing

capability.

C1, D1

E1, F1

C1, D1

E1, F1

Switching Node Output. Connect SW pin to the output inductor. Connect a 47nF bootstrap

capacitor from SW pin to BTST pin.

A2, B2

SW

P

Connection Point to Converter Output. SYS is connected to the converter LC filter output

that powers the system. BAT to SYS internal current (power from battery to system) is

sensed. Connect a 20μF capacitor between SYS pin and GND close to the device (in

addition to C_OUT).

C2, D2

E2, F2

C2, D2

E2, F2

SYS

PMID Pin. PMID is the actual higher voltage port of converter (Buck or Boost) and is

connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET.

Connect a 22μF ceramic capacitor from PMID pin to GND. It is the proper point for

decoupling of high frequency switching currents.

A3, B3

C3

A3, B3

C3

PMID

BTST

DO

P

High-side Driver Positive Supply. It is internally connected to the bootstrap diode cathode.

Use a 47nF ceramic capacitor from SW pin to BTST pin.

Temperature Sense Input Pin. Connect to the battery NTC thermistor that is grounded on

the other side. To program operating temperature window, it can be biased by a resistor

divider between REGN and GND. Charge suspends if TS voltage goes out of the

programmed range. It is recommended to use a 103AT-2 type thermistor.

D3

TS

AI

If NTC or TS pin function is not needed, use a 10kΩ/10kΩ pair for the resistor divider.

Charge Enable Input Pin (Active Low). Battery charging is enabled when CHG_CONFIG bit

is 1 and nCE pin is pulled low.

E3

F3

E3

F3

nCE

DIO

AIO

Battery Voltage Sensing Pin for Charge Current Regulation. BATSNS pin is connected to

the actual battery pack as close as possible to reduce the parasitic trace resistance during

charging.

BATSNS

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

5

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

PIN DESCRIPTION (continued)

NAME

VBUS

REGN

TYPE ⁽¹⁾

FUNCTION

SGM

41516D

41516

Charger Input (V_IN). The internal N-channel reverse blocking MOSFET (RBFET) is

connected between VBUS and PMID pins. Place a 1μF ceramic capacitor from VBUS pin

to GND close to the device.

A4, B4

C4

A4, B4

C4

P

LDO Output that Powers LSFET Driver and Internal Circuits. Internally, the REGN pin is

connected to the anode of the bootstrap diode. Place a 4.7μF (10V rating) ceramic

capacitor between REGN pin and GND. It is recommended to place the capacitor close to

the REGN pin.

BATFET On/Off Control Pin. Use an internal pull-up to a small voltage for maintaining the

default high logic (whenever a source or battery is available). In the ship mode, the

BATFET is off. To exit ship mode and turn BATFET on, a logic low pulse with a duration of

t_SHIPMODE(1s TYP) can be applied to nQON. When VBUS source is not connected, a logic

low pulse with a duration of t_{QON_RST}(10s TYP) resets the system power (SYS) by turning

BATFET off for t_{BATFET_RST}(320ms TYP) and then backs on to provide a full power reset for

system.

D4

nQON

DI

E4

F4

E4

F4

SDA

nINT

DIO

DO

I²C Data Signal. Use a 10kΩ pull-up to the logic high rail.

Open-Drain Interrupt Output Pin. Use a 10kΩ pull-up to the logic high rail. The nINT pin is

active low and sends a negative 256µs pulse to inform host about a new charger status

update or a fault.

Sense Input for DC Input Voltage (Typically from an AC/DC Adaptor). Must be connected

to VBUS pin.

A5

B5

A5

B5

VAC

AI

—

External Direct Charge Enable Pin. This pin can be set high by DCEN to enable an external

direct charging device.

DCEN

Power Source Selection Input. If PSEL is pulled high, the input current limit is set to 500mA

(USB 2.0) and if it is pulled low, the limit is set to 2.4A (adaptor). When the I²C link to the

host is established, the host can program a different input current limit value by writing to

the IINDPM[4:0] register. (SGM41516 only)

C5

—

PSEL

DI

Positive USB Data Line. D+/D- based USB device protocol detection and voltage of this pin

can be set by DP_VSET[1:0]. (SGM41516D only)

—

D5

—

C5

—

D+

nPG

D-

AIO

DO

Open-Drain Active Low Input Power Good Indicator. Use a 10kΩ pull-up to the logic high

rail. A low state indicates a good input (UVLO < VVBUS < ACOV, and above sleep mode

threshold, ILIM > 30mA). (SGM41516 only)

Negative USB Data Line. D+/D- based USB device protocol detection and voltage of this

pin can be set by DM_VSET[1:0]. (SGM41516D only)

D5

AIO

Open-Drain Charge Status Output. Use a 10kΩ pull-up to the logic high rail (or an LED + a

resistor). The STAT pin acts as follows:

During charge: low (LED ON).

E5

F5

E5

F5

STAT

SCL

DO

DI

Charge completed or charger in sleep mode: high (LED OFF).

Charge suspended (in response to a fault): 1Hz, 50% duty cycle pulses (LED BLINKS).

The function can be disabled via EN_ICHG_MON[1:0] register.

I²C Clock Signal. Use a 10kΩ pull-up to the logic high rail.

NOTE:

1. AI = Analog Input, AO = Analog Output, AIO = Analog Input and Output, DI = Digital Input, DO = Digital Output, DIO = Digital

Input and Output, P = Power.

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

6

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

ELECTRICAL CHARACTERISTICS

(V_{VAC_UVLOZ}< V_VAC< V_{VAC_OV}and V_VAC> V_BAT+ V_SLEEP, T_J= -40℃ to +85℃, typical values are at T_J= +25℃, unless otherwise

noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

Quiescent Currents

Battery Discharge Current

(BAT, SW, SYS) in Buck Mode

V_BAT= 4.5V, V_VBUS< V_{VAC_UVLOZ}

leakage between BAT and VBUS, BATFET off

,

I_{BQ_VBUS}

I_{BQ_HIZ_BOFF}

I_{BQ_HIZ_BON}

0.1

9

1

µA

Battery Discharge Current

(BAT) in Buck Mode

V_BAT= 4.5V, HIZ mode and BATFET_DIS = 1

or no VBUS, I²C disabled, BATFET disabled

20

30

40

Battery Discharge Current

(BAT, SW, SYS)

V_BAT= 4.5V, HIZ mode and BATFET_DIS = 0

or no VBUS, I²C disabled, BATFET enabled

15

25

V

_VBUS= 5V, HIZ mode and BATFET_DIS = 1,

no battery

I_{VBUS_HIZ}

µA

V_VBUS= 12V, HIZ mode and BATFET_DIS = 1,

no battery

55

2.5

4

80

Input Supply Current

(VBUS) in Buck Mode

V

_VBUS= 12V, V_VBUS> V_BAT, converter not switching

3.5

I_VBUS

mA

V_BAT= 3.8V, I_SYS= 0A, V_VBUS> V_BAT, V_VBUS> V_{VAC_UVLOZ}

converter switching, BATFET off

,

Battery Discharge Current

in Boost Mode

I_BOOST

V_BAT= 4.2V, I_VBUS= 0A, converter switching

3

BAT Pin, VAC Pin and VBUS Pin Power-Up

VBUS Operating Range

V_{VBUS_OP}

V_VBUSrising

3.9

13.5

3.4

V

VBUS UVLO to Have Active I²C

(with No Battery) Seen by Sense

VAC Pin

V_{VAC_UVLOZ}

3.2

V_VACrising, T_J= +25℃

I²C Active Hysteresis

V_{VAC_UVLOZ_HYS}V_VACfalling from above V_{VAC_UVLOZ}

V_{VAC_PRESENT}

400

3.4

mV

V

V_VACMinimum (as One of the

Conditions) to Turn on REGN

V_VACHysteresis (as One of the

Conditions) to Turn on REGN

3.7

V_VACrising, T_J= +25℃

V_{VAC_PRESENT_HYS}V_VACfalling from above V_{VAC_PRESENT}

400

50

mV

Sleep Mode Falling Threshold

Sleep Mode Rising Threshold

V_SLEEP

20

80

V_VAC- V_BAT, V_{VBUSMIN_FALL}≤ V_BAT≤ V_REG, V_VACfalling

V_SLEEPZ

150

190

230

mV

V

V_VAC- V_BAT, V_{VBUSMIN_FALL}≤ V_BAT≤ V_REG, V_VACrising

6.5V Setting

VAC

OVP[1:0] = 01

6.3

6.5

10.5

14

6.7

Over-Voltage

Rising Threshold

10.5V Setting

14V Setting

6.5V Setting

10.5V Setting

14V Setting

V_{VAC_OV_RISE}

V_VACrising

OVP[1:0] = 10

OVP[1:0] = 11

OVP[1:0] = 01

OVP[1:0] = 10

OVP[1:0] = 11

10.2

13.7

10.8

14.3

110

260

300

VAC

Over-Voltage

Hysteresis

V_{VAC_OV_HYS}

mV

BAT Voltage to Have Active I²C

(No Source on VBUS)

V_{BAT_UVLOZ}

V_BATrising

2.65

V

V_{BAT_DPL_FALL}

V_{BAT_DPL_RISE}

V_{BAT_DPL_HYS}

V_BATfalling

V_BATrising

2

2.25

2.5

BAT Depletion Threshold

2.25

2.75

BAT Depletion Rising Hysteresis

250

mV

mA

Bad Adaptor Detection Current

(Internal Current Sink)

Bad Adaptor Detection (VBUS

Voltage Drop) Falling Threshold

Bad Adaptor Detection (VBUS

Voltage Drop) Hysteresis

I_{BAD_SRC}

Sink current from VBUS to GND

V_VBUSfalling

30

3.8

230

V_{VBUSMIN_FALL}

V_{VBUSMIN_HYS}

3.7

3.9

V

mV

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

7

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

ELECTRICAL CHARACTERISTICS (continued)

(V_{VAC_UVLOZ}< V_VAC< V_{VAC_OV}and V_VAC> V_BAT+ V_SLEEP, T_J= -40℃ to +85℃, typical values are at T_J= +25℃, unless otherwise

noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Power Path Management

I_SYS= 0A, V_BAT= 4.4V, V_BAT> V_{SYS_MIN}

BATFET_DIS = 1

,

V_BAT+

50mV

System Regulation Voltage

V_SYS

V

I_SYS= 0A, V_BAT< SYS_MIN[2:0] = 101 (3.5V),

BATFET_DIS = 1

Minimum DC System Voltage Output

Maximum DC System Voltage Output

V_{SYS_MIN}

V_{SYS_MAX}

3.6

4.4

3.65

4.45

I_SYS= 0A, V_BAT≤ 4.4V, V_BAT> V_{SYS_MIN}= 3.5V,

BATFET_DIS = 1

4.5

Top Reverse Blocking MOSFET

On-Resistance between VBUS and

PMID - Q1

Top Switching MOSFET

On-Resistance between PMID and

SW - Q2

Bottom Switching MOSFET

On-Resistance between SW and

GND - Q3

BATFET Forward Voltage in

Supplement Mode

R_{ON_RBFET}

18

21

mΩ

R_{ON_HSFET}

V_REGN= 5V

R_{ON_LSFET}

V_FWD

23

25

mΩ

mV

Battery Charger

Charge Voltage Program Range

Charge Voltage Step

V_{BAT_REG_RANGE}

V_{BAT_REG_STEP}

3.856

4.624

V

32

mV

4.192

4.184

4.338

4.326

4.385

4.374

-0.4

4.208

4.224

4.232

4.366

4.375

4.415

4.423

0.4

T_J= +25℃

VREG[4:0] = 01011

(4.208V)

T_J= -40℃ to +85℃

T_J= +25℃

4.352

4.400

VREG[4:0] = 01111

(4.352V)

Charge Voltage Setting

V_{BAT_REG}

V

T_J= -40℃ to +85℃

T_J= +25℃

VREG[4:0] = 10001

(4.400V)

T_J= -40℃ to +85℃

T_J= +25℃

V_{BAT_REG}= 4.208V or

V_{BAT_REG_ACC}V_{BAT_REG}= 4.352V or

V_{BAT_REG}= 4.400V

Charge Voltage Setting Accuracy

%

-0.6

0.6

T_J= -40℃ to +85℃

Charge Current Regulation Range

Charge Current Regulation Step

I_{CHG_REG_RANGE}

I_{CHG_REG_STEP}

0

3780

mA

60

0.06

0.24

0.72

1.38

2.04

0.06

0.255

0.76

1.4

I_CHG= 60mA

I_CHG= 240mA

I_CHG= 720mA

I_CHG= 1.38A

I_CHG= 2.04A

0.045

0.215

0.67

1.31

1.97

0.035

0.22

0.695

1.3

0.08

0.275

0.77

V_BAT=3.1V,

T_J= +25℃

1.45

2.11

Charge Current Regulation Setting

I_{CHG_REG}

A

I

_CHG= 60mA

0.085

0.285

0.82

I_CHG= 240mA

I_CHG= 720mA

I_CHG= 1.38A

I_CHG= 2.04A

V_BAT= 3.8V,

T_J= +25℃

1.515

2.16

1.92

2.04

Pre-Charge Current Regulation

Setting

I_PRECHG

160

185

210

mA

IPRECHG[3:0] = 0010 (180mA), T_J= +25℃

Battery LOW Falling Threshold

Battery LOW Rising Threshold

V_{BATLOW_FALL}I_CHG= 480mA

2.83

3.07

2.95

3.15

3.07

3.23

V

V_{BATLOW_RISE}Change from pre-charge to fast charging

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

8

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

ELECTRICAL CHARACTERISTICS (continued)

(V_{VAC_UVLOZ}< V_VAC< V_{VAC_OV}and V_VAC> V_BAT+ V_SLEEP, T_J= -40℃ to +85℃, typical values are at T_J= +25℃, unless otherwise

noted.)

PARAMETER

SYMBOL

CONDITIONS

ITERM[3:0] = 0010 (180mA)

MIN

TYP MAX UNITS

I_CHG> 1.26A,

V_{BAT_REG}= 4.208V,

T_J= +25℃

160

190

220

215

Termination Current Regulation

Setting

I_TERM

mA

I_CHG≤ 1.26A,

V_{BAT_REG}= 4.208V,

T_J= +25℃

ITERM[3:0] = 0010 (180mA)

165

V_SHORT

V_SHORTZ

I_SHORT

V_BATfalling

V_BATrising

1.95

2.15

2

2.05

2.25

Battery Short Voltage

Battery Short Current

V

2.2

90

V_BAT< V_SHORTZ

mA

mV

V_BATfalling, VRECHG = 0 (100mV)

V_BATfalling, VRECHG = 1 (200mV)

V_SYS= 4.2V

90

110

220

20

135

245

Recharge Threshold below

V_{BAT_REG}

V_RECHG

200

System Discharge Load Current

I_{SYS_LOAD}

mA

BATFET MOSFET

On-Resistance

R_{ON_BATFET}

V_BAT= 4.2V, measured from BAT pin to SYS pin

11

17

mΩ

Input Voltage and Current Regulation (DPM: Dynamic Power Management)

VINDPM_OS = 00 (4.4V)

4.32

6.3

4.4

6.4

8

4.48

6.5

V

VINDPM_OS = 01 (6.4V)

VINDPM_OS = 10 (8V)

VINDPM_OS = 11 (11V)

Input Voltage Regulation Limit

V_INDPM

VINDPM[3:0] = 0101

7.88

10.8

8.1

11

11.15

Input Voltage Regulation

Accuracy

V_{INDPM_ACC}

V_{DPM_VBAT}

-2

2

%

V

Input Voltage Regulation Limit

Tracking VBAT

V_BAT= 4V, V_INDPM= 3.9V, T_J= +25℃,

4.22

-2.5

4.33

4.44

2.5

VDPM_BAT_TRACK[1:0] = 11 (300mV)

Input Voltage Regulation

Accuracy Tracking VBAT

V_{DPM_VBAT_ACC}

%

T_J= +25℃

IINDPM[4:0] = 00100 (500mA) 425

IINDPM[4:0] = 01000 (900mA) 820

630

V_VBUS= 5V,

current pulled from SW,

T_J= +25℃

1000

1540

2040

USB Input Current Regulation

Limit

I_INDPM

mA

%

IINDPM[4:0] = 01110 (1.5A)

IINDPM[4:0] = 10011 (2A)

1365

1780

Input Current Limit during System

Start-Up Sequence

I_{IN_START}

270

BAT Pin Over-Voltage Protection

V_{BATOVP_RISE}

V_{BATOVP_FALL}

V_BATrising

V_BATfalling

102.8 103.8 104.8

100.8 101.8 102.8

As percentage of

Battery Over-Voltage Threshold

V

_{BAT_REG}, T_J= +25℃

Thermal Regulation and Thermal Shutdown

120

80

TREG = 1 (120℃)

TREG = 0 (80℃)

Junction Temperature Regulation

Threshold

T_{JUNCTION_REG}Temperature increasing

℃

Thermal Shutdown Rising

Temperature

T_SHUT

Temperature increasing

150

30

℃

Thermal Shutdown Hysteresis

T_{SHUT_HYS}

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

9

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

ELECTRICAL CHARACTERISTICS (continued)

(V_{VAC_UVLOZ}< V_VAC< V_{VAC_OV}and V_VAC> V_BAT+ V_SLEEP, T_J= -40℃ to +85℃, typical values are at T_J= +25℃, unless otherwise

noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

JEITA Thermistor Comparator (Buck Mode)

T1 (0℃) Threshold Voltage

Charge suspends if temperature T is below T1

(T < T1), as percentage of V_REGN

72.7

71.1

67.5

73.2

71.6

68

73.7

72.1

68.5

on TS Pin

V_T1

%

As percentage of V_REGN

V_T1Falling

T2 (10℃) Threshold Voltage

on TS Pin

Charge sets to I_CHG/2 and the lower of 4.1V and

V

_REGif T1 < T < T2, as percentage of V_REGN

V_T2

As percentage of V_REGN

66.2

45.4

66.7

45.9

67.2

46.4

V_T2Falling

V_T3Rising

V_T3

%

T3 (45℃) Threshold Voltage

Charge sets to the lower of 4.1V and V_REG

if T3 < T < T4, as percentage of V_REGN

44

44.5

45

on TS Pin

As percentage of V_REGN

35

35.5

34.2

36

V_T4Rising

V_T4

T4 (60℃) Threshold Voltage

on TS Pin

Charge suspends if T > T4, as percentage of

V_REGN

33.7

34.7

Cold or Hot Thermistor Comparator (Boost Mode)

Cold Temperature Threshold

(TS Pin Voltage Rising Threshold)

TS Voltage Falling

(Exit from Cold Range to Cool)

79.5

78.5

30.7

34

80

79

80.5

79.5

31.7

35

As percentage of V_REGN(approx. -20℃ w/ 103AT)

As percentage of V_REGN

V_BCOLD

%

Hot Temperature Threshold

31.2

34.5

As percentage of V_REGN(approx. 60℃ w/ 103AT)

As percentage of V_REGN

(TS Pin Voltage Falling Threshold)

V_BHOT

TS Voltage Rising

(Exit Hot Range to Warm)

Charge Over-Current Comparator (Cycle-by-Cycle)

HSFET Cycle-by-Cycle

Over-Current Threshold

I_{HSFET_OCP}

I_{BATFET_OCP}

7.1

8

10.3

A

T_J= +25℃

System Overload Threshold

Charge Under-Current Comparator (Cycle-by-Cycle)

LSFET Under-Current Falling

I_{LSFET_UCP}

Change rectifier from synchronous mode to

non-synchronous mode

180

mA

Threshold

PWM

Buck mode

Oscillator frequency, T_J= +25℃

Boost mode

1380

1500

99

1620

PWM Switching Frequency

f_SW

kHz

%

Maximum PWM Duty Cycle ⁽¹⁾

Boost Mode Operation

D_MAX

Boost Mode Regulation Voltage

V_{OTG_REG}

V_BAT= 3.8V, I_PMID= 0A, BOOSTV[1:0] = 10 (5.15V)

5.05

-2

5.15

5.25

2

V

Boost Mode Regulation Voltage

Accuracy

V_{OTG_REG_ACC}V_BAT= 3.8V, I_PMID= 0A, BOOSTV[1:0] = 10 (5.15V)

V_BATfalling, MIN_BAT_SEL = 0

%

2.9

3.1

3

3.1

3.3

V_BATrising, MIN_BAT_SEL = 0

V_{BATLOW_OTG}

3.2

2.5

2.7

Exit Boost Mode due to Low Battery

Voltage

V

V_BATfalling, MIN_BAT_SEL = 1

2.37

2.55

2.63

2.87

V_BATrising, MIN_BAT_SEL = 1

OTG Mode Maximum Output

Current

I_OTG

1.05

5.85

1.25

6

1.5

A

V

BOOST_LIM = 1 (1.2A), T_J= +25℃

OTG Over-Voltage Threshold

V_{OTG_OVP}

Rising threshold

6.15

HSFET Under-Current Falling

Threshold

Change rectifier from synchronous mode to

non-synchronous mode

I_{OTG_HSZCP}

350

mA

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

10

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

ELECTRICAL CHARACTERISTICS (continued)

(V_{VAC_UVLOZ}< V_VAC< V_{VAC_OV}and V_VAC> V_BAT+ V_SLEEP, T_J= -40℃ to +85℃, typical values are at T_J= +25℃, unless otherwise

noted.)

PARAMETER

REGN LDO

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

V_VBUS= 9V, I_REGN= 40mA

V_VBUS= 5V, I_REGN= 20mA

4.5

4.8

4.9

5.2

5

REGN LDO Output Voltage

V_REGN

V

Logic I/O Pin Characteristics (nCE, PSEL, DCEN, SCL, SDA and nINT)

nCE, PSEL,

SCL, SDA,

nINT

Input Low Threshold

Input High Threshold

Input Low Threshold

Input High Threshold

V_IL

V_IH

V_IL

0.4

V

1.3

0.1

REGN

0.1

V

DCEN

V_IH

I_BIAS

V

High-Level Leakage Current

Pull up rail 1.8V

1

µA

Logic I/O Pin Characteristics (nPG, STAT) – Open-Drain

Low-Level Output Voltage

V_OL

0.2

V

NOTE:

1. Guaranteed by design. Not production tested.

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

11

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

TIMING REQUIREMENTS

(V_{VAC_UVLOZ}< V_VAC< V_{VAC_OV}and V_VAC> V_BAT+ V_SLEEP, T_J= +25℃, unless otherwise noted.)

PARAMETER

V_VBUS/V_BATPower-Up

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

V_VBUSrising above ACOV threshold to

turn off Q2

VBUS OVP Reaction Time

t_ACOV

0.1

30

µs

Wait Window for Bad Adaptor Detection

Battery Charger

t_{BAD_SRC}

ms

Deglitch Time for Charge Termination

Deglitch Time for Recharge

t_{TERM_DGL}

t_{RECHG_DGL}

t_{SYSOVLD_DGL}

t_BATOVP

230

112

1

ms

µs

System Over-Current Deglitch Time to Turn off Q4

µs

Battery Over-Voltage Deglitch Time to Disable Charge

t_{BATOVP_DCEN}DCEN active

2.8

14.5

31

3.5

16

4.4

17.9

39

ms

h

Typical Charge Safety Timer Range

Typical Top-Off Timer Range

t_SAFETY

CHG_TIMER = 1

t_{TOP_OFF}

TOPOFF_TIMER[1:0] = 10 (35min)

35

min

nQON Timing and Ship Mode Timing

nQON Negative Pulse Low Pulse Width to Turn on

BATFET and Exit Ship Mode

t_SHIPMODE

0.9

1

1.2

s

nQON Low Time to Reset BATFET

BATFET off Time during Full System Reset

Wait Delay for Entering Ship Mode

Digital Clock and Watchdog Timer

t_{QON_RST}

t_{BATFET_RST}

t_{SM_DLY}

9

10

11.5

355

s

ms

s

285

11

320

12.3

13.5

WATCHDOG[1:0] = 01,

REGN LDO disabled

Watchdog Reset Time

t_WDT

40.9

s

Digital Clock Frequency in Low Power

Digital Clock Frequency

I²C Interface

f_LPDIG

f_DIG

REGN LDO disabled

REGN LDO enabled

31

kHz

500

SCL Clock Frequency

f_SCL

400

kHz

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

12

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

TYPICAL PERFORMANCE CHARACTERISTICS

Charge Efficiency vs. Charge Current

OTG Efficiency vs. OTG Current

100

95

90

85

80

75

70

100

95

90

85

80

75

70

V_BAT= 3.8V, L = 1μH (WURTH 74439344010),

DCR = 5.5mΩ

V_OTG= 5.15V, L = 1μH (WURTH 74439344010),

DCR = 5.5mΩ

V_VBUS= 5V

V_BAT= 3.3V

V

_VBUS= 9V

_VBUS= 12V

V

_BAT= 3.8V

_BAT= 4V

0.1 0.6 1.1 1.6 2.1 2.6 3.1 3.6 4.1

0

0.2

0.4

0.6

0.8

1

1.2

Charge Current (A)

OTG Current (A)

OTG Output Voltage vs. Output Current

Charge Current Accuracy vs. Charge Current

6

5

4

3

2

1

0

10

9

8

7

6

5

4

3

2

1

0

V_BAT= 3.8V, V_OTG= 5.15V

V_VBUS= 5V, V_BAT= 4V

0

0.2

0.4

0.6

0.8

1

1.2

0.5

1

1.5

2

2.5

3

3.5

4

Charge Current (A)

Output Current (A)

SYS_MIN Voltage vs. Junction Temperature

BAT_REG Charge Voltage vs. Junction Temperature

3.85

3.80

3.75

3.70

3.65

3.60

3.55

3.50

4.50

4.45

4.40

4.35

4.30

4.25

4.20

4.15

4.10

4.05

4.00

V_{BAT_REG}= 4.208V

V_{BAT_REG}= 4.352V

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Junction Temperature (℃)

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

13

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Input Current Limit vs. Junction Temperature

Charge Current vs. Junction Temperature

I_CHG= 240mA

2500

2000

1500

1000

500

2000

1800

1600

1400

1200

1000

800

IINDPM = 500mA

IINDPM = 900mA

IINDPM = 1500mA

I

_CHG= 720mA

_CHG= 1380mA

600

400

200

0

-40 -25 -10

5

20 35 50 65 80 95

-40 -25 -10

5

20 35 50 65 80 95 110 125

Junction Temperature (℃)

VBUS Power-Up with Charge Disable (V_BAT= 3.2V)

VBUS Power-Up with Charge Enable (V_BAT= 3.2V)

VBUS

REGN

VBUS

REGN

V_SYS

PMID

I_CHG

V_VBUS= 5V, V_BAT= 3.2V

V_VBUS= 5V, V_BAT= 3.2V, I_CHG= 2A

Time (100ms/div)

Charge Enable

Charge Disable

STAT

nCE

STAT

nCE

SW

I_BAT

V_VBUS= 5V, V_BAT= 3.2V, I_CHG= 2A

Time (10ms/div)

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

14

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

PFM Switching in Buck Mode, Charge Disable

OTG Switching (Boost Mode)

V_SYS

SW

I_L

V_VBUS= 5V, I_SYS= 50mA

V_BAT= 4V, I_LOAD= 50mA, PFM Enable

Time (2μs/div)

Time (10μs/div)

PFM Switching in Buck Mode, Charge Disable

OTG Switching (Boost Mode)

V_SYS

SW

I_L

SW

I_L

V_BAT= 4V, I_LOAD= 1A, PWM

V_VBUS= 9V, I_SYS= 50mA

Time (2μs/div)

Time (1μs/div)

PFM Switching in Buck Mode, Charge Disable

OTG Start-Up

V_SYS

SW

I_L

V_PMID

VBUS

SW

V_VBUS= 12V, I_SYS= 50mA

Time (2μs/div)

Time (20ms/div)

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

15

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

System Load Transient

V_SYS

I_BAT

V_SYS

I_BAT

I_SYS

I_IN

V_VBUS= 5V, I_INDPM= 1A, I_CHG= 1A

V_BAT= 3.7V, I_SYS= 0A to 2A

V_VBUS= 5V,I_INDPM= 2A,I_CHG= 1A,

V_BAT= 3.7V,I_SYS= 0A to 4A

Time (2ms/div)

System Load Transient

V_SYS

I_BAT

I_SYS

I_IN

V_VBUS= 5V, I_INDPM= 1A, I_CHG= 2A

V_BAT= 3.7V, I_SYS= 0A to 2A

V_VBUS= 5V, I_INDPM= 1A, I_CHG= 2A

V_BAT= 3.7V, I_SYS= 0A to 4A

I_IN

Time (2ms/div)

System Load Transient

V_SYS

I_BAT

I_SYS

I_IN

V_VBUS= 5V, I_INDPM= 2A, I_CHG= 2A

V_BAT= 3.7V, I_SYS= 0A to 4A

V_VBUS= 5V, I_INDPM= 2A, I_CHG= 2A

V_BAT= 3.7V, I_SYS= 0A to 2A

I_IN

Time (2ms/div)

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

16

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

PWM Switching in Buck Mode (L = 1µH)

PWM Switching in Buck Mode (L = 1μH)

SW

I_L

V_VBUS= 5V, I_CHG= 1980mA, Charge Enable

V_VBUS= 12V, I_CHG= 1980mA, Charge Enable

Time (1μs/div)

V_INDPMTracking Battery Voltage

VBUS

V_BAT

I_IN

Time (1s/div)

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

17

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

TYPICAL APPLICATION CIRCUIT

22µF

OTG

5V at 1.2A

Input

3.9V to 13.5V

VAC

PMID

LS/SC

DCEN

VBUS

1µF

1µH

VSYS

10µF × 2

SW

47nF

BTST

PHY

PSEL

REGN

SYS

4.7µF

GND

2.2kΩ

SYS

BAT

nPG

I_CHG= 3A

V_REF

STAT

10µF

SGM41516

10kΩ

BATSNS

Host

51pF

REGN

5.23kΩ

SDA

SCL

nINT

47Ω

TS

nCE

nQON

30.1kΩ

10kΩ

Optional

Figure 1. SGM41516 Typical Application Circuit

22µF

OTG

5V at 1.2A

Input

3.9V to 13.5V

VAC

PMID

LS/SC

DCEN

VBUS

1µF

1µH

VSYS

10µF × 2

SW

47nF

D+

D-

BTST

USB

REGN

4.7µF

SYS

GND

SYS

BAT

2.2kΩ

I_CHG= 3A

10µF

V_REF

STAT

SGM41516D

BATSNS

10kΩ

Host

51pF

REGN

5.23kΩ

SDA

SCL

nINT

47Ω

TS

nCE

nQON

30.1kΩ

10kΩ

Optional

Figure 2. SGM41516D Typical Application Circuit

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

18

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

FUNCTIONAL BLOCK DIAGRAM

VBUS

PMID

RBFET (Q1)

VAC

REGN

LDO

REGN

BTST

Q1

Control

Protections:

Voltage & Current

Sensing

OVP

UVP

OCP

UCP

OTP

&

DAC Reference

HSFET (Q2)

D+

SW

(SGM41516D Only)

Converter

Control

Input

Source

Detection

D-

REGN

(SGM41516D Only)

PSEL

(SGM41516 Only)

LSFET (Q3)

GND

SYS

REGN

DCEN

Digital

Control

I_CHG

nPG

(SGM41516 Only)

Q4 Gate

Control

BATFET (Q4)

nINT

BAT

BATSNS

V_PULL-UP

STAT

nQON

nCE

SDA

SCL

Battery

Temperature

Sensing

I²C

Interface

JEITA

Control

TS

SGM41516

SGM41516D

Figure 3. Block Diagram

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

19

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION

The SGM41516/SGM41516D are power management and

charger devices for applications such as cell phones and

tablets that use high capacity single-cell Li-Ion or Li-polymer

batteries. The SGM41516/SGM41516D can accommodate a

wide range of input sources including USB, wall adaptor and

car chargers. It is optimized for 5V input (USB voltage) but is

capable to operate with input voltages from 3.9V to 13.5V. It

also supports JEITA profile for battery charging safety at high

or low temperatures. Automatic power path selection to

power the system (SYS) from the input source (VBUS),

battery (BAT) or both is another feature of the device. Battery

charge current is programmable and can reach to a maximum

of 3.78A (charge). In the Boost mode, the battery voltage is

boosted to power the VBUS pin (1.2A MAX) when it is a

power receiving node (USB OTG) that is typically regulated to

5.15V.

Power-Up from Battery Only (No Input

Source)

When only the battery is presented as a source and its

voltage is above depletion threshold (V_{BAT_DPL_RISE}), the

BATFET turns on and connects the battery to the system.

The quiescent current is minimum because the REGN LDO

remains off. Conduction losses are also low due to small

R_DSONof BATFET. Low losses help to extend the battery run

time.

The discharge current through BATFET is continuously

monitored. In the supplement mode, if a system overload (or

short) occurs (I_BAT> I_{BATFET_OCP}), the BATFET is turned off

immediately and BATFET_DIS bit is set to 1. The BATFET

will not enable until the input source is applied or one of the

BATFET Enable Mode (Exit Ship Mode) methods (explained

later) is used to activate the BATFET.

The device may operate in several different modes:

Power-Up Process from the Input Power

Source

In HIZ mode, the reverse blocking FET (Q1), internal REGN

LDO, converter switches and some other parts of the internal

circuit remain off to save the battery while it supplies DC

power to the system through BATFET.

Upon connection of an input source (VBUS), its voltage

sensed from VAC pin is checked to turn on the internal REGN

LDO regulator and the bias circuits (no matter whether the

battery is present or not). The input current limit is determined

and set before the Buck converter is started. The sequences

of actions when VBUS as input source is powered up are:

In the sleep mode, the switching is stopped. The charger

goes to the sleep mode when the input source voltage (V_VAC

)

is not high enough for charging the battery. In other words,

V_VACis smaller than V_BAT+ V_SLEEP(where V_SLEEPis a small

threshold) and Buck converter is not able to charge, even at

its maximum duty cycle. The Boost may also go to the sleep

mode if similar issue happens in the reverse direction (when

1. REGN LDO power-up.

2. Poor power source detection (qualification).

3. Input power source type detection. (Based on D+/D- or

PSEL input. It is used to set the default input current limit

(IINDPM[4:0]).)

V

_VACis almost equal to or smaller than V_BAT).

In supplement mode, the input source power is not enough to

supply system demanded power and the battery assists by

discharging to the system in parallel, and providing the deficit.

4. Setting of the input voltage limit threshold (VINDPM

threshold).

5. DC/DC converter power-up.

Power-On Reset (POR)

The internal circuit of the device is powered from the greater

Details of the power-up steps are explained in the following

sections.

voltage between V_VBUSand V_BAT. When the voltage of the

selected source goes above its UVLO level (V_VBUS

>

V_{VAC_UVLOZ}or V_BAT> V_{BAT_UVLOZ}), a POR happens and

activates the sleep comparator, battery depletion comparator

and BATFET driver. Upon activation, the I²C interface will

also be ready for communication and all registers reset to

their default values.

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SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

REGN LDO Power-Up

The REGN low dropout regulator powers the internal bias

circuits, HSFET and LSFET gate drivers and TS rail

(thermistor pin). The STAT pin can also be pulled up to REGN.

The REGN enables when the following 2 conditions are

satisfied and remain valid for a 220ms delay time, otherwise

the device stays in high impedance mode (HIZ) with REGN

LDO off.

PSEL pin. A pulse is sent to nINT pin to inform the host when

the input source type detection is completed. Some registers

and pins are also updated as detailed below:

1. Input current limit register (the value in the IINDPM[4:0]) is

changed to set current limit.

2. PG_STAT (power good) bit is set.

3. VBUS_STAT[2:0] register is updated to indicate USB or

adaptor input source types.

1. V_VAC> V_{VAC_PRESENT}

.

The input current is always limited by the IINDPM[4:0] register

and the limit can be updated by the host if needed.

2. V_VAC> V_BAT+ V_SLEEPZ(in Buck mode) or V_VBUS< V_BAT

V_SLEEP(in Boost mode).

+

In HIZ state, the quiescent current drawn from VBUS is very

small (less than I_{VBUS_HIZ}). System is only powered by the

battery in HIZ mode.

Input Current Limit by PSEL (SGM41516)

PSEL pin interfaces with USB physical layer (PHY) for input

current limit setting. The USB PHY device output is used to

detect if the input is a USB host or a charging port. In the

host-control mode, the host must enable IINDET_EN bit for

reading the PSEL value and updating the IINDPM[4:0]. In the

default mode, IINDPM[4:0] is updated automatically by PSEL

value in real time as given in Table 1.

Poor Power Source Detection (Qualification)

When REGN LDO is powered, the input source (adaptor) is

checked for its type and current capacity. To start the Buck

converter, the input (VBUS) must meet the following

conditions:

Table 1. Input Current Limit Setting from PSEL

Input Current

1. V_VBUS< V_{VAC_OV}

.

2. V_VBUS> V_{VBUS_MIN}during t_{BAD_SRC}test period (30ms TYP) in

which the I_{BAD_SRC}(30mA TYP) current is pulled from VBUS.

Input Detection PSEL Pin

VBUS_STAT[2:0]

Limit (I_LIM

)

USB Host SDP

Adaptor

High

Low

500mA

001

010

If the test is failed, the conditions are repeatedly checked

every 2 seconds. As soon as the input source passes

qualification, the VBUS_GD bit in status register is set to 1

and a pulse is sent to the nINT pin to inform the host. Type

detection will start as next step.

2400mA

Input Current Limit by D+/D- Detection (SGM41516D)

The SGM41516D integrates a D+/D- based input source

detection to set the input current limit when VBUS is plugged

in. When the input source is plugged in, the SGM41516D

starts USB BC1.2 detection and set the SDP/DCP related

input current limit. And if the data contact detection timer

expires, the non-standard adaptor detection starts and then

sets the input current limit. Please refer to Table 2 and Table

3.

Input Power Source Type Detection

The input source detection will run through the D+/D- lines or

the PSEL pin while REGN LDO is powered and after the

VBUS_GD bit is set. The SGM41516D can detect the input

source types which include SDP/DCP and non-standard

adaptor through the D+/D- pins following USB BC1.2

Specification. The SGM41516 sets the input current limit via

Table 2. Non-Standard Adaptor Detection

Non-Standard Adaptor

Divider 1

D+ Threshold

VD+ within V2P7

VD+ within V1P2

VD+ within V2P0

VD+ within V2P7

D- Threshold

VD- within V2P0

VD- within V1P2

VD- within V2P7

Input Current Limit (A)

2.1

2

Divider 2

Divider 3

1

Divider 4

2.4

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SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Table 3. Input Current Limit Setting from D+/D- Detection

The BATFET remains on to charge the battery if the battery

charging function is enabled, otherwise BATFET turns off.

D+/D- Detection

USB SDP (USB500)

USB DCP

Input Current Limit (I_INLIM)

500mA

2.4A

2.1A

2A

When converter operates for battery charging, it acts as an

efficient, fixed frequency synchronous Buck converter

regardless of the input/output voltages and currents. However,

it is capable to switch to PFM mode at light load when

charging is disabled or when the detected battery voltage is

less than minimum system voltage setting. PFM operation

can be enabled or prevented in either Buck or Boost mode

using the PFM_DIS bit.

Divider 1

Divider 2

Divider 3

1A

Divider 4

2.4A

500mA

Unknown 5V Adaptor

Force Detection of Input Current Limit

Boost Mode

The host can set IINDET_EN bit to 1 in host mode to force the

device to run. And the IINDET_EN bit returns to 0 by itself and

input result is updated after the detection is completed.

The SGM41516/SGM41516D support USB On-The-Go.

When a load device is connected to the USB port, the

converter can operate as a step-up synchronous converter

(Boost mode) with 1.5MHz switching frequency to supply

power from the battery to that load. The 500mA USB OTG

output current limit requirement is achieved by programming,

however, the Boost converter can deliver 1.2A to the output

(default limit). Converter will be set to Boost mode if at least

30ms is passed from enabling this mode (OTG_CONFIG bit =

1) and the following conditions are satisfied:

D+/D- Output Voltage Setting (SGM41516D)

The host can be set D+/D- output voltages by DP_VSET[1:0]

and DM_VSET[1:0] to HIZ, 0V, 0.6V or 3.3V. When BC1.2

detection runs, these bits are ignored.

Setting of the Input Voltage Limit Threshold

(VINDPM Threshold)

1. V_BAT> V_{BATLOW_OTG}

.

A wide voltage range (3.9V to 5.4V, 5.9V to 9V, 10.5V to 12V)

is supported for the input voltage limit setting in VINDPM[3:0]

and VINDPM_OS[1:0]. 4.5V is the default for USB.

2. V_VBUS< V_BAT+ V_SLEEP(in sleep mode).

3. Acceptable voltage range at TS pin (V_BHOT< V_TS< V_BCOLD).

The output voltage is set to V_VBUS= 5.15V and is maintained

as long as V_BATis above V_{BATLOW_OTG}. The output current can

reach up to the programmed value by BOOST_LIM bit (0.5A

or 1.2A). The VBUS_STAT[2:0] status register bits are set to

111 in Boost mode (OTG).

The device supports dynamic tracking of the battery voltage

(VINDPM). VDPM_BAT_TRACK[1:0] bits can be used to

enable tracking (00 to disable tracking) and set the tracking

offset value. When the tracking is enabled, the input voltage

limit will be set to the larger value between the VINDPM[3:0] and

V_BAT+ VDPM_BAT_TRACK[1:0]. The VDPM_BAT_TRACK[1:0]

tracking offset can be set to 200mV, 250mV or 300mV. And

this function only takes effect when VINDPM_OS[1:0] = 00.

To minimize the output overshoot in Boost mode, the device

starts with PFM first and then switches to PWM. As stated

before, PFM can be avoided by using PFM_DIS bit in Buck

and Boost modes.

DC/DC Converter Power-Up

The 1.5MHz switching converter composed of LSFET and

HSFET is enabled, which can start switching when the input

current limit is set. Converter is initiated with a soft-start when

the system voltage is ramped up. If SYS voltage is less than

2.2V, the input current is limited to 200mA or IINDPM[4:0],

whichever is smaller, otherwise the limit is set to IINDPM[4:0].

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SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

In this mode the WATCHDOG_FAULT bit is low and all

device parameters can be programmed by the host. To

prevent device watchdog from reset that results in going back

to default mode, the host must disable the watchdog timer by

setting WATCHDOG[1:0] = 00, or it must consistently reset the

watchdog timer before expiry by writing 1 to WD_RST to prevent

WATCHDOG_FAULT bit from being set. Every time a 1 is

written to the WD_RST, the watchdog timer will restart

counting. Therefore, it should be reset again before overflow

(expiry) to keep the device in the host mode. If the watchdog

timer expires (WATCHDOG_FAULT bit = 1), the device returns

to default mode and all registers are reset to their default values

except for IINDPM[4:0], VINDPM[3:0], VINDPM_OS[1:0],

BATFET_DLY and BATFET_DIS bits that keep their values

unchanged.

Host Mode and Default Mode Operation with

Watchdog Timer

After a power-on reset, the device starts in default mode

(standalone) with all registers reset as if the watchdog timer is

expired. When the host is in sleep mode or there is no host,

the device stays in the default mode in which the

SGM41516/SGM41516D operate like an autonomous

charger. The battery is charged for 16 hours (default value for

the fast charging safety timer). Then the charge stops while

Buck converter continues to operate to power the system load.

In this mode, WATCHDOG_FAULT bit is high.

Most of the flexibility features of the SGM41516/SGM41516D

become available in the host mode when the device is

controlled by a host with I²C. By setting the WD_RST bit to 1,

the charger mode changes from default mode to host mode.

POR

Watchdog Timer Expired

Reset Registers

Start

Watchdog Timer

I²C Interface Enabled

Y

I²C Write?

Host Mode

Host Programs Registers

N

Default Mode

Reset Watchdog Timer

Reset Selective Registers

Y

WD_RST Bit = 1?

N

Y

N

I²C Write?

Y

N

Watchdog Timer

Expired?

Figure 4. Watchdog Timer Flow Chart

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SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Charge Status Report

STAT is an open-drain output pin that reports the status of

charge and can drive an LED for indication: a low indicates

that charging is in progress, a high shows that charging is

completed or disabled and alternating low/high (blinking)

show a charging fault. The STAT may be disabled (keep the

open-drain switch off) by setting EN_ICHG_MON[1:0] = 11.

Battery Charging Management

The SGM41516/SGM41516D are designed for charging

single-cell Li-Ion or Li-poly batteries with a charge current up

to 3.78A (MAX). The battery connection switch (BATFET) is

in the charge or discharge current path and features low

on-resistance (10mΩ) to allow high efficiency and low voltage

drop.

The CHRG_STAT[1:0] status register reports the present

charging phase and status by two bits: 00 = charging disabled,

01 = in pre-charge, 10 = in fast charging (constant current mode

or constant voltage mode) and 11 = charging completed.

Charging Cycle in Autonomous Mode

Charging is enabled if CHG_CONFIG = 1 and nCE pin is

pulled low. In default mode, the SGM41516/SGM41516D run

a charge cycle with the default parameters itemized in Table

4. At any moment, the device can be controlled by charging to

the host mode.

A negative pulse is sent on nINT pin to inform the host when a

charging cycle is completed.

In addition, the output status of STAT pin can be set by

STAT_SET[1:0] bits, 00 = LED off (HIZ), 01 = LED on (low),

10 = LED blinking at 1s on 1s off, 11 = LED blinking at 1s on

3s off. This two bits only take effect when EN_ICHG_MON[1:0]

= 01.

Table 4. Charging Parameter Default Setting

Default Mode

SGM41516/SGM41516D

Charging Voltage (V_REG

)

4.208V

2.04A

180mA

JEITA

16h

Charging Current (I_CHG

)

Pre-Charge Current (I_PRECHG

)

Battery Charging Profile

The SGM41516/SGM41516D feature a full battery charging

profile with five phases. In the beginning of the cycle, the

battery voltage (V_BAT) is tested, and appropriate current and

voltage regulation levels are selected as shown in Table 5.

Depending on the detected status of the battery, the proper

phase is selected to start or for continuation of the charging

cycle. The phases are trickle charge (V_BAT< 2.2V),

pre-charge, fast-charge (constant current and constant

voltage) and top-off trickle charge.

Termination Current (I_TERM

Temperature Profile

Safety Timer

)

Start a New Charging Cycle

If the converter can start switching and all the following

conditions are satisfied a new charge cycle starts:

• NTC temperature fault is not asserted (TS pin).

• Safety timer fault is not asserted.

• BATFET is not forced off. (BATFET_DIS bit = 0).

• Charging enabled (3 conditions: CHG_CONFIG bit = 1,

ICHG[5:0] register is not 0mA and nCE pin is low).

• Battery voltage is below the programmed full charge level

(V_REG).

Table 5. Charging Current Setting Based on V_BAT

Selected

V_BATVoltage Charging

Current

Default Value

in the Register

CHRG_STAT[1:0]

< 2.2V

2.2V to 3.15V

> 3.15V

I_SHORT

I_PRECHG

I_CHG

90mA

180mA

2.04A

01

10

A new charge cycle starts automatically if battery voltage falls

below the recharge threshold level (V_REG- 100mV or V_REG

-

200mV configured by VRECHG bit). Also, if the charge cycle

is completed, a new charging cycle can be initiated by

toggling of the nCE pin or CHG_CONFIG bit.

Note that in the DPM or thermal regulation modes, normal

charging functions are temporarily modified: The charge

current will be less than the value in the register. The

termination is disabled, and the charging safety timer is

slowed down by counting at half clock rate.

Normally a charge cycle terminates when the charge voltage

is above the recharge threshold level and the charging

current falls below the termination threshold if the device is

not in thermal regulation or Dynamic Power Management

(DPM) mode.

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SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Regulation Voltage

VREG[4:0]

Battery Voltage

Charge Current

ICHG[5:0]

Charge Current

V

_BATLOW(3.15V)

V_SHORTZ(2.2V)

IPRECHG[3:0]

ITERM[3:0]

I_SHORT

Trickle Charge Pre-Charge

Fast Charge and Voltage Regulation

Top-Off Timer Safety Timer

(Optional) Expiration

Figure 5. Battery Charging Profile

Charge Termination

safety timer is suspended, the top-off timer will also be

suspended or if the safety timer is slowed down, the

termination timer will also be slowed down. The

TOPOFF_ACTIVE bit reports the active/not active status of

A charge cycle is terminated when the battery voltage is

higher than the recharge threshold and the charge current

falls below the programmed termination current. Unless there

is a high power demand for system and it needs to operate in

supplement mode, the BATFET turns off at the end of the

charge cycle. Even after termination, the Buck converter

operates continuously to supply the system.

the

top-off

timer.

The

CHRG_STAT[1:0]

and

TOPOFF_ACTIVE bits can be read to find status of the

termination.

Any of the following events resets the top-off timer:

CHRG_STAT[1:0] is set to 11 and a negative pulse is sent to

nINT pint after termination.

1. Disable to enable transition of nCE (charge enable).

2. A low to high change in the status of termination.

3. Set REG_RST bit to 1.

If the charger is regulating input current, input voltage or

junction temperature instead of charge current, termination

will be temporarily prevented. EN_TERM bit is termination

control bit and can be set to 0 to disable termination before it

happens.

The setting of the top-off timer is applied at the time of

termination detection and unless a new charge cycle is

started, modifying the top-off timer parameters after

termination has no effect. A negative pulse is sent to nINT

when top-off timer is started or ended.

At low termination currents (60mA TYP), the offset in the

internal comparator may give rise to a higher (+10mA to

+20mA) actual termination current. A delay in termination can

be added (optional) as a compensation for comparator offset

using a programmable top-off timer. During the delay,

constant voltage charge phase continues and gives the falling

charge current a chance to drop closer to the programmed

value. The top-off delay timer has the same restrictions of the

safety timer. As an example, under some conditions, if the

Temperature Qualification

The charging current and voltage of the battery must be

limited when battery is cold or hot. A thermistor input for

battery temperature monitoring is included in the device that

can protect the battery based on JEITA guidelines.

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SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Compliance with JEITA Guideline

JEITA guideline (April 20, 2007 release) is implemented in the

device for safe charging of the Li-Ion battery. JEITA highlights

the considerations and limits that should be considered for

charging at cold or hot battery temperatures. High charge

current and voltage must be avoided outside normal

operating temperatures (typically 0 ℃ and 60 ℃ ). This

functionality can be disabled if not needed. Four temperature

levels are defined by JEITA from T1 (minimum) to T4

(maximum). Outside this range, charging should be stopped.

The corresponding voltages sensed by NTC are named V_T1to

V_T4. Due to the sensor negative resistance, a higher

temperature results in a lower voltage on TS pin. The battery

cool range is between T1 and T2 and the warm range is

between T3 and T4. Charge must be limited in the cool and

warm ranges.

SGM41516

SGM41516D

BAT

10µF

REGN

4.7µF

R_T1

TS

Li-Ion

Cell

NTC

10kΩ@25℃

R_T2

Figure 6. Battery Thermistor Connection and Bias

Network

One of the conditions for starting a charge cycle is having the

TS voltage within V_T1to V_T4window limits. If during the

charge, battery gets too cold or too hot and TS voltage

exceeds the T1 - T4 limits, charging is suspended (zero

charge current) and the controller waits for the battery

temperature to come back within the T1 to T4 window.

A 103AT-2 type thermistor is recommended to use for the

SGM41516/SGM41516D. Other thermistors may be used

and bias network (see Figure 6) can be calculated based on

the following equations:













1

R_THCOLD×R_THHOT

×

−

(1)

V_T1V_T4

R_T2

=

JEITA recommends reducing charge current to 1/2 of fast

charging current or lower at cool temperatures (T1 - T2). For

warmer temperature (within T3 - T4 range), charge voltage is

recommended to be kept below 4.1V.

















1

R_THHOT

×

−1 −R

×

−1





THCOLD

V_T4

V_T1











1

V_T1



−1



(2)



1

R_T1

=

The SGM41516/SGM41516D exceed the JEITA requirement

by their flexible charge parameter settings. At warm

temperature range (T3 - T4), the charge voltage is set to the

lower of V_REGand 4.1V when JEITA_VSET_H = 0, the charge

voltage is set to V_REGwhen JEITA_VSET_H = 1, and the

charge current can be reduced down to 0%, 20% or 50% of

fast charging current by the JEITA_ISET_H[1:0] bits. At cool

temperatures (T1 - T2), the current setting can be reduced

down to 50% or 20% of fast charging current selectable by

the JEITA_ISET_L bit when JEITA_ISET_L_EN = 1, and the

charge voltage is set to V_REGwhen JEITA_VSET_L = 0, the

charge voltage is set to the lower of V_REGand 4.1V when

JEITA_VSET_L = 1. Additional, the cool threshold T2 and

warm threshold T3 can be changed through JEITA_VT2[1:0]

and JEITA_VT3[1:0], and the charge current can be disabled

by setting JEITA_ISET_L_EN = 0.













1

+









R_T2

R_THCOLD

where V_T1and V_T4are T_COLDand T_HOTthreshold voltages on

TS pin as percentage to V_REGN, R_THCOLDand R_THHOTare

thermistor resistances (R_TH) at desired T1 (Cold) and T4 (Hot)

temperatures. Select T_COLD= 0℃ and T_HOT= 60℃ for Li-Ion

or Li-polymer batteries. For a 103AT-2 type thermistor

R_THCOLD= 27.28kΩ and R_THHOT= 3.02kΩ, the calculation

results are: R_T1= 5.23kΩ and R_T2= 30.1kΩ.

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SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Boost Mode Temperature Monitoring (Battery

Discharge)

the fault condition is removed. If charging cycle is stopped by

a restart or by toggling nCE pin or CHG_CONFIG bit, the

timer resets and restarts a new timing.

The device is capable to monitor the battery temperature for

safety during the Boost mode. The temperature must remain

within the V_BCOLDto V_BHOTthresholds, otherwise the Boost

mode will be suspended and VBUS_STAT[2:0] bits are set to

000. Moreover, NTC_FAULT[2:0] register is updated to report

Boost mode cold or hot condition. Once the temperature

returns within the window, the Boost mode is resumed and

NTC_FAULT[2:0] register is cleared to 000 (normal).

Narrow Voltage DC (NVDC) Design in

SGM41516/SGM41516D

The SGM41516/SGM41516D feature an NVDC design using

the BATFET that connects the system and battery. By using

the linear region of the BATFET, the charger regulates the

system bus voltage (SYS pin) above the minimum setting

using Buck converter even if the battery voltage is very low.

MOSFET linear mode allows for the large voltage difference

between SYS and BAT pins to appear as V_DSacross the

switch while conducting and charging battery. SYS_MIN[2:0]

register sets the minimum system voltage (default 3.5V). If

the system is in minimum system voltage regulation,

VSYS_STAT bit is set.

V_REGN

Boost Disabled

V_BCOLD

(-20℃)

Boost Enabled

V_BHOT

(60℃)

The BATFET operates in linear region when the battery

voltage is below the minimum system voltage setting. The

system voltage is regulated to 180mV (TYP) above the

minimum system voltage setting. The battery gradually gets

charged and its voltage rises above the minimum system

voltage and lets BATFET to change from linear mode to fully

turned-on switch such that the voltage difference between the

system and battery is the small V_DSof fully on BATFET.

Boost Disabled

AGND

Figure 7. TS Pin Thermistor Temperature Window

Settings in Boost Mode

Safety Timer

Abnormal battery conditions may result in prolonged charge

cycles. An internal safety timer is considered to stop charging

in such conditions. If the safety time is expired,

CHRG_FAULT[1:0] bits are set to 11 and a negative pulse is

sent to nINT pin. By default, the charge time limit. And it is 2

hours if the battery voltage does not rise above V_BATLOW

threshold. And it is 16 hours if it goes above V_BATLOW. This

feature is optional and can be disabled by clearing

EN_TIMER bit. The 16 hours limit can also be reduced to 7

hours by clearing CHG_TIMER bit.

The system voltage is always regulated to 50mV (TYP) above

the battery voltage if:

1. The charging is terminated.

2. Charging is disabled and the battery voltage is above the

minimum system voltage setting.

4.5

4.3

4.1

3.9

3.7

The safety timer counts at half clock rate when charger is

running under input voltage regulation, input current

regulation, JEITA cool or thermal regulation. Because in

these conditions, the actual charge current is likely to be less

than the register setting. As an example, if the safety timer is

set to 7 hours and the charger is regulating the input current

(IINDPM_STAT bit = 1) in the whole charging cycle, the

actual safety time will be 16 hours. Clearing the TMR2X_EN

bit will disable the half clock rate feature.

3.5

Charge Enabled

Charge Disabled

Minimum System Voltage

3.3

3.1

2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3

Battery Voltage (V)

Figure 8. System Voltage vs. Battery Voltage

The safety timer is paused if a fault occurs or charger is in

supplement mode, charging is suspended. It will resume once

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SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

SGM41516/SGM41516D Dynamic Power Management

(DPM)

Battery Supplement Mode

If the system voltage drops below the battery voltage, the

BATFET gradually starts to turn on. The threshold margin is

180mV if V_{SYS_MIN}setting is less than V_BAT. And it is 45mV if

V_{SYS_MIN}setting is larger than V_BAT.At low discharge currents,

the BATFET gate voltage is regulated (R_DSmodulation) such

that the BATFET V_DSstays at 30mV. At higher currents, the

BATFET will turn fully on (reaching its lowest R_DSON). From

this point, increasing the discharge current will linearly

increase the BATFET V_DS(determined by R_DSON× I_D). Use of

the MOSFET linear mode at lower currents prevents swinging

oscillation of entering and exiting the supplement mode.

The SGM41516/SGM41516D have

a

dynamic power

management (DPM) feature. To implement DPM, the device

always monitors the input current and voltage to regulate

power demand from the source and avoid input adaptor

overloading or to meet the maximum current limits specified

in the USB specs. Overloading an input source may results in

either current trying to exceed the input current limit (I_INDPM) or

the voltage tending to fall below the input voltage limit

(V_INDPM). With DPM, the device keeps the VSYS regulating to

its minimum setting by reducing the battery charge current

adequately such that the input parameter (voltage or current)

does not exceed the limit. In other words, charge current is

reduces to satisfy I_IN≤ I_INDPMor V_IN≥ V_INDPMwhichever occurs

first. DPM can be either an I_INtype (IINDPM) or V_INtype

(VINDPM) depending on which limit is reached.

BATFET gate regulation V-I characteristics is shown in Figure

10. If the battery voltage falls below its minimum depletion,

the BATFET turns off and exits supplement mode.

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Changing to the supplement mode may be required if the

charge current is decreased and reached to zero, but the

input is still overloaded. In this case, the charger reduces the

system voltage below the battery voltage to allow operation in

the supplement mode and provide a portion of system power

demand from the battery through the BATFET.

The IINDPM_STAT or VINDPM_STAT status bits are set

during an IINDPM or VINDPM respectively. Figure 9

summarizes the DPM behavior (IINDPM type) for a design

example with a 9V/1.2A adaptor, 3.2V battery, 2.8A charge

current setting and 3.4V minimum system voltage setting.

0

10

20

30

40

50

60

70

80

V_{BAT_SYS}(mV)

Voltage

Figure 10. BATFET Gate Regulation V-I Curve

9V

VBUS

BATFET Control for System Power Reset

and Ship Mode

VSYS

3.6V

3.4V

Ship Mode (BATFET Disable)

VBAT

3.2V

3.18V

Ship mode is usually used when the system is stored or in

idle state for a long time or is in shipping. In such conditions, it

is better to completely disconnect battery and make system

voltage zero to minimize the leakage and extend the battery

life. To enter ship mode, the BATFET has to be forced off by

setting BATFET_DIS bit. The BATFET turns off immediately if

BATFET_DLY bit is 0, or turns off after a t_{SM_DLY}delay (12.3

seconds) if BATFET_DLY is set.

Current

4A

ICHG

3.2A

2.8A

ISYS

IIN

1.2A

1.0A

0.5A

-0.6A

DPM

Supplement

Figure 9. DPM Behavior Plot

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28

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Exit Ship Mode (BATFET Enable)

To exit the ship mode and enable the BATFET, one of the

following can be applied:

this function, a negative logic pulse with a minimum width of

t_{QON_RST}(10s TYP) must be applied to the nQON pin that

results in a temporary BATFET turn off for t_{BATFET_RST}(320ms

TYP) that automatically turns on afterward. Setting

BATFET_RST_EN to 0 can disable the function.

With the chip no powered by VBUS:

1. Connect the adaptor to the input with a valid voltage to the

VBUS input.

In summary, the nQON pin controls BATFET and system

reset in two different ways:

2. Pull nQON pin from logic high to low to enable BATFET, for

example, by shorting nQON to GND. The negative pulse

width should be at least a t_SHIPMODE(1s TYP) for deglitching.

1. Enable BATFET: Applying an nQON logic high to low

transition with longer than t_SHIPMODEdeglitch time (negative

pulse) turns on BATFET to exit ship mode (Figure 11 left). HIZ

is also enabled (EN_HIZ = 1) when exiting shipping mode.

After exiting shipping mode, the host can disable HIZ (EN_HIZ

= 0). OTG cannot be enabled (OTG_CONFIG = 1) until HIZ is

disabled.

With the chip already powered by VBUS:

3. Clear BATFET_DIS bit by using host and I²C.

4. Set REG_RST to 1 to reset all registers.

5. Apply a negative pulse to nQON pin (same as 2).

Full System Reset with BATFET Using nQON

When the input source is not present, the BATFET can act as

a load on/off switch between the system and battery. This

feature can be used to apply a power-on reset to the system.

Host can toggle BATFET_DIS bit to cycle power off/on and

reset the system. A push-button connected to nQON pin or a

negative pulse can also be used to manually force a system

power cycle when BATFET is ON (BATFET_DIS bit = 0). For

2. Reset BATFET: By applying a logic low for a duration of at

least t_{QON_RST}to nQON pin while VBUS is not powered and

BATFET is allowed to turn on (BATFET_DIS bit = 0), the

BATFET turns off for t_{BATFET_RST}and then it is re-enabled

resulting in a system power-on reset (Figure 11 right). This

function can be disabled by clearing BATFET_RST_EN bit.

A typical push button circuit for nQON is given in Figure 12.

Press Push Button

nQON

t_{QON_RST}

t_SHIPMODE

t_{BATFET_RST}

BATFET

Status

BATFET off due to I²C

or system overload

BATFET on

BATFET off

Reset BATFET

Turn on BATFET

When BATFET_DIS = 1 or SLEEPZ = 1

When BATFET_DIS = 0 and SLEEPZ = 0

Figure 11. nQON Enable and Reset BATFET Timing

SYS

BATFET (Q4)

Control

BAT

V_PULL-UP

nQON

Figure 12. nQON Manual Operation Circuit

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29

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Status Outputs Pins (nPG, STAT and nINT)

Power Good Indication (nPG Pin and PG_STAT Bit)

When a good input source is connected to VBUS and input

type is detected, the PG_STAT status bit goes high and the

nPG pin goes low. A good input source is detected if all

following conditions on V_VBUSare satisfied and input type

detection is completed:

4. Input source voltage entered the "input good" range:

a) V_VBUSexceeded V_BAT(not in sleep mode).

b) V_VBUScame below V_{VAC_OV}

.

c) V_VBUSremained above V_VBUSMIN(3.8V TYP) when

I_{BAD_SRC}(30mA TYP) load current is applied.

5. Input removed or out of the "input good" range.

6. A DPM event (VINDPM or IINDPM) occurred (a maskable

interrupt).

• V_VBUSis in the operating range: V_{VAC_UVLOZ}< V_VBUS< V_{VAC_OV}

.

• Device is not in sleep mode: V_VBUS> V_BAT+ V_SLEEP

.

Once a fault/flag happens, the INT pulse is asserted

immediately and the fault/flag bits are updated in REG0x09

and REG0x0E. Fault/flag status is not reset in the register

until the host reads it. A new fault/flag will not assert a new

INT pulse until the host reads REG0x09 and REG0x0E and

all the previous faults/flags are cleared. Therefore, in order to

read the current time faults, the host must read REG0x09 two

times consecutively. The first read returns the history of the

fault register status (from the time of the last read or reset)

and the second one checks the current active faults. As an

exception, the NTC_FAULT bit reports the actual real-time

status of TS pin.

• Input source is not poor: V_VBUS> V_VBUSMIN(3.8V TYP) when

I_{BAD_SRC}(30mA TYP) loading is applied. (Poor source

detection.)

• Completed input source type detection.

Charge Status (STAT Pin)

Charging state is indicated with the open-drain STAT pin as

explained in Table 6. This pin is able to drive an LED (see

Figure 1 or Figure 2). The functionality of the STAT pin is

disabled if the EN_ICHG_MON[1:0] bits are set to 11.

Table 6. STAT Pin Function

Charging State

Charging battery (or recharge)

Charging completed

STAT Indicator

Low (LED ON)

High (LED OFF)

Current Pulse Control Protocol

The device provides the control to generate the VBUS current

pulse protocol to communicate with adjustable high voltage

adaptor, in order to signal adaptor to increase/decrease

output voltage. To enable the interface, the EN_PUMPX bit

must be set. Then the host can select the increase/decrease

voltage pulse by setting either the PUMPX_UP or

PUMPX_DN bit to start the VBUS current pulse sequence.

During the current pulse sequence, the PUMPX_UP and

PUMPX_DN bits are set to indicate pulse sequence is in

progress and the device pulses the input current limit

between current limit set forth by IINDPM[4:0] register and the

100mA current limit. When the pulse sequence is completed,

the input current limit is returned to value set by IINDPM[4:0]

register and the PUMPX_UP or PUMPX_DN bit is cleared. In

addition, the EN_PUMPX can be cleared during the current

pulse sequence to terminate the sequence and force charger

to return to input current limit as set forth by the IINDPM[4:0]

register immediately. When EN_PUMPX bit is low, writing to

PUMPX_UP and PUMPX_DN bits would be ignored and

have no effect on VBUS current limit.

Charging is disabled or in sleep mode

Charge is suspended due to input over-voltage,

TS fault, timer faults or system over-voltage or

Boost mode is suspended (TS fault).

1Hz Blinking

EN_ICHG_MON[1:0] = 01, controlled by register

only, no matter with charging state.

STAT_SET[1:0]

nINT Interrupt Output Pin

When a new update occurs in the charger states, a 256μs

negative pulse is sent through the nINT pin to interrupt the

host. The host may not continuously monitor the charger

device and by receiving the interrupt, it can react and check

the charger situation on time.

The following events can generate an interrupt pulse:

1. Faults reflected in REG0x09 register (watchdog, Boost

overload, charge faults and battery over-voltage).

2. Charging completed.

3. PSEL or D+/D- detection identified a connected source

(USB or adaptor).

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SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

SGM41516/SGM41516D Protection Features

Monitoring of Voltage and Current

During the converter operation, the input and system voltages

(VBUS and VSYS) and switch currents are constantly

monitored to assure safe operation of the device in both Buck

and Boost modes, as will be explained below.

circuit on VBUS pin, the Q1 turns off and retries 7 times

(Hiccup). If short is not removed after retries, the OTG will be

disabled by clearing OTG_CONFIG bit. Also, an INT pulse is

sent and the BOOST_FAULT bit is set to 1 in REG0x09.

When the host activates the Boost mode again, the

BOOST_FAULT bit will be cleared.

3. Output Over-Voltage Protection for VBUS

In Boost mode, converter stops switching and exits Boost

mode (by clearing OTG_CONFIG bit) if VBUS voltage rises

above regulation and exceeds the V_{OTG_OVP}over-voltage limit

(6V TYP). An INT pulse is sent and the BOOST_FAULT bit is

set to 1.

Buck Mode Voltage and Current Monitoring

1. Input Over-Voltage (ACOV)

Converter switching will stop as soon as VBUS voltage

exceeds V_{VAC_OV}over-voltage limit that is programmable by

OVP[1:0] in REG0x06. It is selectable among 5.5V, 6.5V

(default), 10.5V and 14V for USB or 5V, 9V or 12V adaptors

respectively.

SGM41516/SGM41516D Thermal Regulation and

Shutdown

Buck Mode Thermal Protections

Each time VBUS exceeds the OVP limit, an INT pulse is

asserted. As long as the over-voltage persists, the

CHRG_FAULT[1:0] bits are set to 01 in REG0x09. Fault will

be cleared to 00 if the voltage comes back below limit (and a

hysteresis threshold) and host reads the fault register.

Charger resumes its normal operation when the voltage

comes back below OVP limit.

Internal junction temperature (T_J) is always monitored to

avoid overheating. A limit of +120 ℃ is considered for

maximum IC surface temperature in Buck mode and if T_J

intends to exceed this level, the device reduces the charge

current to keep maximum temperature limited to +120℃

(thermal regulation mode) and sets the THERM_STAT bit to 1.

As expected, the actual charging current is usually lower than

programmed value during thermal regulation. Therefore, the

safety timer runs at half clock rate and charge termination is

disabled during thermal regulation.

2. System Over-Voltage (SYSOVP)

During a system load transient, the device clamps the system

voltage to protect the system components from over-voltage.

The SYSOVP over-voltage limit threshold is 350mV + V_BAT, or

350mV + V_{SYS_MIN}when in SYSMIN condition (programmed

minimum system regulation voltage + 350mV). Once a

SYSOVP occurs, switching stops to clamp any overshoot and

a 30mA sink current is applied to SYS to pull the voltage

down.

If the junction temperature exceeds T_SHUT(+150℃), thermal

shutdown protection arise in which the converter is turned off,

CHRG_FAULT[1:0] bits are set to 10 in the fault register and

an INT pulse is sent.

When the device recovers and T_Jfalls below the hysteresis

band of T_{SHUT_HYS}(30℃ under T_SHUT), the converter resumes

automatically.

Boost Mode Voltage and Current Monitoring

In Boost mode, the RBFET (reverse blocking) and LSFET

(low-side switch) FET currents and VBUS voltage are

monitored for protection.

Boost Mode Thermal Protections

1. Soft-Start on VBUS

Similar to Buck mode, T_Jis monitored in Boost mode for

thermal shutdown protection. If junction temperature exceeds

T_SHUT(+150 ℃ ), the Boost mode will be disabled

(OTG_CONFIG bit clears). If T_Jfalls below the hysteresis band

of T_{SHUT_HYS}(30℃ under T_SHUT), Boost can recover again by

re-enabling OTG_CONFIG bit by host.

Boost mode begins with a soft-start to prevent large inrush

currents when it is enabled.

2. Output Short Protection for VBUS

Short circuit protection is provided for VBUS output in Boost

mode. To accept different types of load connected to VBUS

and OTG adaptation, an accurate constant current regulation

control is implemented for Boost mode. In case of a short

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SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Battery Protections

Battery Over-Voltage Protection (BATOVP)

I²C Data Communication

START and STOP Conditions

The over-voltage limit for the battery is 4% above the battery

regulation voltage setting. In case of a BATOVP, charging or

external direct charging stops right away, the BAT_FAULT bit

is set to 1 and an INT pulse is sent.

A transaction is started by taking control of the bus by master

if the bus is free. The transaction is terminated by releasing

the bus when the data transfer job is done as shown in Figure

13. All transactions are started by the master which applies a

START condition on the bus lines to take over the bus and

exchange data. At the end, the master terminates the

transaction by applying one (or more) STOP condition.

START condition is when SCL is high and a high to low

transition on the SDA is generated by master. Similarly, a

STOP is defined when SCL is high and SDA goes from low to

high. START and STOP are always generated by a master.

After a START and before a STOP the bus is considered

busy.

Battery Over-Discharge Protection

If battery discharges too much and V_BATfalls below the

depletion level (V_{BAT_DPL_FALL}), the device turns off BATFET to

protect battery. This protection is latched and is not recovered

until an input source is connected to the VBUS pin. In such

condition, the battery will start charging with the small I_SHORT

current (90mA TYP) first as long as V_BAT< V_SHORTZ. When

battery voltage is increased and V_SHORTZ< V_BAT< V_BATLOW

,

the charge current will increase to the pre-charge current

level programmed in the IPRECHG[3:0] register.

SDA

SCL

Battery Over-Current Protection for System

The BATFET will latch off, if its current limit is exceeded due to

a short or large overload on the system (I_BAT> I_{BATFET_OCP}). To

reset this latch off and enable BATFET, the "Exit Ship Mode"

procedure must be followed.

S

P

START

STOP

Figure 13. I²C Bus in START and STOP Conditions

I²C Serial Interface and Data Communication

Standard I²C interface is used to program SGM41516/

SGM41516D parameters and get status reports. I²C is well

known 2-wire serial communication interface that can connect

one (or more) master device(s) to some slave devices for

two-way communication. The bus lines are named serial data

(SDA) and serial clock (SCL). The device that initiates a data

transfer is a master. A master generates the SCL signal.

Slave devices have unique addresses to identify. A master is

typically a micro controller or a digital signal processor.

Data Bit Transmission and Validity

The data bit (high or low) must remain stable on the SDA line

during the HIGH period of the clock. The state of the SDA can

only change when the clock (SCL) is LOW. For each data bit

transmission, one clock pulse is generated by master. Bit

transfer in I²C is shown in Figure 14.

SDA

The SGM41516/SGM41516D operate as a slave device that

address is 0x6B (6BH). It has sixteen 8-bit registers,

numbered from REG0x00 to REG0x0F. A register read

beyond REG0x0F returns 0xFF.

SCL

Data Line Stable Change of Data

and Data Valid

Allowed

Figure 14. I²C Bus Bit Transfer

Physical Layer

The standard I²C interface of SGM41516/SGM41516D

supports standard mode and fast mode communication

speeds. The frequency of standard mode is up to 100kbits/s,

while the fast mode is up to 400kbits/s. Bus lines are pulled

high by weak current source or pull-up resistors and in logic

high state with no clocking when the bus is free. The SDA and

SCL pins are open-drain.

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SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Byte Format

Data is transmitted in 8-bit packets (one byte at a time). The

number of bytes in one transaction is not limited. In each

packet, the 8 bits are sent successively with the Most

Significant Bit (MSB) first. An acknowledge (or not-acknowledge)

bit must come after the 8 data bits. This bit informs the

transmitter whether the receiver is ready to proceed for the

next byte or not. Figure 15 shows the byte transfer process

with I²C interface.

Data Direction Bit and Addressing Slaves

The first byte sent by master after the START is always the

target slave address (7 bits) and an eighth data-direction bit

(R/W). R/W bit is 0 for a WRITE transaction and 1 for READ

(when master is asking for data). Data direction is the same

for all next bytes of the transaction. To reverse it, a new

START or repeated START condition must be sent by master

(STOP will end the transaction). Usually the second byte is a

WRITE sending the register address that is supposed to be

accesses in the next byte(s). The data transfer transaction is

shown in Figure 16.

Acknowledge (ACK) and Not Acknowledge (NCK)

After transmission of each byte by transmitter, an

acknowledge bit is replied by the receiver as ninth bit. With

the acknowledge bit, the receiver informs the transmitter that

the byte is received, and another byte is expected or can be

sent (ACK) or it is not expected (NCK = not ACK). Clock (SCL)

is always generated by the master, including the

acknowledge clock pulse, no matter who is acting as

transmitter or receiver. SDA line is released for receiver

control during the acknowledge clock pulse. And the receiver

can pull the SDA line low as ACK (reply a 0 bit) or let it be

high as NCK during the SCL high pulse. After that, the master

can either STOP (P) to end the transaction or send a new

START (S) condition to start a new transfer (called repeated

start). For example, when master wants to read a register in

slave, one start is needed to send the slave address and

register address, and then, without a stop condition, another

start is sent by master to initiate the receiving transaction

from slave. Master then sends the STOP condition and

releases the bus.

WRITE: If the master wants to write in the register, the third

byte can be written directly as shown in Figure 17 for a single

write data transfer. After receiving the ACK, master may issue

a STOP condition to end the transaction or send the next

register data, which will be written to the next address in a

slave as multi-write. A STOP is needed after sending the last

data.

READ: If the master wants to read a single register (Figure

18), it sends a new START condition along with device

address with R/W bit = 1. After ACK is received, master reads

the SDA line to receive the content of the register. Master

replies with NCK to inform slave that no more data is needed

(single read) or it can send an ACK to request for sending the

next register content (multi-read). This can continue until an

NCK is sent by master. A STOP must be sent by master in

any case to end the transaction.

1

9

1

9

SCL

SDA

MSB

Acknowledgement

signal from receiver

Acknowledgement

signal from receiver

S/Sr

P/Sr

START

or Repeated

START

ACK

STOP

or Repeated

START

Figure 15. Byte Transfer Process

1

9

1

9

1

9

SCL

SDA

R/W

P

S

I²C Slave Address

Data Byte

ACK

START

STOP

Figure 16. Data Transfer Transaction

SG Micro Corp

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33

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Frame 1

Frame 2

1

9

1

9

SCL

SDA

1

0

1

0

1

B7

B6

B5

B4

B3

B2

B1

B0

W

Byte#1 I²C Slave Address Byte

ACK by

Device

Byte#2 Register Address Byte

ACK by

Device

START by

Master

Frame 3

1

9

SCL

(Continued)

SDA

(Continued)

D7

D6

D5

D4

D3

D2

D1

D0

Byte#3 Data Byte 1 to

SGM41516/SGM41516D Register

ACK by

Device

STOP by

Master

Figure 17. A Single Write Transaction

Frame 1

Frame 2

1

9

1

9

SCL

1

0

1

0

1

B7

B6

B5

B4

B3

B2

B1

B0

W

SDA

Byte#1 I²C Slave Address Byte

ACK by

Device

START by

Master

Byte#2 Register Address Byte

ACK by

Device

Frame 3

Frame 4

1

0

9

1

9

SCL

(Continued)

SDA

(Continued)

1

0

1

D7

D6

D5

D4

D3

D2

D1

D0

R

START by

Master

Byte#3 I²C Slave Address Byte

Byte#4 Data Byte from Device

NCK by

Master

STOP by

Master

ACK by

Device

Figure 18. A Single Read Transaction

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SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Data Transactions with Multi-Read or Multi-Write

Multi-read and multi-write are supported by SGM41516/

SGM41516D, as explained in Figure 19 and Figure 20. In the

multi-write, every new data byte sent by master is written to

the next register of the device. A STOP is sent whenever

master is done with writing into device registers.

In a multi-read transaction, after receiving the first register

data (its address is already written to the slave), the master

replies with an ACK to ask the slave for sending the next

register data. This can continue as much as it is needed by

master. Master sends back an NCK after the last received

byte and issues a STOP condition.

Frame 1

Frame 2

1

9

1

9

SCL

SDA

B7

B6

B5

B4

B3

B2

B1

B0

1

0

1

0

1

W

Byte#1 I²C Slave Address Byte

Byte#2 Register Address Byte

ACK by

Device

START by

Master

ACK by

Device

Frame 3

Frame 4

1

9

1

9

SCL

(Continued)

SDA

(Continued)

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

Byte#3 Data Byte 1 to

SGM41516/SGM41516D Register

ACK by

Device

Byte#4 Data Byte 2 to

SGM41516/SGM41516D Register

ACK by

Device

Frame N

1

9

SCL

(Continued)

SDA

(Continued)

D7

D6

D5

D4

D3

D2

D1

D0

Byte#N Data Byte n to

SGM41516/SGM41516D Register

ACK by

Device

STOP by

Master

Figure 19. A Multi-Write Transaction

SG Micro Corp

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SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Frame 1

Frame 2

1

9

1

9

SCL

SDA

1

0

1

0

1

B7

B6

B5

B4

B3

B2

B1

B0

W

Byte#1 I²C Slave Address Byte

ACK by

Device

START by

Master

Byte#2 Register Address Byte

ACK by

Device

Frame 3

Frame 4

1

9

1

9

SCL

(Continued)

SDA

(Continued)

1

0

1

0

1

D7

D6

D5

D4

D3

D2

D1

D0

R

Byte#3 I²C Slave Address Byte

Byte#4 Data Byte 1 from Device

ACK by

Master

START by

Master

ACK by

Device

Frame 5

Frame N

1

9

1

9

SCL

(Continued)

SDA

(Continued)

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D3

D2

D1

D0

D4

Byte#5 Data Byte 2 from Device

ACK by

Master

Byte#N Data Byte n from Device

NCK by

Master

STOP by

Master

Figure 20. A Multi-Read Transaction

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

36

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

REGISTER MAPS

All registers are 8-bit and individual bits are named from D[0] (LSB) to D[7] (MSB).

I²C Register Address Map

FUNCTION

STAT

FLAG

MASK

THRESHOLD SETTING

ENABLE

0x08[4:3]

0x09[5:4]

CHARGE

─

0x01[4]

VREG

VREG_FT

ICHG

0x0A[4]

─

0x04[7:3]

0x0F[7:6]

0x02[5:0]

0x03[7:4]

0x03[3:0]

0x04[0]

0x05[2]

0x04[2:1]

─

0x0F[7:6]

─

IPRECHG

ITERM

─

0x05[7]

─

VRECHG

CHG_TIMER

TOPOFF_TIMER

TMR2X

0x09[5:4]

0x0A[3]

─

0x05[3]

0x04[2:1]

0x07[6]

0x06[3:0]

0x0F[1:0]

VINDPM

0x0A[6]

─

0x0A[1]

─

VDPM_BAT_TRACK

IINDPM

─

0x0A[5]

─

0x0A[0]

─

0x07[1:0]

0x00[4:0]

0x02[6]

0x07[1:0]

─

Q1_FULLON

0x08[7:5]

0x0A[7]

VBUS

─

PG

IINDET

0x08[2]

─

0x07[7]

─

INPUT_DET_DONE

EN_ICHG_MON

STAT_SET

SYS_MIN

0x0E[7] (SGM41516)

─

0x00[6:5]

─

0x0F[3:2]

0x01[3:1]

─

0x08[0]

HIZ MODE

WATCHDOG

WD_RST

─

0x00[7]

0x05[5:4]

0x01[6]

0x01[5]

─

0x09[7]

0x05[5:4]

─

OTG

0x08[7:5]

0x06[5:4]

0x01[0]

0x02[7]

0x07[3]

─

MIN_BAT_SEL

BOOST_LIM

BATFET

─

0x07[5]

0x07[2]

0x01[7]

─

BATFET_RST

PFM

─

DCEN

0x0F[4]

ARDCEN_ITS

0x05[6]

0x0D[6]

0x0D[5]

PUMPX

─

0x0D[7]

DP_VSET

DM_VSET

─

0x0D[4:3]

0x0D[2:1]

─

JEITA

0x09[2:0]

0x0D[0]

JEITA_VT2

JEITA_VT3

JEITA_VSET_L

JEITA_VSET_H

JEITA_ISET_L

JEITA_ISET_H

TREG

─

0x0C[3:2]

0x0C[1:0]

0x0C[7]

0x07[4]

0x05[0]

0x0C[5:4]

0x05[1]

─

0x0C[6]

─

0x08[1]

0x09[5:4]

TSHUT

0x0A[2]

0x09[5:4]

BUS OVP

─

0x06[7:6]

─

BAT OVP

BOOST FAULT

REG_RST

0x09[3]

─

0x09[6]

─

0x0B[7]

─

ITERM TIMER

Part ID

0x05[6]

0x0B[3:0]

─

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

37

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

REGISTER MAPS (continued)

I²C Slave Address of SGM41516/SGM41516D: 0x6B

Bit Types:

R:

Read only

R/W:

n:

Read/Write

Parameter code formed by the bits as an unsigned binary number.

REG0x00: Input Current Limit Register [Reset = 0x17]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

Enable HIZ Mode

0 = Disable (default)

1 = Enable

In HIZ mode, the VBUS pin is effectively disconnected from internal

circuit. Some leakage current may exist.

REG_RST

or Watchdog

D[7]

EN_HIZ

0

R/W

Enable STAT Pin Function

00 = Enable following charging state (default)

01 = Enable following STAT_SET[1:0] bits

10 = Reserved

D[6:5] EN_ICHG_MON[1:0]

00

R/W

REG_RST

11 = Disable (float pin)

These bits turn on or off the function of the STAT open-drain output

pin (charge status or customer customized indicator).

Input Current Limit Value (n: 5 bits):

= 100 + 100n (mA)

IINDPM[4]

1 = 1600mA

IINDPM[3]

1 = 800mA

Offset: 100mA

Range: 100mA (00000) - 3.1A (11110),

3.8A (11111)

IINDPM[2]

1 = 400mA

D[4:0]

IINDPM[4:0]

10111

R/W

REG_RST

Default: 2400mA (10111), not typical

IINDPM[1]

1 = 200mA

IINDPM changes after an input source detection.

IINDPM[0]

1 = 100mA

Host can overwrite IINDPM after input source

detection is completed.

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

38

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

REGISTER MAPS (continued)

REG0x01: Charger Control 1 Register [Reset = 0x1A]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

Enable PFM Mode

0 = Enable (default)

1 = Disable

D[7]

PFM_DIS

0

R/W

REG_RST

Enable Pulse Frequency Modulation.

PFM is normally used to save power at light load by reducing

converter switching frequency.

I²C Watchdog Timer Reset

0 = Normal (default)

1 = Reset

Watchdog timer reset control bit. Write 1 to this bit to avoid watchdog

expiry. WD_RST resets to 0 after watchdog timer reset (expiry).

REG_RST

or Watchdog

D[6]

D[5]

D[4]

WD_RST

0

1

R/W

Enable OTG

0 = OTG disable (default)

1 = OTG enable

This bit has priority over charge enable in the CHG_CONFIG.

REG_RST

or Watchdog

OTG_CONFIG

CHG_CONFIG

Enable Battery Charging

0 = Charge disable

1 = Charge enable (default)

Charge is enabled when CHG_CONFIG bit is 1 and nCE pin is

pulled low.

REG_RST

or Watchdog

Minimum System Voltage

000 = 2.6V

001 = 2.8V

010 = 3V

011 = 3.2V

100 = 3.4V

101 = 3.5V (default)

110 = 3.6V

D[3:1]

SYS_MIN[2:0]

101

R/W

REG_RST

111 = 3.7V

Minimum System Voltage Value.

Offset: 2.6V

Range: 2.6V (000) - 3.7V (111)

Default: 3.5V (101)

Minimum Battery Voltage for OTG Mode

0 = 2.95V V_BATfalling (default)

1 = 2.6V V_BATfalling

D[0]

MIN_BAT_SEL

0

R/W

REG_RST

Default:

V

_BATfalling, V_{BATLOW_OTG}= 2.95V.

_BATrising, V_{BATLOW_OTG}= 3.15V.

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

39

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

REGISTER MAPS (continued)

REG0x02: Charge Current Limit Register [Reset = 0XA2]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

Boost Mode Current Limit

0 = 0.5A

1 = 1.2A (default)

The current limit options listed values are the minimum specs. Actual

value is typically higher.

REG_RST

or Watchdog

D[7]

BOOST_LIM

1

R/W

VBUS FET Switch (Q1)

0 = Use higher R_DSONif I_INDPM< 700mA (for better accuracy) (default)

1 = Use lower R_DSONalways (fully ON for better efficiency)

D[6]

Q1_FULLON

0

R/W

REG_RST

Used to control the on-resistance of Q1 (VBUS switch) for better

input current measurement accuracy.

Note that Q1 is off in Boost mode.

ICHG[5]

1 = 1920mA

ICHG[4]

1 = 960mA

Fast Charge Current Value (n: 6 bits):

= 60n (mA) (n ≤ 63)

ICHG[3]

Offset: 0mA

1 = 480mA

REG_RST

or Watchdog

D[5:0]

ICHG[5:0]

100010

R/W

Range: 0mA (000000) - 3780mA (111111)

ICHG[2]

Default: 2040mA (100010)

1 = 240mA

Notes:

ICHG[1]

Setting I_CHG= 0mA disables charge.

1 = 120mA

ICHG[0]

1 = 60mA

REG0x03: Pre-Charge and Termination Current Limit Register [Reset = 0x22]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

Pre-Charge Current Limit (n: 4 bits):

= 60 + 60n (mA) (n ≤ 12)

IPRECHG[3]

1 = 480mA

0

R/W

IPRECHG[2]

1 = 240mA

Offset: 60mA

Range: 60mA (0000) - 780mA (1100)

Default: 180mA (0010)

0

1

0

1

0

R/W

REG_RST

or Watchdog

D[7:4]

IPRECHG[3:0]

IPRECHG[1]

1 = 120mA

Note:

IPRECHG[0]

1 = 60mA

Values above 12D = 1100 (780mA) are clamped

to 12D = 1100 (780mA).

ITERM[3]

1 = 480mA

Termination Current Limit (n: 4 bits):

= 60 + 60n (mA)

ITERM[2]

1 = 240mA

REG_RST

or Watchdog

D[3:0]

ITERM[3:0]

Offset: 60mA

Range: 60mA (0000) - 960mA (1111)

Default: 180mA (0010)

ITERM[1]

1 = 120mA

ITERM[0]

1 = 60mA

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

40

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

REGISTER MAPS (continued)

REG0x04: Battery Voltage Limit Register [Reset = 0x58]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

VREG[4]

1 = 512mV

0

R/W

Charge Voltage Limit (n: 5 bits):

= 3856 + 32n (mV) if n ≤ 24, n≠15;

VREG[3]

1 = 256mV

= 4.352V

Offset: 3.856V

Range: 3.856V (00000) - 4.624V (11000)

Default: 4.208V (01011)

Special Value: 4.352V (01111)

if n = 15

1

0

1

R/W

VREG[2]

1 = 128mV

REG_RST

or Watchdog

D[7:3]

VREG[4:0]

VREG[1]

1 = 64mV

Note:

Values above 24D = 11000 (4.624V) are clamped

to 24D = 11000 (4.624V).

VREG[0]

1 = 32mV

Top-Off Timer

00 = Disabled (default)

01 = 15 minutes

10 = 30 minutes

11 = 45 minutes

REG_RST

or Watchdog

D[2:1] TOPOFF_TIMER[1:0]

00

R/W

The charge extension time added after the termination condition is

detected.

If disabled, charging terminates as soon as termination conditions

are met.

Battery Recharge Threshold

0 = 100mV below VREG[4:0] (default)

1 = 200mV below VREG[4:0]

A recharge cycle will start if a fully charged battery voltage drops below

VREG - VRECHG settings.

REG_RST

or Watchdog

D[0]

VRECHG

0

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

41

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

REGISTER MAPS (continued)

REG0x05: Charger Control 2 Register [Reset = 0x9F]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

Charging Termination Enable

0 = Disable

1 = Enable (default)

REG_RST

or Watchdog

D[7]

EN_TERM

1

R/W

DCEN Reset Enable or ITERM Timer Setting

0 = Allow resetting DCEN or set 200ms (default)

1 = Don′t allow resetting DCEN or set 16ms

When DCEN = 1 and IBUS over-current occurs, set this bit 0 or 1 to

allow resetting DCEN or not.

REG_RST

or Watchdog

D[6]

ARDCEN_ITS

0

R/W

When DCEN = 0, set this bit 0 or 1 to set ITERM detection timer to

200ms or 16ms.

Watchdog Timer Setting

00 = Disable watchdog timer

01 = 40s (default)

10 = 80s

11 = 160s

REG_RST

or Watchdog

D[5:4]

D[3]

WATCHDOG[1:0]

EN_TIMER

01

1

R/W

Expiry time of the watchdog timer if it is not reset.

Charge Safety Timer Enable

0 = Disable

1 = Enable (default)

When enabled the pre-charge and fast charge periods are included

in the timing.

REG_RST

or Watchdog

Charge Safety Timer Setting

0 = 7h

1 = 16h (default)

REG_RST

or Watchdog

D[2]

D[1]

CHG_TIMER

TREG

1

R/W

Thermal Regulation Threshold

0 = 80℃

1 = 120℃ (default)

For Buck mode.

REG_RST

or Watchdog

JEITA Charging Current

0 = 50% of I_CHG

1 = 20% of I_CHG(default)

When JEITA_ISET_L_EN = 1.

JEITA_ISET_L

(0℃ - 10℃)

REG_RST

or Watchdog

D[0]

1

R/W

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

42

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

REGISTER MAPS (continued)

REG0x06: Charger Control 3 Register [Reset = 0xE6]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

VAC Pin OVP Threshold

00 = 5.5V

01 = 6.5V (5V input)

10 = 10.5V (9V input)

D[7:6]

OVP[1:0]

11

R/W

REG_RST

11 = 14V (12V input) (default)

OVP threshold for input supply.

Boost Mode Voltage Regulation

00 = 4.85V

D[5:4]

BOOSTV[1:0]

10

R/W

01 = 5.00V

REG_RST

10 = 5.15V (default)

11 = 5.30V

VINDPM Threshold (n: 4 bits):

= Offset + 0.1n (V)

VINDPM[3]

1 = 800mV

Offset: 3.9V (VINDPM_OS = 00, default)

Range: 3.9V (0000) - 5.4V (1111)

Default: 4.5V (0110)

VINDPM[2]

1 = 400mV

D[3:0]

VINDPM[3:0]

0110

R/W

Offset: 5.9V (VINDPM_OS = 01)

Range: 5.9V (0000) - 7.4V (1111)

REG_RST

VINDPM[1]

1 =200mV

Offset: 7.5V (VINDPM_OS = 10)

Range: 7.5V (0000) - 9V (1111)

VINDPM[0]

1 =100mV

Offset: 10.5V (VINDPM_OS = 11)

Range: 10.5V (0000) - 12V (1111)

REG0x07: Charger Control 4 Register [Reset = 0x4C]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

Input Current Limit Detection

0 = Not in input current limit detection (default)

1 = Force input current limit detection when VBUS is present

Reloads with 0 when input detection is completed.

REG_RST

or Watchdog

D[7]

IINDET_EN

0

R/W

Enable Half Clock Rate Safety Timer

0 = Disable

1 = Safety timer slows down during DPM, JEITA cool, or thermal

regulation (default)

REG_RST

or Watchdog

D[6]

D[5]

TMR2X_EN

1

0

R/W

Slow down by a factor of 2.

Disable BATFET

0 = Allow BATFET (Q4) to turn on (default)

1 = Turn off BATFET (Q4) after a t_{SM_DLY}delay time (REG0x07 D[3])

BATFET_DIS

REG_RST

t

_{SM_DLY}is typically 12.3 seconds.

JEITA Charging Voltage

0 = Set charge voltage to the lower of 4.1V and V_REG(default)

1 = Set charge voltage to V_REG

JEITA_VSET_H

REG_RST

or Watchdog

D[4]

D[3]

D[2]

0

1

R/W

(45℃ - 60℃)

BATFET Turn Off Delay Control

0 = Turn off BATFET immediately

1 = Turn off BATFET after t_{SM_DLY}(default)

BATFET_DIS bit is set.

BATFET_DLY

REG_RST

Enable BATFET Reset

0 = Disable BATFET reset

1 = Enable BATFET reset (default)

REG_RST

or Watchdog

BATFET_RST_EN

Dynamic VINDPM Tracking

00 = Disable (V_INDPMset by register)

01 = V_BAT+ 200mV

10 = V_BAT+ 250mV

VDPM_BAT_

TRACK[1:0]

D[1:0]

00

R/W

REG_RST

11 = V_BAT+ 300mV

Set V_INDPMto track V_BATvoltage. Actual V_INDPMis the larger of

VINDPM[3:0] and this register value.

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

43

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

REGISTER MAPS (continued)

REG0x08: Charger Status 1 Register [Reset = 0xXX]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

VBUS Status Register (SGM41516D)

000 = No input

001 = USB host SDP

010 = USB CDP (1.5A)

011 = USB DCP (2.4A)

101 = Unknown adaptor (500mA)

110 = Non-standard adaptor (1A/2A/2.1A/2.4A)

111 = OTG

D[7:5]

VBUS_STAT[2:0]

xxx

R

N/A

VBUS Status Register (SGM41516)

000 = No input

001 = USB host SDP (500mA) → PSEL HIGH

010 = Adaptor 2.4A → PSEL LOW

111 = OTG

Other values are reserved.

Current limit value is reported in IINDPM[4:0] register.

Charging Status

00 = Charge disable

D[4:3]

CHRG_STAT[1:0]

xx

R

01 = Pre-charge (V_BAT< V_BATLOW

)

N/A

10 = Fast charging (constant current or voltage)

11 = Charging terminated

Input Power Status (VBUS in good voltage range and not poor)

0 = Input power source is not good

1 = Input power source is good

D[2]

D[1]

D[0]

PG_STAT

THERM_STAT

VSYS_STAT

x

R

N/A

Thermal Regulation Status

0 = Not in thermal regulation

1 = In thermal regulation

System Voltage Regulation Status

0 = Not in VSYSMIN regulation (V_BAT> V_{SYS_MIN}

)

1 = In VSYSMIN regulation (V_BAT< V_{SYS_MIN}

)

REG0x09: Fault Status Register [Reset = 0xXX]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

Watchdog Fault Status

0 = Normal (no fault)

1 = Watchdog timer expired

D[7] WATCHDOG_FAULT

x

R

N/A

Boost Mode Fault Status

0 = Normal

1 = VBUS is overloaded in OTG, or VBUS OVP, or battery voltage

too low (any condition that prevents Boost starting)

D[6]

BOOST_FAULT

x

R

Charging Fault Status

00 = Normal

D[5:4] CHRG_FAULT[1:0]

xx

x

R

01 = Input fault (VAC OVP or V_BAT< V_VBUS< 3.8V)

10 = Thermal shutdown

11 = Charge safety timer expired

N/A

Battery Fault Status

0 = Normal

D[3]

BAT_FAULT

1 = Battery over-voltage (BATOVP)

JEITA Condition Based on Battery NTC Temperature Measurement

000 = Normal

010 = Warm

011 = Cool (Buck mode only)

101 = Cold

D[2:0]

NTC_FAULT[2:0]

xxx

R

N/A

110 = Hot

NTC fault bits are updated in real time and does not need a read to

reset.

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

44

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

REGISTER MAPS (continued)

REG0x0A: Charger Status 2 Register [Reset = 0xXX]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

N/A

Good Input Source Detected

0 = A good VBUS is not attached

1 = A good VBUS attached

D[7]

VBUS_GD

x

R

Input Voltage Regulation (Dynamic Power Management)

0 = Not in VINDPM

1 = In VINDPM

D[6]

D[5]

D[4]

D[3]

D[2]

VINDPM_STAT

IINDPM_STAT

CV_STAT

x

0

R

N/A

Input Current Regulation (Dynamic Power Management)

0 = Not in IINDPM

1 = In IINDPM

N/A

CV Mode Status Indicator when DCEN = 1

0 = VBAT is lower than VREG

1 = VBAT approaches to VREG

R

N/A

Active Top-Off Timer Counting Status

0 = Top-off timer not counting

1 = Top-off timer counting

TOPOFF_ACTIVE

ACOV_STAT

R

N/A

Input Over-Voltage Status (AC adaptor is the input source)

0 = No over-voltage (no ACOV)

1 = Over-voltage detected (ACOV)

R

N/A

VINDPM Event Detection Interrupt Mask

0 = Allow VINDPM INT pulse (default)

1 = Mask VINDPM INT pulse

D[1] VINDPM_INT_MASK

R/W

REG_RST

IINDPM Event Detection Mask

0 = Allow IINDPM to send INT pulse (default)

1 = Mask IINDPM INT pulse

D[0]

IINDPM_INT_MASK

REG0x0B: Part Information Register [Reset = 0x6X]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

Register Reset

0 = No effect (keep current register settings) (default)

1 = Reset R/W bits of all registers to the default and reset safety

timer (It also resets itself to 0 after register reset is completed.)

D[7]

REG_RST

0

R/W

REG_RST

1

Part ID

1100 = SGM41516

1101 = SGM41516D

D[6:3]

PN[3:0]

R

N/A

0

x

D[2]

SGMPART

1

R

N/A

D[1:0]

DEV_REV[1:0]

xx

Revision

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

45

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

REGISTER MAPS (continued)

REG0x0C: Charger Control 5 Register [Reset = 0x75]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

JEITA Charging Voltage

0 = Set charge voltage to V_REG(default)

1 = Set charge voltage to the lower of 4.1V and V_REG

JEITA_VSET_L

(0℃ - 10℃)

REG_RST

or Watchdog

D[7]

0

R/W

Charge Enable during Cool Temperature

0 = Disable

1 = Enable (default)

JEITA_ISET_L_EN

REG_RST

or Watchdog

D[6]

1

R/W

(0℃ - 10℃)

Charge Current Setting during Warm Temperature

00 = 0% of I_CHG

01 = 20% of I_CHG

10 = 50% of I_CHG

11 = 100% of I_CHG(default)

JEITA_ISET_H[1:0]

REG_RST

or Watchdog

D[5:4]

11

(45℃ - 60℃)

In warm condition, the safety timer does not become 2X.

JEITA Cool Threshold Setting

00 = V_T2= 70.75% (5.5℃)

01 = V_T2= 68.25% (10℃) (default)

10 = V_T2= 65.25% (15℃)

REG_RST

or Watchdog

D[3:2]

D[1:0]

JEITA_VT2[1:0]

JEITA_VT3[1:0]

01

R/W

11 = V_T2= 62.25% (20℃)

JEITA Warm Threshold Setting

00 = V_T3= 48.25% (40℃)

01 = V_T3= 44.75% (45℃) (default)

10 = V_T3= 40.75% (50.5℃)

11 = V_T3= 37.75% (54.5℃)

REG_RST

or Watchdog

REG0x0D: Charger Control 6 Register [Reset = 0x01]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

Current Pulse Control Enable

0 = Disable (default)

1 = Enable (PUMPX_UP and PUMPX_DN)

REG_RST

or Watchdog

D[7]

0

R/W

EN_PUMPX

Current Pulse Control Voltage up Enable

0 = Disable (default)

1 = Enable

This bit is can only be set when EN_PUMPX bit is set and returns to

0 after current pulse control sequence is completed.

REG_RST

or Watchdog

D[6]

D[5]

0

R/W

PUMPX_UP

PUMPX_DN

Current Pulse Control Voltage down Enable

0 = Disable (default)

1 = Enable

This bit is can only be set when EN_PUMPX bit is set and returns to

0 after current pulse control sequence is completed.

REG_RST

or Watchdog

D+ Output Voltage Setting

00 = HIZ (default)

01 = 0V

10 = 0.6V

11 = 3.3V

REG_RST

or Watchdog

D[4:3]

00

R/W

DP_VSET[1:0]

Register bits are reset to default value when input source is

plugged-in and can be changed after D+/D- detection is completed.

D- Output Voltage Setting

00 = HIZ (default)

01 = 0V

10 = 0.6V

11 = 3.3V

REG_RST

or Watchdog

D[2:1]

D[0]

00

1

R/W

DM_VSET[1:0]

JEITA_EN

Register bits are reset to default value when input source is

plugged-in and can be changed after D+/D- detection is completed.

JEITA Enable

0 = Disable

1 = Enable (default)

REG_RST

or Watchdog

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

46

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

REGISTER MAPS (continued)

REG0x0E: Charger Flag Register [Reset = 0xXX]

BITS

BIT NAME

INPUT_DET_DONE

Reserved

DEFAULT

TYPE

DESCRIPTION

RESET BY

VBUS Input Detection Done Flag

0 = Normal

1 = Detection done

D[7]

x

R

NA

PSEL or DPDM detection done flag after VBUS plug in or set

FORCE_DPDM = 1.

D[6:0]

xxxxxxx

Reserved

NA

REG0x0F: Charger Control 7 Register [Reset = 0x00]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

VREG Fine Tuning

00 = Disable (default)

01 = V_REG+ 8mV

10 = V_REG- 8mV

REG_RST

or Watchdog

D[7:6]

00

R/W

VREG_FT

11 = V_REG- 16mV

REG_RST

or Watchdog

D[5]

D[4]

0

R/W

Reserved

DCEN

DCEN Pin Output Control

0 = Low (default)

1 = High

REG_RST

or Watchdog

When BATOVP time reaches t_{BATOVP_DCEN}, the bit resets to default.

STAT Pin Output Setting

00 = LED off (HIZ) (default)

01 = LED on (low)

REG_RST

or Watchdog

D[3:2]

D[1:0]

00

R/W

STAT_SET[1:0]

10 = LED blinking 1s on 1s off

11 = LED blinking 1s on 3s off

This bits only takes effect when EN_ICHG_MON[1:0] = 01.

VINDPM Offset

00 = 3.9V (default)

01 = 5.9V

REG_RST

VINDPM_OS[1:0]

10 = 7.5V

11 = 10.5V

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

47

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

APPLICATION INFORMATION

The SGM41516/SGM41516D are typically used as a charger

with power path management in smart phones, tablets and

other portable devices. In the design, it comes along with a

host controller (a processor with I²C interface) and a

single-cell Li-Ion or Li-polymer battery.

the converter does not operate at D ≈ 50%, the worst case

capacitor RMS current can be estimated from (5) in which D

is the closest operating duty cycle to 0.5.

I_CIN= I_CHG× D× 1−D

(

)

(5)

For SGM41516/SGM41516D, place C_INacross PMID and

GND pins close to the chip. Voltage rating of the capacitor

must be at least 25% higher than the normal input voltage to

minimize voltage derating. A rating of 25V or higher is

preferred for a 15V input voltage. For a 13.5V input voltage,

the preferred rating is 25V or higher.

Detailed Design Procedure

Inductor Design

Small energy storage elements (inductor and capacitor) can

be used due to the high frequency (1.5MHz) switching

converter used in the SGM41516/SGM41516D. Inductor

should tolerate currents higher than the maximum charge

current (I_CHG) plus half the inductor peak to peak ripple

current (∆I) without saturation:

A C_IN= 22μF is suggested.

Output Capacitor Design

The output capacitance (on the system) must have enough

RMS (ripple) current rating to carry the inductor switching

ripple and provide enough energy for system transient current

demands. I_COUT(C_OUTRMS current) can be calculated by:

∆I

2

(3)

I_SAT> I_CHG

+

The inductor ripple current is determined by the input voltage

(V_VBUS), duty cycle (D = V_BAT/V_VBUS), switching frequency (f_S=

1.5MHz) and the inductance (L). In CCM:

I_RIPPLE

I_COUT

=

≈ 0.29×I_RIPPLE

V_VBUS×D× 1−D

(

)

2× 3

(4)

(6)

(7)

∆I =

f_S×L

And the output voltage ripple can be calculated by:

Inductor ripple current is maximum when D ≈ 0.5. If the input

voltage range (V_VBUS) is limited higher, D values can be

considered.



₂









V_OUT

∆V_O=

1−

8LC_OUTf_S

V_VBUS

Increasing L or C_OUT(the LC filter) can reduce the ripple.

In the practical designs, inductor peak to peak current ripple

is selected in a range from 20% to 40% of the maximum DC

current ∆I = (0.2 ~ 0.4) × I_CHGfor a good trade-off between

inductor size and efficiency. Selecting higher ripple allows

choosing of smaller inductance.

The internal loop compensation of the device is optimized for >

22μF ceramic output capacitor. 10V, X7R (or X5R) ceramic

capacitors are recommended for the output.

Input Power Supply Considerations

For each application, V_VBUSand I_CHGare known, so L can be

calculated from (4) and current rating of the inductor can be

selected from (3). Choose an inductor that has small DCR

and core losses at 1.5MHz to have high efficiency and cool

operation at full load.

To power the system from the SGM41516/SGM41516D,

either an input power source with a voltage range from 3.9V

to 13.5V and at least 100mA current rating should power

VBUS, or a single-cell Li-Ion battery with voltage higher than

V_{BAT_UVLOZ}should be connected to BAT pin of the device. The

input source must have enough current rating to allow

maximum power delivery through charger (Buck converter) to

the system.

Input Capacitor Design

Select low ESR ceramic input capacitor (X7R or X5R) with

sufficient voltage and RMS ripple current rating for decoupling

of the input switching ripple current (I_CIN). The RMS ripple

current in the worst case is around the I_CHG/2 when D ≈ 0.5. If

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

48

SGM41516

SGM41516D

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

APPLICATION INFORMATION (continued)

It is better to avoid using vias for these connections and keep

Layout Guidelines

the high frequency current paths short enough and on the

same layer. A GND copper layer under the component layer

helps to reduce noise emissions. Pay attention to the DC

current and AC current paths in the layout and keep them

short and decoupled as much as possible.

The switching node (SW) creates very high frequency noises,

which are several times higher than f_SW(1.5MHz) due to

sharp rise and fall of the voltage and current in the switches.

To reduce the ringing issues and noise generation, it is

important to design a proper layout for minimizing the current

path impedance and loop area. A graphical guideline for the

current loops and their frequency content is provided in

Figure 21. The following considerations can help to make a

better layout.

4. For analog signals, it is better to use a separate analog

ground (AGND) branched only at one point from GND pin. To

avoid high current flow through the AGND path, it should be

connected to GND only at one point (preferably the GND pin).

1. Place the input capacitor between PMID and GND pins as

close as possible to the chip with the shortest copper

connections (avoid vias). Choose the smallest capacitor size.

5. Place decoupling capacitors close to the IC pins with the

shortest copper connections.

6. Solder the exposed thermal pad of the package to the PCB

ground planes. Ensure that there are enough thermal vias

directly under the IC, connecting to the ground plane on the

other layers for better heat dissipation and cooling of the

device.

2. Connect one pin of the inductor as close as possible to the

SW pin of the device and minimize the copper area

connected to the SW node to reduce capacitive coupling from

SW area to nearby signal traces. This decreases the noise

induced through parasitic stray capacitances and

displacement currents to other conductors. SW connection

should be wide enough to carry the charging current. Keep

other signals and traces away from SW if possible.

7. Select proper sizes for the vias and ensure enough copper

is available to carry the current for the given current path.

Vias usually have some considerable parasitic inductance

and resistance.

3. Place output capacitor GND pin as close as possible to the

GND pin of the device and the GND pin of input capacitor C_IN.

DC Current

DC Current Path

(I_AC≈ 0)

SYS

SW

(Boost Mode

Direction)

Switching Frequency

and Its Low Order

Very High

Frequency

(Current Path)

SYS

Harmonics

(Current Path)

Load

Transient

Current Path

C_IN

C_OUT

Figure 21. The Paths and Loops Carrying High Frequency, DC Currents and Very High Frequency

(for Layout Design Consideration)

REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (DECEMBER 2022) to REV.A

Page

Changed from product preview to production data.............................................................................................................................................All

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

49

PACKAGE INFORMATION

PACKAGE OUTLINE DIMENSIONS

WLCSP-2.0×2.4-30B

D

0.22

0.20

0.4

30 × Φ

A1 CORNER

E

0.4

TOP VIEW

RECOMMENDED LAND PATTERN (Unit: mm)

30 × Φd

5

4

3

2

1

A

B

C

D

E

F

A

e

A1

e

SIDE VIEW

BOTTOM VIEW

Dimensions In Millimeters

Symbol

MIN

MOD

0.575

MAX

0.625

0.220

2.030

2.430

0.290

A

A1

D

E

0.525

0.180

1.970

2.370

0.230

0.200

2.000

2.400

d

0.260

e

0.400 BSC

NOTE: This drawing is subject to change without notice.

SG Micro Corp

TX00223.000

www.sg-micro.com

PACKAGE INFORMATION

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

P2

P0

W

Q2

Q4

Q2

Q4

Q2

Q4

Q1

Q3

Q1

Q3

Q1

Q3

B0

Reel Diameter

P1

A0

K0

Reel Width (W1)

DIRECTION OF FEED

NOTE: The picture is only for reference. Please make the object as the standard.

KEY PARAMETER LIST OF TAPE AND REEL

Reel Width

Reel

Diameter

A0

B0

K0

P0

P1

P2

W

Pin1

Package Type

W1

(mm)

(mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant

WLCSP-2.0×2.4-30B

7″

9.0

2.15

2.55

0.75

4.0

2.0

8.0

Q1

SG Micro Corp

TX10000.000

www.sg-micro.com

PACKAGE INFORMATION

CARTON BOX DIMENSIONS

NOTE: The picture is only for reference. Please make the object as the standard.

KEY PARAMETER LIST OF CARTON BOX

Length

(mm)

Width

(mm)

Height

(mm)

Reel Type

Pizza/Carton

7″ (Option)

7″

368

442

227

410

224

8

18

SG Micro Corp

www.sg-micro.com

TX20000.000


型号：	SGM41516/D
厂家：	Shengbang Microelectronics Co, Ltd
描述：	High Input Voltage, 3.78A Single-Cell Battery Charger with NVDC Power Path Management 电池
文件：	总52页 (文件大小：1694K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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