SGM58601 [SGMICRO]
Ultra-Low Noise, 24-Bit Analog-to-Digital Converter;
| 型号： | SGM58601 |
| 厂家： | 
Shengbang Microelectronics Co, Ltd |
| 描述： | Ultra-Low Noise, 24-Bit Analog-to-Digital Converter |
| 文件： | 总37页 (文件大小：1289K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SGM58600/SGM58601/SGM58602
Ultra-Low Noise,
24-Bit Analog-to-Digital Converters
GENERAL DESCRIPTION
FEATURES
The SGM58600, SGM58601 and SGM58602 are low noise,
24-bit, 60kSPS, delta-sigma (ΔΣ) analog-to-digital converters
(ADCs).
● Supply Voltage Ranges:
Analog Supply: 5V
Digital Supply: 2.7V to 5V
● Noise-Free Resolution: Up to 22 Bits
● Data Output Rate: Up to 60kSPS
● Integral Nonlinearity (INL):
The SGM58600, SGM58601 and SGM58602 have
a
fourth-order delta-sigma modulator plus a fifth-order Sinc filter
(Sinc5) optimized for low noise performance.
0.0012%FSR (TYP) at PGA = 1
● 24-Bit No Missing Codes
The flexible inputs multiplexer supports single-ended input or
differential input configuration.
● Fast Channel Cycling
18.3 Bits Noise-Free (21.2 Effective Bits) at 1.4kHz
● Flexible Input Multiplexer
The SGM58600, SGM58601 and SGM58602 feature a
selectable input buffer that increases the input impedance,
and the low noise programmable gain amplifier (PGA)
provides gains from 1 to 128 in binary steps.
2 Single-Ended Inputs or 1 Differential Inputs
(SGM58600)
8 Single-Ended Inputs or 4 Differential Inputs
(SGM58601)
The devices have an SPI-compatible interface.
The SGM58600 is available in Green SSOP-20 and
TQFN-3.5×3.5-20L packages, the SGM58601 is available in
Green SSOP-28 and TQFN-5×5-28L packages, and the
SGM58602 is available in a Green TQFN-5×5-20L package.
They are all specified from -40℃ to +125℃.
3 Single-Ended Inputs or 2 Differential Inputs
(SGM58602)
● Low Noise Programmable Gain Amplifier:
30nV Input-Referred Noise
● One-Shot Conversions with Single-Cycle Settling
● Chopper-Stabilized Input Buffer
● Supports Self and System Calibration for All PGA
Settings
● Supports SPI-Compatible Serial Interface
APPLICATIONS
Lab Instrumentation
Measurement and Test
Industrial Process Control
Medical Instruments
SG Micro Corp
FEBRUARY 2022–REV. A
www.sg-micro.com
SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESCRIPTION
ORDERING
NUMBER
PACKAGE
MARKING
PACKING
OPTION
MODEL
SGM58600
XSS20
XXXXX
SSOP-20
TQFN-3.5×3.5-20L
SSOP-28
SGM58600XSS20G/TR
Tape and Reel, 2000
Tape and Reel, 5000
Tape and Reel, 2000
Tape and Reel, 5000
Tape and Reel, 5000
-40℃ to +125℃
-40℃ to +125℃
-40℃ to +125℃
-40℃ to +125℃
-40℃ to +125℃
SGM58600
SGMOV1
XTRL20
XXXXX
SGM58600XTRL20G/TR
SGM58601XSS28G/TR
SGM58601XTQK28G/TR
SGM58602XTRM20G/TR
SGM58601
XSS28
XXXXX
SGM58601
SGM58602
SGM58601
XTQK28
XXXXX
TQFN-5×5-28L
TQFN-5×5-20L
SGM58602
XTRM20
XXXXX
MARKING INFORMATION
NOTE: XXXXX = Date Code, Trace Code and Vendor Code.
X X X X X
Vendor Code
Trace Code
Date Code - Year
Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If
you have additional comments or questions, please contact your SGMICRO representative directly.
OVERSTRESS CAUTION
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed in Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods
may affect reliability. Functional operation of the device at any
conditions beyond those indicated in the Recommended
Operating Conditions section is not implied.
AVDD to AGND.................................................... -0.3V to 6V
DVDD to DGND.............................................. -0.3V to AVDD
AGND to DGND................................................ -0.3V to 0.3V
Input Current (Continuous) ...........................................10mA
Analog Inputs to AGND........................-0.3V to AVDD + 0.3V
Digital Inputs
DIN, SCLK, nCS, nRESET, nSYNC/nPDWN to DGND
........................................................................... -0.3V to 6V
D0/CLKOUT, D1, D2, D3, XTAL1/CLKIN, XTAL2 to DGND
.......................................................... -0.3V to DVDD + 0.3V
Junction Temperature .................................................+150℃
Storage Temperature Range........................-65℃ to +150℃
Lead Temperature (Soldering, 10s).............................+260℃
ESD Susceptibility
ESD SENSITIVITY CAUTION
This integrated circuit can be damaged if ESD protections are
not considered carefully. SGMICRO recommends that all
integrated circuits be handled with appropriate precautions.
Failure to observe proper handling and installation procedures
can cause damage. ESD damage can range from subtle
performance degradation tocomplete device failure. Precision
integrated circuits may be more susceptible to damage
because even small parametric changes could cause the
device not to meet the published specifications.
HBM.............................................................................4000V
CDM ............................................................................1000V
RECOMMENDED OPERATING CONDITIONS
Operating Temperature Range ....................-40℃ to +125℃
DISCLAIMER
SG Micro Corp reserves the right to make any change in
circuit design, or specifications without prior notice.
SG Micro Corp
www.sg-micro.com
FEBRUARY 2022
2
SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
PIN CONFIGURATIONS
SGM58600 (TOP VIEW)
SGM58600 (TOP VIEW)
AVDD
AGND
1
2
20
19
18
17
16
15
14
13
12
11
D1
D0/CLKOUT
SCLK
DIN
20
19
18
17
16
VREFN
3
15 SCLK
14 DIN
VREFP
AINCOM
AIN0
1
2
3
4
5
4
VREFP
5
AINCOM
AIN0
DOUT
SGM58600
13 DOUT
12 nDRDY
11 nCS
SGM58600
nDRDY
6
AIN1
AIN1
7
nCS
nSYNC/nPDWN
8
XTAL1/CLKIN
nSYNC/nPDWN
nRESET
DVDD
6
7
8
9
10
9
XTAL2
DGND
10
SSOP-20
TQFN-3.5×3.5-20L
SGM58601 (TOP VIEW)
SGM58601 (TOP VIEW)
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVDD
AGND
D3
2
3
D2
VREFN
VREFP
AINCOM
AIN0
D1
28 27 26 25 24 23 22
4
D0/CLKOUT
SCLK
SCLK
VREFP
AINCOM
AIN0
1
2
3
21
5
20 DIN
6
DIN
19
18
DOUT
nDRDY
AIN1
7
DOUT
nDRDY
nCS
AIN1
4
5
6
SGM58601
SGM58601
AIN2
17 nCS
16
15 XTAL2
8
AIN2
AIN3
XTAL1/CLKIN
AIN3
9
AIN4
7
AIN4
10
11
12
13
14
XTAL1/CLKIN
XTAL2
DGND
8
9
10 11 12 13 14
AIN5
AIN6
AIN7
DVDD
nRESET
nSYNC/nPDWN
SSOP-28
TQFN-5×5-28L
SGM58602 (TOP VIEW)
20
19
18
17
16
15 SCLK
14 DIN
VREFP
AIN0
1
2
3
4
5
AIN1
SGM58602
13 DOUT
AIN2
12 nDRDY
11 nCS
AIN3
6
7
8
9
10
TQFN-5×5-20L
SG Micro Corp
FEBRUARY 2022
www.sg-micro.com
3
SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
PIN DESCRIPTION
PIN
TYPE (1)
FUNCTION
SGM58600
SGM58601
SGM58602
NAME
TQFN-
3.5×3.5-20L
TQFN-
5×5-28L
TQFN-
5×5-20L
SSOP-20
SSOP-28
1
2
3
4
5
6
7
‒
‒
‒
‒
‒
‒
18
1
2
26
18
19
20
1
AVDD
AGND
VREFN
VREFP
AINCOM
AIN0
A
Analog Power Supply.
19
20
1
27
28
1
A
Analog Ground.
3
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
Negative Reference Input.
Positive Reference Input.
Analog Input Common.
Analog Input 0.
4
2
5
2
‒
3
6
3
2
4
7
4
3
AIN1
Analog Input 1.
‒
8
5
4
AIN2
Analog Input 2.
‒
9
6
5
AIN3
Analog Input 3.
‒
10
11
12
13
7
‒
AIN4
Analog Input 4.
‒
8
‒
AIN5
Analog Input 5.
‒
9
‒
AIN6
Analog Input 6.
‒
10
‒
AIN7
Analog Input 7.
Synchronization Input/Power-Down Input.
Active low.
8
5
14
11
6
nSYNC/nPDWN
DI (2)
9
6
7
15
16
17
18
19
20
21
22
23
24
25
26
27
28
12
13
14
15
16
17
18
19
20
21
22
23
24
25
7
8
nRESET
DVDD
DGND
XTAL2
XTAL1/CLKIN
nCS
DI (2)
D
Reset Input. Active low.
Digital Power Supply.
10
11
12
13
14
15
16
17
18
19
20
‒
8
9
D
D (3)
Digital Ground.
9
‒
Crystal Oscillator Connection.
Crystal Oscillator Connection/Clock Input.
Chip Select. Active low.
Data Ready Output. Active low.
Serial Data Output.
10
11
12
13
14
15
16
17
‒
10
11
12
13
14
15
16
17
‒
D/DI
DI (2)
DO
nDRDY
DOUT
DIN
DO
DI (2)
DI (2)
DIO (4)
DIO (4)
DIO (4)
DIO (4)
Serial Data Input.
SCLK
Serial Clock Input.
D0/CLKOUT
D1
Digital Input/Output 0/Clock Output.
Digital Input/Output 1.
D2
Digital Input/Output 2.
‒
‒
‒
D3
Digital Input/Output 3.
Exposed
Pad
Exposed
Pad
Exposed
Pad
Exposed pad should be soldered to PCB
board and connected to AGND.
‒
‒
AGND
‒
NOTES:
1. A = Analog, AI = Analog Input, D = Digital, DI = Digital Input, DO = Digital Output, DIO = Digital Input and Output.
2. Schmitt-trigger logic input.
3. If the external clock input is applied to XTAL1/CLKIN, stay disconnected.
4. Schmitt-trigger logic input when the pin is used as an input.
SG Micro Corp
www.sg-micro.com
FEBRUARY 2022
4
SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
ELECTRICAL CHARACTERISTICS
(VAVDD = 5V, VDVDD = 3.3V, VREF = 2.5V, fCLKIN = 7.68MHz, PGA[2:0] = 1, Full = -40℃ to +125℃. Typical values are at TA = +25℃,
unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Analog Inputs
Full-Scale Input Voltage
(AINP - AINN)
±2VREF/PGA
V
V
Buffer off
Buffer on
AGND - 0.1
AVDD + 0.1
AVDD
Absolute Input Voltage
(AIN0 - AIN7, AINCOM to AGND)
AGND
1
Programmable Gain Amplifier
Differential Input Impedance
128
Buffer off, PGA[2:0] = 1
Buffer off, PGA[2:0] = 2 or 4
Buffer off, PGA[2:0] = 8
Buffer off, PGA[2:0] = 16, 32, 64 or 128
Buffer on
67
35
kΩ
kΩ
kΩ
kΩ
MΩ
255
190
3.2
0.5
2.2
9
SDCS[1:0] = 01
Sensor Detection Current Sources
ISDC
SDCS[1:0] = 10
μA
SDCS[1:0] = 11
System Performance
Resolution
24
24
Bit
Bit
SPS (1)
%FSR (2)
No Missing Codes
Data Rate
All data rates and PGA settings
fCLKIN = 7.68MHz
fDATA
2.5
60000
0.002
Integral Nonlinearity
Offset Error
Differential input, PGA[2:0] = 1
After calibration
0.0012
On the level of the noise
PGA[2:0] = 1
±200
Offset Drift
Gain Error
Gain Drift
nV/℃
PGA[2:0] = 64
±25
After calibration, PGA[2:0] = 1, buffer on
After calibration, PGA[2:0] = 64, buffer on
PGA[2:0] = 1
±0.003
%
±0.035
±0.45
ppm/℃
PGA[2:0] = 64
±1.5
Common-Mode Rejection Ratio
Noise
CMRR
fCM (3) = 60Hz, fDATA = 30kSPS (4)
92
65
110
dB
See Noise Performance Tables
AVDD Power Supply Rejection
DVDD Power Supply Rejection
±5% Δ in AVDD
80
dB
dB
±10% Δ in DVDD
100
NOTES:
1. SPS = Samples Per Second.
2. FSR = Full-Scale Range = 4VREF/PGA.
3. fCM = Common-Mode Input Signal Frequency.
4. Setting a digital filter notch at 60Hz (fDATA = 60SPS, 30SPS, 15SPS, 10SPS, 5SPS, or 2.5SPS), this can improve the
common-mode rejection of this frequency.
SG Micro Corp
www.sg-micro.com
FEBRUARY 2022
5
SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = 5V, VDVDD = 3.3V, VREF = 2.5V, fCLKIN = 7.68MHz, PGA[2:0] = 1, Full = -40℃ to +125℃. Typical values are at TA = +25℃,
unless otherwise noted.)
PARAMETER
Voltage Reference Inputs
Reference Input Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VREF
VREF ≡ VREFP - VREFN
0.5
2.5
2.6
V
V
Buffer off
Buffer on
Buffer off
Buffer on
AGND - 0.1
AGND
VREFP - 0.5
VREFP - 0.5
VAVDD + 0.1
VAVDD
Negative Reference Input
Positive Reference Input
Voltage Reference Impedance
VREFN
VREFN + 0.5
VREFN + 0.5
VREFP
V
buffer off
buffer on
33
6
kΩ
Zeff
fCLKIN = 7.68MHz
MΩ
Digital Input/Output
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Hysteresis
VIH
VIL
0.8 × VDVDD
DGND
VDVDD
V
V
0.2 × VDVDD
VOH
VOL
IOH = 5mA
IOL = 5mA
0.8 × VDVDD
V
0.2 × VDVDD
V
0.5
V
Input Leakage
0 < VDIGITAL INPUT < DVDD
1
μA
External crystal between XTAL1 and XTAL2
External oscillator driving CLKIN
7.68
7.68
Master Clock Rate
MHz
Power Requirements
AVDD Supply Voltage
DVDD Supply Voltage
VAVDD
VDVDD
4.75
2.7
5.25
AVDD
2
V
V
Power-down mode
Standby mode
0.46
0.21
2.7
μA
mA
0.27
3.8
7
PGA = 1, buffer off
AVDD Current
PGA = 64, buffer off
Normal mode
4.7
mA
PGA = 1, buffer on
3.2
4.4
7.5
3.5
160
1
PGA = 64, buffer on
Power-down mode
5
0.13
120
0.55
μA
μA
DVDD Current
Standby mode, CLKOUT off, DVDD = 3.3V
Normal mode, CLKOUT off, DVDD = 3.3V
mA
Normal mode, PGA = 1, buffer off,
DVDD = 3.3V
15
22
Power Dissipation
mW
Standby mode, DVDD = 3.3V
1.5
1.9
SG Micro Corp
www.sg-micro.com
FEBRUARY 2022
6
SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
TIMING CHARACTERISTICS
PARAMETER
SCLK Cycle Time
SYMBOL
CONDITIONS
MIN
50
25
25
0
MAX
UNITS
ns
t1
t2H
t2L
t3
SCLK High Time
ns
SCLK Low Time
ns
nCS Falling Edge to First SCLK Rising Edge Setup Time (1)
Valid DIN to SCLK Falling Edge Setup Time
Valid DIN to SCLK Falling Edge Hold Time
ns
t4
20
0
ns
t5
ns
Delay from Last SCLK Edge for DIN to First SCLK Rising Edge
for DOUT: RDATA, RDATAC, RREG Commands
t6
20
ns
SCLK Rising Edge to Valid New DOUT, Propagation Delay (2)
SCLK Rising Edge to DOUT Invalid, Hold Time
Last SCLK Falling Edge to DOUT High-Impedance (3)
nCS Low after Final SCLK Falling Edge
t7
t8
20
ns
ns
ns
ns
ns
ns
0
10
t9
t10
0
RREG, WREG, RDATA
RDATAC, nSYNC
100
100
Final SCLK Falling Edge of Command to First SCLK Rising
Edge of Next Command
t11
RDATAC, nRESET, STANDBY,
SELFOCAL, SYSOCAL,
Wait for nDRDY to go low
SELFGCAL, SYSGCAL, SELFCAL
nRESET, nSYNC/nPDWN, Pulse Width
t12
t13
See Figure 2
See Figure 3
0.5
30
μs
Conversion Data Invalid while Being Updated
(nDRDY Shown with No Data Retrieval)
(4)
τCLKIN
NOTES:
1. nCS can be tied low.
2. DOUT load = 20pF and 100kΩ to DGND.
3. DOUT goes high-impedance immediately when nCS goes high.
4. Master clock period (τCLKIN = 1/fCLKIN).
nCS
t10
t3
t1
t2H
SCLK
DIN
t11
t6
t2L
t4
t5
MSB
LSB
t7
t8
t9
LSB
MSB
DOUT
Figure 1. Serial Interface Timing Diagram
t12
nRESET, nSYNC/nPDWN
Figure 2. nRESET and nSYNC/nPDWN Timing Diagram
t13
nDRDY
Figure 3. nDRDY Update Timing Diagram
SG Micro Corp
www.sg-micro.com
FEBRUARY 2022
7
SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
TYPICAL PERFORMANCE CHARACTERISTICS
Noise Histogram
Noise Histogram
80
70
60
50
40
30
20
10
0
30
25
20
15
10
5
PGA = 1, Data Rate = 2.5SPS, Buffer Off,
256 Readings
PGA = 1, Data Rate = 1kSPS, Buffer Off,
4096 Readings
0
Output Code (LSB)
Output Code (LSB)
Noise Histogram
Noise Histogram
35
30
25
20
15
10
5
50
40
30
20
10
0
PGA = 1, Data Rate = 30kSPS, Buffer Off,
4096 Readings
PGA = 1, Data Rate = 60kSPS, Buffer Off,
4096 Readings
0
Output Code (LSB)
Output Code (LSB)
Noise Histogram
Noise Histogram
50
40
30
20
10
0
35
30
25
20
15
10
5
PGA = 64, Data Rate = 2.5SPS, Buffer Off,
256 Readings
PGA = 64, Data Rate = 1kSPS, Buffer Off,
4096 Readings
0
Output Code (LSB)
Output Code (LSB)
SG Micro Corp
www.sg-micro.com
FEBRUARY 2022
8
SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Noise Histogram
Noise Histogram
30
25
20
15
10
5
50
40
30
20
10
0
PGA = 64, Data Rate = 30kSPS, Buffer Off,
4096 Readings
PGA = 64, Data Rate = 60kSPS, Buffer Off,
4096 Readings
0
Output Code (LSB)
Output Code (LSB)
Noise Histogram
Noise Histogram
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
PGA = 128, Data Rate = 2.5SPS, Buffer Off,
256 Readings
PGA = 128, Data Rate = 1kSPS, Buffer Off,
4096 Readings
0
0
Output Code (LSB)
Output Code (LSB)
Noise Histogram
Noise Histogram
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
PGA = 128, Data Rate = 30kSPS, Buffer Off,
4096 Readings
PGA = 128, Data Rate = 60kSPS, Buffer Off,
4096 Readings
0
0
Output Code (LSB)
Output Code (LSB)
SG Micro Corp
FEBRUARY 2022
www.sg-micro.com
9
SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Offset Drift Histogram
Offset Drift Histogram
40
35
30
25
20
15
10
5
30
25
20
15
10
5
PGA = 1, 90 Units from 3 Production Lots
PGA = 64, 90 Units from 3 Production Lots
0
0
Offset Drift (nV/℃)
Offset Drift (nV/℃)
Gain Drift Histogram
Gain Drift Histogram
80
70
60
50
40
30
20
10
0
35
30
25
20
15
10
5
PGA = 1, 90 Units from 3 Production Lots
PGA = 64, 90 Units from 3 Production Lots
0
Gain Drift (ppm/℃)
Gain Drift (ppm/℃)
Gain Error Histogram
Gain Error Histogram
60
50
40
30
20
10
0
50
40
30
20
10
0
PGA = 1, 3 Production Lots
PGA = 64, 3 Production Lots
Gain Error (%)
Gain Error (%)
SG Micro Corp
www.sg-micro.com
FEBRUARY 2022
10
SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Effective Number of Bits vs. Temperature
PGA = 1
Effective Number of Bits vs. Input Voltage
PGA = 1
23
22
21
20
19
18
23
22
21
20
19
18
Data Rate = 1kSPS
Data Rate = 1kSPS
Data Rate = 30kSPS
Data Rate = 30kSPS
-50
-25
0
25
50
75
100
125
125
5
0
1
1
1
2
3
4
5
Input Voltage (V)
Temperature (℃)
Analog Supply Current vs. Temperature
PGA = 64, Buffer On
Analog Supply Current vs. PGA
Buffer On
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
Buffer Off
PGA = 64, Buffer Off
PGA = 1, Buffer On
PGA = 1, Buffer Off
-50
-25
0
25
50
75
100
2
4
8
16
32
64
128
PGA Setting
Temperature (℃)
Integral Nonlinearity vs. Input Voltage
PGA = 1
Integral Nonlinearity vs. PGA
0.0015
0.001
0.0005
0
0.008
0.007
0.006
0.005
0.004
0.003
0.002
0.001
0
+25℃
-40℃
+125℃
Buffer On
-0.0005
-0.001
-0.0015
+85℃
Buffer Off
32 64
-5 -4 -3 -2 -1
0
1
2
3
4
2
4
8
16
128
PGA Setting
Input Voltage (V)
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SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
FUNCTIONAL BLOCK DIAGRAM
VREFP
VREFN
AVDD
DVDD
SGM58600
SGM58601
SGM58602
Buffer
Buffer
Σ
A/D Converter
VREF
XTAL1/CLKIN
XTAL2
Clock
Generator
2
AIN0
AIN1
2 × VREF
AIN2
SGM58602
Only
Input
Multiplexer
and
Sensor
Detection
AIN3
AIN4
AIN5
AIN6
nRESET
VIN • PGA
4th-Order
Modulator
Programmable
Digital Filter
PGA
1:128
Buffer
Control
Σ
nSYNC/nPDWN
SGM58601
Only
nDRDY
SCLK
DIN
AIN7
AINCOM
SPI
Serial
Interface
General
Purpose
Digital I/O
SGM58600/1
Only
DOUT
nCS
AGND
D3 D2 D1 D0/CLKOUT
DGND
SGM58601
Only
Figure 4. Block Diagram
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SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
DETAILED DESCRIPTION
single-ended inputs. The SGM58602 provides 4 analog
inputs, which can be configured as 2 independent differential
inputs, 3 single-ended inputs. When using the SGM58600 or
SGM58602 programming the inputs, make sure to select only
the available inputs when programming the input multiplexer
control register (MUX).
Overview
The SGM58600, SGM58601 and SGM58602 are ultra-low
noise analog-to-digital converters (ADCs). The block diagram
of the SGM5860x ADCs is shown in Figure 4.
The SGM58600 supports 1 differential input or 2 single-ended
inputs and has
SGM58601 supports 4 differential inputs or 8 single-ended
inputs and has general-purpose digital I/Os. The
2 general-purpose digital I/Os. The
To minimize the power consumption of the chip, it’s better to
keep any unused inputs floating.
4
SGM58602 supports 2 differential inputs or 3 single-ended
inputs and has 2 general-purpose digital I/Os.
Open/Short Sensor Detection
Figure 5 shows a demo connection of external sensor equal
These chips provide a configurable data rate from 2.5SPS to
60kSPS, the selection is a tradeoff between accuracy and
speed.
circuits, in which RSENS is the sensor equal output impedance.
Please note that when the SDCS (Sensor Detection Current
Source) is enabled, the input buffer is forced on regardless of
BUFEN bit setting.
Noise Performance
The typical noise performance with the inputs shorted
externally is summarized from Table 1 to Table 6. For the six
tables, the following conditions apply: TA = +25℃, VAVDD = 5V,
VDVDD = 3.3V, VREF = 2.5V, and fCLKIN = 7.68MHz. ENOB is
given by:
AVDD
SDCS
ln FSR / RMS Noise
(
)
(1)
ENOB =
ln 2
( )
AINP
Where:
FSR = Full-scale range.
Input
Buffer
RSENS
AINN
The noise-free bits of resolution are shown in Table 3. Table 1
to Table 3 show that the chip performance when the input
buffer is enabled. Table 4 to Table 6 show that the chip
performance when the input buffer is disabled.
SDCS
Input Multiplexer
The SGM58601 provides 9 analog inputs, which can be
Figure 5. Sensor Detection Circuitry
configured as
4
independent differential inputs,
8
single-ended inputs, or a combination of differential and
single-ended inputs. The SGM58600 provides 3 analog
inputs, which can be configured as 1 differential input or 2
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SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
DETAILED DESCRIPTION (continued)
Table 1. Input-Referred Noise (μV, RMS) with Buffer On
Table 3. Noise-Free Resolution (Bits) with Buffer On
Data
Rate
(SPS)
Data
Rate
(SPS)
PGA
PGA
1
2
4
8
16
32
64
128
1
2
4
8
16
32
64
128
2.5
5
0.331 0.198 0.150 0.071 0.048 0.036 0.030 0.030
0.360 0.193 0.158 0.089 0.066 0.049 0.039 0.041
0.415 0.237 0.183 0.119 0.097 0.069 0.057 0.055
0.475 0.254 0.209 0.140 0.115 0.083 0.068 0.068
0.536 0.281 0.243 0.189 0.146 0.107 0.090 0.088
0.580 0.310 0.262 0.196 0.159 0.118 0.098 0.095
0.714 0.370 0.318 0.256 0.203 0.149 0.125 0.123
0.783 0.416 0.335 0.279 0.220 0.165 0.135 0.137
1.047 0.531 0.410 0.360 0.286 0.210 0.176 0.175
2.367 1.198 0.903 0.810 0.634 0.466 0.392 0.389
2.5
5
22.2 22.1 21.2 21.5 21.0 20.5 19.8 18.9
21.8 21.7 21.1 21.2 20.6 19.9 19.3 18.2
21.7 21.4 20.9 20.5 20.0 19.4 18.7 17.7
21.5 21.2 20.7 20.2 19.8 19.1 18.4 17.5
21.1 21.2 20.5 19.9 19.2 18.8 18.1 17.1
21.0 21.1 20.4 19.8 19.2 18.6 17.9 17.0
20.8 20.8 20.1 19.3 18.8 18.2 17.5 16.5
20.7 20.6 20.0 19.3 18.7 18.1 17.3 16.4
20.3 20.3 19.6 18.8 18.3 17.6 16.9 15.9
19.2 19.1 18.5 17.7 17.0 16.5 15.7 14.8
10
15
25
30
50
60
100
500
10
15
25
30
50
60
100
500
1000 3.216 1.690 1.321 1.131 0.901 0.662 0.547 0.541
2000 4.298 2.296 1.795 1.575 1.287 0.932 0.770 0.768
3750 5.519 3.012 2.342 2.129 1.692 1.252 1.041 1.036
7500 7.249 3.986 3.122 2.927 2.317 1.732 1.443 1.437
15000 9.227 5.082 4.013 3.759 2.938 2.217 1.866 1.849
30000 10.762 5.958 4.602 4.274 3.344 2.536 2.154 2.114
60000 52.543 26.520 14.262 8.798 5.671 3.900 3.123 3.100
1000 18.7 18.7 18.0 17.2 16.6 16.1 15.3 14.3
2000 18.3 18.2 17.6 16.8 15.8 15.5 14.8 13.8
3750 17.9 17.8 17.2 16.3 15.6 15.1 14.3 13.3
7500 17.5 17.3 16.7 15.9 15.2 14.6 13.8 12.8
15000 17.0 17.0 16.4 15.5 14.8 14.3 13.5 12.6
30000 16.8 16.7 16.1 15.3 14.7 14.0 13.3 12.3
60000 14.6 14.6 14.5 14.2 13.9 13.4 12.7 11.8
Table 2. Effective Number of Bits (ENOB, Bits) with Buffer On
Data
Rate
(SPS)
PGA
1
2
4
8
16
32
64
128
2.5
5
24.8 24.6 24.0 24.1 23.6 23.0 22.3 21.3
24.7 24.6 23.9 23.7 23.2 22.6 21.9 20.9
24.5 24.3 23.7 23.3 22.6 22.1 21.4 20.4
24.3 24.2 23.5 23.1 22.4 21.9 21.1 20.1
24.2 24.1 23.3 22.7 22.0 21.5 20.7 19.8
24.0 23.9 23.2 22.6 21.9 21.3 20.6 19.6
23.7 23.7 22.9 22.2 21.6 21.0 20.3 19.3
23.6 23.5 22.8 22.1 21.4 20.9 20.1 19.1
23.2 23.2 22.5 21.7 21.1 20.5 19.8 18.8
22.0 22.0 21.4 20.6 19.9 19.4 18.6 17.6
10
15
25
30
50
60
100
500
1000 21.6 21.5 20.9 20.1 19.4 18.8 18.1 17.1
2000 21.1 21.1 20.4 19.6 18.9 18.4 17.6 16.6
3750 20.8 20.7 20.0 19.2 18.5 17.9 17.2 16.2
7500 20.4 20.3 19.6 18.7 18.0 17.5 16.7 15.7
15000 20.0 19.9 19.2 18.3 17.7 17.1 16.4 15.4
30000 19.8 19.7 19.1 18.2 17.5 16.9 16.1 15.2
60000 17.5 17.5 17.4 17.1 16.7 16.3 15.6 14.6
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SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
DETAILED DESCRIPTION (continued)
Table 4. Input-Referred Noise (μV, RMS) with Buffer Off
Table 6. Noise-Free Resolution (Bits) with Buffer Off
Data
Rate
(SPS)
Data
Rate
(SPS)
PGA
PGA
1
2
4
8
16
32
64
128
1
2
4
8
16
32
64
128
2.5
5
0.335 0.191 0.152 0.065 0.051 0.039 0.030 0.032
0.384 0.196 0.169 0.095 0.069 0.050 0.042 0.041
0.439 0.218 0.187 0.123 0.091 0.068 0.059 0.056
0.481 0.252 0.213 0.147 0.112 0.088 0.069 0.069
0.570 0.287 0.238 0.184 0.143 0.107 0.087 0.088
0.603 0.305 0.265 0.205 0.158 0.120 0.096 0.095
0.725 0.377 0.315 0.259 0.202 0.152 0.125 0.124
0.763 0.409 0.338 0.278 0.222 0.164 0.139 0.135
2.5
5
22.2 22.2 21.4 21.5 20.9 20.4 19.7 18.7
22.0 21.9 21.0 20.9 20.5 19.8 19.2 18.2
21.7 21.7 20.9 20.5 19.9 19.4 18.7 17.8
21.5 21.5 20.8 20.1 19.6 19.2 18.4 17.5
21.3 21.2 20.6 20.0 19.3 18.8 18.1 17.1
21.2 21.2 20.3 19.7 19.2 18.6 17.9 17.0
20.9 20.7 20.1 19.4 18.7 18.3 17.5 16.4
20.8 20.6 19.9 19.3 18.6 18.1 17.3 16.4
20.4 20.3 19.6 18.8 18.2 17.5 16.9 16.0
19.3 19.1 18.6 17.7 16.9 16.5 15.7 14.9
10
15
25
30
50
60
10
15
25
30
50
60
100
500
100 1.042 0.552 0.425 0.362 0.284 0.214 0.176 0.174
500 2.319 1.199 0.888 0.818 0.633 0.472 0.394 0.388
1000 3.138 1.678 1.314 1.137 0.888 0.666 0.555 0.544
2000 4.254 2.288 1.786 1.583 1.261 0.924 0.779 0.763
3750 5.493 2.998 2.346 2.136 1.694 1.257 1.047 1.041
7500 7.236 4.008 3.131 2.949 2.309 1.733 1.440 1.424
15000 9.215 5.025 3.959 3.768 2.940 2.241 1.867 1.858
30000 10.592 5.835 4.550 4.289 3.333 2.560 2.143 2.136
60000 52.462 26.249 14.158 8.795 5.653 3.947 3.119 3.089
1000 18.8 18.7 18.0 17.2 16.5 16.0 15.3 14.3
2000 18.3 18.1 17.6 16.8 16.1 15.5 14.7 13.8
3750 17.9 17.8 17.2 16.3 15.7 15.1 14.4 13.4
7500 17.5 17.4 16.7 15.8 15.2 14.6 13.8 12.9
15000 17.1 16.9 16.4 15.5 14.9 14.3 13.5 12.5
30000 16.8 16.7 16.2 15.2 14.6 14.1 13.4 12.3
60000 14.6 14.6 14.5 14.3 13.9 13.5 12.8 11.9
Table 5. Effective Number of Bits (ENOB, Bits) with Buffer Off
Data
Rate
(SPS)
PGA
1
2
4
8
16
32
64
128
2.5
5
24.8 24.6 24.0 24.2 23.6 23.0 22.3 21.2
24.6 24.6 23.8 23.7 23.1 22.6 21.8 20.9
24.4 24.5 23.7 23.3 22.7 22.1 21.3 20.4
24.3 24.2 23.5 23.0 22.4 21.8 21.1 20.1
24.1 24.1 23.3 22.7 22.1 21.5 20.8 19.8
24.0 24.0 23.2 22.5 21.9 21.3 20.6 19.6
23.7 23.7 22.9 22.2 21.6 21.0 20.3 19.3
23.6 23.5 22.8 22.1 21.4 20.9 20.1 19.1
23.2 23.1 22.5 21.7 21.1 20.5 19.8 18.8
22.0 22.0 21.4 20.5 19.9 19.3 18.6 17.6
10
15
25
30
50
60
100
500
1000 21.6 21.5 20.9 20.1 19.4 18.8 18.1 17.1
2000 21.2 21.1 20.4 19.6 18.9 18.4 17.6 16.6
3750 20.8 20.7 20.0 19.2 18.5 17.9 17.2 16.2
7500 20.4 20.3 19.6 18.7 18.0 17.5 16.7 15.7
15000 20.0 19.9 19.3 18.3 17.7 17.1 16.4 15.4
30000 19.8 19.7 19.1 18.2 17.5 16.9 16.2 15.2
60000 17.5 17.5 17.4 17.1 16.8 16.3 15.6 14.6
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SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
DETAILED DESCRIPTION (continued)
The effective impedances with buffer off for fCLKIN = 7.68MHz
is shown in Table 8.
Programmable Gain Amplifier (PGA)
The PGA[2:0] is controlled by the ADCON register. We
suggest recalibrating the analog-to-digital converter after
changing the PGA setting.
Table 8. Effective Impedances with Buffer Off
PGA Setting
Zeff (kΩ)
67
Table 7. Full-Scale Input Voltage (VIN) vs. PGA Setting
1
2
Full-Scale Input Voltage (1)
35
PGA Setting
(VREF = 2.5V)
4
35
1
2
±5V
8
255
190
190
190
190
±2.5V
16
32
64
128
4
±1.25V
8
±0.625V
16
32
64
128
±312.5mV
±156.25mV
±78.125mV
±39.0625mV
NOTE:
1. fCLKIN = 7.68MHz.
NOTE:
Analog Input Buffer
1. Positive inputs minus negative inputs is the voltage range and at
the same time to make sure that both positive inputs and negative
inputs are absolutely positive respect to ground (listed in the
Electrical Characteristics section).
To increase the input impedance of SGM5860x, the input
buffer can be enabled by the BUFEN bit in the STATUS
register. The input impedance equal circuits are shown in
Figure 6. Table 9 lists the values of Zeff for the different PGA
settings. The equal input impedance changes inversely with
the CLKIN frequency (fCLKIN). For example, when the fCLKIN is
reduced by half to 3.84MHz, Zeff for PGA = 1 will double from
3.2MΩ to 6.4MΩ.
Modulator Input Circuitry
The SGM5860x modulator measures the input signal by
using internal capacitors that are continuously sampled and
reverse sampled between the differential inputs.
Table 9. Effective Impedances with Buffer On
When the chip is converting, it draws current from input. The
equal input impedance Zeff = VIN/IAVERAGE. Figure 6 shows the
input equal circuitry by their effective impedances.
PGA Setting
Zeff (MΩ)
1
2
3.2
1.7
1
4
8
21
10
5
AIN0
16
32
64
128
AIN1
AINP
AIN2
SGM58602
2.4
1
Only
AIN3
AIN4
AIN5
AIN6
AIN7
Input
Multiplexer
Zeff
SGM58601
Only
NOTE:
1. fCLKIN = 7.68MHz.
AINN
AINCOM
SGM58600/1
Only
Voltage Reference Inputs (VREFP, VREFN)
The voltage reference of the SGM5860x ADC is the
differential voltage between VREFP and VREFN: VREF = VREFP
VREFN
-
.
Figure 6. Analog Input Effective Impedances with Buffer
On/Off
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SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
DETAILED DESCRIPTION (continued)
Digital Filter
Frequency Response
The chip low-pass digital filter can be calculated based on the
Inside the chip, there is a Sinc5 filter and an average filter
after the modulator. Its equal architecture is shown in Figure
7.
following equation:
H f = HSinc5 (f) × HAverager
( )
f
( )
(2)
5
Table 10 shows the data rate setting and real data rate under
fCLKIN = 7.68MHz. Note that if the fCLKIN increases, the read
data rate increases accordingly. For example, the fCLKIN from
7.68MHz to 10MHz increases the data rate for DR[7:0] =
11110001 from 60000SPS to 78125SPS.
256π × f
fCLKIN
256π × Num_Ave f
sin
sin
fCLKIN
=
×
4π × f
fCLKIN
256π × f
64 × sin
Num_Ave × sin
fCLKIN
To eliminate 50Hz (or 60Hz) noise from power supply, set the
data rate equal to 2.5SPS, 5SPS, 10SPS, 15SPS, 30SPS, or
50SPS (or 60Hz).
Table 10. Number of Averages and Data Rate Setting
Number of Averages for
DRATE DR[7:0]
Programmable Filter
(Num_Ave)
Data Rate (1) (SPS)
Table 11. First-Notch Frequency and -3dB Bandwidth Filter
Data Rate (1) (SPS) First-Notch (Hz)
-3dB Bandwidth (Hz)
11110001
11110000
11100000
11010000
11000000
10110000
10100001
10010010
10000010
01110010
01100011
01010011
01000011
00110011
00100011
00010011
00000011
1
1
60000
30000
15000
7500
3750
2000
1000
500
100
60
60000
30000
15000
7500
3750
2000
1000
500
60000
30000
15000
7500
3750
2000
1000
500
100
60
12000
6106
4807
3003
1615
878
2
4
8
15
30
441
60
221
300
500
600
1000
1200
2000
3000
6000
12,000
100
44.2
26.5
22.1
13.3
11.1
6.63
4.42
2.21
1.1
60 (2)
50 (3)
30 (2)
25 (3)
15 (2)
10 (4)
5 (4)
50
50
30
30
25
25
15
15
10
10
5
5
2.5
2.5 (4)
2.5
NOTE:
1. fCLKIN = 7.68MHz.
NOTES:
1. fCLKIN = 7.68MHz.
2. Notch at 60Hz.
3. Notch at 50Hz.
4. Notch at 50Hz and 60Hz.
Modulator Rate = fCLKIN/4
Data Rate = fCLKIN/256
Data Rate = (fCLKIN/256)(1/Num_Ave)
Analog
Modulator
Programmable
Averager
Sinc5 Filter
Num_Ave (Set by DRATE Register)
Digital Filter
Figure 7. Architecture of the Analog Modulator and Digital Filter
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SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
DETAILED DESCRIPTION (continued)
Figure 8. Frequency Response (Data Rate = 60kSPS)
Figure 9. Frequency Response(Data Rate = 2.5SPS)
Figure 10. Frequency Response Out to 7.68MHz
(Data Rate = 60kSPS)
Figure 11. Frequency Response Out to 7.68MHz
(Data Rate = 2.5SPS)
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SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
DETAILED DESCRIPTION (continued)
indicate data is ready, and there is no data setting time (all
Settling Time
Table 12 shows the settling time for the different data rates.
processing data are discarded internally).
Table 12. Settling Time for Different Data Rates
1. When nDRDY goes low, indicating that data is ready to
read.
Data Rate (1) (SPS)
Settling Time (t14) (ms)
60000
30000
15000
7500
3750
2000
1000
500
100
60
0.12
0.20
0.27
0.33
0.47
0.67
1.20
2.20
10.2
16.9
20.3
33.5
40.2
67.0
100.2
200.2
400.2
2. It will take 14 × τCLKIN for nDRDY to go from low to high,
after WREG command is received by ADC.
Table 13 shows the throughput speed when cycling the input
multiplexer.
Table 13. Multiplexer Cycling Throughput
Data Rate (1) (SPS)
Cycling Throughput (1/t15) (Hz)
60000
30000
15000
7500
3750
2000
1000
500
100
60
8210
4874
3678
2954
2119
1418
829
453
98
50
30
25
15
10
5
59.3
49.5
29.8
24.8
15
2.5
50
NOTES:
1. fCLKIN = 7.68MHz.
30
25
2. In one-shot mode, a small additional delay is needed to start the
device from standby.
15
10
10
Settling Time Using the Input Multiplexer
The fastest way to switch the input multiplexer is to issue a
WREG command immediately when nDRDY goes low, then
the next channel conversion starts and we can read
conversion data of previous channel at the same time. Figure
12 shows a timing demo of channel switching and data read.
Note that when cycling through channel, nDRDY goes low to
5
5
2.5
2.5
NOTE:
1. fCLKIN = 7.68MHz.
t14
t15
nDRDY
14 × τCLKIN
RDATA
14 × τCLKIN
RDATA
WREG 23h
to MUX reg
WREG 45h
to MUX reg
DIN
Data from
MUX = 01h
Data from
MUX = 23h
DOUT
MUX
01h
23h
AINP = AIN2, AINN = AIN3
45h
AINP = AIN4, AINN = AIN5
Register AINP = AIN0, AINN = AIN1
Figure 12. Cycling the SGM5860x Input Multiplexer
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SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
DETAILED DESCRIPTION (continued)
Settling Time Using One-Shot Mode
Issue a STANDBY command can let chip go into low power
standby mode. A WAKEUP command can wake up the chip
and perform one time one-shot conversion. It will take t18 plus
3 nRDRY conversion cycles to wake up and fully settle the
conversion data. After the conversion, if we want to go to
standby again, another STANDBY command is needed.
Figure 13 shows the sequence.
Data Format
The SGM5860x output 24-bit data in binary two's complement
format. The ideal output codes for different input signals are
summarized as shown in Table 15.
Table 15. Ideal Output Code for Different Input Signals
Input Signal VIN (AINP - AINN)
Ideal Output Code (1)
+ 2VREF
≥
7FFFFFh
PGA
+ 2VREF
000001h
000000h
FFFFFFh
PGA 223 - 1
Settling Time while Continuously Converting
In the continuous mode, when there is a step change of the
input, it usually needs several nDRDY periods to fully set up
the data, which is shown in Table 14.
0
- 2VREF
PGA 223 - 1
(
)
223
- 2V
REF
Table 14. Data Settling Delay vs. Data Rate
≤
800000h
PGA 223 - 1
Data Rate (SPS)
Settling Time (nDRDY Periods)
NOTE:
60000
30000
15000
7500
3750
2000
1000
500
100
60
5
5
3
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1. Except for effects of INL, noise, offset, and gain errors.
General-Purpose Digital I/O (D0 to D3)
The SGM58601 has 4 digital I/O pins and the SGM58600/2
have 2 digital I/O pins. All I/O pins are separately controllable
by IO registers. During standby and power-down modes, the
GPIOs are still active. If GPIOs work as output, they keep
driving output. If the digital I/O pins are not used, either
configure them as input and connect them to ground or
configure them as outputs. This will reduce power dissipation.
50
Clock Output (D0/CLKOUT)
The clock output can be a clock source for other processor.
30
25
Clock Generation
15
The chip clock source can be an external oscillator (need an
external crystal 7.68MHz), or an external clock source. When
the source is an oscillator, two capacitors (typically 5pF to
20pF) are needed to connect both of oscillator's output pins to
ground.
10
5
2.5
Standby Mode
Wake Up and First Valid Data
3 × nDRDY Duty Cycles
Standby Mode
SGM5860x
Status
t18
③
②
①
nDRDY
DIN
STANDBY
RDATA
STANDBY
WAKEUP
ADC Data
DOUT
Figure 13. One-Shot Conversions Using the STANDBY Command
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FEBRUARY 2022
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SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
DETAILED DESCRIPTION (continued)
Table 16. Self Offset and System Offset Calibration Timing
Calibration
The chip has offset calibration (OFCx) and gain calibration
(FSCx) registers, which is used to compensate and minimize
offset error and gain error of ADC results.
Self Offset Calibration and
Data Rate (1) (SPS)
System Offset Calibration Time
60000
30000
15000
7500
3750
2000
1000
500
100
60
226µs
392µs
Offset errors are corrected with the offset calibration registers
(OFCx) and gain errors are corrected with the full-scale
calibration registers (FSCx).
525µs
685µs
925µs
The output of the SGM5860x after calibration is given by:
1.4ms
(3)
2.4ms
PGA × V
3
4
IN
Output =
×
- OFC FSC
2VREF
4.4ms
20.4ms
33.7ms
40.4ms
67.1ms
80.4ms
134.0ms
200.3ms
400.4ms
800.3ms
OFC is a binary two's complement number, the ideal value is
0. FSC is unipolar, and the ideal number is 0x555555. OFC
and FSC keep the same with different data rate settlings. For
noise consideration, offset and full-scale errors can be
calibrated at a lower data rate.
50
30
25
15
The SGM5860x provides chip self calibration and system
10
calibration function (these are
a series of command
SELFOCAL, SELFGCAL, SELFCAL, SYSOCAL, and
SYSGCAL). Once calibration is initiated, nDRDY goes high
until the process is completed.
5
2.5
NOTE: 1. fCLKIN = 7.68MHz.
After
a reset, the chip issue a chip self calibration
Table 17. Self Gain Calibration Timing
automatically. Calibration should be performed after the
buffer configuration or PGA changes.
PGA Setting
Data Rate (1) (SPS)
1, 2
4, 8, 16, 32, 64, 128
780µs
Self-Calibration
The time required for self offset calibration for the different
data rate settings is shown in Table 16. The calibration time is
decreased with fCLKIN increasing. After a self-offset calibration,
OFC registers is updated automatically.
60000
30000
15000
7500
3750
2000
1000
500
100
60
337µs
592µs
1.37ms
792µs
1.83ms
992ms
1.4ms
2.3ms
3.2ms
The time required for self gain calibration under the different
data rate and PGA settings is shown in Table 17. Self gain
calibration can update the FSC registers.
2.1ms
4.9ms
3.6ms
8.4ms
6.6ms
15.4ms
30.6ms
50.6ms
60.6ms
100.6ms
120.4ms
200.5ms
300.0ms
600.2ms
1200ms
71.4ms
118.0ms
141.4ms
234.8ms
281.0ms
468.0ms
701.0ms
1400ms
2800ms
50
30
25
15
10
5
2.5
NOTE: 1. fCLKIN = 7.68MHz.
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SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
DETAILED DESCRIPTION (continued)
Table 19. System Gain (Offset) Calibration Timing
The time required for self-calibration under the different data
rate settings is shown in Table 18. Self-calibration can update
both the OFC and FSC registers.
Data Rate (1) (SPS)
System Gain Calibration Time
60000
30000
15000
7500
3750
2000
1000
500
100
60
229µs
400µs
Table 18. Self-Calibration Timing
528µs
PGA Setting
Data Rate (1) (SPS)
667µs
1, 2
4, 8, 16, 32, 64, 128
890µs
930µs
60000
30000
15000
7500
3750
2000
1000
500
100
60
447µs
1.4ms
780µs
1.55ms
2.09ms
2.63ms
3.7ms
2.4ms
1ms
4.4ms
1.3ms
20.4ms
33.7ms
40.4ms
67.0ms
80.4ms
133.7ms
200.4ms
400.4ms
800.4ms
1.8ms
2.8ms
5.5ms
50
4.8ms
9.5ms
30
8.8ms
17.5ms
81ms
25
40.8ms
67.4ms
80.8ms
134.1ms
160.8ms
267.2ms
400.6ms
800ms
1600ms
15
134ms
10
50
161ms
5
30
268ms
2.5
25
322ms
NOTE:
1. fCLKIN = 7.68MHz.
15
534ms
10
800ms
5
1600ms
3200ms
Auto-Calibration
Auto-calibration is allowed to enable (ACAL bit in STATUS
2.5
register) when completing the write command (WREG).
NOTE:
1. fCLKIN = 7.68MHz.
Serial Interface
The SGM5860x has an SPI-compatible interface, including
System Calibration
nCS, SCLK, DIN and DOUT.
To perform a system offset calibration, the user must supply a
zero input differential signal. The time required for system
offset calibration under the different data rate settings is
shown in Table 19. System offset calibration can update the
OFC registers.
Reset
There are two methods to reset the SGM5860x: the nRESET
input pin and RESET command.
To perform a system gain calibration, the user must supply a
full-scale input signal to the SGM5860x. The time required for
system gain calibration under the different data rate settings
is shown in Table 19. System gain calibration can update the
FSC registers.
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SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
DETAILED DESCRIPTION (continued)
Synchronization
Power-Down Mode
There are two kinds of ways to synchronize input sampling,
SYNC command and nSYNC/nPDWN pin control. The first
method is to shift in 8-bit SYNC command, this makes the
chip ready to synchronize, and then issue WAKEUP
command to synchronize the sampling of the input signal on
the first rising edge of SCLK shifted in by WAKEUP. The
second method is to pull nSYNC/nPDWN pin low and then
set it high, synchronization happens on the rising edge of
nSYNC/nPDWN.
In power-down mode, all circuits are turned off, including
oscillator and clock output. To enter power-down, set
nSYNC/nPDWN pin low and keep it for 20 nDRDY cycles.
To get out of power-down mode, set the nSYNC/nPDWN pin
high, it will take the chip about 30ms to wake up if an external
crystal oscillator is used. It will take about 8192 CLKIN cycles
to wake up if an external clock source is used.
Power-Up
After a power-up, all registers is reset to their default values.
And then a self-calibration is performed automatically. We still
suggest that one more self-calibration by user's own control
software before the system starts running.
Standby Mode
In standby mode, the chip turns off all analog circuits and
some of the digital circuits. The oscillator circuits still keep
working. A WAKEUP command lets the chip exit standby
mode. Details see Figure 13.
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SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
REGISTER MAPS
Table 20. Register Maps
Register
Address
Register
Name
Reset
Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
STATUS
MUX
x1h
01h
20h
F0h
E0h
xxh
xxh
xxh
xxh
xxh
xxh
ID[3:0]
ORDER
ACAL
BUFEN
nDRDY
PSEL[3:0]
CLK[1:0]
NSEL[3:0]
ADCON
DRATE
IO
0
SDCS[1:0]
PGA[2:0]
DR[7:0]
DIR[3:0]
DIO[3:0]
OFC0
OFC1
OFC2
FSC0
FSC1
FSC2
OFC[7:0]
OFC[15:8]
OFC[23:16]
FSC[7:0]
FSC[15:8]
FSC[23:16]
REF_
BUFP
REF_
BUFM
AIN_
BUFP
AIN_
BUFM
0Bh
STATUS2
00h
Reserved
STATUS: Status Register
Register address: 00h
Reset value = x1h
DEFAULT
VALUE
BITS
BIT NAME
DESCRIPTION
COMMENT
D[7:4]
ID[3:0]
Factory Programmable Identification Bits
Read only.
ORDER setting has no effect on input data.
Output data is always out by most significant byte firstly.
ORDER setting only has effect on the shifting out
sequence within byte.
0000
Data Output Bit Order
0 = Most significant bit first (default)
1 = Least significant bit first
D[3]
D[2]
ORDER
ACAL
0
When auto-calibration is enabled, self-calibration starts
at the completion of the WREG command that changes
the values of the PGA[2:0] bits in the ADCON register,
DR[7:0] in the DRATE register or BUFEN bit in the
STATUS register.
Auto-Calibration
0 = Auto-calibration disabled (default)
1 = Auto-calibration enabled
0
0
Analog Input Buffer Enable
0 = Buffer disabled. Positive and negative
buffers are controlled by AIN_BUFP and
AIN_BUFM further (default)
1 = Buffer enabled. Positive and negative
buffers are enabled no matter how AIN_BUFP,
AIN_BUFM are
D[1]
D[0]
BUFEN
nDRDY
Data Ready
Read only. This bit copies the status of nDRDY pin.
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SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
REGISTER MAPS (continued)
MUX: Input Multiplexer Control Register
Register address: 01h
Reset value = 01h
DEFAULT
BITS
BIT NAME
DESCRIPTION
COMMENT
VALUE
Positive Input Channel (AINP) Select
0000 = AIN0 (SGM5860x) (default)
0001 = AIN1 (SGM5860x)
0010 = AIN2 (SGM58601/2 only)
0011 = AIN3 (SGM58601/2 only)
0100 = AIN4 (SGM58601 only)
0101 = AIN5 (SGM58601 only)
0110 = AIN6 (SGM58601 only)
0111 = AIN7 (SGM58601 only)
1xxx = AINCOM (SGM58600/1 only)
Ensure only available inputs are selected when
using the SGM58600.
When PSEL[3] = 1, PSEL[2], PSEL[1], PSEL[0]
are don′t care.
D[7:4]
PSEL[3:0]
0000
Negative Input Channel (AINN) Select
0000 = AIN0 (SGM5860x)
0001 = AIN1 (SGM5860x) (default)
0010 = AIN2 (SGM58601/2 only)
0011 = AIN3 (SGM58601/2 only)
0100 = AIN4 (SGM58601 only)
0101 = AIN5 (SGM58601 only)
0110 = AIN6 (SGM58601 only)
0111 = AIN7 (SGM58601 only)
1xxx = AINCOM (SGM58600/1 only)
Ensure to only select the available inputs when
using the SGM58600.
When NSEL[3] = 1, NSEL[2], NSEL[1], NSEL[0]
are don′t care.
D[3:0]
NSEL[3:0]
0001
ADCON: A/D Control Register
Register address: 02h
Reset value = 20h
DEFAULT
BITS
BIT NAME
DESCRIPTION
Reserved. Always 0.
COMMENT
VALUE
D[7]
Reserved
Read only.
0
D0/CLKOUT Clock Out Rate
00 = Clock out off
01 = Clock out frequency = fCLKIN (default)
10 = Clock out frequency = fCLKIN/2
11 = Clock out frequency = fCLKIN/4
When CLKOUT is not used, it is recommended
to turn it off.
D[6:5]
D[4:3]
CLK[1:0]
01
Sensor Detection Current Sources
00 = Sensor detection off (default)
01 = Sensor detection current = 0.5μA
10 = Sensor detection current = 2μA
11 = Sensor detection current = 9μA
SDCS[1:0]
00
Programmable Gain Amplifier
000 = 1 (default)
001 = 2
010 = 4
D[2:0]
PGA[2:0]
011 = 8
000
100 = 16
101 = 32
110 = 64
111 = 128
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SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
REGISTER MAPS (continued)
DRATE: A/D Data Rate Register
Register address: 03h
Reset value = F0h
DEFAULT
BITS
BIT NAME
DESCRIPTION
COMMENT
VALUE
Data Rate
11110001 = 60000SPS
11110000 = 30000SPS (default)
11100000 = 15000SPS
11010000 = 7500SPS
11000000 = 3750SPS
10110000 = 2000SPS
10100001 = 1000SPS
10010010 = 500SPS
10000010 = 100SPS
01110010 = 60SPS
The 17 valid data rate settings are shown in the
table.
D[7:0]
DR[7:0]
11110000
01100011 = 50SPS
01010011 = 30SPS
01000011 = 25SPS
00110011 = 15SPS
00100011 = 10SPS
00010011 = 5SPS
00000011 = 2.5SPS
IO: GPIO Control Register
Register address: 04h
Reset value = E0h
DEFAULT
BITS
BIT NAME
DESCRIPTION
COMMENT
VALUE
Digital I/O Direction for Pin D3
DIR[3] 0 = It's an output
For SGM58601 only.
For SGM58601 only.
1
1
1
0
1 = It's an input (default)
Digital I/O Direction for Pin D2
DIR[2] 0 = It's an output
1 = It's an input (default)
D[7:4] DIR[3:0]
Digital I/O Direction for Pin D1
DIR[1] 0 = It's an output
1 = It's an input (default)
Digital I/O Direction for Pin D0/CLKOUT
DIR[0] 0 = It's an output (default)
1 = It's an input
It’s used for GPIO pins data read and write.
When the GPIO pin is an input configuration, a
write operation has no effect on it.
D[3:0]
DIO[3:0]
Status of Digital I/O Pins D3, D2, D1, D0/CLKOUT
A read operation is effective on both input pins
and output pins.
0000
When D0/CLKOUT is used for clock output,
DIO[0] setting has no effect.
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SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
REGISTER MAPS (continued)
OFC0: Offset Calibration Byte 0 - Least Significant Byte
Register address: 05h
Reset value is determined by the calibration results.
BITS
7
6
5
4
3
2
2
2
2
2
2
1
1
1
1
1
1
0
0
0
0
0
0
BIT NAME
OFC[7:0]
OFC1: Offset Calibration Byte 1
Register address: 06h
Reset value is determined by the calibration results.
BITS
7
6
5
4
3
BIT NAME
OFC[15:8]
OFC2: Offset Calibration Byte 2 - Most Significant Byte
Register address: 07h
Reset value is determined by the calibration results.
BITS
7
6
5
4
3
BIT NAME
OFC[23:16]
FSC0: Full-Scale Calibration Byte 0 - Least Significant Byte
Register address: 08h
Reset value is determined by the calibration results.
BITS
7
6
5
4
3
BIT NAME
FSC[7:0]
FSC1: Full-Scale Calibration Byte 1
Register address: 09h
Reset value is determined by the calibration results.
BITS
7
6
5
4
3
BIT NAME
FSC[15:8]
FSC2: Full-Scale Calibration Byte 2 - Most Significant Byte
Register address: 0Ah
Reset value is determined by the calibration results.
BITS
7
6
5
4
3
BIT NAME
FSC[23:16]
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SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
REGISTER MAPS (continued)
STATUS2: Status2 Register
Register address: 0Bh
Reset Value = 00h
DEFAULT
BITS
BIT NAME
DESCRIPTION
COMMENT
VALUE
D[7:4]
Reserved
Reserved, should be always set 0000.
0000
0
Positive Reference Input Buffer Enable
0 = Buffer disabled (default)
1 = Buffer enabled
D[3]
D[2]
D[1]
D[0]
REF_BUFP
REF_BUFM
AIN_BUFP
AIN_BUFM
Negative Reference Input Buffer Enable
0 = Buffer disabled (default)
1 = Buffer enabled
0
Positive Analog Input Buffer Enable
0 = Buffer disabled (default)
1 = Buffer enabled
Functions when BUFEN = 0.
Functions when BUFEN = 0.
0
0
Negative Analog Input Buffer Enable
0 = Buffer disabled (default)
1 = Buffer enabled
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SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
COMMAND DEFINITIONS
Table 21 summarizes the commands that control the operation of the SGM5860x. All commands are single byte excluding RREG
and WREG.
Table 21. Command Definitions
Command
WAKEUP
RDATA (2)
RDATAC (2)
SDATAC (2)
RREG
Description
Complete SYNC and Exit Standby Mode
Read Data
First Command Byte
0000 0000 (00h)
0000 0001 (01h)
0000 0011 (03h)
0000 1111 (0Fh)
0001 ssss (1xh)
0101 ssss (5xh)
1111 0000 (F0h)
1111 0001 (F1h)
1111 0010 (F2h)
1111 0011 (F3h)
1111 0100 (F4h)
1111 1100 (FCh)
1111 1101 (FDh)
1111 1110 (FEh)
1111 1111 (FFh)
Second Command Byte
Read Data Continuous
Stop Read Data Continuous
Read from Register ssss
Write to Register ssss
0000 qqqq
0000 qqqq
WREG
SELFCAL
SELFOCAL
SELFGCAL
SYSOCAL
SYSGCAL
SYNC
Offset and Gain Self-Calibration
Offset Self-Calibration
Gain Self-Calibration
System Offset Calibration
System Gain Calibration
Synchronize the A/D Conversion
Begin Standby Mode
STANDBY
RESET (2)
WAKEUP
Reset to Power-Up Values
Complete SYNC and Exit Standby Mode
NOTE:
1. qqqq = number of registers to be read/written - 1. For example, to read/write three registers, set qqqq = 0b0010. ssss = starting register
address for read/write commands.
2. Issue this command after nDRDY goes low.
SELFCAL: Offset and Gain Self-Calibration
Issue an offset and gain self-calibration command. When the
calibration starts, nDRDY goes high. When the calibration
completes, nDRDY goes low, and settled data is ready. Do
not perform any more operation during this calibration.
SYSOCAL: System Offset Calibration
Issue a system offset calibration command. When beginning
the calibration, nDRDY goes high. When the calibration
completes, nDRDY goes low, and settled data is ready. Do
not do any more operation during this calibration.
SELFOCAL: Offset Self-Calibration
SYSGCAL: System Gain Calibration
Issue an offset self-calibration command. When beginning the
calibration, nDRDY goes high. When the calibration
completes, nDRDY goes low, and settled data is ready. Do
not do any more operation during this calibration.
Issue a system gain calibration command. When beginning
the calibration, nDRDY goes high. When the calibration
completes, nDRDY goes low, and settled data is ready. Do
not do any more operation during this calibration.
SELFGCAL: Gain Self-Calibration
RESET: Reset Registers to Default Values
Reset all registers to default values except CLK[1:0] setting
(which is in ADCON register).
Issue a gain self-calibration command. When beginning the
calibration, nDRDY goes high. When the calibration
completes, nDRDY goes low, and settled data is ready. Do
not do any more operation during this calibration.
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SGM58600
Ultra-Low Noise,
SGM58601/SGM58602
24-Bit Analog-to-Digital Converters
COMMAND DEFINITIONS (continued)
WAKEUP: Complete SYNC or Exit Standby
Mode
The WAKEUP command is used in conjunction with the
SYNC and STANDBY commands. It provides two values: all
zeros or all ones.
RDATAC: Read Data Continuous
When nDRDY is low, issue the RDATAC command, the chip
will give out ADC conversion results continuously, see details
in Figure 14.
nDRDY
RDATAC
DIN
t6
ADC Data
ADC Data
ADC Data
DOUT
Figure 14. RDATAC Command Sequence
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (FEBRUARY 2022) to REV.A
Page
Changed from product preview to production data .................................................................................................................................................All
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30
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
SSOP-20
D
2.25
6.55
E
E1
b
e
0.43
0.65
RECOMMENDED LAND PATTERN (Unit: mm)
L
A
A1
c
θ
A2
Dimensions
In Millimeters
Dimensions
In Inches
Symbol
MIN
MAX
MIN
MAX
A
A1
A2
b
1.730
0.230
1.600
0.380
0.250
7.400
5.500
8.000
0.068
0.009
0.063
0.015
0.010
0.291
0.217
0.315
0.050
1.400
0.220
0.090
7.000
5.100
7.600
0.002
0.055
0.009
0.004
0.276
0.201
0.299
c
D
E
E1
e
0.65 BSC
0.026 BSC
L
0.550
0°
0.950
8°
0.022
0°
0.037
8°
θ
NOTES:
1. Body dimensions do not include mode flash or protrusion.
2. This drawing is subject to change without notice.
SG Micro Corp
TX00027.000
www.sg-micro.com
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
SSOP-28
D
E1
E
6.55
2.25
b
e
0.43
0.65
RECOMMENDED LAND PATTERN (Unit: mm)
L
A
A1
θ
A2
c
Dimensions
In Millimeters
Dimensions
In Inches
Symbol
MIN
MAX
MIN
MAX
A
A1
A2
b
2.000
0.079
0.050
1.650
0.220
0.090
9.900
5.000
7.400
0.002
0.065
0.009
0.004
0.390
0.197
0.291
1.850
0.380
0.250
10.500
5.600
8.200
0.073
0.015
0.010
0.413
0.220
0.323
c
D
E
E1
e
0.65 BSC
0.026 BSC
L
0.550
0°
0.950
8°
0.022
0°
0.037
8°
θ
NOTES:
1. Body dimensions do not include mode flash or protrusion.
2. This drawing is subject to change without notice.
SG Micro Corp
TX00029.000
www.sg-micro.com
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
TQFN-3.5×3.5-20L
D
N20
PIN 1#
N1
D1
e
E
E1
L
DETAIL A
b
TOP VIEW
BOTTOM VIEW
2.05
0.85
A
A1
A2
SIDE VIEW
2.05
2.60 4.30
ALTERNATE A-1
ALTERNATE A-2
0.28
0.50
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTION
RECOMMENDED LAND PATTERN (Unit: mm)
Dimensions In Millimeters
Symbol
MIN
0.700
-
MOD
0.750
MAX
0.800
0.050
A
A1
A2
D
-
0.203 REF
3.500
3.450
2.000
3.450
2.000
0.200
3.550
2.100
3.550
2.100
0.300
D1
E
2.050
3.500
E1
b
2.050
0.250
e
0.500 BSC
0.400
L
0.350
0.450
NOTE: This drawing is subject to change without notice.
SG Micro Corp
TX00190.000
www.sg-micro.com
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
TQFN-5×5-20L
D
N20
PIN 1#
N1
D1
E1
E
e
L
DETAIL A
b
TOP VIEW
BOTTOM VIEW
3.15
A
A1
A2
SIDE VIEW
3.15
3.90 5.60
ALTERNATE A-1 ALTERNATE A-2
0.85
0.30
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTION
0.65
RECOMMENDED LAND PATTERN (Unit: mm)
Dimensions In Millimeters
Symbol
MIN
MOD
0.750
MAX
0.800
0.050
A
A1
A2
D
0.700
0.000
-
0.203 REF
5.000
4.950
3.100
4.950
3.100
0.250
5.050
3.200
5.050
3.200
0.350
D1
E
3.150
5.000
E1
b
3.150
0.300
e
0.650 BSC
0.550
L
0.500
0.600
NOTE: This drawing is subject to change without notice.
SG Micro Corp
TX00191.000
www.sg-micro.com
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
TQFN-5×5-28L
D
N28
PIN 1#
N1
D1
E
E1
e
DETAIL A
b
L
TOP VIEW
BOTTOM VIEW
3.15
A
A1
A2
SIDE VIEW
4.10
3.15
5.60
ALTERNATE A-1 ALTERNATE A-2
0.75
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTION
0.25
0.50
RECOMMENDED LAND PATTERN (Unit: mm)
Dimensions In Millimeters
Symbol
MIN
MOD
0.750
MAX
0.800
0.050
A
A1
A2
D
0.700
0.000
-
0.203 REF
5.000
4.950
3.100
4.950
3.100
0.200
5.050
3.200
5.050
3.200
0.300
D1
E
3.150
5.000
E1
b
3.150
0.250
e
0.500 BSC
0.450
L
0.400
0.500
NOTE: This drawing is subject to change without notice.
SG Micro Corp
TX00088.001
www.sg-micro.com
PACKAGE INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
P2
P0
W
Q2
Q4
Q2
Q4
Q2
Q4
Q1
Q3
Q1
Q3
Q1
Q3
B0
Reel Diameter
P1
A0
K0
Reel Width (W1)
DIRECTION OF FEED
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF TAPE AND REEL
Reel Width
Reel
Diameter
A0
B0
K0
P0
P1
P2
W
Pin1
Package Type
W1
(mm)
(mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant
SSOP-20
SSOP-28
13″
13″
13″
13″
13″
12.4
16.4
12.4
12.4
12.4
8.15
8.20
3.80
5.30
5.30
7.60
10.50
3.80
5.30
5.30
1.88
0.30
0.95
1.10
1.10
4.0
4.0
4.0
4.0
4.0
12.0
12.0
8.0
2.0
2.0
2.0
2.0
2.0
16.0
16.0
12.0
12.0
12.0
Q1
Q1
Q2
Q2
Q2
TQFN-3.5×3.5-20L
TQFN-5×5-20L
TQFN-5×5-28L
8.0
8.0
SG Micro Corp
TX10000.000
www.sg-micro.com
PACKAGE INFORMATION
CARTON BOX DIMENSIONS
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF CARTON BOX
Length
(mm)
Width
(mm)
Height
(mm)
Reel Type
Pizza/Carton
13″
386
280
370
5
SG Micro Corp
www.sg-micro.com
TX20000.000
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