LH28F160S5HNS-S1 [SHARP]
Flash, 1MX16, 90ns, PDSO56, 16 X 23.70 MM, 1.80 MM HEIGHT, LEAD FREE, PLASTIC, SSOP-56;
| 型号： | LH28F160S5HNS-S1 |
| 厂家： | 
SHARP ELECTRIONIC COMPONENTS |
| 描述： | Flash, 1MX16, 90ns, PDSO56, 16 X 23.70 MM, 1.80 MM HEIGHT, LEAD FREE, PLASTIC, SSOP-56 光电二极管 内存集成电路 |
| 文件： | 总63页 (文件大小：691K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY PRODUCT SPECIFICATION
Integrated Circuits Group
LH28F160S5HNS-S1
Flash Memory
16Mbit (2Mbitx8/1Mbitx16)
(Model Number: LHF16KS1)
Lead-free (Pb-free)
Spec. Issue Date: October 8, 2004
Spec No: EL16X079
LHF16KS1
●Handle this document carefully for it contains material protected by international copyright
law. Any reproduction, full or in part, of this material is prohibited without the express
written permission of the company.
●When using the products covered herein, please observe the conditions written herein
and the precautions outlined in the following paragraphs. In no event shall the company
be liable for any damages resulting from failure to strictly adhere to these conditions and
precautions.
(1) The products covered herein are designed and manufactured for the following
application areas. When using the products covered herein for the equipment listed
in Paragraph (2), even for the following application areas, be sure to observe the
precautions given in Paragraph (2). Never use the products for the equipment listed
in Paragraph (3).
•Office electronics
•Instrumentation and measuring equipment
•Machine tools
•Audiovisual equipment
•Home appliance
•Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment
which demands high reliability, should first contact a sales representative of the
company and then accept responsibility for incorporating into the design fail-safe
operation, redundancy, and other appropriate measures for ensuring reliability and
safety of the equipment and the overall system.
•Control and safety devices for airplanes, trains, automobiles, and other
transportation equipment
•Mainframe computers
•Traffic control systems
•Gas leak detectors and automatic cutoff devices
•Rescue and security equipment
•Other safety devices and safety equipment, etc.
(3) Do not use the products covered herein for the following equipment which demands
extremely high performance in terms of functionality, reliability, or accuracy.
•Aerospace equipment
•Communications equipment for trunk lines
•Control equipment for the nuclear power industry
•Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above
three Paragraphs to a sales representative of the company.
●Please direct all queries regarding the products covered herein to a sales representative
of the company.
Rev. 2.0
LHF16KS1
1
CONTENTS
PAGE
PAGE
1 INTRODUCTION ...................................................... 3
5 DESIGN CONSIDERATIONS .................................30
5.1 Three-Line Output Control .................................30
5.2 STS and Block Erase, Full Chip Erase, (Multi)
Word/Byte Write and Block Lock-Bit Configuration
Polling................................................................30
5.3 Power Supply Decoupling..................................30
1.1 Product Overview................................................ 3
2 PRINCIPLES OF OPERATION................................ 6
2.1 Data Protection ................................................... 7
5.4 V Trace on Printed Circuit Boards..................30
3 BUS OPERATION.................................................... 7
3.1 Read ................................................................... 7
3.2 Output Disable .................................................... 7
3.3 Standby............................................................... 7
3.4 Deep Power-Down.............................................. 7
3.5 Read Identifier Codes Operation......................... 8
3.6 Query Operation.................................................. 8
3.7 Write.................................................................... 8
PP
5.5 V , V , RP# Transitions.................................31
CC
PP
5.6 Power-Up/Down Protection................................31
5.7 Power Dissipation ..............................................31
6 ELECTRICAL SPECIFICATIONS...........................32
6.1 Absolute Maximum Ratings ...............................32
6.2 Operating Conditions .........................................32
6.2.1 Capacitance .................................................32
6.2.2 AC Input/Output Test Conditions..................33
6.2.3 DC Characteristics........................................34
6.2.4 AC Characteristics - Read-Only Operations .36
6.2.5 AC Characteristics - Write Operations..........39
6.2.6 Alternative CE#-Controlled Writes................41
6.2.7 Reset Operations .........................................43
6.2.8 Block Erase, Full Chip Erase, (Multi)
4 COMMAND DEFINITIONS....................................... 8
4.1 Read Array Command....................................... 11
4.2 Read Identifier Codes Command...................... 11
4.3 Read Status Register Command....................... 11
4.4 Clear Status Register Command....................... 11
4.5 Query Command............................................... 12
4.5.1 Block Status Register .................................. 12
4.5.2 CFI Query Identification String..................... 13
4.5.3 System Interface Information....................... 13
4.5.4 Device Geometry Definition......................... 14
4.5.5 SCS OEM Specific Extended Query Table.. 14
4.6 Block Erase Command...................................... 15
4.7 Full Chip Erase Command ................................ 15
4.8 Word/Byte Write Command............................... 16
4.9 Multi Word/Byte Write Command...................... 16
4.10 Block Erase Suspend Command..................... 17
4.11 (Multi) Word/Byte Write Suspend Command... 17
4.12 Set Block Lock-Bit Command.......................... 18
4.13 Clear Block Lock-Bits Command..................... 18
4.14 STS Configuration Command ......................... 19
Word/Byte Write and Block Lock-Bit
Configuration Performance...........................44
7 ADDITIONAL INFORMATION ................................45
7.1 Ordering Information..........................................45
8 PACKAGE AND PACKING SPECIFICATION........46
Rev. 2.0
LHF16KS1
2
LH28F160S5HNS-S1
16M-BIT (2MBx8/1MBx16)
Smart 5 Flash MEMORY
● Smart 5 Technology
● Enhanced Data Protection Features
5V V
5V V
Absolute Protection with V =GND
CC
PP
PP
Flexible Block Locking
Erase/Write Lockout during Power
Transitions
● Common Flash Interface (CFI)
Universal & Upgradable Interface
● Extended Cycling Capability
100,000 Block Erase Cycles
● Scalable Command Set (SCS)
3.2 Million Block Erase Cycles/Chip
● High Speed Write Performance
32 Bytes x 2 plane Page Buffer
2µs/Byte Write Transfer Rate
● Low Power Management
Deep Power-Down Mode
Automatic Power Savings Mode
● High Speed Read Performance
Decreases I in Static Mode
CC
70ns(5V±0.25V), 90ns(5V±0.5V)
● Automated Write and Erase
Command User Interface
Status Register
● Operating Temperature
-40°C to +85°C
● Enhanced Automated Suspend Options
Write Suspend to Read
● Industry-Standard Packaging
56-Lead SSOP
Block Erase Suspend to Write
Block Erase Suspend to Read
TM*
● ETOX
V Nonvolatile Flash
Technology
● High-Density Symmetrically-Blocked
Architecture
● CMOS Process
Thirty-two 64K-byte Erasable Blocks
(P-type silicon substrate)
● SRAM-Compatible Write Interface
● Not designed or rated as radiation
hardened
● User-Configurable x8 or x16 Operation
SHARP’s LH28F160S5HNS-S1 Flash memory with Smart 5 technology is a high-density, low-cost, nonvolatile,
read/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage
and extended cycling provide for highly flexible component suitable for resident flash arrays, SIMMs and memory
cards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For
secure code storage applications, such as networking, where code is either directly executed out of flash or
downloaded to DRAM, the LH28F160S5HNS-S1 offers three levels of protection: absolute protection with V at
PP
GND, selective hardware block locking, or flexible software block locking. These alternatives give designers
ultimate control of their code security needs.
The LH28F160S5HNS-S1 is conformed to the flash Scalable Command Set (SCS) and the Common Flash
Interface (CFI) specification which enable universal and upgradable interface, enable the highest system/device
data transfer rates and minimize device and system-level implementation costs.
TM
The LH28F160S5HNS-S1 is manufactured on SHARP’s 0.35µm ETOX * V process technology. It come in
industry-standard package: the 56-Lead SSOP, ideal for board constrained applications.
*ETOX is a trademark of Intel Corporation.
Rev. 2.0
LHF16KS1
3
execute code from any other flash memory array
location.
1 INTRODUCTION
This datasheet contains LH28F160S5HNS-S1
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications.
Individual block locking uses a combination of bits
and WP#, Thirty-two block lock-bits, to lock and
unlock blocks. Block lock-bits gate block erase, full
chip erase and (multi) word/byte write operations.
Block lock-bit configuration operations (Set Block
Lock-Bit and Clear Block Lock-Bits commands) set
and cleared block lock-bits.
1.1 Product Overview
The LH28F160S5HNS-S1 is a high-performance
16M-bit Smart 5 Flash memory organized as
2MBx8/1MBx16. The 2MB of data is arranged in
thirty-two 64K-byte blocks which are individually
erasable, lockable, and unlockable in-system. The
memory map is shown in Figure 3.
The status register indicates when the WSM’s block
erase, full chip erase, (multi) word/byte write or block
lock-bit configuration operation is finished.
The STS output gives an additional indicator of WSM
activity by providing both a hardware signal of status
(versus software polling) and status masking
(interrupt masking for background block erase, for
example). Status polling using STS minimizes both
CPU overhead and system power consumption. STS
pin can be configured to different states using the
Configuration command. The STS pin defaults to
RY/BY# operation. When low, STS indicates that the
WSM is performing a block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration.
STS-High Z indicates that the WSM is ready for a
new command, block erase is suspended and (multi)
word/byte write are inactive, (multi) word/byte write
are suspended, or the device is in deep power-down
mode. The other 3 alternate configurations are all
pulse mode for use as a system interrupt.
Smart 5 technology provides a choice of V
and
CC
V
combinations, as shown in Table 1, to meet
PP
system performance and power expectations. 5V V
CC
provides the highest read performance. V
at 5V
PP
eliminates the need for a separate 12V converter,
while =5V maximizes erase and write
performance. In addition to flexible erase and
V
PP
program voltages, the dedicated V
pin gives
PP
complete data protection when V ≤V
.
PP
PPLK
Table 1. V and V Voltage Combinations
CC
PP
Offered by Smart 5 Technology
V
Voltage
V
Voltage
CC
PP
5V
5V
Internal
V
and
V
detection Circuitry
CC
PP
The access time is 70ns (t
temperature range (-40°C to +85°C) and V
voltage range of 4.75V-5.25V. At lower V
) over the extended
AVQV
automatically configures the device for optimized
read and write operations.
supply
CC
voltage,
CC
the access time is 90ns (4.5V-5.5V).
A Command User Interface (CUI) serves as the
interface between the system processor and internal
operation of the device. A valid command sequence
written to the CUI initiates device automation. An
internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration operations.
The Automatic Power Savings (APS) feature
substantially reduces active current when the device
is in static mode (addresses not switching). In APS
mode, the typical I
current is 1 mA at 5V V
.
CCR
CC
When either CE # or CE #, and RP# pins are at V ,
CC
0
1
the I
CMOS standby mode is enabled. When the
CC
RP# pin is at GND, deep power-down mode is
enabled which minimizes power consumption and
provides write protection during reset. A reset time
A block erase operation erases one of the device’s
64K-byte blocks typically within 0.34s (5V V , 5V
CC
V
) independent of other blocks. Each block can be
PP
(t
) is required from RP# switching high until
PHQV
independently erased 100,000 times (3.2 million
block erases per device). Block erase suspend mode
allows system software to suspend block erase to
read or write data from any other block.
outputs are valid. Likewise, the device has a wake
time (t ) from RP#-high until writes to the CUI are
PHEL
recognized. With RP# at GND, the WSM is reset and
the status register is cleared.
A word/byte write is performed in byte increments
typically within 9.24µs (5V V , 5V V ). A multi
The device is available in 56-Lead SSOP (Shrink
Small Outline Package). Pinout is shown in Figure 2.
CC
PP
word/byte write has high speed write performance of
2µs/byte (5V V , 5V V ). (Multi) Word/byte write
CC
PP
suspend mode enables the system to read data or
Rev. 2.0
LHF16KS1
4
DQ0-DQ15
Output
Buffer
Input
Buffer
Query
ROM
VCC
I/O Logic
BYTE#
Idenrifier
Register
CE#
WE#
OE#
RP#
WP#
Command
Register
Status
Register
D
a
a
P
g
e
Multiplexer
Data
Comparator
STS
VPP
Y
Input
Y Gating
Decoder
A0-A20
Write State
Machine
Buffer
Program/Erase
Voltage Switch
VCC
Address
Latch
X
32
64KByte
Blocks
Decoder
GND
Address
Counter
Figure 1. Block Diagram
1
56
CE0#
VPP
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A12
A13
A14
A15
NC
CE1#
NC
A20
A19
A18
A17
A16
VCC
GND
DQ6
DQ14
DQ7
RP#
A11
A10
A9
A1
A2
A3
A4
A5
A6
A7
GND
A8
VCC
DQ9
DQ1
DQ8
DQ0
A0
BYTE#
NC
NC
DQ2
DQ10
DQ3
DQ11
GND
56 LEAD SSOP
PINOUT
1.8mm x 16mm x 23.7mm
TOP VIEW
DQ15
STS
OE#
WE#
WP#
DQ13
DQ5
DQ12
DQ4
VCC
Figure 2. SSOP 56-Lead Pinout
Rev. 2.0
LHF16KS1
5
Table 2. Pin Descriptions
Symbol
Type
Name and Function
ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are
internally latched during a write cycle.
A0: Byte Select Address. Not used in x16 mode(can be floated).
A1-A4: Column Address. Selects 1 of 16 bit lines.
A -A
INPUT
0
20
A5-A15: Row Address. Selects 1 of 2048 word lines.
A16-A20 : Block Address.
DATA INPUT/OUTPUTS:
DQ -DQ :Inputs data and commands during CUI write cycles; outputs data during memory
0
7
array, status register, query, and identifier code read cycles. Data pins float to high-
impedance when the chip is deselected or outputs are disabled. Data is internally latched
during a write cycle.
INPUT/
OUTPUT
DQ -DQ
0
15
DQ -DQ :Inputs data during CUI write cycles in x16 mode; outputs data during memory
8
15
array read cycles in x16 mode; not used for status register, query and identifier code read
mode. Data pins float to high-impedance when the chip is deselected, outputs are
disabled, or in x8 mode(Byte#=V ). Data is internally latched during a write cycle.
IL
CHIP ENABLE: Activates the device’s control logic, input buffers decoders, and sense
CE #,
0
INPUT
INPUT
amplifiers. Either CE # or CE # V deselects the device and reduces power consumption
0
1
IH
CE #
1
to standby levels. Both CE # and CE # must be V to select the devices.
0
1
IL
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets
internal automation. RP# V enables normal operation. When driven V , RP# inhibits
IH
IL
RP#
write operations which provides data protection during power transitions. Exit from deep
power-down sets the device to read array mode.
OE#
WE#
INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
INPUT
latched on the rising edge of the WE# pulse.
STS (RY/BY#): Indicates the status of the internal WSM. When configured in level mode
(default mode), it acts as a RY/BY# pin. When low, the WSM is performing an internal
OPEN
DRAIN
OUTPUT
operation (block erase, full chip erase, (multi) word/byte write or block lock-bit
configuration). STS High Z indicates that the WSM is ready for new commands, block
erase is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is
suspended or the device is in deep power-down mode. For alternate configurations of the
STATUS pin, see the Configuration command.
STS
WRITE PROTECT: Master control for block locking. When V , Locked blocks can not be
erased and programmed, and block lock-bits can not be set and reset.
IL
WP#
INPUT
INPUT
BYTE ENABLE: BYTE# V places device in x8 mode. All data is then input or output on
IL
BYTE#
DQ , and DQ
float. BYTE# V places the device in x16 mode , and turns off the A
0-7
8-15
I
H
0
input buffer.
BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE, BLOCK LOCK-
BIT CONFIGURATION POWER SUPPLY: For erasing array blocks, writing bytes or
V
SUPPLY
configuring block lock-bits. With V ≤V
, memory contents cannot be altered. Block
PP
PP
PPLK
erase, full chip erase, (multi) word/byte write and block lock-bit configuration with an invalid
(see DC Characteristics) produce spurious results and should not be attempted.
V
PP
DEVICE POWER SUPPLY: Internal detection configures the device for 5V operation. Do
, all write attempts to the flash memory are
not float any power pins. With V ≤V
CC
LKO
V
SUPPLY
CC
inhibited. Device operations at invalid V voltage (see DC Characteristics) produce
CC
spurious results and should not be attempted.
GND
NC
SUPPLY GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internal connected; it may be driven or floated.
Rev. 2.0
LHF16KS1
6
2 PRINCIPLES OF OPERATION
1FFFFF
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
The LH28F160S5HNS-S1 Flash memory includes an
on-chip WSM to manage block erase, full chip erase,
(multi) word/byte write and block lock-bit
configuration functions. It allows for: 100% TTL-level
control inputs, fixed power supplies during block
erase, full chip erase, (multi) word/byte write and
block lock-bit configuration, and minimal processor
overhead with RAM-Like interface timings.
1F0000
1EFFFF
1E0000
1DFFFF
1D0000
1CFFFF
1C0000
1BFFFF
1B0000
1AFFFF
1A0000
19FFFF
After initial device power-up or return from deep
power-down mode (see Bus Operations), the device
defaults to read array mode. Manipulation of external
memory control pins allow array read, standby, and
output disable operations.
190000
18FFFF
180000
17FFFF
170000
16FFFF
160000
15FFFF
Status register, query structure and identifier codes
can be accessed through the CUI independent of the
150000
14FFFF
V
voltage. High voltage on V enables successful
PP
PP
140000
13FFFF
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration. All functions
associated with altering memory contents⎯block
erase, full chip erase, (multi) word/byte write and
block lock-bit configuration, status, query and
identifier codes⎯are accessed via the CUI and
verified through the status register.
130000
12FFFF
120000
11FFFF
110000
10FFFF
100000
0FFFFF
0F0000
0EFFFF
Commands
are
written
using
standard
0E0000
0DFFFF
microprocessor write timings. The CUI contents serve
as input to the WSM, which controls the block erase,
full chip erase, (multi) word/byte write and block lock-
bit configuration. The internal algorithms are
regulated by the WSM, including pulse repetition,
internal verification, and margining of data.
Addresses and data are internally latch during write
cycles. Writing the appropriate command outputs
array data, accesses the identifier codes, outputs
query structure or outputs status register data.
0D0000
0CFFFF
0C0000
0BFFFF
0B0000
0AFFFF
0A0000
09FFFF
090000
08FFFF
8
080000
07FFFF
7
Interface software that initiates and polls progress of
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration can be stored in any
block. This code is copied to and executed from
system RAM during flash memory updates. After
successful completion, reads are again possible via
the Read Array command. Block erase suspend
allows system software to suspend a block erase to
read or write data from any other block. Write
suspend allows system software to suspend a (multi)
word/byte write to read data from any other flash
memory array location.
070000
06FFFF
6
060000
05FFFF
5
050000
04FFFF
4
040000
03FFFF
3
030000
02FFFF
2
020000
01FFFF
1
010000
00FFFF
0
000000
Figure 3. Memory Map
Rev. 2.0
LHF16KS1
7
2.1 Data Protection
3.2 Output Disable
Depending on the application, the system designer
With OE# at a logic-high level (V ), the device
IH
may choose to make the V
power supply
outputs are disabled. Output pins DQ -DQ
are
PP
0
15
switchable (available only when block erase, full chip
erase, (multi) word/byte write and block lock-bit
placed in a high-impedance state.
configuration are required) or hardwired to V
.
3.3 Standby
PPH1
The device accommodates either design practice and
encourages optimization of the processor-memory
interface.
Either CE # or CE # at a logic-high level (V ) places
0
1
IH
the device in standby mode which substantially
reduces device power consumption. DQ -DQ
0
15
When V ≤V
, memory contents cannot be
PPLK
outputs are placed in a high-impedance state
independent of OE#. If deselected during block
erase, full chip erase, (multi) word/byte write and
block lock-bit configuration, the device continues
functioning, and consuming active power until the
operation completes.
PP
altered. The CUI, with multi-step block erase, full chip
erase, (multi) word/byte write and block lock-bit
configuration
command
sequences,
provides
protection from unwanted operations even when high
voltage is applied to V . All write functions are
PP
disabled when V is below the write lockout voltage
CC
V
or when RP# is at V . The device’s block
3.4 Deep Power-Down
LKO
IL
locking capability provides additional protection from
inadvertent code or data alteration by gating block
erase, full chip erase and (multi) word/byte write
operations.
RP# at V initiates the deep power-down mode.
IL
In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low for
3 BUS OPERATION
a minimum of 100 ns. Time t
is required after
PHQV
return from power-down until initial memory access
outputs are valid. After this wake-up interval, normal
operation is restored. The CUI is reset to read array
mode and status register is set to 80H.
The local CPU reads and writes flash memory in-
system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
3.1 Read
During block erase, full chip erase, (multi) word/byte
write or block lock-bit configuration modes, RP#-low
will abort the operation. STS remains low until the
reset operation is complete. Memory contents being
altered are no longer valid; the data may be partially
Information can be read from any block, identifier
codes, query structure, or status register independent
of the V voltage. RP# must be at V .
PP
IH
erased or written. Time t
is required after RP#
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes, Query
or Read Status Register) to the CUI. Upon initial
device power-up or after exit from deep power-down
mode, the device automatically resets to read array
mode. Five control pins dictate the data flow in and
out of the component: CE# (CE #, CE #), OE#, WE#,
PHWL
goes to logic-high (V ) before another command can
IH
be written.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase, full
chip erase, (multi) word/byte write and block lock-bit
configuration. If a CPU reset occurs with no flash
memory reset, proper CPU initialization may not
occur because the flash memory may be providing
status information instead of array data. SHARP’s
flash memories allow proper CPU initialization
following a system reset through the use of the RP#
input. In this application, RP# is controlled by the
same RESET# signal that resets the system CPU.
0
1
RP# and WP#. CE #, CE # and OE# must be driven
0
1
active to obtain data at the outputs. CE #, CE # is
0
1
the device selection control, and when active enables
the selected memory device. OE# is the data output
(DQ -DQ ) control and when active drives the
0
15
selected memory data onto the I/O bus. WE# and
RP# must be at V . Figure 17, 18 illustrates a read
IH
cycle.
Rev. 2.0
LHF16KS1
8
3.5 Read Identifier Codes Operation
3.6 Query Operation
The read identifier codes operation outputs the
manufacturer code, device code, block status codes
for each block (see Figure 4). Using the manufacturer
and device codes, the system CPU can automatically
match the device with its proper algorithms. The
block status codes identify locked or unlocked block
setting and erase completed or erase uncompleted
condition.
The query operation outputs the query structure.
Query database is stored in the 48Byte ROM. Query
structure allows system software to gain critical
information for controlling the flash component.
Query structure are always presented on the lowest-
order data output (DQ -DQ ) only.
0
7
3.7 Write
Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register. When
1FFFFF
V
=V
and V =V
, the CUI additionally
CC
CC1/2
PP
PPH1
Reserved for
Future Implementation
controls block erase, full chip erase, (multi) word/byte
write and block lock-bit configuration.
The Block Erase command requires appropriate
command data and an address within the block to be
erased. The Word/byte Write command requires the
command and address of the location to be written.
Set Block Lock-Bit command requires the command
and block address within the device (Block Lock) to
be locked. The Clear Block Lock-Bits command
requires the command and address within the device.
1F0006
1F0005
1F0004
Block 31 Status Code
1F0003
Reserved for
Future Implementation
1F0000
1EFFFF
Block 31
(Blocks 2 through 30)
020000
01FFFF
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active.
The address and data needed to execute a command
are latched on the rising edge of WE# or CE#
(whichever goes high first). Standard microprocessor
write timings are used. Figures 19 and 20 illustrate
WE# and CE#-controlled write operations.
Reserved for
Future Implementation
010006
010005
010004
010003
4 COMMAND DEFINITIONS
Block 1 Status Code
Reserved for
Future Implementation
When the V voltage ≤ V
Read operations from
PPLK,
PP
the status register, identifier codes, query, or blocks
are enabled. Placing on enables
010000
00FFFF
Block 1
V
V
PP
PPH1
successful block erase, full chip erase, (multi)
word/byte write and block lock-bit configuration
operations.
Reserved for
Future Implementation
Device operations are selected by writing specific
commands into the CUI. Table 4 defines these
commands.
000006
000005
000004
000003
000002
000001
000000
Block 0 Status Code
Device Code
Manufacturer Code
Block 0
Figure 4. Device Identifier Code Memory Map
Rev. 2.0
LHF16KS1
9
Table 3. Bus Operations(BYTE#=V )
IH
Mode
Notes
1,2,3,9
3
RP#
CE #
CE #
OE#
WE# Address
V
X
X
DQ
0-15
STS
X
X
0
1
PP
Read
V
V
V
V
V
V
X
X
D
IH
IL
IL
IL
IH
IH
OUT
Output Disable
V
V
V
V
High Z
IH
IL
IL
IH
V
V
IH
IH
Standby
3
V
V
V
X
V
X
X
X
X
X
High Z
X
IH
IH
IL
V
IL
IH
Deep Power-Down
Read Identifier
Codes
4
9
V
X
X
X
See
Figure 4
See Table
7~11
X
X
High Z High Z
Note 5 High Z
IL
V
V
V
V
V
IH
IL
IL
IL
IH
Query
Write
9
V
V
V
V
V
X
X
Note 6 High Z
IH
IL
IL
IL
IH
3,7,8,9
V
V
V
V
V
X
D
IN
X
IH
IL
IL
IH
IL
Table 3.1. Bus Operations(BYTE#=V )
IL
Mode
Read
Output Disable
Notes
1,2,3,9
3
RP#
CE #
CE #
OE#
WE# Address
V
X
X
DQ
0-7
STS
X
X
0
1
PP
V
V
V
V
V
V
X
X
D
IH
IL
IL
IL
IH
IH
OUT
V
V
V
V
High Z
IH
IL
IL
IH
V
V
IH
IH
Standby
3
V
V
V
X
V
X
X
X
X
X
High Z
X
IH
IH
IL
V
IL
IH
Deep Power-Down
Read Identifier
Codes
4
9
V
X
X
X
See
Figure 4
See Table
7~11
X
X
High Z High Z
Note 5 High Z
IL
V
V
V
V
V
IH
IL
IL
IL
IH
Query
9
V
V
V
V
V
X
X
Note 6 High Z
IH
IL
IL
IL
IH
Write
3,7,8,9
V
V
V
V
V
X
D
IN
X
IH
IL
IL
IH
IL
NOTES:
1. Refer to DC Characteristics. When V ≤V
, memory contents can be read, but not altered.
PPLK
PP
2. X can be V or V for control pins and addresses, and V
or V
for V . See DC Characteristics for
IL
IH
PPLK
PPH1 PP
V
and V
voltages.
PPLK
PPH1
3. STS is V (if configured to RY/BY# mode) when the WSM is executing internal block erase, full chip erase,
OL
(multi) word/byte write or block lock-bit configuration algorithms. It is floated during when the WSM is not busy,
in block erase suspend mode with (multi) word/byte write inactive, (multi) word/byte write suspend mode, or
deep power-down mode.
4. RP# at GND 0.2V ensures the lowest deep power-down current.
5. See Section 4.2 for read identifier code data.
6. See Section 4.5 for query data.
7. Command writes involving block erase, full chip erase, (multi) word/byte write or block lock-bit configuration are
reliably executed when V =V
and V =V
.
PP
PPH1
CC
CC1/2
8. Refer to Table 4 for valid D during a write operation.
IN
9. Don’t use the timing both OE# and WE# are V .
IL
Rev. 2.0
LHF16KS1
10
(10)
Table 4. Command Definitions
Bus Cycles Notes
First Bus Cycle
Second Bus Cycle
(1)
(2)
(3)
(1)
(2)
(3)
Command
Read Array/Reset
Read Identifier Codes
Req’d
Oper
Write
Write
Addr
X
Data
FFH
90H
Oper
Addr
Data
1
≥2
4
X
Read
Read
Read
IA
QA
X
ID
QD
SRD
Query
≥2
2
1
Write
Write
Write
Write
Write
Write
X
X
X
BA
X
WA
98H
70H
50H
20H
30H
40H
Read Status Register
Clear Status Register
Block Erase Setup/Confirm
Full Chip Erase Setup/Confirm
Word/Byte Write Setup/Write
Alternate Word/Byte Write
Setup/Write
2
5
Write
Write
Write
BA
X
WA
D0H
D0H
WD
2
2
5,6
5,6
2
≥4
1
Write
Write
Write
WA
10H
E8H
B0H
Write
Write
WA
WD
N-1
Multi Word/Byte Write
Setup/Confirm
9
5
WA
X
WA
Block Erase and (Multi)
Word/byte Write Suspend
Confirm and Block Erase and
(Multi) Word/byte Write Resume
Block Lock-Bit Set Setup/Confirm
Block Lock-Bit Reset
Setup/Confirm
1
2
2
5
7
8
Write
Write
Write
X
BA
X
D0H
60H
60H
Write
Write
BA
X
01H
D0H
STS Configuration
Level-Mode for Erase and Write
(RY/BY# Mode)
2
Write
X
B8H
Write
X
00H
STS Configuration
Pulse-Mode for Erase
STS Configuration
Pulse-Mode for Write
STS Configuration
Pulse-Mode for Erase and Write
2
2
2
Write
Write
Write
X
X
X
B8H
B8H
B8H
Write
Write
Write
X
X
X
01H
02H
03H
NOTES:
1. BUS operations are defined in Table 3 and Table 3.1.
2. X=Any valid address within the device.
IA=Identifier Code Address: see Figure 4.
QA=Query Offset Address.
BA=Address within the block being erased or locked.
WA=Address of memory location to be written.
3. SRD=Data read from status register. See Table 14 for a description of the status register bits.
WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high
first).
ID=Data read from identifier codes.
QD=Data read from query database.
4. Following the Read Identifier Codes command, read operations access manufacturer, device and block status
codes. See Section 4.2 for read identifier code data.
5. If the block is locked, WP# must be at V to enable block erase or (multi) word/byte write operations. Attempts
IH
to issue a block erase or (multi) word/byte write to a locked block while RP# is V .
IH
6. Either 40H or 10H are recognized by the WSM as the byte write setup.
7. A block lock-bit can be set while WP# is V .
IH
8. WP# must be at V to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block
IH
lock-bits.
9. Following the Third Bus Cycle, inputs the write address and write data of ’N’ times. Finally, input the confirm
command ’D0H’.
10. Commands other than those shown above are reserved by SHARP for future device implementations and
should not be used.
Rev. 2.0
LHF16KS1
11
4.1 Read Array Command
4.3 Read Status Register Command
Upon initial device power-up and after exit from deep
power-down mode, the device defaults to read array
mode. This operation is also initiated by writing the
Read Array command. The device remains enabled
for reads until another command is written. Once the
internal WSM has started a block erase, full chip
erase, (multi) word/byte write or block lock-bit
configuration, the device will not recognize the Read
Array command until the WSM completes its
operation unless the WSM is suspended via an Erase
Suspend and (Multi) Word/byte Write Suspend
command. The Read Array command functions
The status register may be read to determine when a
block erase, full chip erase, (multi) word/byte write or
block lock-bit configuration is complete and whether
the operation completed successfully(see Table 14).
It may be read at any time by writing the Read Status
Register command. After writing this command, all
subsequent read operations output data from the
status register until another valid command is written.
The status register contents are latched on the falling
edge of OE# or CE#(Either CE # or CE #),
0
1
whichever occurs. OE# or CE#(Either CE # or CE #)
0
1
must toggle to V before further reads to update the
IH
independently of the V voltage and RP# must be
status register latch. The Read Status Register
PP
V .
command functions independently of the V voltage.
IH
PP
RP# must be V .
IH
4.2 Read Identifier Codes Command
The extended status register may be read to
determine multi word/byte write availability(see Table
14.1). The extended status register may be read at
any time by writing the Multi Word/Byte Write
command. After writing this command, all subsequent
read operations output data from the extended status
register, until another valid command is written. Multi
Word/Byte Write command must be re-issued to
update the extended status register latch.
The identifier code operation is initiated by writing the
Read Identifier Codes command. Following the
command write, read cycles from addresses shown in
Figure 4 retrieve the manufacturer, device, block lock
configuration and block erase status (see Table 5 for
identifier code values). To terminate the operation,
write another valid command. Like the Read Array
command, the Read Identifier Codes command
functions independently of the V voltage and RP#
PP
4.4 Clear Status Register Command
must be V . Following the Read Identifier Codes
IH
command, the following information can be read:
Status register bits SR.5, SR.4, SR.3 and SR.1 are
set to "1"s by the WSM and can only be reset by the
Clear Status Register command. These bits indicate
various failure conditions (see Table 14). By allowing
system software to reset these bits, several
operations (such as cumulatively erasing or locking
multiple blocks or writing several bytes in sequence)
may be performed. The status register may be polled
to determine if an error occurs during the sequence.
Table 5. Identifier Codes
Code
Address
00000
00001
00002
00003
Data
Manufacture Code
B0
Device Code
D0
(1)
X0004
Block Status Code
(1)
X0005
•Block is Unlocked
•Block is Locked
DQ =0
0
To clear the status register, the Clear Status Register
command (50H) is written. It functions independently
DQ =1
0
•Last erase operation
completed successfully
•Last erase operation did
not completed successfully
•Reserved for Future Use
NOTE:
of the applied V
Voltage. RP# must be V . This
DQ =0
PP
IH
1
command is not functional during block erase, full
chip erase, (multi) word/byte write block lock-bit
configuration, block erase suspend or (multi)
word/byte write suspend modes.
DQ =1
1
DQ
2-7
1. X selects the specific block status code to be
read. See Figure 4 for the device identifier code
memory map.
Rev. 2.0
LHF16KS1
12
Table 6. Example of Query Structure Output
4.5 Query Command
Mode
Offset Address
Output
DQ
DQ
Query database can be read by writing Query
command (98H). Following the command write, read
cycle from address shown in Table 7~11 retrieve the
critical information to write, erase and otherwise
control the flash component. A of query offset
address is ignored when X8 mode (BYTE#=V ).
15~8
7~0
A , A , A , A , A , A
0
5
4
3
2
1
1 , 0 , 0 , 0 , 0 , 0 (20H) High Z
"Q"
X8 mode 1 , 0 , 0 , 0 , 0 , 1 (21H) High Z
1, 0 , 0 , 0 , 1 , 0 (22H) High Z
1 , 0 , 0 , 0 , 1 , 1 (23H) High Z
A , A , A , A , A
"Q"
"R"
"R"
0
IL
5
4
3
2
1
Query data are always presented on the low-byte
data output (DQ -DQ ). In x16 mode, high-byte
X16 mode 1 , 0 , 0 , 0 , 0 (10H)
1 , 0 , 0 , 0 , 1 (11H)
00H
00H
"Q"
"R"
0
7
(DQ -DQ ) outputs 00H. The bytes not assigned to
8
15
any information or reserved for future use are set to
"0". This command functions independently of the
V
voltage. RP# must be V .
PP
IH
4.5.1 Block Status Register
This field provides lock configuration and erase status for the specified block. These informations are only available
when device is ready (SR.7=1). If block erase or full chip erase operation is finished irregulary, block erase status
bit will be set to "1". If bit 1 is "1", this block is invalid.
Table 7. Query Block Status Register
Offset
Length
Description
(Word Address)
(BA+2)H
01H
Block Status Register
bit0 Block Lock Configuration
0=Block is unlocked
1=Block is Locked
bit1 Block Erase Status
0=Last erase operation completed successfully
1=Last erase operation not completed successfully
bit2-7 reserved for future use
Note:
1. BA=The beginning of a Block Address.
Rev. 2.0
LHF16KS1
13
4.5.2 CFI Query Identification String
The Identification String provides verification that the component supports the Common Flash Interface
specification. Additionally, it indicates which version of the spec and which Vendor-specified command set(s) is(are)
supported.
Table 8. CFI Query Identification String
Offset
Length
Description
(Word Address)
10H,11H,12H
03H
Query Unique ASCII string "QRY"
51H,52H,59H
13H,14H
15H,16H
17H,18H
19H,1AH
02H
02H
02H
02H
Primary Vendor Command Set and Control Interface ID Code
01H,00H (SCS ID Code)
Address for Primary Algorithm Extended Query Table
31H,00H (SCS Extended Query Table Offset)
Alternate Vendor Command Set and Control Interface ID Code
0000H (0000H means that no alternate exists)
Address for Alternate Algorithm Extended Query Table
0000H (0000H means that no alternate exists)
4.5.3 System Interface Information
The following device information can be useful in optimizing system interface software.
Table 9. System Information String
Offset
Length
Description
(Word Address)
1BH
01H
V
Logic Supply Minimum Write/Erase voltage
CC
27H (2.7V)
V Logic Supply Maximum Write/Erase voltage
CC
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
01H
01H
01H
01H
01H
01H
01H
01H
01H
01H
01H
55H (5.5V)
Programming Supply Minimum Write/Erase voltage
V
PP
27H (2.7V)
Programming Supply Maximum Write/Erase voltage
V
PP
55H (5.5V)
Typical Timeout per Single Byte/Word Write
3
03H (2 =8µs)
Typical Timeout for Maximum Size Buffer Write (32 Bytes)
6
06H (2 =64µs)
Typical Timeout per Individual Block Erase
10
0AH (0AH=10, 2 =1024ms)
Typical Timeout for Full Chip Erase
15
0FH (0FH=15, 2 =32768ms)
N
Maximum Timeout per Single Byte/Word Write, 2 times of typical.
4
04H (2 =16, 8µsx16=128µs)
N
Maximum Timeout Maximum Size Buffer Write, 2 times of typical.
4
04H (2 =16, 64µsx16=1024µs)
N
Maximum Timeout per Individual Block Erase, 2 times of typical.
4
04H (2 =16, 1024msx16=16384ms)
N
Maximum Timeout for Full Chip Erase, 2 times of typical.
4
04H (2 =16, 32768msx16=524288ms)
Rev. 2.0
LHF16KS1
14
4.5.4 Device Geometry Definition
This field provides critical details of the flash device geometry.
Table 10. Device Geometry Definition
Description
Offset
(Word Address)
Length
27H
01H
Device Size
15H (15H=21, 2 =2097152=2M Bytes)
21
28H,29H
2AH,2BH
2CH
02H
02H
01H
02H
02H
Flash Device Interface description
02H,00H (x8/x16 supports x8 and x16 via BYTE#)
Maximum Number of Bytes in Multi word/byte write
5
05H,00H (2 =32 Bytes )
Number of Erase Block Regions within device
01H (symmetrically blocked)
The Number of Erase Blocks
1FH,00H (1FH=31 ==> 31+1=32 Blocks)
The Number of "256 Bytes" cluster in a Erase block
00H,01H (0100H=256 ==>256 Bytes x 256= 64K Bytes in a Erase Block)
2DH,2EH
2FH,30H
4.5.5 SCS OEM Specific Extended Query Table
Certain flash features and commands may be optional in a vendor-specific algorithm specification. The optional
vendor-specific Query table(s) may be used to specify this and other types of information. These structures are
defined solely by the flash vendor(s).
Table 11. SCS OEM Specific Extended Query Table
Offset
Length
Description
(Word Address)
31H,32H,33H
03H
PRI
50H,52H,49H
34H
35H
36H,37H,
38H,39H
01H
01H
04H
31H (1) Major Version Number , ASCII
30H (0) Minor Version Number, ASCII
0FH,00H,00H,00H
Optional Command Support
bit0=1 : Chip Erase Supported
bit1=1 : Suspend Erase Supported
bit2=1 : Suspend Write Supported
bit3=1 : Lock/Unlock Supported
bit4=0 : Queued Erase Not Supported
bit5-31=0 : reserved for future use
01H
Supported Functions after Suspend
bit0=1 : Write Supported after Erase Suspend
bit1-7=0 : reserved for future use
03H,00H
3AH
01H
02H
3BH,3CH
Block Status Register Mask
bit0=1 : Block Status Register Lock Bit [BSR.0] active
bit1=1 : Block Status Register Valid Bit [BSR.1] active
bit2-15=0 : reserved for future use
3DH
3EH
3FH
01H
01H
V
Logic Supply Optimum Write/Erase voltage(highest performance)
CC
50H(5.0V)
Programming Supply Optimum Write/Erase voltage(highest performance)
V
PP
50H(5.0V)
reserved Reserved for future versions of the SCS Specification
Rev. 2.0
LHF16KS1
15
erase setup is first written, followed by a full chip
erase confirm. After a confirm command is written,
device erases the all unlocked blocks from block 0 to
Block 31 block by block. This command sequence
4.6 Block Erase Command
Block erase is executed one block at a time and
initiated by a two-cycle command. A block erase
setup is first written, followed by an block erase
requires
appropriate
sequencing.
Block
preconditioning, erase and verify are handled
internally by the WSM (invisible to the system). After
the two-cycle full chip erase sequence is written, the
device automatically outputs status register data
when read (see Figure 6). The CPU can detect full
chip erase completion by analyzing the output data of
the STS pin or status register bit SR.7.
confirm.
This command sequence requires
appropriate sequencing and an address within the
block to be erased (erase changes all block data to
FFH). Block preconditioning, erase and verify are
handled internally by the WSM (invisible to the
system). After the two-cycle block erase sequence is
written, the device automatically outputs status
register data when read (see Figure 5). The CPU can
detect block erase completion by analyzing the
output data of the STS pin or status register bit SR.7.
When the full chip erase is complete, status register
bit SR.5 should be checked. If erase error is
detected, the status register should be cleared before
system software attempts corrective actions. The CUI
remains in read status register mode until a new
command is issued. If error is detected on a block
during full chip erase operation, WSM stops erasing.
Reading the block valid status by issuing Read ID
Codes command or Query command informs which
blocks failed to its erase.
When the block erase is complete, status register bit
SR.5 should be checked. If a block erase error is
detected, the status register should be cleared before
system software attempts corrective actions. The CUI
remains in read status register mode until a new
command is issued.
This two-step command sequence of set-up followed
by execution ensures that block contents are not
accidentally erased. An invalid Block Erase command
sequence will result in both status register bits SR.4
and SR.5 being set to "1". Also, reliable block erasure
This two-step command sequence of set-up followed
by execution ensures that block contents are not
accidentally erased. An invalid Full Chip Erase
command sequence will result in both status register
bits SR.4 and SR.5 being set to "1". Also, reliable full
can only occur when V =V
and V =V
. In
CC
CC1/2
PP
PPH1
chip erasure can only occur when V =V
and
the absence of this high voltage, block contents are
protected against erasure. If block erase is attempted
CC
CC1/2
V
=V
. In the absence of this high voltage, block
PP
PPH1
contents are protected against erasure. If full chip
while V ≤V
, SR.3 and SR.5 will be set to "1".
PP
PPLK
erase is attempted while V ≤V
, SR.3 and SR.5
Successful block erase requires that the
corresponding block lock-bit be cleared or if set, that
PP
PPLK
will be set to "1". When WP#=V , all blocks are
IH
erased independent of block lock-bits status. When
WP#=V . If block erase is attempted when the
IH
WP#=V , only unlocked blocks are erased. In this
corresponding block lock-bit is set and WP#=V ,
IL
IL
case, SR.1 and SR.5 will not be set to "1". Full chip
erase can not be suspended.
SR.1 and SR.5 will be set to "1".
4.7 Full Chip Erase Command
This command followed by a confirm command
(D0H) erases all of the unlocked blocks. A full chip
Rev. 2.0
LHF16KS1
16
continue monitoring XSR.7 by writing multi word/byte
write setup with write address until XSR.7 transitions
to 1. When XSR.7 transitions to 1, the device is ready
for loading the data to the buffer. A word/byte count
(N)-1 is written with write address. After writing a
word/byte count(N)-1, the device automatically turns
back to output status register data. The word/byte
count (N)-1 must be less than or equal to 1FH in x8
mode (0FH in x16 mode). On the next write, device
start address is written with buffer data. Subsequent
writes provide additional device address and data,
depending on the count. All subsequent address
must lie within the start address plus the count. After
the final buffer data is written, write confirm (D0H)
must be written. This initiates WSM to begin copying
the buffer data to the Flash Array. An invalid Multi
Word/Byte Write command sequence will result in
both status register bits SR.4 and SR.5 being set to
"1". For additional multi word/byte write, write another
multi word/byte write setup and check XSR.7. The
Multi Word/Byte Write command can be queued
while WSM is busy as long as XSR.7 indicates "1",
because LH28F160S5HNS-S1 has two buffers. If an
error occurs while writing, the device will stop writing
and flush next multi word/byte write command loaded
in multi word/byte write command. Status register bit
SR.4 will be set to "1". No multi word/byte write
command is available if either SR.4 or SR.5 are set
to "1". SR.4 and SR.5 should be cleared before
issuing multi word/byte write command. If a multi
word/byte write command is attempted past an erase
block boundary, the device will write the data to Flash
Array up to an erase block boundary and then stop
writing. Status register bits SR.4 and SR.5 will be set
to "1".
4.8 Word/Byte Write Command
Word/byte write is executed by a two-cycle command
sequence. Word/Byte Write setup (standard 40H or
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the word/byte write and write verify
algorithms internally. After the word/byte write
sequence is written, the device automatically outputs
status register data when read (see Figure 7). The
CPU can detect the completion of the word/byte write
event by analyzing the STS pin or status register bit
SR.7.
When word/byte write is complete, status register bit
SR.4 should be checked. If word/byte write error is
detected, the status register should be cleared. The
internal WSM verify only detects errors for "1"s that
do not successfully write to "0"s. The CUI remains in
read status register mode until it receives another
command.
Reliable word/byte writes can only occur when
V
=V
and V =V
. In the absence of this
CC
CC1/2
PP
PPH1
high voltage, memory contents are protected against
word/byte writes. If word/byte write is attempted while
V
≤V
, status register bits SR.3 and SR.4 will be
PP
PPLK
set to "1". Successful word/byte write requires that
the corresponding block lock-bit be cleared or, if set,
that WP#=V . If word/byte write is attempted when
IH
the corresponding block lock-bit is set and WP#=V ,
SR.1 and SR.4 will be set to "1". Word/byte write
IL
operations with V <WP#<V
produce spurious
IL
IH
results and should not be attempted.
Reliable multi byte writes can only occur when
4.9 Multi Word/Byte Write Command
V
=V
and V =V
. In the absence of this
CC
CC1/2
PP
PPH1
high voltage, memory contents are protected against
multi word/byte writes. If multi word/byte write is
Multi word/byte write is executed by at least four-
cycle or up to 35-cycle command sequence. Up to
32 bytes in x8 mode (16 words in x16 mode) can be
loaded into the buffer and written to the Flash Array.
First, multi word/byte write setup (E8H) is written with
the write address. At this point, the device
automatically outputs extended status register data
(XSR) when read (see Figure 8, 9). If extended
status register bit XSR.7 is 0, no Multi Word/Byte
Write command is available and multi word/byte write
setup which just has been written is ignored. To retry,
attempted while V ≤V
, status register bits SR.3
PP
PPLK
and SR.4 will be set to "1". Successful multi
word/byte write requires that the corresponding block
lock-bit be cleared or, if set, that WP#=V . If multi
IH
byte write is attempted when the corresponding block
lock-bit is set and WP#=V , SR.1 and SR.4 will be
IL
set to "1".
Rev. 2.0
LHF16KS1
17
write operations initiated during block erase suspend
have completed.
4.10 Block Erase Suspend Command
The Block Erase Suspend command allows block-
erase interruption to read or (multi) word/byte-write
data in another block of memory. Once the block-
erase process starts, writing the Block Erase
Suspend command requests that the WSM suspend
the block erase sequence at a predetermined point in
the algorithm. The device outputs status register data
when read after the Block Erase Suspend command
is written. Polling status register bits SR.7 and SR.6
can determine when the block erase operation has
been suspended (both will be set to "1"). STS will
4.11 (Multi) Word/Byte Write Suspend
Command
The (Multi) Word/Byte Write Suspend command
allows (multi) word/byte write interruption to read data
in other flash memory locations. Once the (multi)
word/byte write process starts, writing the (Multi)
Word/Byte Write Suspend command requests that
the WSM suspend the (multi) word/byte write
sequence at a predetermined point in the algorithm.
The device continues to output status register data
when read after the (Multi) Word/Byte Write Suspend
command is written. Polling status register bits SR.7
and SR.2 can determine when the (multi) word/byte
write operation has been suspended (both will be set
to "1"). STS will also transition to High Z.
also transition to High Z. Specification t
the block erase suspend latency.
defines
WHRH2
At this point, a Read Array command can be written
to read data from blocks other than that which is
suspended. A (Multi) Word/Byte Write command
sequence can also be issued during erase suspend
to program data in other blocks. Using the (Multi)
Word/Byte Write Suspend command (see Section
4.11), a (multi) word/byte write operation can also be
suspended. During a (multi) word/byte write operation
with block erase suspended, status register bit SR.7
will return to "0" and the STS (if set to RY/BY#)
Specification t
defines the (multi) word/byte
WHRH1
write suspend latency.
At this point, a Read Array command can be written
to read data from locations other than that which is
suspended. The only other valid commands while
(multi) word/byte write is suspended are Read Status
Register and (Multi) Word/Byte Write Resume. After
(Multi) Word/Byte Write Resume command is written
to the flash memory, the WSM will continue the
(multi) word/byte write process. Status register bits
SR.2 and SR.7 will automatically clear and STS will
output will transition to V . However, SR.6 will
OL
remain "1" to indicate block erase suspend status.
The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status register
bits SR.6 and SR.7 will automatically clear and STS
return to V . After the (Multi) Word/Byte Write
OL
command is written, the device automatically outputs
status register data when read (see Figure 11). V
PP
must remain at V
(the same V level used for
PPH1
PP
will return to V . After the Erase Resume command
(multi) word/byte write) while in (multi) word/byte
OL
is written, the device automatically outputs status
write suspend mode. RP# must also remain at V .
IH
register data when read (see Figure 10). V
must
WP# must also remain at the same level used for
(multi) word/byte write. BYTE# must be the same
level as writing the (Multi) Word/Byte Write command
when the (Multi) Word/Byte Write Resume command
is written.
PP
remain at V
(the same V level used for block
PPH1
PP
erase) while block erase is suspended. RP# must
also remain at V . WP# must also remain at the
IH
same level used for block erase. BYTE# must be the
same level as writing the Block Erase command
when the Block Erase Resume command is written.
Block erase cannot resume until (multi) word/byte
Rev. 2.0
LHF16KS1
18
block lock-bits can be cleared using only the Clear
Block Lock-Bits command. See Table 13 for a
summary of hardware and software write protection
options.
4.12 Set Block Lock-Bit Command
A flexible block locking and unlocking scheme is
enabled via block lock-bits. The block lock-bits gate
program and erase operations With WP#=V ,
IH
Clear block lock-bits operation is executed by a two-
cycle command sequence. A clear block lock-bits
setup is first written. After the command is written, the
device automatically outputs status register data
when read (see Figure 13). The CPU can detect
completion of the clear block lock-bits event by
analyzing the STS Pin output or status register bit
SR.7.
individual block lock-bits can be set using the Set
Block Lock-Bit command. See Table 13 for a
summary of hardware and software write protection
options.
Set block lock-bit is executed by a two-cycle
command sequence. The set block lock-bit setup
along with appropriate block or device address is
written followed by either the set block lock-bit
confirm (and an address within the block to be
locked). The WSM then controls the set block lock-bit
algorithm. After the sequence is written, the device
automatically outputs status register data when read
(see Figure 12). The CPU can detect the completion
of the set block lock-bit event by analyzing the STS
pin output or status register bit SR.7.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bit error
is detected, the status register should be cleared.
The CUI will remain in read status register mode until
another command is issued.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock-Bits
command sequence will result in status register bits
SR.4 and SR.5 being set to "1". Also, a reliable clear
block lock-bits operation can only occur when
When the set block lock-bit operation is complete,
status register bit SR.4 should be checked. If an error
is detected, the status register should be cleared.
The CUI will remain in read status register mode until
a new command is issued.
V
=V
and V =V
. If a clear block lock-bits
CC
CC1/2
PP
PPH1
operation is attempted while V ≤V
, SR.3 and
PPLK
PP
SR.5 will be set to "1". In the absence of this high
voltage, the block lock-bits content are protected
against alteration. A successful clear block lock-bits
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally set. An invalid Set Block Lock-Bit
command will result in status register bits SR.4 and
SR.5 being set to "1". Also, reliable operations occur
operation requires WP#=V . If it is attempted with
IH
WP#=V , SR.1 and SR.5 will be set to "1" and the
IL
operation will fail. Clear block lock-bits operations
only when V =V
absence of this high voltage, block lock-bit contents
are protected against alteration.
and V =V
. In the
CC
CC1/2
PP
PPH1
with V <RP# produce spurious results and should
IH
not be attempted.
If a clear block lock-bits operation is aborted due to
A successful set block lock-bit operation requires
WP#=V . If it is attempted with WP#=V , SR.1 and
V
or V
transitioning out of valid range or RP#
PP
CC
IH
IL
active transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-bits
is required to initialize block lock-bit contents to
known values.
SR.4 will be set to "1" and the operation will fail. Set
block lock-bit operations with WP#<V produce
spurious results and should not be attempted.
IH
4.13 Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. With WP#=V ,
IH
Rev. 2.0
LHF16KS1
19
Table 12. STS Configuration Coding Description
4.14 STS Configuration Command
Configuration
Effects
Bits
The Status (STS) pin can be configured to different
states using the STS Configuration command. Once
the STS pin has been configured, it remains in that
configuration until another configuration command is
issued, the device is powered down or RP# is set to
Set STS pin to default level mode
(RY/BY#). RY/BY# in the default
level-mode of operation will indicate
00H
WSM status condition.
V . Upon initial device power-up and after exit from
Set STS pin to pulsed output signal
for specific erase operation. In this
mode, STS provides low pulse at
the completion of BLock Erase,
Full Chip Erase and Clear Block
Lock-bits operations.
IL
deep power-down mode, the STS pin defaults to
RY/BY# operation where STS low indicates that the
WSM is busy. STS High Z indicates that the WSM is
ready for a new operation.
01H
To reconfigure the STS pin to other modes, the STS
Configuration is issued followed by the appropriate
configuration code. The three alternate configurations
are all pulse mode for use as a system interrupt. The
STS Configuration command functions independently
of the V voltage and RP# must be V .
Set STS pin to pulsed output signal
for a specific write operation. In this
02H
03H
mode, STS provides low pulse at
the completion of (Multi) Byte Write
and Set Block Lock-bit operation.
Set STS pin to pulsed output signal
for specific write and erase
operation. STS provides low pulse
at the completion of Block Erase,
Full Chip Erase, (Multi) Word/Byte
Write and Block Lock-bit
PP
IH
Configuration operations.
Table 13. Write Protection Alternatives
WP#
Block
Lock-Bit
0
Operation
Effect
Block Erase,
V or V
Block Erase and (Multi) Word/Byte Write Enabled
IL
IH
(Multi) Word/Byte
Write
Block is Locked. Block Erase and (Multi) Word/Byte Write
Disabled
1
V
IL
Block Lock-Bit Override. Block Erase and (Multi) Word/Byte
Write Enabled
V
IH
Full Chip Erase
0,1
X
V
All unlocked blocks are erased, locked blocks are not erased
All blocks are erased
IL
V
IH
Set Block Lock-Bit
Clear Block Lock-Bits
X
V
Set Block Lock-Bit Disabled
Set Block Lock-Bit Enabled
Clear Block Lock-Bits Disabled
Clear Block Lock-Bits Enabled
IL
V
IH
X
V
IL
V
IH
Rev. 2.0
LHF16KS1
20
Table 14. Status Register Definition
WSMS
7
BESS
6
ECBLBS
WSBLBS
VPPS
WSS
DPS
1
R
0
5
4
3
2
NOTES:
SR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
Check STS or SR.7 to determine block erase, full chip
erase, (multi) word/byte write or block lock-bit
configuration completion.
SR.6 = BLOCK ERASE SUSPEND STATUS
1 = Block Erase Suspended
SR.6-0 are invalid while SR.7="0".
0 = Block Erase in Progress/Completed
If both SR.5 and SR.4 are "1"s after a block erase, full
chip erase, (multi) word/byte write, block lock-bit
SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS
STATUS
configuration or STS configuration attempt, an improper
command sequence was entered.
1 = Error in Erase or Clear Blocl Lock-Bits
0 = Successful Erase or Clear Block Lock-Bits
SR.3 does not provide a continuous indication of V
PP
level. The WSM interrogates and indicates the V level
only after block erase, full chip erase, (multi) word/byte
write or block lock-bit configuration command
PP
SR.4 = WRITE AND SET BLOCK LOCK-BIT STATUS
1 = Error in Write or Set Block Lock-Bit
0 = Successful Write or Set Block Lock-Bit
sequences. SR.3 is not guaranteed to reports accurate
feedback only when V ≠V
.
PP
PPH1
SR.3 = V STATUS
PP
1 = V Low Detect, Operation Abort
SR.1 does not provide a continuous indication of block
lock-bit values. The WSM interrogates block lock-bit,
and WP# only after block erase, full chip erase, (multi)
word/byte write or block lock-bit configuration command
sequences. It informs the system, depending on the
attempted operation, if the block lock-bit is set and/or
PP
0 = V OK
PP
SR.2 = WRITE SUSPEND STATUS
1 = Write Suspended
0 = Write in Progress/Completed
WP# is not V . Reading the block lock configuration
codes after writing the Read Identifier Codes command
indicates block lock-bit status.
IH
SR.1 = DEVICE PROTECT STATUS
1 = Block Lock-Bit and/or WP# Lock Detected,
Operation Abort
0 = Unlock
SR.0 is reserved for future use and should be masked
out when polling the status register.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
Table 14.1. Extended Status Register Definition
SMS
7
R
6
R
R
R
R
R
1
R
0
5
4
3
2
NOTES:
XSR.7 = STATE MACHINE STATUS
1 = Multi Word/Byte Write available
0 = Multi Word/Byte Write not available
After issue a Multi Word/Byte Write command: XSR.7
indicates that a next Multi Word/Byte Write command is
available.
XSR.6-0=RESERVED FOR FUTURE ENHANCEMENTS
XSR.6-0 is reserved for future use and should be
masked out when polling the extended status register.
Rev. 2.0
LHF16KS1
21
Start
Bus
Command
Comments
Operation
Data=70H
Addr=X
Write 70H
Read Status
Register
Write
Read
Read Status
Register
Status Register Data
Check SR.7
Standby
1=WSM Ready
0=WSM Busy
0
SR.7=
1
Data=20H
Write
Write
Erase Setup
Addr=Within Block to be Erased
Write 20H,
Erase
Data=D0H
Block Address
Confirm
Addr=Within Block to be Erased
Write D0H,
Block Address
Read
Status Register Data
Read Status
Register
Check SR.7
Suspend Block
Erase Loop
Standby
1=WSM Ready
0=WSM Busy
No
0
Suspend
Repeat for subsequent block erasures.
SR.7=
1
Block Erase
Yes
Full status check can be done after each block erase or after a sequence of
block erasures.
Write FFH after the last operation to place device in read array mode.
Full Status
Check if Desired
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
Bus
Command
Comments
Operation
Check SR.3
Standby
1
1=V Error Detect
PP
SR.3=
V
Range Error
PP
Check SR.1
0
1=Device Protect Detect
Standby
WP#=V ,Block Lock-Bit is Set
IL
Only required for systems
1
implementing lock-bit configuration
Device Protect Error
SR.1=
0
Check SR.4,5
Standby
Standby
Both 1=Command Sequence Error
1
1
Command Sequence
Error
Check SR.5
SR.4,5=
0
1=Block Erase Error
SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status
Register Command in cases where multiple blocks are erased
before full status is checked.
SR.5=
0
Block Erase Error
If error is detected, clear the Status Register before attempting
retry or other error recovery.
Block Erase Successful
Figure 5. Automated Block Erase Flowchart
Rev. 2.0
LHF16KS1
22
Start
Bus
Command
Comments
Operation
Data=70H
Addr=X
Read Status
Register
Write 70H
Write
Read
Read Status
Register
Status Register Data
Check SR.7
Standby
1=WSM Ready
0=WSM Busy
0
SR.7=
1
Data=30H
Addr=X
Full Chip Erase
Setup
Write
Write
Read
Write 30H
Write D0H
Data=D0H
Addr=X
Full Chip Erase
Confirm
Status Register Data
Read Status
Register
Check SR.7
Standby
1=WSM Ready
0=WSM Busy
Full status check can be done after each full chip erase.
0
SR.7=
1
Write FFH after the last operation to place device in read array mode.
Full Status
Check if Desired
Full Chip Erase
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
Bus
Command
Comments
Operation
Check SR.3
Standby
1
1=V Error Detect
PP
SR.3=
V
Range Error
PP
Check SR.4,5
Standby
Standby
0
Both 1=Command Sequence Error
Check SR.5
1
Command Sequence
Error
SR.4,5=
0
1=Full Chip Erase Error
SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status
Register Command in cases where multiple blocks are erased
before full status is checked.
1
If error is detected, clear the Status Register before attempting
retry or other error recovery.
SR.5=
0
Full Chip Erase Error
Full Chip Erase
Successful
Figure 6. Automated Full Chip Erase Flowchart
Rev. 2.0
LHF16KS1
23
Start
Bus
Command
Comments
Operation
Data=70H
Addr=X
Read Status
Register
Write
Read
Write 70H
Read Status
Register
Status Register Data
Check SR.7
Standby
1=WSM Ready
0=WSM Busy
0
SR.7=
1
Data=40H or 10H
Setup Word/Byte
Write
Write
Write
Addr=Location to Be Written
Write 40H or 10H,
Address
Data=Data to Be Written
Word/Byte Write
Addr=Location to Be Written
Write Word/Byte
Data and Address
Read
Status Register Data
Read
Check SR.7
Status Register
Standby
1=WSM Ready
0=WSM Busy
Suspend Word/Byte
Write Loop
No
Suspend
Word/Byte
Write
Repeat for subsequent word/byte writes.
0
SR.7=
1
SR full status check can be done after each word/byte write, or after a sequence of
word/byte writes.
Yes
Write FFH after the last word/byte write operation to place device in
read array mode.
Full Status
Check if Desired
Word/byte Write
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
Bus
Command
Comments
Operation
Check SR.3
Standby
1
1=V Error Detect
PP
SR.3=
V
Range Error
PP
Check SR.1
0
1=Device Protect Detect
Standby
Standby
WP#=V ,Block Lock-Bit is Set
IL
Only required for systems
1
implementing lock-bit configuration
Device Protect Error
Word/byte Write Error
SR.1=
Check SR.4
0
1=Data Write Error
1
SR.4,SR.3 and SR.1 are only cleared by the Clear Status Register
command in cases where multiple locations are written before
full status is checked.
SR.4=
0
If error is detected, clear the Status Register before attempting
retry or other error recovery.
Word/Byte Write
Successful
Figure 7. Automated Word/byte Write Flowchart
Rev. 2.0
LHF16KS1
24
Start
Write E8H,
Start Address
Bus
Command
Comments
Operation
Read Extend
Status Register
Setup
Data=E8H
Write
Read
Addr=Start Address
Multi Word/Byte Write
No
Extended Status Register Data
0
Yes
Write Buffer
Time Out
XSR.7=
1
Check XSR.7
Standby
1=Multi Word/Byte Write Ready
0=Multi Word/Byte Write Busy
Write Word or Byte Count (N)-1,
Start Address
Data=Word or Byte Count (N)-1
Addr=Start Address
Write
(Note1)
Write Buffer Data,
Start Address
Data=Buffer Data
Write
Addr=Start Address
(Note2,3)
Data=Buffer Data
Write
X=1
Addr=Device Address
(Note4,5)
Data=D0H
Addr=X
Write
Read
Yes
X = N
Status Register Data
No
Check SR.7
Standby
Yes
1=WSM Ready
0=WSM Busy
Abort Buffer
Write Commnad?
Write Another
Block Address
No
1. Byte or word count values on DQ are loaded into the count register.
0-7
Multi Word/Byte Write
Abort
2. Write Buffer contents will be programmed at the start address.
3. Align the start address on a Write Buffer boundary for maximum
programming performance.
Write Buffer Data,
Device Address
4.The device aborts the Multi Word/Byte Write command if the current address is
outside of the original block address.
X=X+1
5.The Status Register indicates an "improper command sequence" if the Multi
Word/Byte command is aborted. Follow this with a Clear Status Register command.
SR full status check can be done after each multi word/byte write,
or after a sequence of multi word/byte writes.
Write D0H
Write FFH after the last multi word/byte write operation to place device in
read array mode.
Another
Buffer
Yes
Write ?
No
Read Status
Register
Suspend Multi Word/Byte
Write Loop
No
Suspend
Multi Word/Byte
Write
0
Yes
SR.7=
1
Full Status
Check if Desired
Multi Word/Byte Write
Complete
Figure 8. Automated Multi Word/Byte Write Flowchart
Rev. 2.0
LHF16KS1
25
FULL STATUS CHECK PROCEDURE FOR
MULTI WORD/BYTE WRITE OPERATION
Bus
Read Status Register
Command
Comments
Operation
Check SR.3
Standby
Standby
1=V Error Detect
PP
1
SR.3=
0
V
Range Error
PP
Check SR.1
1=Device Protect Detect
WP#=V ,Block Lock-Bit is Set
IL
Only required for systems
1
1
1
implementing lock-bit configuration
SR.1=
0
Device Protect Error
Check SR.4,5
Standby
Standby
Both 1=Command Sequence Error
Check SR.4
Command Sequence
Error
SR.4,5=
0
1=Data Write Error
SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status Register
command in cases where multiple locations are written before
full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
Multi Word/Byte Write
Error
SR.4=
0
Multi Word/Byte Write
Successful
Figure 9. Full Status Check Procedure for Automated Multi Word/Byte Write
Rev. 2.0
LHF16KS1
26
Start
Bus
Command
Comments
Operation
Erase
Data=B0H
Addr=X
Write
Read
Write B0H
Suspend
Status Register Data
Addr=X
Read
Status Register
Check SR.7
1=WSM Ready
0=WSM Busy
Standby
0
0
Check SR.6
SR.7=
1
1=Block Erase Suspended
0=Block Erase Completed
Standby
Write
Erase
Data=D0H
Addr=X
Resume
Block Erase Completed
SR.6=
1
(Multi) Word/Byte Write
Read
Read or
Write ?
Read Array Data
(Multi) Word/Byte Write Loop
No
Done?
Yes
Write FFH
Write D0H
Block Erase Resumed
Read Array Data
Figure 10. Block Erase Suspend/Resume Flowchart
Rev. 2.0
LHF16KS1
27
Start
Bus
Command
Comments
Operation
(Multi) Word/Byte Write
Suspend
Data=B0H
Addr=X
Write B0H
Write
Read
Status Register Data
Addr=X
Read
Status Register
Check SR.7
1=WSM Ready
0=WSM Busy
Standby
Standby
0
0
SR.7=
1
Check SR.2
1=(Multi) Word/Byte Write
Suspended
0=(Multi) Word/Byte Write
Completed
(Multi) Word/Byte Write
Completed
Data=FFH
Addr=X
SR.2=
1
Read Array
Write
Read
Read Array locations other
than that being written.
Write FFH
(Multi) Word/Byte Write Data=D0H
Addr=X
Write
Resume
Read Array Data
Done
No
Reading
Yes
Write D0H
Write FFH
(Multi) Word/Byte Write
Resumed
Read Array Data
Figure 11. (Multi) Word/Byte Write Suspend/Resume Flowchart
Rev. 2.0
LHF16KS1
28
Start
Bus
Command
Comments
Operation
Set Block
Write 60H,
Data=60H
Write
Write
Block Address
Lock-Bit Setup
Addr=Block Address
Write 01H,
Set Block
Data=01H,
Block Address
Lock-Bit Confirm
Addr=Block Address
Read
Status Register
Read
Status Register Data
Check SR.7
0
Standby
1=WSM Ready
0=WSM Busy
SR.7=
1
Repeat for subsequent block lock-bit set operations.
Full status check can be done after each block lock-bit set operation
or after a sequence of block lock-bit set operations.
Write FFH after the last block lock-bit set operation to place device in
read array mode.
Full Status
Check if Desired
Set Block Lock-Bit
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
Bus
Command
Comments
Operation
Check SR.3
Standby
1=V Error Detect
PP
1
SR.3=
V
Range Error
PP
Check SR.1
1=Device Protect Detect
Standby
0
WP#=V
IL
Check SR.4,5
1
Device Protect Error
Standby
Standby
Both 1=Command
Sequence Error
SR.1=
0
Check SR.4
1=Set Block Lock-Bit Error
1
Command Sequence
Error
SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple block lock-bits are set before
full status is checked.
SR.4,5=
0
If error is detected, clear the Status Register before attempting
retry or other error recovery.
1
SR.4=
0
Set Block Lock-Bit Error
Set Block Lock-Bit
Successful
Figure 12. Set Block Lock-Bit Flowchart
Rev. 2.0
LHF16KS1
29
Start
Bus
Command
Comments
Operation
Clear Block
Data=60H
Addr=X
Write
Write
Write 60H
Write D0H
Lock-Bits Setup
Clear Block
Data=D0H
Addr=X
Lock-Bits Confirm
Read
Status Register Data
Read
Status Register
Check SR.7
Standby
1=WSM Ready
0=WSM Busy
0
Write FFH after the Clear Block Lock-Bits operation to
place device in read array mode.
SR.7=
1
Full Status
Check if Desired
Clear Block Lock-Bits
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
Bus
Command
Operation
Comments
Check SR.3
Standby
1=V Error Detect
PP
1
SR.3=
V
Range Error
PP
Check SR.1
1=Device Protect Detect
WP#=V
Standby
0
IL
Check SR.4,5
1
Device Protect Error
Standby
Standby
Both 1=Command
Sequence Error
SR.1=
0
Check SR.5
1=Clear Block Lock-Bits Error
1
Command Sequence
Error
SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status
Register command.
SR.4,5=
If error is detected, clear the Status Register before attempting
retry or other error recovery.
0
1
Clear Block Lock-Bits
Error
SR.5=
0
Clear Block Lock-Bits
Successful
Figure 13. Clear Block Lock-Bits Flowchart
Rev. 2.0
LHF16KS1
30
STS, in default mode, is also High Z when the device
is in block erase suspend (with (multi) word/byte write
inactive), (multi) word/byte write suspend or deep
power-down modes.
5 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
The device will often be used in large memory arrays.
5.3 Power Supply Decoupling
SHARP
provides
three
control
inputs
to
accommodate multiple memory connections. Three-
Line control provides for:
Flash memory power switching characteristics require
careful device decoupling. System designers are
interested in three supply current issues; standby
current levels, active current levels and transient
peaks produced by falling and rising edges of CE#
and OE#. Transient current magnitudes depend on
the device outputs’ capacitive and inductive loading.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks. Each
device should have a 0.1µF ceramic capacitor
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will
not occur.
To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while
deselected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
connected between its V and GND and between its
CC
V
and GND. These high-frequency, low inductance
PP
capacitors should be placed as close as possible to
package leads. Additionally, for every eight devices,
a 4.7µF electrolytic capacitor should be placed at the
array’s power supply connection between V
and
CC
GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductance.
5.2 STS and Block Erase, Full Chip
Erase, (Multi) Word/Byte Write and
Block Lock-Bit Configuration Polling
5.4 V Trace on Printed Circuit Boards
PP
Updating flash memories that reside in the target
system requires that the printed circuit board
STS is an open drain output that should be
connected to V
by a pullup resistor to provide a
designer pay attention to the V Power supply trace.
CC
PP
hardware method of detecting block erase, full chip
erase, (multi) word/byte write and block lock-bit
configuration completion. In default mode, it
transitions low after block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration
The V
pin supplies the memory cell current for
PP
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration. Use similar trace
widths and layout considerations given to the V
power bus. Adequate
decoupling will decrease V
overshoots.
CC
V
supply traces and
voltage spikes and
PP
commands and returns to V
when the WSM has
OH
PP
finished executing the internal algorithm. For
alternate STS pin configurations, see the
Configuration command.
STS can be connected to an interrupt input of the
system CPU or controller. It is active at all times.
Rev. 2.0
LHF16KS1
31
powers-up first. Internal circuitry resets the CUI to
read array mode at power-up.
5.5 V , V , RP# Transitions
CC PP
Block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration are not guaranteed if
A system designer must guard against spurious
writes for V
voltages above V
when V
is
V
falls outside of a valid V
range, V
falls
CC
LKO
PP
PP
PPH1
CC
active. Since both WE# and CE# must be low for a
outside of a valid V
range, or RP#=V . If V
CC1/2
IL PP
command write, driving either to V will inhibit writes.
error is detected, status register bit SR.3 is set to "1"
along with SR.4 or SR.5, depending on the attempted
IH
The CUI’s two-step command sequence architecture
provides added level of protection against data
alteration.
operation. If RP# transitions to V during block
IL
erase, full chip erase, (multi) word/byte write or block
lock-bit configuration, STS(if set to RY/BY# mode)
will remain low until the reset operation is complete.
Then, the operation will abort and the device will
enter deep power-down. The aborted operation may
leave data partially altered. Therefore, the command
sequence must be repeated after normal operation is
In-system block lock and unlock capability prevents
inadvertent data alteration. The device is disabled
while RP#=V regardless of its control inputs state.
IL
5.7 Power Dissipation
restored. Device power-off or RP# transitions to V
clear the status register.
IL
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory’s nonvolatility
increases usable battery life because data is retained
when system power is removed.
The CUI latches commands issued by system
software and is not altered by V or CE# transitions
PP
or WSM actions. Its state is read array mode upon
power-up, after exit from deep power-down or after
V
transitions below V
.
CC
LKO
In addition, deep power-down mode ensures
extremely low power consumption even when system
power is applied. For example, portable computing
products and other power sensitive applications that
use an array of devices for solid-state storage can
After block erase, full chip erase, (multi) word/byte
write or block lock-bit configuration, even after V
transitions down to V
read array mode via the Read Array command if
subsequent access to the memory array is desired.
PP
, the CUI must be placed in
PPLK
consume negligible power by lowering RP# to V
IL
standby or sleep modes. If access is again needed,
the devices can be read following the t
and
5.6 Power-Up/Down Protection
PHQV
t
wake-up cycles required after RP# is first
PHWL
raised to V . See AC Characteristics⎯ Read Only
and Write Operations and Figures 17, 18, 19, 20 for
more information.
The device is designed to offer protection against
accidental block and full chip erasure, (multi)
word/byte writing or block lock-bit configuration during
power transitions. Upon power-up, the device is
IH
indifferent as to which power supply (V
or V
)
PP
CC
Rev. 2.0
LHF16KS1
32
*WARNING: Stressing the device beyond the
"Absolute Maximum Ratings" may cause permanent
damage. These are stress ratings only. Operation
beyond the "Operating Conditions" is not
recommended and extended exposure beyond the
"Operating Conditions" may affect device reliability.
6 ELECTRICAL SPECIFICATIONS
6.1 Absolute Maximum Ratings*
Operating Temperature
During Read, Erase, Write and
Block Lock-Bit Configuration .....-40°C to +85°C
(1)
NOTES:
Temperature under Bias............... -40°C to +85°C
Storage Temperature........................ -65°C to +125°C
Voltage On Any Pin
1. Operating
temperature
is
for
extended
temperature product defined by this specification.
2. All specified voltages are with respect to GND.
Minimum DC voltage is -0.5V on input/output pins
and -0.2V on
V
and
V
pins. During
(2)
CC
PP
(except V , V )............... -0.5V to V +0.5V
CC
PP
CC
transitions, this level may undershoot to -2.0V for
periods <20ns. Maximum DC voltage on
(2)
V
V
Suply Voltage............................-0.2V to +7.0V
CC
input/output pins and V
is V +0.5V which,
CC
CC
during transitions, may overshoot to V +2.0V for
CC
Update Voltage during
PP
periods <20ns.
Erase, Write and
Block Lock-Bit Configuration ......-0.2V to +7.0V
3. Output shorted for no more than one second. No
more than one output shorted at a time.
(2)
(3)
Output Short Circuit Current ........................ 100mA
6.2 Operating Conditions
Temperature and V Operating Conditions
CC
Symbol
Parameter
Operating Temperature
Min.
-40
4.75
4.50
Max.
+85
5.25
5.50
Unit
°C
V
Test Condition
Ambient Temperature
T
A
V
V
V
Supply Voltage (5V±0.25V)
Supply Voltage (5V±0.5V)
CC1
CC
CC
V
V
CC2
(1)
6.2.1 CAPACITANCE
T =+25°C, f=1MHz
A
Symbol
Parameter
Input Capacitance
Output Capacitance
Typ.
7
9
Max.
10
12
Unit
pF
pF
Condition
C
V =0.0V
IN
IN
C
V
=0.0V
OUT
OUT
NOTE:
1. Sampled, not 100% tested.
Rev. 2.0
LHF16KS1
6.2.2 AC INPUT/OUTPUT TEST CONDITIONS
33
3.0
1.5
INPUT
1.5
TEST POINTS
OUTPUT
0.0
AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 14. Transient Input/Output Reference Waveform for V =5V±0.25V
CC
(High Speed Testing Configuration)
2.4
2.0
0.8
2.0
0.8
INPUT
TEST POINTS
OUTPUT
0.45
AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0." Input timing begins at VIH
(2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.
Figure 15. Transient Input/Output Reference Waveform for V =5V±0.5V
CC
(Standard Testing Configuration)
Test Configuration Capacitance Loading Value
1.3V
Test Configuration
C (pF)
L
V
V
=5V±0.25V
30
100
1N914
CC
=5V±0.5V
CC
RL=3.3kΩ
DEVICE
UNDER
TEST
OUT
CL Includes Jig
Capacitance
CL
Figure 16. Transient Equivalent Testing
Load Circuit
Rev. 2.0
LHF16KS1
34
6.2.3 DC CHARACTERISTICS
DC Characteristics
V
=5V
Test
CC
Symbol
Parameter
Notes
Typ.
Max.
Unit
Conditions
I
Input Load Current
1
V
=V Max.
LI
CC CC
±1
µA
V =V or GND
IN
CC
I
Output Leakage Current
1
V
V
=V Max.
LO
CC
CC
±10
100
µA
µA
=V or GND
OUT
CC
I
V
Standby Current
1,3,6
CMOS Inputs
V =V Max.
CC
CE#=RP#=V ±0.2V
TTL Inputs
V
CE#=RP#=V
RP#=GND±0.2V
I (STS)=0mA
OUT
CCS
CC
25
2
CC
CC
4
mA
µA
=V Max.
CC CC
IH
I
V
Deep Power-Down
1
CCD
CC
20
Current
I
V
Read Current
1,5,6
CMOS Inputs
=V Max.
CE#=GND
CCR
CC
V
CC
CC
50
mA
f=8MHz, I
=0mA
OUT
TTL Inputs
V =V Max., CE#=V
CC
65
35
mA
mA
CC
IL
f=8MHz, I
=0mA
OUT
I
V
Write Current
CC
1,7
1,7
CCW
((Multi) W/B Write or Set Block
Lock Bit)
V
V
V
=5.0V±0.5V
=5.0V±0.5V
PP
PP
I
Erase Current
CC
CCE
(Block Erase, Full Chip Erase,
Clear Block Lock Bits)
30
10
mA
mA
I
I
I
V
Write or Block Erase
CC
1,2
1
CCWS
1
CE#=V
IH
Suspend Current
V
CCES
Standby Current
±2
10
±15
200
µA
µA
V
V
≤V
>V
PPS
PP
PP
PP
CC
CC
I
I
V
V
Read Current
Deep Power-Down
1
1
PPR
PP
PP
PPD
0.1
5
µA
RP#=GND±0.2V
Current
Write Current
I
V
1,7
1,7
1
PPW
PP
((Multi) W/B Write or Set Block
Lock Bit)
V
(Block Erase, Full Chip Erase,
Clear Block Lock Bits)
V
80
mA
V
=5.0V±0.5V
=5.0V±0.5V
PP
I
Erase Current
PP
PPE
40
mA
µA
V
V
PP
I
I
Write or Block Erase
PP
PPWS
10
200
=V
PP
PPH1
Suspend Current
PPES
Rev. 2.0
LHF16KS1
35
DC Characteristics (Continued)
V
=5V
Test
CC
Symbol
Parameter
Input Low Voltage
Input High Voltage
Notes
Min.
-0.5
Max.
0.8
Unit
V
Conditions
V
7
7
IL
V
V
IH
CC
2.0
V
V
V
V
V
V
+0.5
V
Output Low Voltage
3,7
3,7
3,7
V
I
=V Min.
CC CC
=5.8mA
OL
0.45
OL
V
Output High Voltage
(TTL)
Output High Voltage
(CMOS)
V
I
=V Min.
OH1
CC
CC
2.4
=-2.5mA
OH
V
0.85
V
I
=V Min.
OH2
CC
CC
V
=-2.5mA
CC
OH
V
V
I
=V Min.
CC
CC
CC
-0.4
=-100µA
OH
V
V
Lockout during Normal
PP
4,7
PPLK
1.5
5.5
Operations
during Write or Erase
V
V
PP
PPH1
4.5
2.0
V
V
Operations
Lockout Voltage
V
V
CC
LKO
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal V voltage and T =+25°C.
CC
A
2. I
and I
are specified with the device de-selected. If read or byte written while in erase suspend mode,
CCWS
CCES
the device’s current draw is the sum of I
3. Includes STS.
or I
and I
or I
, respectively.
CCW
CCWS
CCES
CCR
4. Block erases, full chip erases, (multi) word/byte writes and block lock-bit configurations are inhibited when
V
≤V , and not guaranteed in the range between V (max.) and V (min.) and above V (max.).
PP
PPLK
PPLK
PPH1
PPH1
5. Automatic Power Savings (APS) reduces typical I
to 1mA at 5V V in static operation.
CCR
CC
6. CMOS inputs are either V ±0.2V or GND±0.2V. TTL inputs are either V or V .
CC
IL
IH
7. Sampled, not 100% tested.
Rev. 2.0
LHF16KS1
36
(1)
6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS
V
=5V±0.5V, 5V±0.25V, T =-40°C to +85°C
A
CC
LH28F160S5H-
V
=5V±0.25V
V =5V±0.5V
CC
CC
(5)
L70
LH28F160S5H-
(4)
Versions
(6)
L90
Sym.
Parameter
Notes
Min.
Max.
Min.
Max.
Unit
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
Address to Output Delay
CE# to Output Delay
RP# High to Output Delay
OE# to Output Delay
CE# to Output in Low Z
CE# High to Output in High Z
OE# to Output in Low Z
OE# High to Output in High Z
70
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVQV
ELQV
PHQV
GLQV
ELQX
EHQZ
GLQX
GHQZ
OH
70
70
400
30
90
90
400
35
2
2
3
3
3
3
0
0
0
0
25
10
30
10
Output Hold from Address, CE# or
OE# Change, Whichever Occurs First
BYTE# to Output Delay
3
0
0
ns
t
t
t
t
t
FLQV
FHQV
FLQZ
ELFL
ELFH
3
3
3
70
25
5
90
30
5
ns
ns
ns
BYTE# to Output in High Z
CE# Low to BYTE# High or Low
NOTES:
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE# may be delayed up to t
3. Sampled, not 100% tested.
-t
after the falling edge of CE# without impact on t
.
ELQV GLQV
ELQV
4. See Ordering Information for device speeds (valid operational combinations).
5. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Speed
Configuration) for testing characteristics.
6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard
Configuration) for testing characteristics.
Rev. 2.0
LHF16KS1
37
Device
Address Selection
Standby
Data Valid
VIH
ADDRESSES(A)
Address Stable
VIL
tAVAV
VIH
CE#(E)
VIL
tEHQZ
VIH
OE#(G)
VIL
tGHQZ
VIH
WE#(W)
VIL
tGLQV
tELQV
tGLQX
tELQX
tOH
VOH
DATA(D/Q)
VOL
HIGH Z
HIGH Z
Valid Output
tAVQV
V
CC
tPHQV
VIH
RP#(P)
VIL
NOTE: CE# is defined as the latter of CE0# and CE1# going Low or the first of CE0# or CE1# going High.
Figure 17. AC Waveform for Read Operations
Rev. 2.0
LHF16KS1
38
Device
Address Selection
Standby
Data Valid
VIH
ADDRESSES(A)
Address Stable
VIL
tAVAV
VIH
CE#(E)
VIL
tEHQZ
tAVFL=tELFL
VIH
OE#(G)
VIL
tGHQZ
tELFL
tFLQV=tAVQV
VIH
BYTE#(F)
VIL
tGLQV
tELQV
tOH
tGLQX
tELQX
VOH
HIGH Z
HIGH Z
HIGH Z
DATA(D/Q)
Valid
Output
Data Output
tFLQZ
(DQ -DQ )
0
7
VOL
tAVQV
VOH
HIGH Z
DATA(D/Q)
(DQ -DQ
Data
Output
)
15
8
VOL
NOTE: CE# is defined as the latter of CE0# and CE1# going Low or the first of CE0# or CE1# going High.
Figure 18. BYTE# Timing Waveforms
Rev. 2.0
LHF16KS1
39
(1)
6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS
V
=5V±0.5V, 5V±0.25V, T =-40°C to +85°C
CC
A
LH28F160S5H-
V
=5V±0.25V
V =5V±0.5V
CC
CC
(7)
L70
LH28F160S5H-
(5)
Versions
(8)
L90
Sym.
Parameter
Notes
Min.
Max.
Min.
Max.
Unit
t
t
Write Cycle Time
RP# High Recovery to WE# Going
Low
70
90
ns
AVAV
PHWL
2
1
1
µs
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CE# Setup to WE# Going Low
WE# Pulse Width
10
40
100
100
40
40
5
5
10
30
10
40
100
100
40
40
5
5
10
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELWL
WLWH
SHWH
VPWH
AVWH
DVWH
WHDX
WHAX
WHEH
WHWL
WHRL
WHGL
QVVL
WP# V Setup to WE# Going High
2
2
3
3
IH
V
Setup to WE# Going High
PP
Address Setup to WE# Going High
Data Setup to WE# Going High
Data Hold from WE# High
Address Hold from WE# High
CE# Hold from WE# High
WE# Pulse Width High
WE# High to STS Going Low
Write Recovery before Read
90
90
0
0
0
0
V
Hold from Valid SRD, STS High Z
2,4
2,4
PP
WP# V Hold from Valid SRD, STS
QVSL
IH
0
0
ns
High Z
t
t
BYTE# Setup to WE# Going High
BYTE# Hold from WE# High
50
NOTE 6
50
NOTE 6
ns
ns
FVWH
WHFV
NOTES:
1. Read timing characteristics during block erase, full chip erase, (multi) wrod/byte write and block lock-bit
configuration operations are the same as during read-only operations. Refer to AC Characteristics for read-only
operations.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid A and D for block erase, full chip erase, (multi) word/byte write or block lock-bit
IN
IN
configuration.
4. V should be held at V
until determination of block erase, full chip erase, (multi) word/byte write or block
PP
PPH1
lock-bit configuration success (SR.1/3/4/5=0).
5. See Ordering Information for device speeds (valid operational combinations).
6. BYTE# should be in stable until determination of block erase, full chip erase, (multi) word/byte write, block lock-
bit configuration or STS configuration success (SR.7=1).
7. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed
Configuration) for testing characteristics.
8. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard
Configuration) for testing characteristics.
Rev. 2.0
LHF16KS1
40
1
2
3
4
5
6
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
AIN
AIN
ADDRESSES(A)
CE#(E)
tWHAX
tAVAV
tAVWH
tELWL
tWHEH
tWHGL
OE#(G)
tWHQV1,2,3,4
tWHWL
WE#(W)
tWLWH
tDVWH
tWHDX
High Z
Valid
SRD
DIN
DIN
DIN
DATA(D/Q)
BYTE#(F)
STS(R)
tPHWL
tFVWH
tWHFV
tWHRL
High Z
VOL
VIH
tQVSL
tSHWH
WP#(S)
VIL
VIH
VIL
RP#(P)
tVPWH
tQVVL
VPPH1
VPPLK
VIL
V
(V)
PP
NOTES:
1. VCC power-up and standby.
2. Write each setup command.
3. Write each confirm command or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
7. CE# is defined as the latter of CE0# and CE1# going Low or the first of CE0# or CE1# going High.
Figure 19. AC Waveform for WE#-Controlled Write Operations
Rev. 2.0
LHF16KS1
41
(1)
6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES
V
=5V±0.5V, 5V±0.25V, T =-40°C to +85°C
A
CC
LH28F160S5H-
V
=5V±0.25V
V =5V±0.5V
CC
CC
(7)
L70
LH28F160S5H-
(5)
Versions
(8)
L90
Sym.
Parameter
Write Cycle Time
RP# High Recovery to CE# Going Low
WE# Setup to CE# Going Low
CE# Pulse Width
Notes
Min.
70
1
Max.
Min.
90
1
Max.
Unit
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
PHEL
WLEL
ELEH
SHEH
VPEH
AVEH
DVEH
EHDX
EHAX
EHWH
EHEL
EHRL
EHGL
QVVL
QVSL
2
0
0
50
100
100
40
40
5
5
0
25
50
100
100
40
40
5
5
0
25
WP# V Setup to CE# Going High
2
2
3
3
IH
V
Setup to CE# Going High
PP
Address Setup to CE# Going High
Data Setup to CE# Going High
Data Hold from CE# High
Address Hold from CE# High
WE# Hold from CE# High
CE# Pulse Width High
CE# High to STS Going Low
Write Recovery before Read
Hold from Valid SRD, STS High Z
WP# V Hold from Valid SRD, STS
90
90
0
0
0
0
V
2,4
2,4
PP
IH
0
0
ns
High Z
t
t
BYTE# Setup to CE# Going High
BYTE# Hold from CE# High
50
NOTE 6
50
NOTE 6
ns
ns
FVEH
EHFV
NOTES:
1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold and
inactive WE# times should be measured relative to the CE# waveform.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid A and D for block erase, full chip erase, (multi) word/byte write or block lock-bit
IN
IN
configuration.
4. V should be held at V
until determination of block erase, full chip erase, (multi) word/byte write or block
PP
PPH1
lock-bit configuration success (SR.1/3/4/5=0).
5. See Ordering Information for device speeds (valid operational combinations).
6. BYTE# should be in stable until determination of block erase, full chip erase, (multi) word/byte write, block lock-
bit configuration or STS configuration success (SR.7=1).
7. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed
Configuration) for testing characteristics.
8. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard
Configuration) for testing characteristics.
Rev. 2.0
LHF16KS1
42
1
2
3
4
5
6
VIH
VIL
AIN
AIN
ADDRESSES(A)
CE#(E)
tEHAX
tAVEH
tEHEL
tELEH
tDVEH
tAVAV
VIH
VIL
tEHGL
VIH
OE#(G)
VIL
VIH
WE#(W)
VIL
tEHQV1,2,3,4
tEHWH
tEHDX
tWLEL
VIH
High Z
Valid
SRD
DIN
DIN
DIN
DATA(D/Q)
BYTE#(F)
STS(R)
VIL
tPHEL
tFVEH
tEHFV
VIH
VIL
tEHRL
High Z
VOL
VIH
tQVSL
tSHEH
WP#(S)
VIL
VIH
RP#(P)
VIL
tVPEH
tQVVL
VPPH1
VPPLK
VIL
V
(V)
PP
NOTES:
1. VCC power-up and standby.
2. Write each setup command.
3. Write each confirm command or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
7. CE# is defined as the latter of CE0# and CE1# going Low or the first of CE0# or CE1# going High.
Figure 20. AC Waveform for CE#-Controlled Write Operations
Rev. 2.0
LHF16KS1
43
6.2.7 RESET OPERATIONS
High Z
STS(R)
VOL
VIH
RP#(P)
VIL
tPLPH
(A)Reset During Read Array Mode
High Z
STS(R)
VOL
tPLRH
VIH
RP#(P)
VIL
tPLPH
(B)Reset During Block Erase, Full Chip Erase, (Multi) Word/Byte Write
or Block Lock-Bit Configuretion
5V
VCC
VIL
t5VPH
VIH
RP#(P)
VIL
(C)VCC Power Up Timing
Figure 21. AC Waveform for Reset Operation
Reset AC Specifications
V
=5V
CC
Symbol
Parameter
Notes
Min.
Max.
Unit
t
RP# Pulse Low Time
PLPH
100
ns
(If RP# is tied to V , this specification is not applicable)
CC
t
RP# Low to Reset during Block Erase, Full Chip Erase,
(Multi) Word/Byte Write or Block Lock-Bit Configuration
PLRH
1,2
3
13.1
µs
ns
t
V
at 4.5V to RP# High
CC
100
5VPH
NOTES:
1. If RP# is asserted while a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration
operation is not executing, the reset will complete within 100ns.
2. A reset time, t
, is required from the latter of STS going High Z or RP# going high until outputs are valid.
PHQV
3. When the device power-up, holding RP# low minimum 100ns is required after V has been in predefined range
CC
and also has been in stable there.
Rev. 2.0
LHF16KS1
44
6.2.8 BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE AND BLOCK
(3)
LOCK-BIT CONFIGURATION PERFORMANCE
V
=5V±0.5V, 5V±0.25V, T =-40°C to +85°C
A
CC
V
Typ.
=4.5V-5.5V
PP
(1)
Sym.
Parameter
Notes
Max.
Unit
t
t
t
t
Word/Byte Write Time
(using W/B write, in word mode)
Word/Byte Write Time
(using W/B write, in byte mode)
Word/Byte Write Time
(using multi word/byte write)
Block Write Time
(using W/B write, in word mode)
Block Write Time
(using W/B write, in byte mode)
Block Write Time
WHQV1
EHQV1
WHQV1
EHQV1
2
9.24
120
120
120
3.7
7.5
1.5
µs
µs
µs
s
2
2
2
2
2
2
9.24
2
0.31
0.61
0.13
s
s
(using multi word/byte write)
t
t
WHQV2
EHQV2
Block Erase Time
0.34
10.9
9.24
10
s
s
Full Chip Erase Time
Set Block Lock-Bit Time
320
120
t
t
t
t
t
t
t
t
WHQV3
EHQV3
WHQV4
EHQV4
WHRH1
EHRH1
WHRH2
EHRH2
2
2
µs
Clear Block Lock-Bits Time
0.34
5.6
10
7
s
Write Suspend Latency Time to Read
Erase Suspend Latency Time to Read
µs
µs
9.4
13.1
NOTES:
1. Typical values measured at T =+25°C and nominal voltages. Assumes corresponding block lock-bits are not
A
set. Subject to change based on device characterization.
2. Excludes system-level overhead.
3. Sampled but not 100% tested.
Rev. 2.0
LHF16KS1
45
7 ADDITIONAL INFORMATION
7.1 Ordering Information
Product line designator for all SHARP Flash products
-
1
S
2 8 1 6 0 5
S H NS
L H
F
Device Density
160 = 16-Mbit
Access Speed (ns)
70:70ns (5V,30pF), 90ns (5V)
10:100ns (5V)
Architecture
Package
S = Regular Block
T = 56-Lead TSOP
R = 56-Lead TSOP(Reverse Bend)
NS = 56-Lead SSOP
B = 64-Ball CSP
Power Supply Type
5 = Smart 5 Technology
Operating Temperature
Blank = 0°C ~ +70°C
H = -40°C ~ +85°C
D = 64-Lead SDIP
Valid Operational Combinations
V
=5V±0.5V
V
=5V±0.25V
CC
CC
100pF load,
TTL I/O Levels
LH28F160S5H-L90
30pF load,
1.5V I/O Levels
LH28F160S5H-L70
Option
Order Code
1
LH28F160S5HNS-S1
Rev. 2.0
i
A-1 RECOMMENDED OPERATING CONDITIONS
A-1.1 At Device Power-Up
AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
VCC(min)
VCC
GND
*1
tVR
tR
t2VPH
tPHQV
VIH
(P)
RP#
(RST#)
VIL
VCCWH1/2
(VPPH1/2)
*2
(V)
VCCW
(VPP)
GND
tR or tF
tR or tF
tAVQV
VIH
Valid
Address
ADDRESS (A)
VIL
tR
tF
tELQV
VIH
VIL
VIH
VIL
VIH
VIL
VIH
(E)
CE#
(W)
WE#
tR
tF
tGLQV
(G)
OE#
(S)
WP#
VIL
VOH
High Z
Valid
Output
DATA
(D/Q)
V
OL
*1 t5VPH for the device in 5V operations.
*2 To prevent the unwanted writes, system designers should consider the VCCW (VPP) switch, which connects VCCW (VPP)
to GND during read operations and VCCWH1/2 (VPPH1/2) during write or erase operations.
See the application note AP-007-SW-E for details.
Figure A-1. AC Timing at Device Power-Up
For the AC specifications t , t , t in the figure, refer to the next page. See the “ELECTRICAL SPECIFICATIONS“
VR
R
F
described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in
the next page.
Rev. 1.10
ii
A-1.1.1 Rise and Fall Time
Symbol
Parameter
Notes
1
Min.
0.5
Max.
Unit
t
t
t
V
Rise Time
CC
30000
µs/V
µs/V
µs/V
VR
Input Signal Rise Time
Input Signal Fall Time
1, 2
1, 2
1
1
R
F
NOTES:
1. Sampled, not 100% tested.
2. This specification is applied for not only the device power-up but also the normal operations.
t (Max.) and t (Max.) for RP# (RST#) are 100µs/V.
R
F
Rev. 1.10
iii
A-1.2 Glitch Noises
Do not input the glitch noises which are below V (Min.) or above V (Max.) on address, data, reset, and control signals,
IH
IL
as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a).
Input Signal
VIH (Min.)
Input Signal
VIH (Min.)
VIL (Max.)
VIL (Max.)
Input Signal
Input Signal
(a) Acceptable Glitch Noises
(b) NOT Acceptable Glitch Noises
Figure A-2. Waveform for Glitch Noises
See the “DC CHARACTERISTICS“ described in specifications for V (Min.) and V (Max.).
IH
IL
Rev. 1.10
iv
(1)
A-2 RELATED DOCUMENT INFORMATION
Document No.
Document Name
AP-001-SD-E
AP-006-PT-E
AP-007-SW-E
Flash Memory Family Software Drivers
Data Protection Method of SHARP Flash Memory
RP#, V Electric Potential Switching Circuit
PP
NOTE:
1. International customers should contact their local SHARP or distribution sales office.
Rev. 1.10
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited
Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied.
ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND
FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible,
for any incidental or consequential economic or property damage.
NORTH AMERICA
EUROPE
JAPAN
SHARP Corporation
SHARP Microelectronics of the Americas
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Phone: (1) 360-834-2500
Fax: (1) 360-834-8903
SHARP Microelectronics Europe
Division of Sharp Electronics (Europe) GmbH
Sonninstrasse 3
20097 Hamburg, Germany
Phone: (49) 40-2376-2286
Fax: (49) 40-2376-2232
Electronic Components & Devices
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Osaka 545-8522, Japan
Phone: (81) 6-6621-1221
Fax: (81) 6117-725300/6117-725301
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Fast Info: (1) 800-833-9437
www.sharpsma.com
www.sharpsme.com
TAIWAN
SINGAPORE
KOREA
SHARP Electronic Components
(Korea) Corporation
RM 501 Geosung B/D, 541
Dohwa-dong, Mapo-ku
Seoul 121-701, Korea
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(Taiwan) Corporation
8F-A, No. 16, Sec. 4, Nanking E. Rd.
Taipei, Taiwan, Republic of China
Phone: (886) 2-2577-7341
SHARP Electronics (Singapore) PTE., Ltd.
438A, Alexandra Road, #05-01/02
Alexandra Technopark,
Singapore 119967
Phone: (65) 271-3566
Phone: (82) 2-711-5813 ~ 8
Fax: (82) 2-711-5819
Fax: (886) 2-2577-7326/2-2577-7328
Fax: (65) 271-3855
CHINA
HONG KONG
SHARP Microelectronics of China
(Shanghai) Co., Ltd.
SHARP-ROXY (Hong Kong) Ltd.
3rd Business Division,
28 Xin Jin Qiao Road King Tower 16F
Pudong Shanghai, 201206 P.R. China
Phone: (86) 21-5854-7710/21-5834-6056
Fax: (86) 21-5854-4340/21-5834-6057
Head Office:
17/F, Admiralty Centre, Tower 1
18 Harcourt Road, Hong Kong
Phone: (852) 28229311
Fax: (852) 28660779
www.sharp.com.hk
No. 360, Bashen Road,
Xin Development Bldg. 22
Shenzhen Representative Office:
Room 13B1, Tower C,
Waigaoqiao Free Trade Zone Shanghai
200131 P.R. China
Electronics Science & Technology Building
Shen Nan Zhong Road
Email: smc@china.global.sharp.co.jp
Shenzhen, P.R. China
Phone: (86) 755-3273731
Fax: (86) 755-3273735
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