LH28F400SUB [SHARP]
4M (512K 】 8, 256K 】 16) Flash Memory; 4M （ 512K × 8 ， 256K × 16 ）快闪记忆体
| 型号： | LH28F400SUB |
| 厂家： | 
SHARP ELECTRIONIC COMPONENTS |
| 描述： | 4M (512K 】 8, 256K 】 16) Flash Memory |
| 文件： | 总34页 (文件大小：276K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4M (512K × 8, 256K × 16)
Flash Memory
LH28F400SUB-Z0
49-PIN CSP
TOP VIEW
FEATURES
• User-Configurable x8 or x16 Operation
1
2
3
4
5
6
7
• 5 V Write/Erase Operation
A
B
C
D
E
A1
A4
A7
VPP
A9
A12
A15
(5V V , 3.3V V )
PP
CC
– No Requirement for DC/DC Converter to
Write/Erase
A2
A3
A5
A6
A17
RY/BY
NC
RP
NC
NC
A8
WE
NC
A11
A10
A14
A13
• 150 ns Maximum Access Time
(V = 3.3 V ± 0.3 V)
CC
A0
DQ9
DQ13 A16
• Min. 2.7 V Read Capability
DQ15
/
OE
DQ1 DQ3 DQ11 DQ4 DQ6
A-1
– 160 ns Maximum Access Time
(V = 2.7 V)
CC
F GND DQ8 DQ10 VCC DQ12 DQ14 GND
• 32 Independently Lockable Blocks (16K)
• 100,000 Erase Cycles per Block
G
CE
DQ0 DQ2 VCC DQ5 DQ7
BYTE
• Automated Byte Write/Block Erase
– Command User Interface
– Status Register
28F400SUB-1
Figure 1. CSP Configuration
– RY»/BY» Status Output
• System Performance Enhancement
– Erase Suspend for Read
– Two-Byte Write
– Full Chip Erase
• Data Protection
– Hardware Erase/Write Lockout during
Power Transition
– Software Erase/Write Lockout
• Independently Lockable for Write/Erase
on Each Block (Lock Block and Protect
Set/Reset)
• 4 µA (Typ.) I in CMOS Standby
CC
• 0.2 µA (Typ.) Deep Power-Down
• State-of-the-Art 0.45 µm ETOX™ Flash
Technology
• Extended Temperature Operation
– -20°C to +85°C
• 49-Pin, .67 mm × 8 mm × 8 mm
CSP Package
1
LH28F400SUB-Z0
4M (512K × 8, 256K × 16) Flash Memory
DQ8 - DQ15
DQ0 - DQ7
OUTPUT
BUFFER
OUTPUT
BUFFER
INPUT
BUFFER
INPUT
BUFFER
DATA
QUEUE
REGISTERS
ID
I/O
LOGIC
BYTE
REGISTER
CSR
OUTPUT
MULTIPLEXER
REGISTER
ESRs
CE
OE
WE
RP
CUI
DATA
COMPARATOR
INPUT
BUFFER
A-1,0 - A17
Y GATING/SENSING
Y-DECODER
X-DECODER
RY/BY
WSM
ADDRESS
QUEUE
LATCHES
. . .
. . .
PROGRAM/
ERASE
VOLTAGE
SWITCH
ADDRESS
COUNTER
VPP
VCC
GND
28F400SUB-2
Figure 2. LH28F400SU Block Diagram
2
4M (512K × 8, 256K × 16) Flash Memory
LH28F400SUB-Z0
PIN DESCRIPTION
SYMBOL
TYPE
NAME AND FUNCTION
BYTE-SELECT ADDRESSES: Selects between high and low byte when device is in
x8 mode. This address is latched in x8 Data Writes. Not used in x16 mode (i.e., the
DQ15/A-1 Input buffer is turned off when BYTE is high).
DQ15 - A-1 INPUT
WORD-SELECT ADDRESSES: Select a word within one 16K block. These
addresses are latched during Data Writes.
A0 - A12
INPUT
INPUT
BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These addresses are
latched during Data Writes, Erase and Lock-Block operations.
A13 - A17
LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles.
DQ0 - DQ7 INPUT/OUTPUT Outputs array, buffer, identifier or status data in the appropriate Read mode.
Floated when the chip is de-selected or the outputs are disabled.
HIGH-BYTE DATA BUS: Inputs data during x16 Data Write operations. Outputs
array, buffer or identifier data in the appropriate Read mode; not used for Status
register reads. Floated when the chip is de-selected or the outputs are disabled.
DQ8 - DQ15 INPUT/OUTPUT
DQ15/A-1 is address.
CHIP ENABLE INPUT: Activate the device’s control logic, input buffers, decoders
and sense amplifiers. CE» must be low to select the device.
CE»
RP»
INPUT
INPUT
RESET/POWER-DOWN: With RP» low, the device is reset, any current operation is
aborted and device is put into the deep power down mode. When the power is
turned on, RP» pin is turned to low in order to return the device to default con-
figuration. When the power transition is occurred, or the power on/off, RP» is
required to stay low in order to protect data from noise. When returning from Deep
Power-Down, a recovery time of 750 ns is required to allow these circuits to power-
up. When RP» goes low, any current or pending WSM operation(s) are terminated,
and the device is reset. All Status registers return to ready (with all status flags
cleared). After returning, the device is in read array mode.
OUTPUT ENABLE: Gates device data through the output buffers when low. The
outputs float to tri-state off when OE» is high.
OE»
INPUT
INPUT
WRITE ENABLE: Controls access to the CUI, Data Queue Registers and Address
Queue Latches. WE is active low, and latches both address and data (command or
array) on its rising edge.
WE
READY/BUSY: Indicates status of the internal WSM. When low, it indicates that the
WSM is busy performing an operation. When the WSM is ready for new operation or
Erase is Suspended, or the device is in deep power-down mode RY/» BY» pin is floated.
OPEN DRAIN
OUTPUT
RY»/BY»
BYTE ENABLE: BYTE low places device in x8 mode. All data is then input or
output on DQ0 - DQ7, and DQ8 - DQ15 float. Address A-1 selects between the high
INPUT
BYTE
VPP
and low byte. BYTE high places the device in x16 mode, and turns off the A
-1
input buffer. Address A0, then becomes the lowest order address.
ERASE/WRITE POWER SUPPLY (5.0 V ±0.5 V): For erasing memory array blocks
or writing words/bytes into the flash array.
SUPPLY
VCC
GND
NC
SUPPLY
SUPPLY
DEVICE POWER SUPPLY (3.0 V ±0.3 V): Do not leave any power pins floating.
GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating.
NO CONNECT: No internal connection to die, lead may be driven or left floating
3
LH28F400SUB-Z0
4M (512K × 8, 256K × 16) Flash Memory
INTRODUCTION
A Command User Interface (CUI) serves as the sys-
tem interface between the microprocessor or
microcontroller and the internal memory operation.
Sharp’s LH28F400SU 4M Flash Memory is a revolu-
tionary architecture which enables the design of truly
mobile, high performance, personal computing and
communication products. With innovative capabilities,
3.3V low power operation and very high read/write per-
formance, the LH28F400SU is also the ideal choice for
designing embedded mass storage flash memory
systems.
Internal Algorithm Automation allowsByteWrites and
Block Erase operations to be executed using a Two-
Write command sequence to the CUI in the same way
as the LH28F008SA 8M Flash memory.
A Superset of commands have been added to the
basic LH28F008SA command-set to achieve higher
write performance and provide additional capabilities.
These new commands and features include:
The LH28F400SU’s independently lockable 32 sym-
metrical blocked architecture (16K each) extended
cycling, low power operation, very fast write and read
performance and selective block locking provide a highly
flexible memory component suitable for cellular phone,
facsimile, game, PC, printer and handy terminal. The
LH28F400SU’s 5.0 V/3.3 V power supply operation
enables the design of memory cards which can be read
in 3.3 V system and written in 5.0 V/3.3 V systems. Its
x8/x16 architecture allows the optimization of memory
to processor interface.The flexible block locking option
enables bundling of executable application software in
a Resident Flash Array or memory card. Manufactured
on Sharp’s 0.45 µm ETOX™ process technology, the
LH28F400SU is the most cost-effective, high-density
3.3 V flash memory.
• Software Locking of Memory Blocks
• Memory Protection Set/Reset Capability
• Two-Byte Serial Writes in 8-bit Systems
• Erase All Unlocked Blocks
Writing of memory data is performed typically within
20 µs per byte. Writing of memory data is performed
typically within 30 µs per word.A Block Erase operation
erases one of the 32 blocks in typically 0.8 seconds,
independent of the other blocks.
LH28F400SU allows to erase all unlocked blocks. It
is desirable in case of which you have to implement
Erase operation maximum 32 times.
LH28F400SU enables Two-Byte serial Write which
is operated by three times command input. Writing of
memory data is performed typically within 30 µs per
two-byte. This feature can improve 8-bit system write
performance by up to typically 15 µs per byte.
DESCRIPTION
The LH28F400SU is a high performance 4M
(4,194,304 bit) block erasable non-volatile random
access memory organized as either 256K × 16 or
512K × 8. The LH28F400SU includes thirty-two 16K
(16,384) blocks. A chip memory map is shown in
Figure 3.
All operations are started by a sequence of Write
commands to the device. Status Register (described in
detail later) and a RY»/BY» output pin provide informa-
tion on the progress of the requested operation.
The implementation of a new architecture, with many
enhanced features, will improve the device operating
characteristics and results in greater product reliability
and ease of use.
Same as the LH28F008SA, LH28F400SU requires
an operation to complete before the next operation can
be requested, also it allows to suspend block erase to
read data from any other block, and allow to resume
erase operation.
Among the significant enhancements of the
LH28F400SU:
• 3 V Read, 5 V Write/Erase Operation
The LH28F400SU provides user-selectable block
locking to protect code or data such as Device Drivers,
PCMCIA card information, ROM-Executable OS or
Application Code. Each block has an associated non-
volatile lock-bit which determines the lock status of the
block.In addition, the LH28F400SU has a software con-
trolled master Write Protect circuit which prevents any
modifications to memory blocks whose lock-bits are set.
(5V V , 3V V
)
PP
CC
• Low Power Capability (2.7 V V Read)
CC
• Improved Write Performance
• Dedicated Block Write/Erase Protection
• Command-Controlled Memory Protection
Set/ResetCapability
The LH28F400SU will be available in a 49-pin,
.67 mm thick × 8 mm × 8 mm CSP package.This form
factor and pinout allow for very high board layout densi-
ties.
4
4M (512K × 8, 256K × 16) Flash Memory
LH28F400SUB-Z0
When the device power-up or RP» turns High, Write
Protect Set/Confirm command must be written. Other-
wise, all lock bits in the device remain being locked,
can’t perform the Write to each block and single Block
Erase. Write Protect Set/Confirm command must be
written to reflect the actual lock status. However, when
the device power-on or RP » turns High, Erase All
Unlocked Blocks can be used. If used, Erase is per-
formed with reflecting actual lock status, and after that
Write and Block Erase can be used.
MEMORY MAP
7FFFFH
16KB BLOCK
31
30
29
28
27
7C000H
7BFFFH
78000H
77FFFH
74000H
73FFFH
70000H
6FFFFH
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
6C000H
6BFFFH
16KB BLOCK
16KB BLOCK
16KB BLOCK
26
25
24
68000H
67FFFH
64000H
63FFFH
60000H
5FFFFH
The LH28F400SU contains a Compatible Status
Register (CSR) which is 100% compatible with the
LH28F008SA Flash memory’s Status Register.This reg-
ister, when used alone, provides a straightforward
upgrade capability to the LH28F400SU from a
LH28F008SA-based design.
16KB BLOCK
23
5C000H
5BFFFH
58000H
57FFFH
16KB BLOCK
16KB BLOCK
16KB BLOCK
22
21
20
54000H
53FFFH
50000H
4FFFFH
The LH28F400SU incorporates an open drain
RY »/BY» output pin. This feature allows the user to OR-
tie many RY»/BY» pins together in a multiple memory con-
figuration such as a Resident Flash Array.
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
19
18
17
16
15
14
13
12
11
10
9
4C000H
4BFFFH
48000H
47FFFH
The LH28F400SU is specified for a maximum
44000H
43FFFH
access time of 150 ns (t
) at 3.3 V operation (3.0 to
ACC
40000H
3FFFFH
3.6 V) over the extended temperature range (-20 to
+85°C). A corresponding maximum access time of
3C000H
3BFFFH
160 ns (t
) at 2.7 V (-20 to +85°C) is achieved for
ACC
38000H
37FFFH
reduced power consumption applications.
34000H
33FFFH
The LH28F400SU incorporates an Automatic Power
Saving (APS) feature which substantially reduces the
active current when the device is in static mode of
operation (addresses not switching).
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
30000H
2FFFFH
2C000H
2BFFFH
28000H
27FFFH
24000H
23FFFH
In APS mode, the typical I current is 1 mA at 3.3 V.
CC
8
A Deep Power-Down mode of operation is invoked
when the RP» (called PWD on the LH28F008SA) pin
transitions low, any current operation is aborted and the
device is put into the deep power down mode.This mode
brings the device power consumption to less than 8 µA,
and provides additional write protection by acting as a
device reset pin during power transitions. When the
power is turned on, RP» pin is turned to low in order to
return the device to default configuration. When the
power transition is occurred, or at the power on/off, RP»
is required to stay low in order to protect data from noise.
A recovery time of 750 ns is required from RP» switch-
ing high until outputs are again valid.In the Deep Power-
Down state, the WSM is reset (any current operation
will abort) and the CSR register is cleared.
20000H
1FFFFH
7
1C000H
1BFFFH
6
18000H
17FFFH
5
14000H
13FFFH
16KB BLOCK
16KB BLOCK
16KB BLOCK
4
3
2
10000H
0FFFFH
0C000H
0BFFFH
08000H
07FFFH
16KB BLOCK
16KB BLOCK
1
0
04000H
03FFFH
00000H
NOTE: In Byte-wide (x8) mode A-1 is the lowest order address.
In Word-wide (x16) mode A-1 don't care, address values are
ignored A1.
28F400SUB-3
A CMOS Standby mode of operation is enabled when
CE» transitions high and RP» stays high with all input
control pins at CMOS levels. In this mode, the device
Figure 3. Memory Map
draws an I standby current of 15 µA.
CC
5
LH28F400SUB-Z0
4M (512K × 8, 256K × 16) Flash Memory
BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS
Bus Operations for Word-Wide Mode (BY»TE» = V )
IH
MODE
RP»
VIH
VIH
VIH
VIL
VIH
VIH
VIH
CE»
VIL
VIL
VIH
X
OE»
VIL
VIH
X
WE
VIH
VIH
X
A0
X
DQ0-15 RY»/BY» NOTE
Read
DOUT
High-Z
High-Z
High-Z
00B0H
ID
X
X
1, 2, 7
1, 6, 7
1, 6, 7
1, 3
Output Disable
Standby
X
X
X
Deep Power-Down
Manufacturer ID
Device ID
X
X
X
VOH
VOH
VOH
X
VIL
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIL
VIL
VIH
X
4
4
Write
DIN
1, 5, 6
Bus Operations for Byte-Wide Mode (BY»TE» = V )
IL
MODE
RP»
VIH
VIH
VIH
VIL
VIH
VIH
VIH
CE»
VIL
VIL
VIH
X
OE»
VIL
VIH
X
WE
VIH
VIH
X
A0
X
DQ0-7
DOUT
High-Z
High-Z
High-Z
B0H
RY»/BY» NOTE
Read
X
X
1, 2, 7
1, 6, 7
1, 6, 7
1, 3
Output Disable
Standby
X
X
X
Deep Power-Down
Manufacturer ID
Device ID
X
X
X
VOH
VOH
VOH
X
VIL
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIL
VIL
VIH
X
4
ID
4
Write
DIN
1, 5, 6
NOTES:
1. X can be V or V for address or control pins except for RY»/BY», which is either V or V .
IH
IL
OL
OH
2. RY»/BY» output is open drain. When the WSM is ready, Erase is suspended or the device is in deep
power-down mode, RY»/BY» will be at V if it is tied to V through a resistor. When the RY»/BY»
OH
CC
at V is independent of OE» while a WSM operation is in progress.
3. RP» OaLt GND ± 0.2 V ensures the lowest deep power-down current.
4. A at V provide manufacturer ID codes. A at V provide device ID codes. Device ID code = 23H (x8).
0
IL
0
IH
Device ID Code = 6623H (x16). All other addresses are set to zero.
5. Commands for different Erase operations, Data Write Operations, and Lock-Block operations can only
be successfully completed when V = V
.
PP
PPH
6. While the WSM is running, RY»/BY» in Level-Mode (default) stays at V until all operations are complete.
OL
RY »/BY» goes to V
when the WSM is not busy or in erase suspend mode.
OH
7. RY»/BY» may be at V while the WSM is busy performing various operations. For example, a status
OL
register read during a write operation.
6
4M (512K × 8, 256K × 16) Flash Memory
LH28F400SUB-Z0
LH28F008SA-Compatible Mode Command Bus Definitions
FIRST BUS CYCLE
COMMAND
SECOND BUS CYCLE
NOTE
OPER.
Write
Write
Write
Write
Write
Write
Write
Write
ADDRESS
DATA
FFH
90H
70H
50H
40H
10H
20H
B0H
OPER.
Read
Read
Read
ADDRESS
DATA
AD
Read Array
X
X
X
X
X
X
X
X
AA
IA
X
Intelligent Identifier
Read Compatible Status Register
Clear Status Register
Word Write
ID
1
2
3
CSRD
Write
Write
Write
Write
WA
WA
BA
X
WD
WD
Alternate Word Write
Block Erase/Confirm
Erase Suspend/Resume
D0H
D0H
4
4
ADDRESS
DATA
AA = Array Address
BA = Block Address
IA = Identifier Address
WA = Write Address
X = Don’t Care
AD = Array Data
CSRD = CSR Data
ID = Identifier Data
WD = Write Data
NOTES:
1. Following the intelligent identifier command, two Read operations access the manufacturer and device signature codes.
2. The CSR is automatically available after device enters Data Write, Erase or Suspend operations.
3. Clears CSR.3, CSR.4, and CSR.5. See Status register definitions.
4. While device performs Block Erase, if you issue Erase Suspend command (B0H), be sure to confirm ESS (Erase-Suspend-Status) is
set to 1 on compatible status register. In the case, ESS bit was not set to 1, also completed the Erase (ESS = 0, WSMS = 1), be sure
to issue Resume command (D0H) after completed next Erase command. Beside, when the Erase Suspend command is issued, while
the device is not in Erase, be sure to issue Resume command (D0H) after the next erase completed.
LH28F400SU Performance Enhancement Command Bus Definitions
FIRST BUS CYCLE
SECOND BUS CYCLE
THIRD BUS CYCLE
OPER. ADD. DATA
COMMAND
MODE
NOTE
OPER. ADD. DATA OPER. ADD.
DATA
D0H
D0H
D0H
Protect Set/Confirm
Protect Reset/Confirm
Lock Block/Confirm
Write
Write
Write
X
X
X
57H
47H
77H
Write 0FFH
Write 0FFH
1, 2
3
Write
BA
X
1, 2, 4
Erase All Unlocked
Blocks
Write
Write
X
X
A7H Write
FBH Write
D0H
1, 2
Two-Byte Write
x8
A1 WD (L, H) Write
WA WD (H, L) 1, 2, 5
ADDRESS
DATA
BA = Block Address
WA = Write Address
X = Don’t Care
AD = Array Data
WD (L, H) = Write Data (Low, High)
WD (H, L) = Write Data (High, Low)
NOTES:
1. After initial device power-up, or return from deep power-down mode, the block lock status bits default to the locked state independent of
the data in the corresponding lock bits. In order to upload the lock bit status, it requires to write Protect Set/Confirm command.
2. To reflect the actual lock-bit status, the Protect Set/Confirm command must be written after Lock Block/Confirm command.
3. When Protect Reset/Confirm command is written, all blocks can be written and erased regardless of the state of the lock-bits.
4. The Lock Block/Confirm command must be written after Protect Reset/Confirm command was written.
5. A is automatically complemented to load second byte of data A value determines which WD is supplied first: A = 0 looks at the
-1
-1
-1
WDL, A = 1 looks at the WDH. In word-wide (x16) mode A don't care.
-1
-1
6. Second bus cycle address of Protect Set/Confirm and Protect Reset/Confirm command is 0FFH. Specifically A - A = 0, A - A = 1,
9
8
7
0
others are don’t care.
7
LH28F400SUB-Z0
4M (512K × 8, 256K × 16) Flash Memory
Compatible Status Register
WSMS
7
ESS
6
ES
5
DWS
4
VPPS
3
R
2
R
1
R
0
NOTES:
CSR.7
=
=
=
=
=
WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
1. RY»/BY» output or WSMS bit must be checked to determine
completion of an operation (Erase Suspend, Erase or Data
Write) before the appropriate Status bit (ESS, ES or DWS)
is checked for success.
CSR.6
CSR.5
CSR.4
CSR.3
ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase in Progress/Completed
2. If DWS and ES are set to ‘1’ during an erase attempt, an
improper command sequence was entered. Clear the CSR
and attempt the operation again.
ERASE STATUS (ES)
1 = Error in Block Erasure
0 = Successful Block Erase
3. The VPPS bit, unlike an A/D converter, does not provide
continuous indication of V level. The WSM interrogates
PP
V
’s level only after the Data-Write or Erase command
PP
sequences have been entered, and informs the system if
DATA-WRITE STATUS (DWS)
1 = Error in Data Write
0 = Data Write Successful
V
has not been switched on. VPPS is not guaranteed to
PP
report accurate feedback between V
and V
.
PPH
PPL
4. CSR.2 - CSR.0 = Reserved for future enhancements.
These bits are reserved for future use and should be
masked out when polling the CSR.
V
STATUS (VPPS)
PP
1 = V Low Detect, Operation Abort
PP
0 = V OK
PP
4M FLASH MEMORY
The Compatible Status Register (CSR) is used to
determine which blocks are locked.In order to see Lock
Status of a certain block, a Word/Byte Write command
(WA = Block Address, WD = FFH) is written to the CUI,
after issuing Set Write Protect command. If CSR.7,
CSR.5 and CSR.4 (WSMS, ES and DWS) are set to
'1's, the block is locked. If CSR.7 is set to '1', the block is
not locked.
SOFTWARE ALGORITHMS
Overview
With the advanced Command User Interface, its Per-
formance Enhancement commands and Status Regis-
ters, the software code required to perform a given
operation may become more intensive but it will result
in much higher write/erase performance compared with
current flash memory architectures.
Reset Write Protect command enables Write/Erase
operation to each block.
In the case of Block Erase is performed, the block
lock information is also erased. Block Lock command
and SetWrite Protect command must be written to pro-
hibit Write/Erase operation to each block.
The software flowcharts describing how a given
operation proceeds are shown here. Figures 4 through
6 depict flowcharts using the 2nd generation flash de-
vice in the LH28F008SA-compatible mode. Figures 7
through 12 depict flowcharts using the 2nd generation
flash device’s performance enhancement commands
mode.
There are unassigned commands. It is not recom-
mended that the customer use any command other than
the valid commands specified in "Command Bus Defi-
nitions”.Sharp reserved the right to redefine these codes
for future functions.
When the device power-up or the device is reset by
RP» pin, all blocks come up locked. Therefore, Word/
Byte SerialWrite,Two Byte SerialWriteand Block Erase
can not be performed in each block. However, at that
time, Erase All Unlocked Block is performed normally, if
used, and reflect actual lock status, also the unlocked
block data is erased. When the device power-up or the
device is reset by RP» pin, Set Write Protect command
must be written to reflect actual block lock status.
Please do not execute reprogramming 0 for the bit
which has already been programed 0. Overwrite opera-
tion may generate unerasable bit. In case of
reporgramming 0 to the Byte data which has been pro-
gramed 1.
• Program 0 for the bit in which you want to change
data from 1 to 0.
• Program 1 for the bit which has already been pro-
Reset Write Protect command must be written be-
fore Write Block Lock command.To reflect actual block
lock status, Set Write Protect command is succeeded.
gramed 0.
For example, changing Byte data from 10111101 to
10111100 requires 11111110 programing.
8
4M (512K × 8, 256K × 16) Flash Memory
LH28F400SUB-Z0
BUS
OPERATION
START
COMMAND
COMMENTS
Write
Write
Read
Word/Byte
Write
D = 40H or 10H
A = X
WRITE 40H or 10H
D = WD
A = WA
WRITE
DATA/ADDRESS
Q = CSRD
Toggle CE or OE
to update CSRD.
A = X
READ COMPATIBLE
STATUS REGISTER
Standby
Check CSR.7
1 = WSM Ready
0 = WSM Busy
0
CSR.7 =
Repeat for subsequent Word/Byte Writes.
CSR Full Status Check can be done after each Word/Byte Write,
or after a sequence of Word/Byte Writes.
1
Write FFH after the last operation to reset device
to read array mode.
CSR FULL STATUS
CHECK IF DESIRED
See Command Bus Cycle notes for description of codes.
OPERATION
COMPLETE
CSR FULL STATUS CHECK PROCEDURE
READ CSRD
(see above)
BUS
OPERATION
COMMENTS
COMMAND
Standby
Check CSR.4, 5
1 = Data Write Unsuccessful
0 = Data Write Successful
0
DATA WRITE
SUCCESSFUL
CSR.4, 5 =
1
Check CSR.3
1 = VPP Low Detect
0 = VPP OK
Standby
CSR.3, 4, 5 should be cleared, if set, before further attempts
are initiated.
1
VPP LOW
CSR.3 =
0
DETECT
CLEAR CSRD
RETRY/ERROR
RECOVERY
28F400SUB-4
Figure 4. Word/Byte Writes with Compatible Status Register
9
LH28F400SUB-Z0
4M (512K × 8, 256K × 16) Flash Memory
START
BUS
OPERATION
COMMAND
COMMENTS
Write
Write
Read
Block Erase
Confirm
D = 20H
A = X
WRITE 20H
D = D0H
A = BA
WRITE D0H AND
BLOCK ADDRESS
Q = CSRD
Toggle CE or OE
to update CSRD.
A = X
READ COMPATIBLE
STATUS REGISTER
SUSPEND
ERASE LOOP
Standby
Check CSR.7
NO
1 = WSM Ready
0 = WSM Busy
YES
0
SUSPEND
ERASE
CSR.7 =
Repeat for subsequent Block Erasures.
CSR Full Status Check can be done after each Block Erase,
or after a sequence of Block Erasures.
1
Write FFH after the last operation to reset
device to read array mode.
CSR FULL STATUS
CHECK IF DESIRED
See Command Bus Cycle notes for description of codes.
OPERATION
COMPLETE
CSR FULL STATUS CHECK PROCEDURE
READ CSRD
(see above)
BUS
OPERATION
COMMAND
COMMENTS
Check CSR.4, 5
1 = Erase Error
Standby
0 = Erase Successful
Both 1 = Command
Sequence Error
0
1
ERASE
SUCCESSFUL
CSR.4, 5 =
1
Check CSR.3
1 = VPP Low Detect
0 = VPP OK
Standby
VPP LOW
DETECT
CSR.3, 4, 5 should be cleared, if set, before further attempts
are initiated.
CSR.3 =
0
NOTE:
If CSR.3 (VPPS) is set to '1', after clearing CSR.3/4/5,
1. Issue Reset WP command.
2. Retry Single Block Erase command.
3. Set WP command is issued, if necessary.
CLEAR CSRD
RETRY/ERROR
RECOVERY
If CSR.3 (VPPS) is set to '0', after clearing CSR.3/4/5,
1. Retry Single Block Erase command.
(NOTE)
If power is off or RP is set low during erase operation,
1. Clear CSR.3/4/5 and issue Reset WP command,
2. Retry Single Block Erase command.
3. Set WP command is issued, if necessary.
28F400SUB-5
Figure 5. Block Erase with Compatible Status Register
10
4M (512K × 8, 256K × 16) Flash Memory
LH28F400SUB-Z0
START
BUS
OPERATION
COMMAND
COMMENTS
Write
Read
Erase
Suspend
D = B0H
A = X
WRITE B0H
Q = CSRD
READ COMPATIBLE
STATUS REGISTER
Toggle CE or OE
to update CSRD.
A = X
Standby
Standby
Check CSR.7
1 = WSM Ready
0 = WSM Busy
0
CSR.7 =
Check CSR.6
1 = Erase Suspended
0 = Erase Completed
1
D = FFH
A = X
Write
Read
Read
Array
0
CSR.6 =
ERASE COMPLETED
Q = AD
1
Read must be from
block other than the
one suspended.
WRITE FFH
Write
Erase
Resume
D = D0H
A = X
READ ARRAY DATA
See Command Bus Cycle notes for description of codes.
DONE
NO
READING?
YES
WRITE D0H
WRITE FFH
READ ARRAY DATA
ERASE RESUMED
28F400SUB-6
Figure 6. Erase Suspend to Read Array with Compatible Status Register
11
LH28F400SUB-Z0
4M (512K × 8, 256K × 16) Flash Memory
BUS
OPERATION
START
COMMENTS
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
COMMAND
Read
READ COMPATIBLE
STATUS REGISTER
0
Write
Read
Reset
Write Protect
After Write D = 47H A = X,
Write D = D0H A = 0FFH
CSR.7 =
Q = CSRD
1
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
RESET WP
READ COMPATIBLE
STATUS REGISTER
Write
Write
Lock Block
Confirm
D = 77H
A = X
D = D0H
A = BA
0
CSR.7 =
Read
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
1
WRITE 77H
Write
Set
After Write D = 57H A = X,
Write Protect Write D = D0H A = 0FFH
WRITE D0H AND
BLOCK ADDRESS
NOTE:
See CSR Full Status Check for Data-Write operation.
If CSR.4, 5 is set, as it is command sequence error,
should be cleared before further attempts are initiated.
READ COMPATIBLE
STATUS REGISTER
Write FFH after the last operation to reset device to read
array mode.
See Command Bus Definitions for description of codes.
0
CSR.7 =
1
(NOTE)
1
CSR.4, 5 =
0
LOCK
ANOTHER
YES
BLOCK?
NO
SET WP
OPERATION COMPLETE
28F400SUB-7
Figure 7. Block Locking Scheme
12
4M (512K × 8, 256K × 16) Flash Memory
LH28F400SUB-Z0
START
START
RESET WP
(NOTE 1)
RESET WP
(NOTE 1)
ERASE BLOCK
(NOTE 2)
WRITE MORE
DATA TO BLOCK
(NOTE 4)
SET WP
(NOTE 3)
SET WP
(NOTE 3)
WRITE NEW DATA
TO BLOCK
OPERATION
COMPLETE
(NOTE 4)
FLOW TO ADD DATA
RELOCK BLOCK
(NOTE 5)
OPERATION
COMPLETE
FLOW TO REWRITE DATA
NOTES:
1. Use Reset-Write-Protect flowchart. Enable Write/Erase operation to all blocks.
2. Use Block-Erase flowchart. Erasing a block clears any previously established lockout for that block.
3. Use Set-Write-Protect flowchart. This step re-implements protection to locked blocks.
4. Use Word/Byte-Write or 2-Byte-Write flowchart sequences to write data.
5. Use Block-Lock flowchart to write lock bit if desired.
28F400SUB-8
Figure 8. Updating Data in a Locked Block
13
LH28F400SUB-Z0
4M (512K × 8, 256K × 16) Flash Memory
(Apply to LH28F400SU, x16/x8, 48TSOP/56TSOP/44SOP
BUS
OPERATION
START
COMMAND
COMMENTS
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
Read
READ COMPATIBLE
STATUS REGISTER
0
Write
Write
2-Byte
Write
D = FBH
A = X
CSR.7 =
D = WD
1
A-1 = 0 loads low byte
of Data Register.
A-1 = 1 loads high byte
of Data Register.
Other Addresses = X
WRITE FBH
WRITE DATA/A-1
Write
D = WD
A = WA
Internally, A-1 is automatically
complemented to load the
alternate byte location of the
Data Register.
WRITE
DATA/ADDRESS
READ COMPATIBLE
STATUS REGISTER
Q = CSRD
Read
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
0
CSR.7 =
NOTE:
If CSR.4, 5 is set, as it is command sequence error,
should be cleared before further attempts are initiated.
1
CSR Full Status Check can be done after each 2-Byte Write,
or after a sequence of 2-Byte Writes.
(NOTE)
1
Write FFH after the last operation to reset device to read
array mode.
CSR.4, 5 =
See Command Bus Cycle notes for description of codes.
0
ANOTHER
2-BYTE
YES
WRITE?
NO
OPERATION COMPLETE
28F400SUB-9
Figure 9. Two-Byte Serial Writes with Compatible Status Registers (LH28F400SU)
14
4M (512K × 8, 256K × 16) Flash Memory
LH28F400SUB-Z0
START
(NOTE)
BUS
COMMAND
COMMENTS
D = A7H
OPERATION
Write
Erase All
Unlocked
Blocks
WRITE A7H
WRITE D0H
A = X
Write
Read
D = D0H
A = X
Confirm
Q = CSRD
Toggle CE or OE
to update CSRD
A = X
READ COMPATIBLE
STATUS REGISTER
SUSPEND
ERASE LOOP
NO
Standby
Check CSR.7
1 = WSM Ready
0 = WSM Busy
0
YES
SUSPEND
ERASE
CSR.7 =
1
CSR Full Status Check can be done after Erase All Unlocked
Block, or after a sequence of Erasures.
Write FFH after the last operation to reset
device to read array mode.
See Command Bus Cycle notes for description of codes.
CSR FULL STATUS
CHECK IF DESIRED
NOTE:
If power is off or RP is set low during erase operation,
1. Clear CSR.3/4/5 and issue Reset WP command.
2. Retry Erase All Unlocked Block Erase command to
erase all blocks, or issue Single Block Erase to
erase all of the unlocked blocks in sequence.
3. Set WP command is issued, if necessary.
OPERATION
COMPLETE
CSR FULL STATUS CHECK PROCEDURE
BUS
OPERATION
READ CSRD
(see above)
COMMAND
COMMENTS
Check CSR.4, 5
Standby
1 = Erase Error
0 = Erase Successful
Both 1 = Command
Sequence Error
0
ERASE
SUCCESSFUL
CSR.4, 5 =
1
Check CSR.3
1 = VPP Low Detect
0 = VPP OK
Standby
CSR.3, 4, 5 should be cleared, if set, before further attempts
are initiated.
1
VPP LOW
DETECT
CSR.3 =
0
NOTE:
If CSR.3 (VPPS) is set to '1', after clearing CSR.3/4/5,
1. Issue Reset WP command.
2. Retry Erase All Unlocked Block Erase command to erase
all blocks, or issue Single Block Erase to erase all of the
unlocked blocks in sequence.
CLEAR CSRD
RETRY/ERROR
RECOVERY
(NOTE)
3. Set WP command is issued, if necessary.
If CSR.3 (VPPS) is set to '0', after clearing CSR.3/4/5,
1. Retry Erase All Unlocked Block Erase command.
28F400SUB-10
Figure 10. Erase All Unlocked Blocks with Compatible Status Registers
15
LH28F400SUB-Z0
4M (512K × 8, 256K × 16) Flash Memory
BUS
OPERATION
START
COMMAND
COMMENTS
Check CSR.7
Read
READ COMPATIBLE
STATUS REGISTER
1 = WSM Ready
0 = WSM Busy
Write
Write
Set
Write Protect
D = 57H
A = X
Set Confirm
D = D0H
A = 0FFH
0
CSR.7 =
(A9 - A8 = 0, A7 - A0 = 1,
Others = X)
1
Read
Read
Check CSR.7
1 = WSM Ready
0 = WSM Busy
WRITE 57H
Check CSR.4, 5
1 = Unsuccesful
0 = Successful
WRITE CONFIRM
DATA/ADDRESS
NOTE:
If CSR.4, 5 is set, as it is command sequence error,
should be cleared before further attempts are initiated.
READ COMPATIBLE
STATUS REGISTER
Upon device power-up or toggle RP, Set Write
Protect command must be written to reflect the actual
lock-bit status.
Write FFH after the last operation to reset device to
Read Array Mode.
0
CSR.7 =
See Command Bus Cycle notes for description of codes.
1
(NOTE)
1
CSR.4, 5 =
0
OPERATION
COMPLETE
28F400SUB-11
Figure 11. Set Write Protect
16
4M (512K × 8, 256K × 16) Flash Memory
LH28F400SUB-Z0
BUS
OPERATION
START
COMMAND
COMMENTS
Check CSR.7
Read
READ COMPATIBLE
STATUS REGISTER
1 = WSM Ready
0 = WSM Busy
Write
Write
Reset
Write Protect
D = 47H
A = X
Reset
Confirm
D = D0H
A = 0FFH
0
CSR.7 =
(A9 - A8 = 0, A7 - A0 = 1,
Others = X)
1
Read
Read
Check CSR.7
1 = WSM Ready
0 = WSM Busy
WRITE 47H
Check CSR.4, 5
1 = Unsuccesful
0 = Successful
WRITE CONFIRM
DATA/ADDRESS
NOTE:
If CSR.4, 5 is set, as it is command sequence error,
should be cleared before further attempts are initiated.
READ COMPATIBLE
STATUS REGISTER
Reset Write Protect command enables Write/Erase
operation to all blocks.
Write FFH after the last operation to reset device to
Read Array Mode.
0
CSR.7 =
See Command Bus Cycle notes for description of codes.
1
(NOTE)
1
CSR.4, 5 =
0
OPERATION
COMPLETE
28F400SUB-12
Figure 12. Reset Write Protect
17
LH28F400SUB-Z0
4M (512K × 8, 256K × 16) Flash Memory
NOTE:
1
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings*
1. V
supply range during read is 2.7 to 3.6 V.
CC
*WARNING: Stressing the device beyond the “Abso-
lute Maximum Ratings” may cause permanent dam-
age. These are stress ratings only. Operation beyond
the “Operating Conditions” is not recommended and
extended exposure beyond the“Operating Conditions”
may affect device reliability.
Temperature under bias ......................-20°C to +85°C
Storage temperature ......................... -65°C to +125°C
V
= 3.3 V ± 0.3 V Systems
CC
SYMBOL
TA
PARAMETER
MIN.
-20
MAX.
85.0
7.0
UNITS TEST CONDITIONS
NOTE
Operating Temperature, Commercial
VCC with Respect to GND
°C
V
Ambient Temperature
1
2
2
VCC
-0.2
-0.2
VPP
VPP Supply Voltage with Respect to GND
7.0
V
Voltage on any Pin (Except VCC, VPP
with Respect to GND
)
V
-0.5 VCC + 0.5
V
2
I
Current into any Non-Supply Pin
Output Short Circuit Current
±30
mA
mA
IOUT
100.0
3
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC voltage is -0.5 V on input/output pins. During transitions, this level may undershoot to -2.0 V for periods < 20 ns. Maximum
DC voltage on input/output pins is V + 0.5 V which, during transitions, may overshoot to V + 2.0 V for periods < 20 ns.
CC
CC
3. Output shorted for no more than one second. No more than one output shorted at a time.
Capacitance
For 3.3 V Systems
SYMBOL
PARAMETER
TYP. MAX. UNITS
TEST CONDITIONS
NOTE
Capacitance Looking into an
Address/Control Pin
7
10
pF
TA = 25°C, f = 1.0 MHz
1
CIN
Capacitance Looking into an
Address/Control Pin A-1
9
9
12
12
50
2.5
pF
pF
pF
ns
TA = 25°C, f = 1.0 MHz
TA = 25°C, f = 1.0 MHz
For VCC = 3.3 V ±0.3 V
50 Ω transmission line delay
1
1
1
COUT
Capacitance Looking into an Output Pin
Load Capacitance Driven by Outputs for
Timing Specifications
CLOAD
Equivalent Testing Load Circuit VCC ± 10%
NOTE:
1. Sampled, not 100% tested.
18
4M (512K × 8, 256K × 16) Flash Memory
LH28F400SUB-Z0
Timing Nomenclature
For 3.3 V systems use 1.5 V cross point definitions.
Each timing parameter consists of 5 characters. Some common examples are defined below:
t
t
t
t
t
t
t
t
time (t) from CE» (E) going low (L) to the outputs (Q) becoming valid (V)
time (t) from OE (G) going low (L) to the outputs (Q) becoming valid (V)
time (t) from address (A) valid (V) to the outputs (Q) becoming valid (V)
time (t) from address (A) valid (V) to WE (W) going high (H)
time (t) from WE» (W) going high (H) to when the data (D) can become undefined (X)
CE
OE
ELQV
GLQV
»
ACC AVQV
t
»
AS
DH
AVWH
WHDX
t
PIN CHARACTERS
Address Inputs
PIN STATES
A
D
Q
E
G
H
L
High
Low
Data Inputs
Data Outputs
V
X
Z
Valid
CE» (Chip Enable)
OE» (Output Enable)
WE (Write Enable)
RP» (Deep Power-Down Pin)
RY»/BY» (Ready/Busy)
Any Voltage Level
VCC at 3.0 V Min.
Driven, but not necessarily valid
High Impedance
W
P
R
V
3 V
3.0
2.5 ns OF 50 Ω TRANSMISSION LINE
TEST
1.5 OUTPUT
TEST POINTS
INPUT 1.5
0.0
FROM OUTPUT
UNDER TEST
POINT
NOTE:
AC test inputs are driven at 3.0 V for a Logic '1'
and 0.0 V for a Logic '0'. Input timing begins,
and output timing ends at 1.5 V. Input rise
and fall times (10% to 90%) < 10 ns.
TOTAL CAPACITANCE = 50 pF
28F400SUB-13
28F400SUB-14
Figure 13. Transient Input/Output
Figure 14. Transient Equivalent Testing
Reference Waveform (V = 3.3 V)
Load Circuit (V = 3.3 V)
CC
CC
19
LH28F400SUB-Z0
4M (512K × 8, 256K × 16) Flash Memory
DC Characteristics
V
V
= 3.3 V ± 0.3 V, T = -20°C to +85°C (Erase/Write)
CC
CC
A
= 2.7 V ~ 3.6 V, T = -20°C to +85°C (Read)
A
SYMBOL
PARAMETER
Input Load Current
Output Leakage Current
TYP.
MIN.
MAX. UNITS
TEST CONDITIONS
NOTE
IIL
±1
µA
µA
VCC = VCC MAX., VIN = VCC or GND
VCC = VCC MAX., VIN = VCC or GND
1
1
ILO
±10
VCC = VCC MAX.,
4
15
µA
CE», RP» = VCC ±0.2 V
BYTE = VCC ±0.2 V or GND ±0.2 V
ICCS
VCC Standby Current
1, 4
VCC = VCC MAX.,
CE», RP» = VIH
BYTE = VIH or VIL
0.3
0.2
4
8
mA
µA
VCC Deep Power-Down
Current
ICCD
1
RP» = GND ±0.2 V
VCC = VCC MAX.,
CMOS: CE» = GND ±0.2 V
BYTE = GND ±0.2 V or VCC ±0.2 V
Inputs = GND ±0.2 V or VCC ±0.2 V
TTL: CE» = VIL,
1
ICCR
VCC Read Current
35
mA
1, 3, 4
BYTE = VIH or VIL
Inputs = VIL or VIH
f = 8 MHz, IOUT = 0 mA
VCC = VCC MAX.,
CMOS: CE» = GND ±0.2 V
BYTE = VCC ±0.2 V or GND ±0.2 V
Inputs = GND ±0.2 V or VCC ±0.2 V
TTL: CE = VIL,
2
ICCR
VCC Read Current
10
20
mA
1, 3, 4
BYTE = VIH or VIL
Inputs = VIL or VIH
f = 4 MHz, IOUT = 0 mA
ICCW
ICCE
VCC Write Current
8
6
16
12
mA
mA
Word/Byte Write in Progress
Block Erase in Progress
1
1
VCC Block Erase Current
VCC Erase Suspend
Current
CE» = VIH
Block Erase Suspended
ICCES
IPPS
3
6
±10
8
mA
µA
µA
1, 2
1
VPP Standby Current
±1
0.2
VPP ≤ VCC
VPP Deep Power-Down
Current
IPPD
1
RP» = GND ±0.2 V
20
4M (512K × 8, 256K × 16) Flash Memory
LH28F400SUB-Z0
DC Characteristics (Continued)
V
V
= 3.3 V ± 0.3 V, T = -20°C to +85°C (Erase/Write)
CC
CC
A
= 2.7 V ~ 3.6 V, T = -20°C to +85°C (Read)
A
SYMBOL
PARAMETER
TYPE
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
IPPR
VPP Read Current
200
µA
VPP > VCC
1
VPP = VPPH, Word/Byte
Write in Progress
IPPW
VPP Write Current
VPP Erase Current
15
20
35
40
mA
mA
µA
1
1
VPP = VPPH
,
IPPE
Block Erase in Progress
VPP Erase Suspend
Current
VPP = VPPH,
Block Erase Suspended
IPPES
200
1
5
VIL
VIH
Input Low Voltage
Input High Voltage
-0.3
2.0
0.8
V
V
VCC + 0.3
VCC = VCC MIN. and
IOL = 4 mA
VOL
Output Low Voltage
0.4
V
V
V
V
V
V
IOH = 2 mA
VCC = VCC MIN.
1
VOH
2.4
VCC - 0.2
0.0
Output High Voltage
IOH = 100 µA
VCC = VCC MIN.
2
VOH
VPP during Normal
Operations
VPPL
5.5
5.5
6
VPP during Write/Erase
Operations
VPPH
5.0
4.5
VCC Erase/Write
Lock Voltage
VLKO
1.4
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at V = 3.3 V, V = 5.0 V, T = 25°C. These currents are valid for all
CC
PP
product versions (package and speeds).
2. I
I
is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of
CCES
CCES
and I
.
CCR
3. Automatic Power Saving (APS) reduces I
to less than 1 mA in Static operation.
CCR
4. CMOS inputs are either V ± 0.2 V or GND ± 0.2 V. TTL Inputs are either V or V .
CC
IL
IH
5. In 2.7 V < V < 3.0 V operation, TTL-level input of RP» is V (MAX.) = 0.6 V.
CC
IL
6. V
in read is V - 0.2 V < V
< 5.5 V or GND < V < GND + 0.2 V.
PPL
CC
PPL
PPL
21
LH28F400SUB-Z0
4M (512K × 8, 256K × 16) Flash Memory
AC Characteristics - Read Only Operations1
V
= 3.3 V ± 0.3 V, T = -20°C to +85°C
A
CC
SYMBOL
tAVAV
tAVGL
tAVQV
tELQV
tPHQV
tGLQV
tELQX
tEHQZ
tGLQX
tGHQZ
PARAMETER
Read Cycle Time
MIN.
150
0
MAX.
UNITS
NOTE
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup to OE» Going Low
Address to Output Delay
CE» to Output Delay
3
2
150
150
750
50
RP» High to Output Delay
OE» to Output Delay
2
3
3
3
3
CE» to Output in Low Z
CE» to Output in High Z
OE» to Output in Low Z
OE» to Output in High Z
0
0
55
40
Output Hold from Address, CE» or
OE» change, whichever occurs first
tOH
0
ns
ns
ns
3
3
3
tFLGZ
BYTE Low to Output in High Z
60
tFLEL
tFHEL
BYTE High or Low to CE» Low
20
NOTES:
1. See AC Input/Output Reference Waveforms for timing measurements.
2. OE may be delayed up to t - t after the falling edge of CE» without impact on t
ELQV
»
.
ELQV
GLQV
3. Sampled, not 100% tested.
22
4M (512K × 8, 256K × 16) Flash Memory
LH28F400SUB-Z0
1
AC Characteristics - Read Only Operations (Continued)
V
= 2.85 V ± 0.15 V, T = -20°C to +85°C
A
CC
SYMBOL
tAVAV
tAVGL
tAVQV
tELQV
tPHQV
tGLQV
tELQX
tEHQZ
tGLQX
tGHQZ
PARAMETER
Read Cycle Time
MIN.
160
0
MAX.
UNITS
ns
NOTE
Address Setup to OE» Going Low
Address to Output Delay
CE» to Output Delay
ns
3
2
160
160
830
55
ns
ns
RP» High to Output Delay
OE» to Output Delay
ns
ns
2
3
3
3
3
CE» to Output in Low Z
CE» to Output in High Z
OE» to Output in Low Z
OE» to Output in High Z
0
0
ns
60
45
ns
ns
ns
Output Hold from Address, CE» or
OE» change, whichever occurs first
tOH
0
ns
ns
ns
3
3
3
tFLGZ
BYTE Low to Output in High Z
65
tFLEL
tFHEL
BYTE High or Low to CE» Low
25
NOTES:
1. See AC Input/Output Reference Waveforms for timing measurements.
2. OE may be delayed up to t - t after the falling edge of CE» without impact on t
3. Sampled, not 100% tested.
»
.
ELQV
GLQV
ELQV
23
LH28F400SUB-Z0
4M (512K × 8, 256K × 16) Flash Memory
DEVICE AND
ADDRESS
VCC
VCC
POWER-UP
STANDBY
SELECTION
OUTPUTS ENABLED
STANDBY POWER-DOWN
DA.TA.V.ALID
. . .
VIH
ADDRESSES (A)
ADDRESSES STABLE
tAVAV
VIL
VIH
VIL
CE (E)
. . .
tEHQZ
VIH
VIL
OE (G)
. . .
. . .
tAVGL
tGHQZ
VIH
VIL
WE (W)
tGLQV
tELQV
tOH
tGLQX
tELQX
. . .
VALID.O.U.TPUT
VOH
VOL
HIGH-Z
HIGH-Z
DATA (D/Q)
tAVQV
5.0 V
GND
VCC
tPHQV
VIH
VIL
RP (P)
28F400SUB-15
Figure 15. Read Timing Waveforms
24
4M (512K × 8, 256K × 16) Flash Memory
LH28F400SUB-Z0
. . .
. . .
VIH
ADDRESSES (A)
VIL
ADDRESSES STABLE
tAVAV
VIH
CE (E)
VIL
. . .
. . .
tEHQZ
VIH
OE (G)
VIL
tFLEL
tGHQZ
tAVGL
tAVQV
VIH
BYTE (F)
VIL
. . .
tGLQV
tELQV
tOH
tGLQX
tELQX
. . .
DATA OUT.PU.T.
VOH
HIGH-Z
VOL
HIGH-Z
DATA
INPUT
DATA (DQ0 - DQ7)
tAVQV
tFLQZ
VOH
HIGH-Z
HIGH-Z
DATA
OUTPUT
DATA (DQ8 - DQ15
)
VOL
28F400SUB-16
Figure 17. BY»TE» Timing Waveforms
25
LH28F400SUB-Z0
4M (512K × 8, 256K × 16) Flash Memory
POWER-UP AND RESETTIMINGS
VCC POWER UP
RP (P)
3.3 V
3.0 V
VCC (3 V)
0 V
tPL3V
ADDRESS (A)
DATA (Q)
VALID
tAVQV
VALID
3.3 V OUTPUTS
tPHQV
28F400SUB-17
Figure 17. V
Power-Up and RP» Reset Waveforms
CC
SYMBOL
tPL3V
PARAMETER
MIN.
MAX.
UNITS
µs
NOTE
RP# Low to VCC at 3.0 V MIN.
0
1
2
2
tAVQV
Address Valid to Data Valid for VCC = 3.3 V ± 0.3 V
RP# High to Data Valid for VCC = 3.3 V ± 0.3 V
150
750
ns
tPHQV
ns
NOTES:
CE» and OE
»
are switched low after Power-Up.
1. The power supply may start to switch concurrently with RP» going Low. RP» is required to stay low, until V
stays at
CC
recommended operating voltage.
2. The address access time and RP» high to data valid time are shown for 3.3 V V operation. Refer to the
CC
AC Characteristics Read Only Operations also.
26
4M (512K × 8, 256K × 16) Flash Memory
LH28F400SUB-Z0
AC Characteristics for WE»
- Controlled Command Write Operations1
V
= 3.3 V ± 0.3 V, T = -20°C to +85°C
CC
A
SYMBOL
tAVAV
PARAMETER
TYP.
MIN.
150
100
480
10
MAX.
UNITS
ns
NOTE
Write Cycle Time
tVPWH
tPHEL
VPP Setup to WE Going High
RP» Setup to CE» Going Low
CE» Setup to WE Going Low
Address Setup to WE Going High
Data Setup to WE Going High
WE Pulse Width
ns
3
ns
tELWL
ns
tAVWH
tDVWH
tWLWH
tWHDX
tWHAX
tWHEH
tWHWL
tGHWL
tWHRL
120
120
120
10
ns
2, 6
2, 6
ns
ns
Data Hold from WE High
Address Hold from WE High
CE» Hold from WE High
ns
2
2
10
ns
10
ns
WE Pulse Width High
75
ns
Read Recovery before Write
WE High to RY/» BY» Going Low
0
ns
100
ns
RP» Hold from Valid Status Register
Data and RY/» BY» High
tRHPL
0
ns
3
tPHWL
tWHGL
RP» High Recovery to WE Going Low
1
µs
ns
Write Recovery before Read
120
VPP Hold from Valid Status Register
Data and RY/» BY» High
tQVVL
0
µs
1
tWHQV
Duration of Byte Write Operation
Duration of Block Erase Operation
20
8
µs
s
4, 5
4
2
tWHQV
0.3
NOTES:
1. Read timing during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested.
4. Write/Erase durations are measured to valid Status Register (CSR) Data.
5. Byte write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of WE» for all Command Write operations.
27
LH28F400SUB-Z0
4M (512K × 8, 256K × 16) Flash Memory
WRITE VALID
ADDRESS AND DATA
(DATA-WRITE) OR
ERASE CONFIRM
COMMAND
WRITE
DATA-WRITE
OR ERASE
AUTOMATED
DATA-WRITE
OR ERASE
DELAY
DEEP
POWER-DOWN
SETUP COMMAND
VIH
ADDRESSES (A)
AIN
(NOTE 1)
VIL
READ
COMPATIBLE
STATUS
tAVAV
tAVWH
tWHAX
REGISTER DATA
(NOTE 3)
VIH
VIL
ADDRESSES (A)
(NOTE 2)
AIN
tAVWH tWHAX
tAVAV
VIH
VIL
CE (E)
tWHGL
tWHEH
tELWL
VIH
VIL
OE (G)
tWHWL
tWHQV 1, 2
tGHWL
VIH
VIL
WE (W)
tWLWH
tWHDX
tDVWH
VIH
VIL
HIGH-Z
tPHWL
DATA (D/Q)
DIN
DIN
DIN
D
DIN
OUT
tWHRL
VOH
VOL
RY/BY (R)
RP (P)
tRHPL
VIH
VIL
(NOTE 4)
tQVVL
tVPWH
VPPH
VPPL
VPP (V)
NOTES:
1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD.
2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations.
4. RP low transition is only to show tRHPL; not valid for above Read and Write cycles.
28F400SUB-18
Figure 18. AC Waveforms for Command Write Operations
28
4M (512K × 8, 256K × 16) Flash Memory
LH28F400SUB-Z0
AC Characteristics for CE» - Controlled Command Write Operations1
V
= 3.3 V ± 0.3 V, T = -20°C to +85°C
A
CC
SYMBOL
tAVAV
tPHWL
tVPEH
tWLEL
tAVEH
tDVEH
tELEH
tEHDX
tEHAX
tEHWH
tEHEL
tGHEL
tEHRL
PARAMETER
Write Cycle Time
TYP.
MIN.
150
480
100
0
MAX.
UNITS
ns
NOTE
RP» Setup to WE Going Low
VPP Set up to CE» Going High
WE Setup to CE» Going Low
Address Setup to CE» Going High
Data Setup to CE» Going High
CE» Pulse Width
ns
3
3
ns
ns
120
120
120
10
ns
2, 6
2, 6
ns
ns
Data Hold from CE» High
Address Hold from CE» High
WE Hold from CE» High
ns
2
2
10
ns
10
ns
CE» Pulse Width High
75
ns
Read Recovery before Write
CE» High to RY/» BY» Going Low
0
ns
100
ns
RP» Hold from Valid Status Register
Data and RY/» BY» High
tRHPL
0
ns
3
tPHEL
tEHGL
RP» High Recovery to CE» Going Low
1
µs
ns
Write Recovery before Read
120
VPP Hold from Valid Status Register
Data and RY/» BY» High
tQVVL
0
µs
1
tEHQV
Duration of Byte Write Operation
Duration of Block Erase Operation
20
8
µs
s
4, 5
4
2
tEHQV
0.3
NOTES:
1. Read timing during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested.
4. Write/Erase durations are measured to valid Status Register (CSR) Data.
5. Byte Write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of CE» for all Command Write operations.
29
LH28F400SUB-Z0
4M (512K × 8, 256K × 16) Flash Memory
WRITE VALID
ADDRESS AND DATA
(DATA-WRITE) OR
ERASE CONFIRM
COMMAND
WRITE
DATA-WRITE
OR ERASE
AUTOMATED
DATA-WRITE
OR ERASE
DELAY
DEEP
POWER-DOWN
SETUP COMMAND
VIH
ADDRESSES (A)
AIN
(NOTE 1)
VIL
READ
COMPATIBLE
STATUS
tAVAV
tAVEH
tEHAX
REGISTER DATA
VIH
VIL
(NOTE 3)
ADDRESSES (A)
(NOTE 2)
AIN
tAVEH tEHAX
tAVAV
VIH
VIL
WE (W)
tEHWH
tWLEL
tEHGL
VIH
VIL
OE (G)
CE (E)
tEHEL
tEHQV 1, 2
tGHEL
VIH
VIL
tELEH
tEHDX
tDVEH
VIH
VIL
HIGH-Z
DATA (D/Q)
DIN
DIN
DIN
DOUT
DIN
tPHEL
tEHRL
VOH
VOL
RY/BY (R)
RP (P)
tRHPL
VIH
VIL
(NOTE 4)
tQVVL
tVPEH
VPPH
VPPL
VPP (V)
NOTES:
1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD.
2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations.
4. RP low transition is only to show tRHPL; not valid for above Read and Write cycles.
28F400SUB-19
Figure 19. Alternate AC Waveforms for Command Write Operations
30
4M (512K × 8, 256K × 16) Flash Memory
LH28F400SUB-Z0
Erase and Word/Byte Write Performance
V
= 3.3 V ± 0.3 V, T = -20°C to +85°C
A
CC
(1)
SYMBOL
PARAMETER
Byte Write Time
TYP.
MIN.
MAX. UNITS
TEST CONDITIONS
NOTE
2
1
tWHRH
20
µs
µs
µs
2
tWHRH
Two-Byte Serial Write Time
Word Write Time
30
2, 3
2, 4
2
3
tWHRH
30
4
tWHRH
16KB Block Write Time
16KB Block Write Time
16KB Block Write Time
Block Erase Time (16KB)
Full Chip Erase Time
0.33
0.26
1.5
1.2
1.2
13
s
s
s
s
s
Byte Write Mode
5
tWHRH
Two-Byte Serial Write Mode
Word Write Mode
2, 3
2, 4
2
6
tWHRH
0.26
1.1
12 - 26.4
312
2, 5
NOTES:
1. 25°C, V = 5.0 V Sampled.
PP
2. Excludes System-Level Overhead.
3. Two-Byte Serial Write mode is valid at x8-bit configuration only.
4. Word Write mode is valid at x16-bit configuration only.
5. Depends on the number of protected blocks.
31
LH28F400SUB-Z0
4M (512K × 8, 256K × 16) Flash Memory
49CSP (CSP049-P-0808)
INDEX
8.20 [0.323]
7.80 [0.307]
0.10 [0.004]
S
0.40 [0.016]
TYP.
(See Detail)
DETAIL
0.10 [0.004]
S
1.0 [1.039]
1.0 [1.039]
TYP.
TYP.
0.30 [0.012]
0.15 [0.006]
0.48 [0.019]
0.48 [0.016]
MAXIMUM LIMIT
MINIMUM LIMIT
DIMENSIONS IN MM [INCHES]
49CSP
32
4M (512K × 8, 256K × 16) Flash Memory
LH28F400SUB-Z0
ORDERING INFORMATION
LH28F400SU
Device Type
B
-Z0
Speed
Package
150 Access Time (ns)
2
49-pin, .67 mm x 8 mm CSP (CSP049-P-0808)
4M (512K x 8, 256K x 16) Flash Memory
Example: LH28F400SUB-Z0 (4M (512K x 8, 256K x 16) Flash Memory, 150 ns, 49-pin CSP)
28F400SUB-20
33
LH28F400SUB-Z0
4M (512K × 8, 256K × 16) Flash Memory
LIFE SUPPORT POLICY
SHARP components should not be used in medical devices with life support functions or in safety equipment (or similiar applications
where component failure would result in loss of life or physical harm) without the written approval of an officer of the SHARP Corporation.
WARRANTY
SHARP warrants to Customer that the Products will be free from defects in material and workmanship under normal use and service for
a period of one year from the date of invoice. Customer's exclusive remedy for breach of this warranty is that SHARP will either (i) repair
or replace, at its option, any Product which fails during the warranty period because of such defect (if Customer promptly reported the
failure to SHARP in writing) or, (ii) if SHARP is unable to repair or replace, SHARP will refund the purchase price of the Product upon its
return to SHARP. This warranty does not apply to any Product which has been subjected to misuse, abnormal service or handling, or
which has been altered or modified in design or construction, or which has been serviced or repaired by anyone other than SHARP. The
warranties set forth herein are in lieu of, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE ARE SPECIFICALLY
EXCLUDED.
SHARP reserves the right to make changes in specifications at any time and without notice. SHARP does not assume any responsibility
for the use of any circuitry described; no circuit patent licenses are implied.
®
NORTH AMERICA
EUROPE
ASIA
SHARP Corporation
SHARP Electronics Corporation
Microelectronics Group
5700 NW Pacific Rim Blvd., M/S 20
Camas, WA 98607, U.S.A.
Phone: (360) 834-2500
Telex: 49608472 (SHARPCAM)
Facsimile: (360) 834-8903
http://www.sharpmeg.com
SHARP Electronics (Europe) GmbH
Microelectronics Division
Sonninstraße 3
20097 Hamburg, Germany
Phone: (49) 40 2376-2286
Telex: 2161867 (HEEG D)
Facsimile: (49) 40 2376-2232
Integrated Circuits Group
2613-1 Ichinomoto-Cho
Tenri-City, Nara, 632, Japan
Phone: (07436) 5-1321
Telex: LABOMETA-B J63428
Facsimile: (07436) 5-1532
©1997 by SHARP Corporation
Issued October 1996
Reference Code SMT96108
相关型号：
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