LH5164AN-80L [SHARP]
Standard SRAM, 8KX8, 80ns, CMOS, PDSO28, 0.450 INCH, PLASTIC, SOP-28;
| 型号： | LH5164AN-80L |
| 厂家： | 
SHARP ELECTRIONIC COMPONENTS |
| 描述： | Standard SRAM, 8KX8, 80ns, CMOS, PDSO28, 0.450 INCH, PLASTIC, SOP-28 ISM频段 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总13页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LH5164A/AH
CMOS 64K (8K × 8) Static RAM
FEATURES
PIN CONNECTIONS
• 8,192 × 8 bit organization
28-PIN DIP
TOP VIEW
28-PIN SK-DIP
28-PIN SOP
• Access times: 80/100 ns (MAX.)
1
NC
A12
28
27
26
VCC
WE
CE2
• Low-power consumption:
Operating:
2
A7
A6
A5
A4
A3
A2
A1
A0
3
4
5
6
7
8
303 mW (MAX.) LH5164A/D/N
@ 80 ns
248 mW (MAX.) LH5164A/D/N/T
@ 100 ns
275 mW (MAX.) LH5164AH/HD/HN/HT
@ 100 ns
25 A8
A9
23 A11
24
22
21
20
19
18
17
16
15
OE
A10
CE1
I/O8
I/O7
I/O6
I/O5
I/O4
9
10
11
12
13
Standby:
I/O1
I/O2
I/O3
LH5164A/D/N/T: 5.5 µW (MAX.)
LH5164AH/HD/HN/HT:
TA ≤ 85°C: 16.5 µW (MAX.)
TA ≤ 70°C: 5.5 µW (MAX.)
GND 14
5164A-1
Figure 1. Pin Connections for DIP, SK-DIP,
and SOP Packages
• Fully-static operation
• Three-state outputs
• Single +5 V power supply
• TTL compatible I/O
28-PIN TSOP (Type I)
TOP VIEW
28
27
OE
1
A10
2
A11
A9
CE1
I/O8
I/O7
I/O6
I/O5
I/O4
• Wide temperature range available
LH5164A: -10 to +70°C
3
4
26
25
24
A8
LH5164AH: -40 to +85°C
5
CE2
23
22
6
7
WE
VCC
• Packages:
28-pin, 600-mil DIP
8
9
21
20
19
18
GND
I/O3
I/O2
I/O1
NC
A12
A7
28-pin, 300-mil SK-DIP
28-pin, 450-mil SOP
28-pin, 8 × 13 mm2 TSOP (Type I)
10
11
12
13
14
A6
A5
17
16
15
A0
A1
A2
A4
DESCRIPTION
A3
The LH5164A/AH are static RAMs organized as 8,192
× 8 bits. It is fabricated using silicon-gate CMOS proc-
ess technology.
5164A-8
The LH5164AH is designed for wide temperature
range from -40 to +85°C.
Figure 2. Pin Connections for TSOP Package
1
LH5164A/AH
CMOS 64K (8K × 8) Static RAM
A3
A4
7
6
5
4
3
A5
A6
VCC
28
14
MEMORY
ARRAY
(256 x 256)
A7
GND
A8 25
A9
24
2
A12
I/O1
I/O2
11
12
I/O3 13
I/O
CIRCUITS
15
16
17
I/O4
I/O5
I/O6
DATA CONTROL
COLUMN DECODERS
I/O7 18
I/O8
19
COLUMN ADDRESS
BUFFER
27
WE
22
26
OE
CE2
20
CE1
10
A0
9
A1
21
A10 A11
23
8
A2
NOTE: Pin numbers apply to 28-pin DIP, SK-DIP, or SOP.
5164A-2
Figure 3. LH5164A/AH Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
SIGNAL
PIN NAME
A0 - A12
CE1 - CE2
WE
Address inputs
I/O1 - I/O8
VCC
Data inputs and outputs
Power supply
Chip Enable input
Write Enable input
Output Enable input
GND
Ground
OE
NC
No connection
TRUTH TABLE
CE1
CE2
WE
OE
MODE
I/O1 - I/O8
SUPPLY CURRENT
NOTE
H
X
L
L
L
X
L
X
X
L
X
X
X
L
Deselect
Deselect
Write
High-Z
High-Z
DIN
Standby (ISB
)
)
1
1
1
Standby (ISB
H
H
H
Operating (ICC
Operating (ICC
Operating (ICC
)
)
)
H
H
Read
DOUT
High-Z
H
Output disable
NOTE:
1. X = H or L
2
CMOS 64K (8K × 8) Static RAM
LH5164A/AH
ABSOLUTE MAXIMUM RATINGS
80 ns
RATING
100 ns
RATING
PARAMETER
SYMBOL
UNIT
NOTE
Supply voltage
VCC
VIN
-0.3 to +7.0
-0.3 to +7.0
V
1
1, 2
3
Input voltage
-0.3 to VCC + 0.3 -0.3 to VCC + 0.3
V
-10 to +70
-10 to +70
-40 to +85
-55 to +150
°C
°C
°C
Operating temperature
Topr
Tstg
4
Storage temperature
-55 to +150
NOTES:
1. The maximum applicable voltage on any pin with respect to GND.
2.
VIN (MIN.) = -3.0 V for pulse width ≤50 ns.
3. LH5164A/AD/AN/AT
4. LH5164AH/AHD/AHN/AHT
RECOMMENDED OPERATING CONDITIONS 1
80 ns
100 ns
TYP.
PARAMETER
SYMBOL
UNIT
NOTE
MIN.
TYP.
MAX.
MIN.
MAX.
Supply voltage
Input voltage
VCC
VIH
VIL
4.5
2.2
5.0
5.5
4.5
5.0
5.5
VCC + 0.3
0.8
V
V
V
VCC + 0.3
0.8
2.2
-0.3
-0.3
2
NOTES:
1.
T
A = -10 to +70°C (LH5164A/AD/AN/AT), TA = -40 to +85°C (LH5164AH/AHD/AHN/AHT).
2.
VIN (MIN.) = -3.0 V for pulse width ≤50 ns.
DC CHARACTERISTICS 1 (VCC = 5 V ±10%)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Input leakage current
ILI
VIN = 0 to VCC
-1.0
1.0
µA
CE1 = VIH or CE2 = VIL
or OE = VIH or WE = VIL
VI/O = 0 to VCC
Output leakage
current
ILO
-1.0
1.0
µA
CE1 = VIL, VIN = VIL or VIH
CE2 = VIH, Outputs open
tCYCLE
80 ns
=
=
55
mA
45
50
2
3
CE1 = VIL, VIN = VIL or VIH
CE2 = VIH, Outputs open
tCYCLE
100 ns
Operating current
Standby current
ICC
mA
CE1 = VIL, VIN = 0.2 V or
tCYCLE
1.0 µs
=
VCC - 0.2 V
10
CE2 = VIH, Outputs open
CE1 = VIH or CE2 = VIL
5
mA
µA
µA
V
ISB1
TA ≤ 70°C
TA ≤ 85°C
1.0
3.0
0.4
2, 3, 4
3, 4
CE2 ≤ 0.2 V or
CE1 ≥ VCC - 0.2 V
VOL
VOH
IOL = 2.1 mA
IOH = -1 mA
Output voltage
2.4
V
NOTES:
1.
T
A = -10 to 70°C (LH5164A/AD/AN/AT), TA = -40 to +85°C (LH5164AH/AHD/AHN/AHT)
2. LH5164A/AD/AN/AT
3. LH5164AH/AHD/AHN/AHT
4.
CE2 should be ≥ VCC – 0.2 V or ≤ 0.2 V when CE1 ≥ VCC – 0.2 V
3
LH5164A/AH
CMOS 64K (8K × 8) Static RAM
AC CHARACTERISTICS 1
(1) READ CYCLE (VCC = 5 V ±10%)
80 ns
100 ns
PARAMETER
SYMBOL
UNIT
NOTE
MIN.
MAX.
MIN.
MAX.
Read cycle time
tRC
tAA
80
100
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
80
80
80
40
100
100
100
40
(CE1)
(CE2)
tACE1
tACE2
tOE
Chip enable
access time
Output enable access time
Output hold time
tOH
10
10
10
10
10
10
(CE1)
(CE2)
tLZ1
tLZ2
1
1
Chip enable to
output in Low-Z
Output enable to output in
Low-Z
tOLZ
5
5
ns
1
(CE1)
(CE2)
tHZ1
tHZ2
0
0
30
30
0
0
30
30
ns
ns
1
1
Chip enable to
output in High-Z
Output disable to output in
High-Z
tOHZ
0
20
0
20
ns
1
(2) WRITE CYCLE (VCC = 5 V ±10%)
80 ns
100 ns
PARAMETER
SYMBOL
UNIT
NOTE
MIN.
MAX.
MIN.
MAX.
Write cycle time
tWC
tCW
tAW
tAS
80
70
70
0
100
80
80
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip enable to end of write
Address valid to end of write
Address setup time
Write pulse width
tWP
tWR
tDW
tDH
60
0
60
0
Write recovery time
Data valid to end of write
Data hold time
40
0
40
0
Output active from end of write
WE to output in High-Z
OE to output in High-Z
NOTES:
tOW
tWZ
tOHZ
10
0
10
0
2
2
2
30
20
30
20
0
0
1.
TA = -10 to +70°C (LH5164A/AD/AN/AT), TA = -40 to +85°C (LH5164AH/AHD/AHN/AHT)
2.
Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV transition
from steady state levels into the test load.
AC TEST CONDITIONS
PARAMETER
MODE
NOTE
Input voltage amplitude
Input rise/fall time
0.6 to 2.4 V
10 ns
Timing reference level
Output load conditions
1.5 V
1TTL + CL (100 pF)
1
NOTE:
1. Includes scope and jig capacitance.
4
CMOS 64K (8K × 8) Static RAM
LH5164A/AH
CAPACITANCE 1 (TA = 25°C, f = 1 MHz)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input capacitance
CIN
VIN = 0 V
VI/O = 0 V
7
pF
pF
Input/output capacitance
CI/O
10
NOTE:
1. This parameter is sampled and not production tested.
DATA RETENTION CHARACTERISTICS 1
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
CE2 ≤ 0.2 V or
CE1 ≥ VCCDR - 0.2 V
Data retention voltage
VCCDR
2.0
5.5
0.2
V
2
TA =
25°C
µA
2, 3
VCCDR = 3 V,
CE2 ≤ 0.2 V or
CE1 ≥ VCCDR - 0.2 V
TA =
40°C
0.4
0.6
0.2
µA
µA
µA
2, 3
2, 3
2, 4
Data retention current
ICCDR
TA =
25°C
VCCDR = 3 V,
CE2 ≤ 0.2 V or
CE1 ≥ VCCDR - 0.2 V
TA =
70°C
0.6
1.5
2, 4
2, 4
µA
µA
ns
ns
Chip disable to data retention
Recovery time
tCDR
tR
0
tRC
5
NOTES:
1.
TA = -10 to +70°C (LH5164A/AD/AN/AT), TA = -40 to +85°C (LH5164AH/AHD/AHN/AHT)
2.
CE2 should be ≥ VCCDR - 0.2 V or ≤ 0.2 V when CE1 ≥ VCCDR – 0.2 V
3. LH5164A/AD/AN/AT
4. LH5164AH/AHD/AHN/AHT
5. tRC = Read cycle time
5
LH5164A/AH
CMOS 64K (8K × 8) Static RAM
DATA RETENTION MODE
CE1 CONTROL (NOTE)
VCC
4.5 V
tCDR
tR
2.2 V
VCCDR
CE1
CE1 ≥ VCCDR - 0.2 V
0 V
CE2 CONTROL
DATA RETENTION MODE
VCC
4.5 V
tCDR
tR
CE2
VCCDR
0.8 V
0 V
CE2 0.2 V
≥
NOTE: To control data hold at CE1, fix the input level of CE2 between VCCDR to VCCDR - 0.2 V or 0 V to 0.2 V
during the data retention mode.
5164A-6
Figure 4. Low Voltage Data Retention
tRC
A0 - A12
tAA
tACE1
CE1
tLZ1
tACE2
tHZ1
CE2
tLZ2
tOE
tHZ2
tOLZ
OE
tOHZ
DATA VALID
I/O1 - I/O8
tOH
NOTE: WE = 'HIGH.'
5164A-3
Figure 5. Read Cycle
6
CMOS 64K (8K × 8) Static RAM
LH5164A/AH
tWC
A0 - A12
OE
(NOTE 4)
tWR
tAW
tCW
(NOTE 2)
CE1
CE2
tWR
tCW
tWR
tAS
tWP
(NOTE 1)
(NOTE 3)
WE
tOHZ
(NOTE 5)
(NOTE 6)
HIGH-Z
DOUT
tDW
tDH
DIN
DATA VALID
NOTES:
1. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP).
2. tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition,
to the time when the writing is finished.
3. tAS is defined as the time from address change to writing start.
4. tWR is defined as the time from writing finish to address change.
5. If CE1 LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the
outputs will remain high-impedance.
6. While I/O pins are in the output state, input signals with the opposite logic level must not be applied.
5164A-4
Figure 6. Write Cycle 1
7
LH5164A/AH
CMOS 64K (8K × 8) Static RAM
tWC
A0 - A12
tAW
tWR
tCW
(NOTE 4)
(NOTE 2)
CE1
CE2
tWR
tCW
tWR
tAS
tWP
(NOTE 1)
(NOTE 3)
WE
tWZ
tOW
(NOTE 5)
(NOTE 6)
HIGH-Z
tDW
DOUT
tDH
(NOTE 7)
DIN
DATA VALID
OE = 'LOW'
NOTES:
1. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP).
2. tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition,
to the time when the writing is finished.
3. tAS is defined as the time from address change to writing start.
4. tWR is defined as the time from writing finish to address change.
5. If CE1 LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the
outputs will remain high-impedance.
6. If CE1 HIGH transition or CE2 LOW transition occurs at the same time or before WE HIGH transition, the
outputs will remain high-impedance.
7. While I/O pins are in the output state, input signals with the opposite logic level must not be applied.
5164A-5
Figure 7. Write Cycle 2
8
CMOS 64K (8K × 8) Static RAM
LH5164A/AH
PACKAGE DIAGRAMS
28DIP (DIP028-P-0600)
28
15
DETAIL
13.45 [0.530]
12.95 [0.510]
0° TO 15°
1
14
0.30 [0.012]
0.20 [0.008]
36.30 [1.429]
35.70 [1.406]
15.24 [0.600]
TYP.
4.50 [0.177]
4.00 [0.157]
5.20 [0.205]
5.00 [0.197]
3.50 [0.138]
3.00 [0.118]
0.51 [0.020] MIN.
2.54 [0.100]
TYP.
0.60 [0.024]
0.40 [0.016]
MAXIMUM LIMIT
MINIMUM LIMIT
DIMENSIONS IN MM [INCHES]
28DIP-2
28-pin, 600-mil DIP
28DIP (DIP028-P-0300)
DETAIL
28
15
7.05 [0.278]
6.65 [0.262]
0° TO 15°
1
14
0.35 [0.014]
0.15 [0.006]
35.00 [1.378]
34.40 [1.354]
7.62 [0.300]
TYP.
3.65 [0.144]
3.25 [0.128]
4.40 [0.173]
4.00 [0.157]
3.40 [0.134]
3.00 [0.118]
0.51 [0.02] MIN.
2.54 [0.100]
TYP.
0.56 [0.022]
0.36 [0.014]
MAXIMUM LIMIT
MINIMUM LIMIT
DIMENSIONS IN MM [INCHES]
28DIP-6
28-pin, 300-mil SK-DIP
9
LH5164A/AH
CMOS 64K (8K × 8) Static RAM
28SOP (SOP028-P-0450)
1.27 [0.050]
TYP.
0.50 [0.020]
0.30 [0.012]
1.70 [0.067]
28
15
8.80 [0.346]
8.40 [0.331]
12.40 [0.488]
11.60 [0.457]
10.60 [0.417]
1
14
1.70 [0.067]
0.20 [0.008]
0.10 [0.004]
18.20 [0.717]
17.80 [0.701]
0.15 [0.006]
1.025 [0.040]
2.40 [0.094]
2.00 [0.079]
0.20 [0.008]
0.00 [0.000]
1.025 [0.040]
MAXIMUM LIMIT
MINIMUM LIMIT
DIMENSIONS IN MM [INCHES]
28SOP
28-pin, 450-mil SOP
10
CMOS 64K (8K × 8) Static RAM
LH5164A/AH
28TSOP (TSOP028-P-0813)
0.28 [0.011]
0.12 [0.005]
0.55 [0.022]
TYP.
28
15
12.00 [0.472] 13.70 [0.539]
11.60 [0.457] 13.10 [0.516]
12.60 [0.496]
12.20 [0.480]
1
14
8.20 [0.323]
7.80 [0.307]
0.20 [0.008]
0.10 [0.004]
0.15 [0.006]
DETAIL
1.10 [0.043]
0.90 [0.035]
1.20 [0.047]
MAX.
0 - 10°
0.425 [0.017]
0.20 [0.008]
0.00 [0.000]
0.425 [0.017]
1.10 [0.043]
0.90 [0.035]
0.20 [0.008]
0.00 [0.000]
MAXIMUM LIMIT
MINIMUM LIMIT
DIMENSIONS IN MM [INCHES]
28TSOP
2
28-pin, 8 × 13 mm TSOP (Type I)
ORDERING INFORMATION
LH5164A
X
X
- ##
L
Device Type Operating Package Speed Power
Temperature
Low-power standby
10 100
80 80
Access Time (ns)
Blank 28 pin, 600-mil DIP (DIP028-P-0600)
D 28-pin, 300-mil SK-DIP (SK-DIP028-P-0300)
N 28-pin, 450-mil SOP (SOP028-P-0450)
T 28-pin, 8 x 13 mm2 TSOP (Type I) (TSOP028-P-0813)
Blank -10 to 70°C
H -40 to +85°C
CMOS 64K (8K x 8) Static RAM
Example: LH5164AD-10L (CMOS 64K (8K x 8) Static RAM, 100 ns, Low-power standby,
28-pin, 300-mil SK-DIP)
5164A-7
11
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty
for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS
AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A
PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible, for any incidental
or consequential economic or property damage.
NORTH AMERICA
EUROPE
ASIA
SHARP Corporation
SHARP Microelectronics
of the Americas
5700 NW Pacific Rim Blvd.
Camas, WA 98607, U.S.A.
Phone: (360) 834-2500
Fax: (360) 834-8903
SHARP Microelectronics Europe
Sonninstraße 3
20097 Hamburg, Germany
Phone: (49) 40 2376-2286
Fax: (49) 40 2376-2232
http://www.sharpsme.com
Integrated Circuits Group
2613-1 Ichinomoto-Cho
Tenri-City, Nara, 632, Japan
Phone: +81-743-65-1321
Fax: +81-743-65-1532
http://www.sharp.co.jp
http://www.sharpsma.com
FastFocus Static RAM Details
Page 1 of 1
Features
Commercial Temp (-10°C to +70°C),
Tape and Reel
LH5164AN10LTP
64K Slow SRAM
Life Cycle Status
Mature
Applications
Cell Phones,
Copiers,
Fax Machines,
Handheld Electronics,
Instrumentation,
Pagers
Package
28 SOP
Summary
This is a slow, low power, 5 V Static RAM
with an access time of 100 ns. Long Sharp
part number LH5164AN-10L T&R.
Product Data Sheet
Click
to download & view!
HERE
http://www.sharpsma.com/fastfocus/nidetail.asp?t=SLOW_SRAM&p=PCITCAQ2R&n=0
1/17/02
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