LH531000B-S [SHARP]
CMOS 1M (128K x 8) 3 V-Drive MROM; CMOS 1M （ 128K ×8 ） 3 V驱动器MROM
| 型号： | LH531000B-S |
| 厂家： | 
SHARP ELECTRIONIC COMPONENTS |
| 描述： | CMOS 1M (128K x 8) 3 V-Drive MROM |
| 文件： | 总5页 (文件大小：42K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LH531000B-S
CMOS 1M (128K × 8) 3 V-Drive MROM
FEATURES
DESCRIPTION
The LH531000B-S is a mask-programmable ROM
organized as 131,072 × 8 bits. It is fabricated using
silicon-gate CMOS process technology.
• 131,072 words × 8 bit organization
• Access time: 500 ns (MAX.)
• Power consumption:
PIN CONNECTIONS
Operating: 64.8 mW (MAX.)
Standby: 108 µW (MAX.)
28-PIN SOP
TOP VIEW
• Mask-programmable control pin:
28
27
26
25
A15
A12
1
2
VCC
A14
Pin 20 = CE/OE/OE
A13
A8
A7
A6
3
4
• Static operation
• Three-state outputs
A5
A4
A9
5
6
24
23
A11
• Low power supply: 2.6 V to 3.6 V
• Package: 28-pin, 450-mil SOP
22
21
20
A3
A2
A1
7
8
9
A16
A10
CE/OE/OE
A0 10
11
19
18
17
16
15
D7
D6
D5
D4
D3
D0
D1 12
D2 13
GND 14
531000BS-1
Figure 1. Pin Connections for DIP Package
1
LH531000B-S
CMOS 1M MROM
22
1
A16
A15
A14
27
26
2
A13
MEMORY
MATRIX
(131,072 x 8)
A12
A11
23
A10 21
A9
A8
A7
A6
24
25
3
4
5
6
A5
A4
A3
COLUMN SELECTOR
7
A2
A1
A0
8
9
10
SENSE AMPLIFIER
CE
TIMING
BUFFER
GENERATOR
20
CE/OE/OE
OE
BUFFER
OUTPUT BUFFER
19
D7
28
VCC GND
18
D6
14
11
D0
12
D1
13
D2
15
D3
17
D5
16
D4
531000BS-2
Figure 2. LH531000B-S Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
NOTE
SIGNAL
PIN NAME
NOTE
A0 – A16
D0 – D7
Address input
Power supply
(2.6 V to 3.6 V)
VCC
Data output
GND
Ground
Chip Enable input or
Output Enable input
CE/OE/OE
1
NOTE:
1. Active level of CE/OE/OE is mask-programmable.
2
CMOS 1M MROM
LH531000B-S
TRUTH TABLE
CE
OE/OE
MODE
SUPPLY CURRENT
H
L
–
–
–
High-Z
Output
High-Z
Output
Standby
–
Operating
L/H
H/L
Operating
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
Supply voltage
VCC
VIN
–0.3 to +7.0
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
0 to +70
V
V
Input voltage
Output voltage
VOUT
Topr
Tstg
V
Operating temperature
Storage temperature
°C
°C
–65 to +150
RECOMMENDED OPERATING CONDITIONS (TA = 0°C to +70°C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
VCC
2.6
3.6
V
DC CHARACTERISTICS (V = 2.6 V to 3.6 V, T = 0°C to +70°C)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
NOTE
Input ‘Low’ voltage
Input ‘High’ voltage
Output ‘Low’ voltage
Output ‘High’ voltage
Input leakage current
Output leakage current
Operating current
VIL
VIH
–0.3
0.4
VCC + 0.3
0.4
V
V
0.8 × VCC
VOL
VOH
V
IOL = 400 µA
IOH = –100 µA
0.8 × VCC
V
VIN = 0 V to VCC
VOUT = 0 V to VCC
tRC = 500 ns
| ILI
| ILO
ICC
|
10
10
18
30
10
10
µA
µA
mA
µA
pF
pF
|
1
2
Standby current
ISB
CE = VCC – 0.2 V
Input capacitance
Output capacitance
CIN
f = 1 MHz
TA = 25°C
COUT
NOTE:
1. CE/OE = VIH, OE = VIL
2. Outputs open
AC CHARACTERISTICS (V = 2.6 V to 3.6 V, T = 0°C to +70°C)
CC
A
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Read cycle time
tRC
tAA
tACE
tOE
500
ns
ns
ns
ns
ns
ns
ns
Address access time
Chip enable access time
Output enable delay time
Output hold time
500
500
200
tOH
10
CE to output in High-Z
OE to output in High-Z
tCHZ
tOHZ
150
1
NOTE:
1. This is the time required for the output to become high-impedance.
3
LH531000B-S
CMOS 1M MROM
AC TEST CONDITIONS
PARAMETER
RATING
Input voltage amplitude
Input rise/fall time
0.4 V to (0.8 × VCC) V
10 ns
Input/output reference level
Output load condition
1.5 V
1TTL + 100 pF
CAUTION
To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between
the VCC pin and the GND pin.
tRC
A0 - A16
tAA
(NOTE)
CE
tACE
tCHZ
(NOTE)
OE
OE
tOHZ
tOE
(NOTE)
tOH
D0 - D7
DATA VALID
NOTE: The output data becomes valid when the last
intervals, tAA, tACE, or tOE, have concluded.
531000BS-3
Figure 3. Timing Diagram
4
CMOS 1M MROM
LH531000B-S
PACKAGE DIAGRAM
28SOP (SOP028-P-0450)
1.27 [0.050]
TYP.
0.50 [0.020]
0.30 [0.012]
1.70 [0.067]
28
15
8.80 [0.346]
8.40 [0.331]
12.40 [0.488]
11.60 [0.457]
10.60 [0.417]
1
14
1.70 [0.067]
0.20 [0.008]
0.10 [0.004]
18.20 [0.717]
17.80 [0.701]
0.15 [0.006]
1.025 [0.040]
2.40 [0.094]
2.00 [0.079]
0.20 [0.008]
0.00 [0.000]
1.025 [0.040]
MAXIMUM LIMIT
MINIMUM LIMIT
DIMENSIONS IN MM [INCHES]
28SOP
28-pin, 450-mil SOP
ORDERING INFORMATION
LH531000B
Device Type
N
- S
Package
Low-Voltage Operation
28-pin, 450-mil SOP (SOP028-P-0450)
CMOS 1M (128K x 8) Mask-Programmable ROM
Example: LH531000BN-S (CMOS 1M (128K x 8) Mask-Programmable ROM, Low-Voltage Operation,
28-pin, 450-mil SOP)
531000BS-4
5
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