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LH53B16R00 [SHARP]

CMOS 16M (1M x 16/512K x 32) MROM; CMOS 16M （ 1M ×16 / 512K ×32 ） MROM
LH53B16R00
型号： LH53B16R00
厂家： SHARP ELECTRIONIC COMPONENTS    SHARP ELECTRIONIC COMPONENTS
描述：

CMOS 16M (1M x 16/512K x 32) MROM
CMOS 16M （ 1M ×16 / 512K ×32 ） MROM
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LH53B16R00  
CMOS 16M (1M × 16/512K × 32) MROM  
FEATURES  
PIN CONNECTIONS  
• 1,048,576 × 16 bit organization  
(Word mode: W = VIL)  
70-PIN SSOP  
TOP VIEW  
524,288 × 32 bit organization  
(Double Word mode: W = VIH)  
A0  
A1  
A2  
1
2
3
70 NC  
69  
68  
67  
66  
NC  
NC  
W
• Access time: 120 ns (MAX.)  
A3  
A4  
A5  
4
Access time in page mode: 50 ns (MAX.)  
5
OE  
6
65 CE  
• Supply current:  
VCC  
D0  
7
64  
63  
62  
61  
60  
GND  
D31/A-1 (NOTE)  
– Operating: 180 mA (MAX.)  
– Standby: 300 µA (MAX.)  
8
D16  
D1  
D15  
D30  
D14  
9
10  
11  
• TTL compatible I/O  
• Three-state outputs  
• Single +5 V power supply  
• Static operation  
D17  
GND 12  
59 GND  
VCC  
D2  
VCC  
D29  
13  
14  
58  
57  
D18  
D3  
D13  
D28  
D12  
D27  
15  
16  
17  
18  
56  
55  
54  
53  
• Package:  
D19  
D4  
70-pin, 500-mil SSOP  
D20  
D5  
D11  
D26  
D10  
19  
20  
21  
52  
51  
50  
• Others:  
– Non programmable  
– Not designed or rated as radiation  
– hardened  
– CMOS process (P type silicon  
substrate)  
D21  
GND  
VCC  
D6  
22  
49 GND  
VCC  
D25  
23  
24  
25  
26  
27  
28  
29  
30  
31  
48  
47  
46  
45  
44  
43  
42  
41  
40  
D22  
D7  
D9  
D24  
D8  
D23  
DESCRIPTION  
VCC  
NC  
A18  
A17  
GND  
A6  
The LH53B16R00 is a 16M-bit CMOS mask ROM  
(mask-programmable-read-only memory) organized as  
1,048,576 × 16 bits (Word mode) or 524,288 × 32 bits  
(Double Word mode). It is fabricated using silicon-gate  
CMOS process technology.  
A7  
A8  
A9  
A10  
A11  
A12  
A16  
A15  
A14  
A13  
32  
33  
34  
35  
39  
38  
37  
36  
NOTE: D31/A-1 pin becomes LSB address input (A-1) when the  
W pin is set to be LOW in word mode, and data output  
(D31) when set to be HIGH in double word mode.  
53B16R00-1  
Figure 1. Pin Connections  
1
LH53B16R00  
CMOS 16M (1M x 16/512K x 32) MROM  
63 D31  
61 D30  
57 D29  
55 D28  
53 D27  
51 D26  
47  
45  
D25  
D24  
A18 41  
A17 40  
27 D23  
25 D22  
MEMORY  
MATRIX  
(1,048,576 x 16)  
(524,288 x 32)  
39  
A16  
A15 38  
A14 37  
21  
19  
D21  
D20  
A13  
36  
17 D19  
15 D18  
11 D17  
9 D16  
A12 35  
A11  
A10  
34  
33  
A9 32  
62  
60  
D15  
D14  
31  
30  
29  
6
A8  
A7  
A6  
56 D13  
54 D12  
COLUMN SELECTOR  
A5  
A4  
A3  
A2  
52  
50  
D11  
D10  
5
4
46 D9  
44 D8  
26 D7  
24 D6  
3
20  
18  
D5  
D4  
CE  
BUFFER  
TIMING  
GENERATOR  
16 D3  
14 D2  
65  
SENSE AMPLIFIER  
CE  
10  
8
D1  
D0  
OE  
BUFFER  
OE 66  
W 67  
12  
22  
28  
49  
59  
64  
WORD/DOUBLE  
WORD SWITCHOVER  
CIRCUIT  
ADDRESS  
BUFFER  
ADDRESS  
BUFFER  
GND  
63  
A-1  
1
2
7 13 23 43 48 58  
VCC  
A0 A1  
53B16R00-2  
Figure 2. LH53B16R00 Block Diagram  
2
CMOS 16M (1M x 16/512K x 32) MROM  
LH53B16R00  
PIN DESCRIPTION  
SIGNAL  
PIN NAME  
SIGNAL  
PIN NAME  
Address input  
(page mode operation)  
CE  
OE  
Chip enable input  
Output enable input  
Power pin (+5 V)  
Ground  
A-1 - A1  
A2 - A18  
D0 - D31  
Address input  
VCC  
GND  
NC  
Data output  
×16 bit / ×32 bit  
(word/double word)  
mode select input  
No connection  
W
TRUTH TABLE  
DATA OUTPUT  
ADDRESS INPUT  
A-1  
(D31  
SUPPLY  
CURRENT  
CE  
OE  
W
)
D0 - D15  
D16 - D31  
LSB  
MSB  
H
X
H
L
X
X
H
L
X
X
High-Z  
High-Z  
High-Z  
High-Z  
Standby (ISB  
Operating  
Operating  
Operating  
Operating  
)
L
L
L
D0 - D15 D16 - D31  
A0  
A-1  
A-1  
A18  
A18  
A18  
L
L
D0 - D15  
D16 - D31  
High-Z  
High-Z  
L
L
L
H
NOTE:  
X = Don’t care; High-Z = High-impedance  
ABSOLUTE MAXIMUM RATINGS  
PARAMETER  
SYMBOL  
RATING  
UNIT  
Supply voltage  
VCC  
VIN  
-0.3 to +7.0  
-0.3 to VCC + 0.3  
-0.3 to VCC + 0.3  
0 to +70  
V
V
Input voltage  
Output voltage  
VOUT  
TOPR  
TSTG  
V
Operating temperature  
Storage temperature  
°C  
°C  
-65 to +150  
RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C)  
PARAMETER  
SYMBOL  
MIN.  
TYP.  
MAX.  
UNIT  
Supply voltage  
VCC  
4.5  
5.0  
5.5  
V
3
LH53B16R00  
CMOS 16M (1M x 16/512K x 32) MROM  
DC ELECTRICAL CHARACTERISTICS (V  
= 5 V ±10%, T = 0 to +70°C)  
A
CC  
PARAMETER  
SYMBOL  
VIH  
CONDITIONS  
MIN.  
2.2  
MAX.  
UNIT  
NOTE  
Input ‘High’ voltage  
Input ‘Low’ voltage  
Output ‘High’ voltage  
Output ‘Low’ voltage  
Input leakage current  
Output leakage current  
Operating current  
VCC +0.3  
0.8  
V
V
VIL  
-0.3  
2.4  
VOH  
V
IOH = -400 µA  
IOL = 2.0 mA  
VOL  
0.4  
10  
V
| ILI  
|
VIN = 0 V to VCC  
VOUT = 0 V to VCC  
tRC = 120 ns  
µA  
µA  
mA  
mA  
µA  
pF  
pF  
| ILO  
|
10  
1
2
ICC1  
ISB1  
ISB2  
CIN  
180  
2
CE = VIH  
Standby current  
CE = VCC - 0.2 V  
300  
10  
Input capacitance  
Output capacitance  
NOTES:  
f = 1 MHz, tA = 25°C  
COUT  
10  
1. CE = VIH, OE = VIH, output is open  
2. VIN = VIH, VIL, CE = VIL, output is open  
AC ELECTRICAL CHARACTERISTICS (V = 5 V ±10%, T = 0 to +70°C)  
CC  
A
PARAMETER  
SYMBOL  
MIN.  
MAX.  
UNIT  
NOTE  
Read cycle time  
tRC  
tAA  
120  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address access time  
Chip enable access time  
Page address access time  
Output enable delay time  
Output hold time  
120  
120  
50  
tACE  
tAPA  
tOE  
50  
tOH  
5
tCHZ  
tOHZ  
40  
40  
Output floating time  
1
NOTE:  
1. Determined by the time for the output to be opened. (Irrespective of output voltage)  
AC TEST CONDITIONS  
PARAMETER  
RATING  
Input voltage amplitude  
Input signal rise time  
Input signal fall time  
0.4 V to 2.6 V  
10 ns  
10 ns  
Input/output reference level  
Output load condition  
1.5 V  
1TTL + 100 pF  
4
CMOS 16M (1M x 16/512K x 32) MROM  
LH53B16R00  
tRC  
A-1 - A18  
(A0 - A18  
)
tAA  
(NOTE)  
CE  
OE  
tCHZ  
tACE  
(NOTE)  
tOE  
(NOTE)  
tOHZ  
tOH  
D0 - D15  
DATA VALID  
(D0 - D31  
)
NOTE: The output data becomes valid when the  
last intervals, tAA, tACE, tAPA, or tOE, have concluded.  
53B16R00-3  
Figure 3. Read Cycle  
A2 - A18  
A-1 - A1  
(A0 - A1)  
tCHZ  
tAA  
tAPA  
tAPA  
(NOTE)  
(NOTE)  
(NOTE)  
CE  
tOHZ  
tACE  
(NOTE)  
OE  
tOH  
tOH  
tOE  
tOH  
tOH  
(NOTE)  
D0 - D15  
DATA  
VALID  
DATA  
VALID  
DATA  
VALID  
DATA  
VALID  
(D0 - D31  
)
NOTE: The output data becomes valid when the  
last intervals, tAA, tACE, tAPA, or tOE, have concluded.  
53B16R00-4  
Figure 4. Page Mode Read Cycle  
5
LH53B16R00  
CMOS 16M (1M x 16/512K x 32) MROM  
PACKAGE DIAGRAM  
70SSOP (SSOP70-P-500)  
0.15 [0.006]  
36  
M
0.40 [0.015]  
0.20 [0.008]  
.08 [0.003]  
TYP.  
70  
12.90 [0.508]  
12.50 [0.492]  
16.20 [0.638]  
15.60 [0.614]  
14.60 [0.575]  
14.00 [0.551]  
SEE  
DETAIL  
1
35  
28.8 [1.134]  
28.4 [1.118]  
0.20 [0.008]  
0.10 [0.004]  
0.15 [0.006]  
1.275 [0.050]  
2.9 [0.114]  
2.5 [0.098]  
0.20 [0.008]  
0.00 [0.000]  
0.10 [0.004]  
1.275 [0.050]  
2.9 [0.114]  
2.5 [0.098]  
DETAIL  
1.275 [0.050]  
0.25 [0.010]  
0.05 [0.002]  
0 - 10°  
MAXIMUM LIMIT  
MINIMUM LIMIT  
DIMENSIONS IN MM [INCHES]  
70SSOP  
ORDERING INFORMATION  
LH53B16R00  
Device Type  
N
Package  
70-pin, 500-mil SSOP (SSOP70-P-500)  
CMOS 16M (1M x 16 or 500K x 32) Mask-Programmable ROM  
with page mode operation  
Example: LH53B16R00N (CMOS 16M (1M x 16 or 500K x 32) Mask-Programmable ROM, 70-pin, 500-mil SSOP)  
53B16R00-5  
6

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