LH543620M-30 [SHARP]
FIFO, 1KX36, Synchronous, CMOS, PQFP144, 20 X 20 MM, PLASTIC, TQFP-144;
| 型号： | LH543620M-30 |
| 厂家： | 
SHARP ELECTRIONIC COMPONENTS |
| 描述： | FIFO, 1KX36, Synchronous, CMOS, PQFP144, 20 X 20 MM, PLASTIC, TQFP-144 先进先出芯片 |
| 文件： | 总40页 (文件大小：278K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LH543620
1024 × 36 Synchronous FIFO
FUNCTIONAL DESCRIPTION
FEATURES
The LH543620 is a FIFO (First-In, First-Out) memory
device, based on fully-static CMOS RAM technology,
capable of containing up to 1024 36-bit words. It can
replace four or more nine-bit-wide FIFOs in many appli-
cations.
• Fast Cycle Times: 20/25/30 ns
• Selectable 36/18/9-Bit Word Width for Both
Input Port and Output Port
• Byte-Order-Reversal Function (i.e.,
The input port and the output port operate inde-
pendently of each other. Write operations are performed
on the rising edge of the input clock CKI, and enabled by
‘Big-Endian’ ↔ ‘Little-Endian’ Conversion)
• 16-mA-I Three-State Outputs
OL
two enabled signals ENI , ENI . Read operations are
1
2
performed on the rising edge of the output clock CKO and
enabled by two enabled signals ENO , ENO .
• Automatic Byte Parity Checking
• Selectable Byte Parity Generation
1
2
Five status flags are available to monitor the memory
array status: Full, Almost-Full, Half-Full, Almost-Empty,
and Empty. The Almost-Full and Almost-Empty flags are
initialized to a default offset of eight locations from their
respective boundaries, but they are each programmable
over the entire FIFO depth.
• Five Status Flags: Full, Almost-Full,
Half-Full, Almost-Empty, and Empty
• All FIFO Status Flags are Synchronous
(AE, HF, AF Through Programming of
Control Register)
Both the input port and the output port may be set
independently to operate at three data-word widths: 36
bits, 18 bits, or 9 bits. This setting may be changed during
system operation. The LH543620 can perform Byte-Or-
der-Reversal on the four nine-bit bytes of each 36-bit data
word passing through it, thus accomplishing ‘Big Endian’
↔ ‘Little Endian’ conversion.
• Programmed Values may be entered from
either Port
• Two Enable Control Signals for each Port
• Mailbox Register with Synchronized Flags
• Asynchronous Data-Bypass Function
• ‘Smart’ Data-Retransmit Function
When data is read out of the FIFO a byte-parity check
is performed. The parity flag is used to indicate that a
parity error was detected in one of the 9-bit bytes of the
output word.
Parity generation, when selected, creates the parity bit
of each 8-bit byte of the input word. The result is written
into the MSB-bit of each 9-bit byte, overwriting the pre-
vious contents of the bit. The default is odd parity. How-
ever, the FIFO may be programmed to use even parity.
• Configurable for Paralleled FIFO Operation
(72-Bit Data Width)
1
• Space-Saving PQFP and TQFP
Packages
The LH543620 has a data-bypass mode that connects
the output port to the input port asynchronously. Amailbox
facility with Synchronized Flags is provided from the input
port to the output port.
2
• PQFP-to-PGA Package Conversion
The LH543620’s ‘Smart-Retransmit’capability sets the
internal-memory read pointer to any arbitrary memory
location. The ‘Smart-Retransmit’ capability includes a
Marking Function and a Programmable Offset to support
data communication and digital signal processing appli-
cations.
NOTES:
1. This is a final data sheet; except that all references to the TQFP
package have Preliminary status.
2. For PQFP-to-PGA conversion for thru-hole board designs,
SHARP recommends ITT Pomona Electronics’ SMT/PGA Ge-
neric Converter model #5853®. This converter maps the
LH543620 132-pin PQFP to a generic 13 × 13, 132-pin PGA
(100-mil pitch). For more information, contact SHARP or ITT Po-
mona Electronics at 1500 East Ninth Street, Pomona, CA
2-410
1024 × 36 Synchronous FIFO
LH543620
Figure 1. LH543620 Block Diagram
2-411
LH543620
1024 × 36 Synchronous FIFO
PIN DESCRIPTIONS (SUMMARY)
PIN
TYPE *
PIN
TYPE *
PIN NAME
DESCRIPTION
PIN NAME
DESCRIPTION
DATABUS
CONTROL SIGNALS SYNCHRONOUS
TO THE OUTPUT CLOCK
D[35:0]
Q[15:0]
Q[35:16]
36-Bit Input-Port Databus
I
ENO1,ENO2
ADO[2:0]
Output-Port Enables
Output-Port Address
I
I
I/O/Z
O/Z
Three-State 36-Bit Output-
Port Databus
Output-Port Word-Width
Selection
CLOCKS
WSO[1:0]
I
CKI
Input-Port Clock
I
I
RTMD[1:0]
RT
Retransmit Mode Control
Retransmit
I
I
CKO
Output-Port Clock
ASYNCHRONOUS CONTROL
STATUS FLAGS SYNCHRONOUS
TO THE OUTPUT CLOCK
RS
Master Reset
I
I
I
OE
Output Enable
AE
Almost-Empty Flag
Empty Flag
O
O
O
O
BYE
Data-Bypass Enable
EF
Command-Address Port
Reference
PF
Parity-Error Flag
Mailbox-Empty Flag
CAPR
I
MEF
CONTROL SIGNALS SYNCHRONOUS
TO THE INPUT CLOCK
VOLTAGES AND GROUNDS
VCC
VSS
Positive Power
Ground
V
V
ENI1,ENI2
ADI[2:0]
Input-Port Enables
Input-Port Address
I
I
Input-Port Word-Width
Selection
WSI[1:0]
I
STATUS FLAGS SYNCHRONOUS
TO THE INPUT CLOCK
FF
Full Flag
O
O
O
O
AF
HF 1
Almost-Full Flag
Half-Full Flag
Mailbox-Full Flag
MFF
NOTES:
* I = Input, O = Output, V = Voltage, Z = High-Impedance
1. The half-full flag is user-selectable to be synchronized to either
CKI or CKO.
2-412
1024 × 36 Synchronous FIFO
LH543620
132-PIN PQFP PIN CONNECTIONS
132-PIN PQFP
18
19
20
21
22
23
24
25
26
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
MEF
MFF
EF
AE
VSS
HF
AF
FF
PF
CKO
VCC
D28
D29
D30
D31
D32
D33
D34
D35
VCC
ENI1
ENI2
ADI0
ADI1
CHAMFERED
EDGE
27
28
29
30
31
32
33
34
35
Q35
Q34
VSS
Q33
Q32
ADI2
WSI0
WSI1
VSS
CAPR
BYE
ENO1
ENO2
ADO0
ADO1
ADO2
VCC
TOP VIEW
VCC
Q31
Q30
VSS
Q29
Q28
VCC
Q27
Q26
VSS
Q25
Q24
VCC
Q23
Q22
VSS
VSS
36
37
38
39
40
41
42
43
44
45
46
47
48
WSO0
WSO1
RS
90
89
88
87
86
85
84
RTMD0
RTMD1
RT
OE
49
50
VCC
543620-4
Figure 2. Pin Connections for 132-Pin PQFP Package
2-413
LH543620
1024 × 36 Synchronous FIFO
132-PIN PQFP PIN LIST
PIN NAME
D14
D13
D12
D11
D10
D9
PIN NO.
1
PIN NAME
Q15
PIN NO.
61
PIN NAME
D28
PIN NO.
116
117
119
120
121
122
123
124
125
126
127
128
130
131
132
7
Q14
D27
2
62
Q13
D26
3
64
Q12
D25
4
65
Q11
D24
5
67
Q10
D23
6
68
D8
Q9
D22
8
70
D7
Q8
D21
9
71
D6
Q7
D20
10
11
12
13
14
15
16
18
19
20
21
23
24
25
26
27
29
30
32
33
35
36
38
39
41
42
44
45
47
48
52
53
55
56
58
59
73
D5
Q6
D19
74
D4
Q5
D18
76
D3
Q4
CKI
D17
77
D2
Q3
79
D1
Q2
D16
80
D0
Q1
D15
82
MEF
MFF
EF
Q0
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
83
OE
85
17
RT
86
22
AE
RTMD1
RTMD0
RS
87
28
HF
88
31
AF
89
34
FF
WSO1
WSO0
ADO2
ADO1
ADO0
ENO2
EN01
BYE
CAPR
WSI1
WSI0
ADI2
ADI1
ADI0
ENI2
ENI1
D35
90
37
PF
91
40
CKO
Q35
Q34
Q33
Q32
Q31
Q30
Q29
Q28
Q27
Q26
Q25
Q24
Q23
Q22
Q21
Q20
Q19
Q18
Q17
Q16
93
43
94
46
95
49
96
50
97
51
98
54
99
57
101
102
103
104
105
106
107
109
110
111
112
113
114
115
60
63
66
69
72
75
78
81
D34
84
D33
92
D32
100
108
118
129
D31
D30
D29
2-414
1024 × 36 Synchronous FIFO
144-PIN TQFP PIN CONNECTIONS
144-PIN TQFP
LH543620
TOP VIEW
108
107
106
105
104
103
102
101
100
NC
NC
1
D28
D29
D30
D31
D32
D33
D34
D35
2
3
4
5
6
7
8
9
MEF
MFF
EF
AE
VSS
HF
AF
FF
VCC
ENI1
ENI2
ADI0
ADI1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
PF
CKO
VCC
Q35
Q34
VSS
Q33
ADI2
WSI0
WSI1
VSS
NC
CAPR
BYE
ENO1
ENO2
ADO0
ADO1
ADO2
VCC
WSO0
WSO1
RS
Q32
VCC
NC
Q31
Q30
VSS
Q29
Q28
VCC
LH543620
Q27
Q26
VSS
Q25
79
78
77
76
75
74
73
Q24
VCC
Q23
Q22
VSS
VSS
NC
RTMD0
RTMD1
RT
32
33
34
35
36
OE
VCC
NC
543620-33
Figure 3. Pin Connections for 144-pin TQFP Package
2-415
LH543620
1024 × 36 Synchronous FIFO
144-PIN TQFP PIN LIST
PIN NAME
NC
PIN NO.
1
PIN NAME
VCC
Q8
PIN NO.
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
VCC
PIN NAME
97
PIN NO.
D28
2
CKO
PF
98
D29
3
Q9
99
D30
4
VSS
Q10
Q11
VCC
VCC
Q12
Q13
VSS
Q14
Q15
VCC
Q16
Q17
VSS
Q18
Q19
VCC
Q20
Q21
VCC
VCC
NC
FF
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
D31
5
AF
D32
6
HF
D33
7
VSS
AE
D34
8
D35
9
EF
VCC
ENI1
ENI2
ADI0
ADI1
ADI2
WSI0
WSI1
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
MFF
MEF
NC
VCC
VCC
D0
D1
D2
D3
NC
D4
CAPR
BYE
ENO1
ENO2
ADO0
ADO1
ADO2
VCC
WSO0
WSO1
RS
D5
D6
D7
D8
VSS
D9
VSS
VSS
Q22
Q23
VCC
Q24
Q25
VSS
Q26
Q27
VCC
Q28
Q29
VSS
Q30
Q31
NC
D10
D11
D12
D13
D14
NC
D15
D16
D17
VCC
CKI
D18
D19
D20
D21
D22
D23
D24
D25
D26
VSS
VSS
D27
RTMD0
RTMD1
RT
OE
VCC
NC
Q0
Q1
VSS
VSS
Q2
Q3
VCC
Q4
VCC
Q32
Q33
VSS
Q34
Q35
Q5
VSS
Q6
Q7
2-416
1024 × 36 Synchronous FIFO
LH543620
1
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage to VSS Potential
Signal Pin Voltage to VSS Potential 2
DC Output Current 3
RATING
–0.5 V to 7 V
–0.5 V to VCC + 0.5 V
± 75 mA
Storage Temperature Range
Power Dissipation (Package Limit)
NOTES:
–65oC to 150oC
2.5 Watts (Quad Flat Pack)
1. Stresses greater than those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. This is a stress rating for
transient conditions only. Functional operation of the device at these or any other conditions outside those indicated in the ‘Operating Range’
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Negative undershoot of 1.5 V in amplitude is permitted for up to 10 ns, once per cycle.
3. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time.
OPERATING RANGE
SYMBOL
PARAMETER
Temperature, Ambient
Supply Voltage
MIN
0
MAX
70
UNIT
o
TA
C
VCC
VSS
4.5
0
5.5
V
V
V
V
Supply Voltage
0
VIL
Logic LOW Input Voltage 1
–0.5
2.2
0.8
VIH
Logic HIGH Input Voltage
Vcc + 0.5
NOTE:
1. Negative undershoot of 1.5 V in amplitude is permitted for up to 10 ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
SYMBOL
PARAMETER
Input Leakage Current
I/O Leakage Current
TEST CONDITIONS
VCC = 5.5 V, VIN = 0 V To VCC
OE ≥ VIH, 0 V ≤ VOUT ≤ VCC
IOL = 16.0 mA
MIN
–10
–10
TYP
MAX
10
UNIT
µA
µA
V
ILI
ILO
10
VOL
VOH
ICC
Logic LOW Output Voltage
Logic HIGH Output Voltage
Average Supply Current 1,2
0.4
IOH = –8.0 mA
2.4
V
Measured at fC = maximum
205
40
380
85
mA
mA
ICC2
Average Standby Supply Current 1,3 All Inputs = VIHMIN (Clock idle)
All Inputs = VCC
,
Outputs – open,
Control – deasserted,
Clocks = VCC
ICC3
Power-Down Supply Current 1
0.01
1.0
mA
NOTE:
1. ICC, ICC2, and ICC3 are dependent upon actual output loading, and ICC is also dependent on cycle times.
Specified values are with outputs open (for ICC: CL = 0 pF); and, for ICC, operating at minimum cycle times.
2.
3.
I
CC (MAX): Using worst case conditions and data pattern. ICC (TYP): Using VCC = 5 V and average data pattern.
ICC2 (TYP): Using VCC = 5 V and TA = 25°C.
2-417
LH543620
1024 × 36 Synchronous FIFO
AC TEST CONDITIONS
PARAMETER
RATING
+5 V
Input Pulse Levels
V
SS
to 3 V
Input Rise and Fall Times (10% to 90%)
Output Reference Levels
Input Timing Reference Levels
Output Load, Timing Tests
3 ns
1.1 k Ω
1.5 V
1.5 V
DEVICE
UNDER
TEST
680 Ω
*
30 pF
Figure 3
1,2
CAPACITANCE
PARAMETER
RATING
8 pF
CIN MAX. (Input Capacitance)
COUT MAX. (Output Capacitance)
*
INCLUDES JIG AND SCOPE CAPACITANCES
543620-27
10 pF
Figure 4. Output Load Circuit
NOTES:
1. Sample tested only.
2. Capacitances are maximum values at 25oC,
measured at 1.0 MHz, with VIN = 0 V.
2-418
1024 × 36 Synchronous FIFO
LH543620
1
AC ELECTRICAL CHARACTERISTICS (See Timing Diagrams Pages 21-35)
–20
–25
–30
SYMBOL
DESCRIPTION
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
33
fC
Clock Cycle Frequency
50
40
MHz
ns
tC
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data In Setup Time
20
8
25
10
12
6
30
12
14
7
tCH
tCL
tDS
ns
9
ns
5
ns
Data Setup Time When Writing to Resource
Register From Output Port
tDSO
tDH
10
2
12
2
14
2
ns
ns
ns
Data In Hold Time
Data Hold Time When Writing to Resource Register
From Output Port
tDHO
2
2
2
tA
tOH
Data Out Access Time
14
16
18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Out Hold Time
4
5
2
6
2
1
4
6
2
7
2
1
4
7
2
8
2
1
tES
Enable Setup Time
tEH
Enable Hold Time
tOES
tOEH
tOL
Output Enable Setup Time
Output Enable Hold Time
OE to Data Out Low-Z 2
OE to Data Out High-Z 2
OE to Data Valid
tOZ
12
10
14
14
14
14
14
14
14
14
15
12
16
16
16
16
16
16
16
16
19
14
18
18
18
18
18
18
18
18
tOE
tEF
Empty Flag Access Time
Full Flag Access Time
tFF
tAE
AE Flag Access Time
tAF
AF Flag Access Time
tHF
HF Flag Access Time
tPF
Parity Flag Access Time
Mailbox FF Access Time
Mailbox EF Access Time
Address Setup Time
tMFF
tMEF
tAS
10
2
12
2
14
2
tAH
Address Hold Time
tWSS
tWSH
tRTMS
tRTMH
tRTS
tRTH
tRS
WSI and WSO Setup Time
WSI and WSO Hold Time
Retransmit Mode Setup Time
Retransmit Mode Hold Time
Retransmit Setup Time
Retransmit Hold Time
10
2
12
2
14
2
5
6
7
2
2
2
5
6
7
2
2
2
Reset Pulse Width
20
10
25
12
30
15
tRSR
tRF
Reset Recovery Time 2
Reset LOW to Flag Valid
Reset to Data Out LOW
Bypass LOW to Data Valid
Bypass Propagation Delay
Skew Time Between CKO and CKI for FF 3
Skew Time Between CKI and CKO for EF 4
Skew Time Between Clock for Mailbox Flags
30
18
12
12
35
20
16
16
40
22
18
18
tRO
tBA
tBD
tSKEW1
tSKEW2
tSKEWM
NOTES:
7
7
7
9
9
9
11
11
11
2-419
LH543620
1024 × 36 Synchronous FIFO
PIN DESCRIPTIONS (FUNCTIONAL)
PIN NAME
DESCRIPTION
DATABUS
36-bit Input-Port Databus. The D port is the input port for the FIFO memory array, the resource
registers, and the mailbox, or it may be directly connected to the output port. See Figure 4.
D[35:0] is synchronous to the rising edge of CKI.
D[35:0]
Q[35:0]
Three-State 36-Bit Output-Port Databus. The Q port is the output port for the FIFO memory array,
the resource registers, and the mailbox, or it may be directly connected to the input port. See Figure
4. Q[35:0] is synchronous to the rising edge of CKO. The lower 16 bits of the Q port (Q[15:0]) may
also be used as the input port for the resource register.
CLOCKS
Input-Port Clock. CKI is a free-running waveform controlled by an oscillator. It may be irregular or
asynchronous if minimum clock-HIGH times and clock-LOW times are met.
CKI
Output-Port Clock. CKO is a free-running waveform controlled by an oscillator. It may be irregular
or asynchronous if minimum clock-HIGH times and clock-LOW times are met.
CKO
OUTPUT PORT
INPUT PORT
SELECT INPUT
PORT FUNCTION
ADI [2:0] =
SELECT OUTPUT
PORT FUNCTION
ADO [2:0] =
RESOURCE
REGISTER
RESOURCE
REGISTER
MAILBOX
MAILBOX
D → MAILBOX
MFF = L
MAILBOX → Q
MFF = H
MEF = H
MEF = L
CAPR
OE
L
H
L
H
D → RESOURCE
REGISTER (ADI)
RESOURCE
REGISTER (ADO) → Q
IDLE
CAPR
L
H
Q → RESOURCE
IDLE
REGISTER (ADO)
All the operations are synchronized to CKI,
except MEF is set HIGH on CKO.
All the operations are synchronized to CKO,
except MFF is set HIGH on CKI.
*
*
543620-5
Figure 5. Resource Registers, Read and Write
2-420
1024 × 36 Synchronous FIFO
LH543620
PIN NAME
DESCRIPTION
ASYNCHRONOUS CONTROL
Master Reset. When asserted LOW, the LH543620 internal resource registers are set to their
default value. See Table 1. The status flags indicate Empty FIFO.
RS
Output Enable. When asserted LOW, OE forces Q[35:0] to be active. When deasserted HIGH, OE
forces Q[35:0] into a Hi-Z state. Bit 6 of the control register governs whether OE suppresses the
advancement of the Read Pointer (RP). In this case, OE must obey setup time and hold time
relative to CKO.
OE
Data-Bypass Enable. When asserted LOW, BYE connects Q[35:0] directly to D[35:0].
BYE
Command-Address Port Reference. CAPR determines the source of the 16-bit word to be loaded
into the resource register. Whenever CAPR is LOW, the word comes from the Input Port. Whenever
CAPR is HIGH (OE is HIGH), the word comes from the Output Port.
NOTES:
CAPR
1. The destination of the resource register is always the Output Port.
2. CAPR is assumed to be a steady signal. It is not allowed to change ‘on-the-fly’ during operation.
CONTROL SIGNALS SYNCHRONOUS TO THE INPUT CLOCK
Input-Port Enables. ENI1 and ENI2 are active HIGH and synchronous to the rising edge of CKI.
Data is written into the FIFO memory array when both ENI1 and ENI2 are asserted HIGH.
NOTE: ENI1, ENI2 DO NOT ENABLE writing data into the Resource Registers or the Mailbox.
ENI , ENI
1
2
Input-Port Address. ADI[2:0] specifies the Input-Port destination. See Table 1. ADI[2:0] is
synchronized to the rising edge of CKI.
ADI[2:0]
WSI[1:0]
Input-Port Word-Width Selection. WSI[1:0] selects the Input-Port Word-Width. See Table 2.
WSI[1:0] is synchronous to the rising edge of CKI.
Table 1. Input-Port Address
Table 2. Input-Port Word-Width Selection
DEFAULT VALUE
(of the selected
REGISTER)
WSI1 WSI0
FUNCTION
ADI2 ADI1 ADI0
SELECTION
9-Bit Data-Path
Input data D[8:0]
L
L
Width
L
L
L
L
L
RBASE register
0
0
18-Bit Data-Path
Width
Input data D[17:0]
L
H
H
H
L
ROFFSET
register
H
Reserved
L
H
H
L
L
AF offset value
Parity register
AE offset value
Control register
Mailbox
8
0
8
1
0
36-Bit Data-Path
Width
Input data D[35:0]
H
L
H
L
H
H
H
L
H
L
H
Resource
H
H
H
registers write
disabled
2-421
LH543620
1024 × 36 Synchronous FIFO
PIN NAME
DESCRIPTION
STATUS FLAGS SYNCHRONOUS TO THE INPUT CLOCK
Full Flag. FF is synchronous to the rising edge of CKI. When asserted LOW, 1024 36-bit words of
the FIFO memory array contain meaningful data. When FF is asserted, writing data to the FIFO is
disabled.
FF
AF
Almost-Full Flag. When asserted LOW, AF indicates that there are at most ‘p’ vacant 36-bit
words remaining in the FIFO memory array, where ‘p’ is the value of the Almost-Full-Offset-Value.
AF has two synchronization modes depending on Bit 5 of the control register.
Bit 5 = 0 (Default) Asynchronous Mode
Bit 5 = 1: AF is synchronous to the rising edge of CKI.
Half-Full Flag. When asserted LOW, there are at least 513 36-bit words in the FIFO memory
array. HF has three synchronization modes depending on Bits 3 and 4 of the control register. See
Table 3.
HF
Mailbox-Full Flag. MFF is synchronized to the rising edge of CKI. When asserted LOW, it
indicates that a new mail word has been placed in the mailbox.
MFF
CONTROL SIGNALS SYNCHRONOUS TO THE OUTPUT CLOCK
Output-Port Enables. ENO1 and ENO2 are active HIGH, synchronous to the rising edge of CKO.
Data is read from the FIFO memory array when both ENO1, ENO2 are asserted.
ENO , ENO
1
2
NOTE: ENO1, ENO2 DO NOT ENABLE reading data from the Resource Register or the Mailbox.
Output-Port Address. ADO[2:0] specifies the Output-Port source/destination. See Table 4.
ADO[2:0] is synchronous to the rising edge of CKO.
NOTE: In order to read the resource register at the output bus, BYE should be deasserted and the
FIFO memory array should be disabled.
ADO[2:0]
Table 3. HF Synchronization Modes
Table 4. Output-Port Address
DEFAULT VALUE
(of the selected
REGISTER)
CONTROL
REGISTER
ADO2 ADO1 ADO0
SELECTION
FUNCTION
BIT 4 BIT 3
RBASE
register
L
L
L
L
L
0
0
L *
L
L *
H
Asynchronous Mode: HF
Synchronous Mode I: HF is
synchronous to the rising edge of CKO
ROFFSET
register
H
H
H
L
Synchronous Mode II: HF is
synchronous to the rising edge of CKI
AF offset value
Parity register
AE offset value
L
L
H
H
L
L
H
L
8
0
8
H
* Default Mode
H
Control
register
H
H
L
H
L
1
0
Mailbox
H
Resource
registers read Not applicable
disabled
H
H
H
2-422
1024 × 36 Synchronous FIFO
LH543620
PIN NAME
DESCRIPTION
CONTROL SIGNALS SYNCHRONOUS TO THE OUTPUT CLOCK (cont’d)
Output-Port Word-Width Selection. WSO[1:0] is synchronous to the rising edge of CKO.
WSO[1:0] selects the Output-Port Word-Width and controls byte-order-reversal according to
Table 5.
WSO[1:0]
Retransmit Mode Control. RTMD[1:0] is synchronized to the rising edge of CKO. RTMD[1:0]
controls the placement of new contents into the Read Pointer (RP) and/or the Retransmit Base
(RBASE) registers. Whenever Retransmit (RT) is asserted, one of three operations is performed
according to the setting of RTMD[1:0]. See Table 6.
NOTES:
RTMD[1:0]
1. When RTMD[1:0] is set to 0, the FIFO is in depth cascade mode, and the Retransmit
mechanism can not be used. In cascade mode, the Almost-Empty Flag is a handshake signal for
cascading. The Almost-Empty Flag is used as an input to the ENI of the next FIFO in the chain.
2. In standard FIFO operation RTMD[1:0] must not be set to 0 and the Retransmit signal must be
HIGH.
Retransmit. RT is synchronized to the rising edge of CKO. When asserted LOW, RT causes one
of the Retransmit Mode operations to be performed, according to the encoding of RTMD[1:0]. See
Table 6.
RT
NOTE: When RTMD[1:0] = 0 (FIFO is in cascade mode) RT is ignored.
Table 5. Output-Port Word-Width Selection
Table 6. Retransmit Operation Modes
WSO1 WSO0
FUNCTION
RTMD1 RTMD0 OPERATION
ACTION TAKEN
9-Bit Data-Path
Width
Depth
Cascade
Mode
The Almost-Empty
Flag is a handshake
signal for cascading
Output data Q[8:0]
Output data Q[17:0]
L
L
L
L
L
L
18-Bit Data-Path
Width
H
(RBASE) +
(ROFFSET) → RP
Retransmit
H
36-Bit Data-Path
Width With Byte- Output data Q[35:0]
Order-Reversal
(RBASE) +
(ROFFSET) → RP
Retransmit and
H
H
L
36-Bit Data-Path
Output data Q[35:0]
Width
H
H
L
H
and Mark
(RBASE) +
(ROFFSET) →
RBASE
Mark
(RP) → RBASE
H
2-423
LH543620
1024 × 36 Synchronous FIFO
PIN NAME
DESCRIPTION
STATUS FLAGS SYNCHRONOUS TO THE OUTPUT CLOCK
Almost-Empty Flag. The AE flag has two modes of operation depending on the RTMD[1:0]
setting.
1. RTMD[1:0] ≠ 0: AE is a standard Almost-Empty Flag. When asserted LOW, AE implies that
there are at most ‘q’ 36-bit words in the FIFO memory array, where ‘q’ is Almost-Empty-Offset-
Value register value. In this mode AE has two synchronization options depending on the setting of
Bit 2 of the control register.
AE
Bit 2 = 0 (Default) Asynchronous Mode
Bit 2 = 1 Synchronous Mode: AE is synchronous to the rising edge of CKO.
2. RTMD[1:0] = 0: AE is a handshake signal for cascading.
Empty Flag. EF is synchronous to the rising edge of CKO. When asserted LOW, all 1024
36-bit words are vacant. When asserted, EF disables the FIFO Read operation.
EF
PF
Parity-Error Flag. PF is synchronized to the rising edge of CKO. When asserted LOW, PF
implies that a parity error has occurred in at least one 9-bit byte within a 36-bit word read from the
FIFO memory array. If there are no errors, it is deasserted HIGH. When an error is detected, the
parity check result of each 9-bit byte of the 36-bit output word is written to the parity register. The
content of the parity register is frozen until read. The PF signal is delayed by one CKO cycle
compared to the output data (i.e., if the PF is asserted, there was an error in the previous word).
Mailbox-Empty Flag. MEF is synchronous to the rising edge of CKO. When asserted LOW, MEF
indicates that there is no new mail word in the mailbox.
MEF
VOLTAGES AND GROUNDS
Positive Power.
Ground.
V
CC
V
SS
CKI. The operation is enabled if both ENI and ENI are
asserted HIGH. Data Read operations from the FIFO
memory occur at the rising edge of CKO. The operation
1
2
OPERATIONAL DESCRIPTION
The LH543620 has four operating modes: Normal
Mode, Programmable Resource Registers, Mailbox, and
Data Bypass.
is enabled if both ENO and ENO are asserted HIGH.
1
2
The FIFO write and read operations are supported by
the following mechanisms: Byte-Order-Reversal and Bus
Funneling/Defunneling Functions, Status Flags, Retrans-
mit Mechanism, Parity Checking, and Parity Generation.
NORMAL MODE
Normal FIFO operation refers to Read and Write op-
erations to the FIFO memory array. Data Write operations
into the FIFO memory array occur at the rising edge of
2-424
1024 × 36 Synchronous FIFO
LH543620
Byte-Order-Reversal and Bus Funneling/
Defunneling Functions
Example 2: 18-to-36 Defunneling With Byte Reversal
This example performs two functions:
1. Bus width change
Word width can be selected at the Input Port and/or
the Output Port to be 36, 18 or 9 bits wide. When the
Output Port width is selected to be 36 bits, it is possible
to select Byte-Order-Reversal.
2. Big Endian to Little Endian conversion
This configuration can be used for connecting the Intel
80286 to the Motorola 68040.
The funneling mechanism is controlled by the inputs
WSI[1:0] and WSO[1:0] according to Tables 2 and 5. Data
is packed and unpacked from a 36-bit word memory array.
Table 7 describes all combinations offunneling/defunneling.
CONDITIONS
RESULTS
WSI[1:0]
WSO[1:0]
Input 18 bits wide.
Changes to the funneling/defunneling settings during
system operation should be made one clock before a
word boundary, as shown in Example 3.
1
–
Pins used are D[17:0].
Output 36 bits wide with byte
order reversal.
–
2
Example 1: 36-to-9 Funneling
The dataflow structure is illustrated by Figure 6.
CONDITIONS
RESULTS
Example 3: Changing Input Bus Width From 9 to 36
During Operation
WSI[1:0]
WSO[1:0]
Input 36 bits wide.
3
–
CKI
0
WSI
0
ACTION
Output 9 bits wide.
Pins used are Q[8:0].
–
0
Write 1st 9-bit byte
Write 2nd 9-bit byte
Write 3rd 9-bit byte
Write 4th 9-bit byte
Write 1st 36-bit word
1
0
The dataflow structure is illustrated by Figure 5.
2
0
3
3
4
3
Table 7. Bus Funneling/Defunneling *
INPUT
WSI = 0
OUTPUT
CKI
CKO
WSO = 3
Q[35:0]
WSO = 2
Q[35:0]
WSO = 1
WSO = 0
Q[35:9]
cycles
D[35:9]
D[8:0] cycles
Q[35:18] Q[17:0]
Q[8:0]
0
1
2
3
4
5
6
7
8
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxx
B0
B1
B2
B3
B4
B5
B6
B7
B8
0
1
2
3
4
5
6
7
8
B3 B2 B1 B0 B0 B1 B2 B3 B3 B2 B1 B0 B3 B2 B1
B7 B6 B5 B4 B4 B5 B6 B7 B1 B0 B3 B2 B0 B3 B2
B7 B6 B5 B4 B1 B0 B3
B0
B1
B2
B3
B4
B5 B4 B7 B6 B2 B1 B0
B7 B6 B5
WSI = 1
WSO = 3
Q[35:0]
WSO = 2
Q[35:0]
WSO = 1
WSO = 0
Q[35:9]
D[35:18]
D[17:0]
Q[35:18] Q[17:0]
Q[8:0]
0
1
2
3
4
xx
xx
xx
xx
xx
B1 B0
B3 B2
B5 B4
B7 B6
B9 B8
0
1
2
3
4
B3 B2 B1 B0 B0 B1 B2 B3 B3 B2 B1 B0 B3 B2 B1
B7 B6 B5 B4 B4 B5 B6 B7 B1 B0 B3 B2 B0 B3 B2
B7 B6 B5 B4 B1 B0 B3
B0
B1
B2
B3
B4
B5 B4 B7 B6 B2 B1 B0
B7 B6 B5
WSI = 3
WSO = 3
Q[35:0]
WSO = 2
Q[35:0]
WSO = 1
WSO = 0
D[35:0]
Q[35:18] Q[17:0]
Q[35:9]
Q[8:0]
0
1
B3 B2 B1 B0
B7 B6 B5 B4
0
1
B3 B2 B1 B0 B0 B1 B2 B3 B3 B2 B1 B0 B3 B2 B1
B7 B6 B5 B4 B4 B5 B6 B7 B1 B0 B3 B2 B0 B3 B2
B7 B6 B5 B4 B1 B0 B3
B0
B1
B2
B3
B4
B5 B4 B7 B6 B2 B1 B0
B7 B6 B5
* NOTE: B0, B1, . . ., represent data bytes.
2-425
LH543620
1024 × 36 Synchronous FIFO
INPUT: WSI[1:0]=3
OUTPUT: WSO[1:0]=0
LH543620
B3
B7
B3
B0
B1
B2
D35
Q35
BYTE #4 BYTE #8
BYTE #4 BYTE #1 BYTE #2 BYTE #3
BYTE #8
BYTE #7
D27
D26
Q27
Q26
B6
BYTE #7
B2
BYTE #3
B2
B3
B0
B1
BYTE #3 BYTE #4 BYTE #1 BYTE #2
D18
D17
Q18
Q17
B1
B5
B1
B2
B3
B0
BYTE #2 BYTE #6
BYTE #2 BYTE #3 BYTE #4 BYTE #1
BYTE #6
BYTE #5
4
D9
D8
Q9
Q8
B0
B4
B0
B1
B2
B3
BYTE #1 BYTE #5
BYTE #1 BYTE #2 BYTE #3 BYTE #4
D0
Q0
0
1
2
0
1
2
3
CKI
CKO
NOTES:
HEAVY SOLID LINES = Main data path.
SHADED LINES = Not used for this application.
543620-30
Figure 6. Example of 36-to-9 Bus Funneling
INPUT: WSI[1:0]= 1
NOT USED
OUTPUT: WSO[1:0]= 2
LH543620
B0
B4
D35
Q35
BYTE #1 BYTE #5
D27
D26
Q27
Q26
B1
B5
BYTE #2 BYTE #6
NOT USED
D18
D17
Q18
Q17
B1
B3
B5
B7
B2
B6
BYTE #2 BYTE #4 BYTE #6 BYTE #8
BYTE #3 BYTE #7
D9
D8
Q9
Q8
B0
B2
B4
B6
B3
B7
BYTE #1 BYTE #3 BYTE #5 BYTE #7
BYTE #4 BYTE #8
D0
Q0
0
1
2
3
4
0
1
2
3
CKI
CKO
NOTES:
HEAVY SOLID LINES = Main data path.
SHADED LINES = Not used for this application.
543620-31
Figure 7. Example of 18-to-36 Bus Defunneling
With Byte Order Reversal
2-426
1024 × 36 Synchronous FIFO
LH543620
Status Flags
NOTES
There are five status flags:
1. The Retransmit mechanism can be used inde-
pendently and parallel to the write operation.
FF Full Flag
2. RTMD[1:0] must be selected two cycles prior to RT
being asserted and remain stable during RT low.
AF Almost-Full Flag
HF Half-Full Flag
AE Almost-Empty Flag
EF Empty Flag
3. At least two words need to be in the FIFO memory
array prior to performing a retransmit.
4. When using normal read and write operations, theFF
inhibits writing when the FIFO is full and the EF
inhibits reading when the FIFO is empty. This behav-
ior provides a protection from wraparound situations
(i.e., the Read pointer is ahead of the Write Pointer).
This protection is NOT provided when using retrans-
mit. The user should be careful not to write more than
1024 words from the marked point.
The functionality and the synchronization of the status
flags are detailed in the Pins Descriptions (Functional)
section. All status flags are generated for 36-bit word
widths, not according to selected input or output port
widths.
Retransmit Mechanism
With standard FIFO operations, every data word can
be read out of the FIFO once. The Retransmit mechanism
allows reading the data more than once by providing
flexible control of the Read Pointer.
5. When the retransmit mechanism is not used, the
recommended connection is:
RTMD[1:0] = 3
RT = HIGH
Associated with the Retransmit mechanism are three
control lines: RTMD[1:0], RT, and two Resource regis-
ters: RBASE and ROFFSET.
The Retransmit mechanism can be useful in many
applications. For example:
1. Computer-communications applications.
RTMD[1:0] sets the mode of operation. See Table 6.
RT enables the operation synchronous to CKO.
Retransmit allows three modes of operation:
When the receiver reads a block of data and finds no
errors in the data block, it can mark the beginning of
the new message by setting the FIFO in MARK mode
RTMD[1:0] = 3 and assert the RT signal for one clock
cycle.
Mark: RTMD[1:0] = 3 and RT is asserted. The value of
the Read Pointer is saved into the RBASE register.
If the receiver finds an error in the data block, it can
read the last message again by setting the FIFO in
Retransmit mode RTMD[1:0] = 1 and asserting the
RT signal for one cycle.
Retransmit: RTMD[1:0] = 1 and RT is asserted. The
Read Pointer is loaded by the value of RBASE plus the
value of ROFFSET.
Retransmit and Mark: RTMD[1:0] = 2 and RT is as-
serted: The Read Pointer is loaded by the value of
RBASE plus the value of ROFFSET. Then the value of
the Read Pointer is saved into the RBASE register.
2. Overlap addressing for DSP applications.
A typical DSP consists of A/D-FIFO-DSP. In many
applications, the DSP needs to read a block of data
where each block overlaps the previous block (like
the overlap-and-save method for filtering.) The over-
lap addressing can be implemented by using the
LH543620 with no additional hardware as follows:
The timing of the retransmit is illustrated in Figures 26
and 27.
When RT is asserted and RTMD[1:0] is set to 1 or 2,
the flags change their value to indicate a ‘Retransmit
state’, i.e., EF, AE, FF deasserted; AF, HF asserted.
Three enable-read cycles are required to read the new
data word. The flagsreflectthe newstatus. Theretransmit
is acknowledged even when the output is disabled
(ENO = LOW), but enable-read cycles are needed to fill
the pipeline with new information before reading the new
data.
The FIFO is set to retransmit and mark mode:
RTMD[1:0] = 2, the AF offset register is programmed
to N = Block Size, and the ROFFSET register is
programmed to (N – Overlap). The data is loaded into
the FIFO each time CKin is triggered.
The DSP can sense the AF flag of the FIFO. When-
ever this flag is being asserted, a new block of data
is available in the FIFO. The DSP then reads a block
of data, and then asserts the FIFO’s RT signal, which
causes the RP and RBASE register to be set at the
beginning of the new block.
2-427
LH543620
1024 × 36 Synchronous FIFO
Parity Checking
PROGRAMMABLE RESOURCE REGISTERS
The Parity checking mechanism is always active. Par-
ity checking is done separately for each of the 9-bit bytes
of the 36-bit word read from the memory array. Toggling
Bit 0 of the control register selects odd or even parity.
When a parity error is detected in one or more bytes, the
signal PF is asserted and the result of the individual parity
checks are written to the parity register. See Example 3.
The LH543620 has six programmable resource regis-
ters. The resource registers may be loaded from either
the Input Port or the Output Port. They can be read from
the Output Port. The selection and loading or reading of
the resource registers is controlled by ADI, ADO and
CAPR. See Tables 1 and 4 and Figure 4.
The resource registers are:
To avoid a possible invalid PF signal, ENO and ENO
should not be deasserted during the CLKO low time.
1
2
Control (Default = 1).
AE Offset – Offset value of the AE flag (Default = 8).
AF Offset – Offset value of the AF flag (Default = 8).
The parity register is frozen until read. When read, the
parity register is released and ready to store the next
parity error data.
RT Offset – Offset value of the Retransmit mechanism
(Default = 0).
Parity Generation
RT Base – Base register of the Retransmit mechanism
(Default = 0).
After Reset, parity generation is not active. Parity
generation is active only when Bit 1 of the control register
is HIGH. The parity mechanism, when enabled, creates
a parity bit for each of the bytes of the input word. The
parity bit for each byte is created based on its 8 least
significant bits of each 9-bit byte of the input-data word
and on Bit 0 of the control register (it specifies odd or even
parity). The result of the parity generation is written back
to the MSB of the data byte. See Example 4.
Parity
EXAMPLE 3
PARITY CHECK
Q35
Q0
Output word:
Odd parity:
Even parity:
100111100 000111100 100111000 000111000
Parity Register = 0110; PF-Asserted Low
Parity Register = 1001; PF-Asserted Low
EXAMPLE 4
PARITY GENERATION
D35
D0
Input word:
100111100 000111100 100111000 000111000
100111100 100111100 000111000 000111000
Output, odd parity:
Output, even parity: 000111100 000111100 100111000 100111000
2-428
1024 × 36 Synchronous FIFO
LH543620
Control Register (See Figure 7)
Output Port:
After reset, the control register’s value is 1. This sets
the following conditions:
Data from the Output Port is written to a resource
register when:
Odd parity
the value of the output-address field, ADO, selects the
register (see Table 4)
Disabling parity generation (parity check is active).
AF, HF, AE flags are asynchronous.
OE signal does not control the Read pointer.
Read/Write Resource Register Mode
CAPR is HIGH
OE is HIGH
NOTE: ADI[2:0] should remain stable whenever data is
coming in from the output port.
It is possible to write to the resource registers from
either the Input Port or the Output Port. Reading from the
resource register is possible only from the Output Port.
The source port for the write operation is determined by
the control signal CAPR.
Data is read from a resource register to the Output Port
when:
the value of the output-address field, ADO, selects the
register (see Table 4)
Input Port:
OE is LOW
Data from the Input Port iswritten toa resourceregister
when:
Both operations are enabled by ADO[2:0] and are
synchronous to CKO.
the value of the input-address field, ADI, selects the
register (see Table 1)
MAILBOX
The mailbox mechanism includes:
CAPR is LOW
One 36-bit data register.
TheoperationisenabledbyADI[2:0]andsynchronized
to CKI.
Two status flags:
– MFF Mailbox Full Flag
– MEF Mailbox Empty Flag
6
5 4 3 2 1 0
0 EVEN PARITY
1 ODD PARITY
0 PARITY GENERATION IS DISABLED
1 PARITY GENERATION IS ENABLED
0 AE ASYNCHRONOUS
1 AE SYNCHRONOUS TO CKO
0 HF ASYNCHRONOUS
1 HF SYNCHRONOUS TO CKO
2 OR 3 HF SYNCHRONOUS TO CKI
0 AF ASYNCHRONOUS
1 AF SYNCHRONOUS TO CKI
0 OE DOES NOT CONTROL THE READ POINTER
1 OE CONTROLS THE READ POINTER
543620-29
Figure 8. LH543620 Control Register
2-429
LH543620
Writing to the Mailbox is enabled from the Input Port
1024 × 36 Synchronous FIFO
The recommended control setting for bypass is:
when the Input Port address field ADI[2:0] = 6. The write
operation is synchronous to the rising edge of CKI.
ENI = LOW, ENO = LOW, ADI[2:0] = 7,
ADO[2:0] = 7, OE = LOW, BYE = LOW
When writing to the Mailbox, the status flags are
changed as follows:
OPERATIONAL MODES AND CONFIGURATIONS
Interlocked Width Expansion (Figure 8A)
MEF is deasserted HIGH on the rising edge of CKO.
MFF is asserted LOW on the rising edge of CKI.
Two LH543620s may be configured to expand the
width to 72 bits. This is accomplished by:
A Mailbox read is enabled from the Output Port, when
the Output Port address field ADO[2:0] = 6. The Read
operation is synchronized to CKO.
Cross-connecting the FF output of each FIFO to ENI
1
(or ENI ) input of the other FIFO.
2
Cross-connecting the EF output of each FIFO to ENO
1
When reading the Mailbox, the status flags are
changed as follows:
(or ENO ) input of the other FIFO.
2
The composite status flags are the OR function of the
individual flags.
MEF is asserted LOW on the rising edge of CKO.
MFF is deasserted HIGH on the rising edge of CKI.
Pipeline Cascading Mode and ‘Two-Dimension’
Pipeline Cascading Mode (Figure 8B and 8C)
After reset the Mailbox is empty (i.e., MFF = HIGH,
MEF = LOW).
Depth cascading is accomplished by:
When using Mailbox, the transmitter side can transfer
a message to the receiver side without interrupting the
data in the FIFO memory array.
Setting the upper FIFO into cascade mode:
RTMD[1:0] = 0
Connecting the same free-running clock to CKO of the
upper FIFO and to CKI input of the lower FIFO.
DATA BYPASS MODE
Data Bypass mode is selected when BYE = LOW. In
this mode, data may be transferred asynchronously from
the Input Port to the Output Port. The device may be
placed in Data Bypass mode without voiding the contents
of the FIFO memory array, the Mailbox Register, or the
Resource Register. However, if the input is enabled
Connecting the AE output of the upper FIFO to ENI
1
input (or ENI ) of the lower FIFO.
2
Connecting the FF output of the lower FIFO to ENO
1
input (or ENO ) of the upper FIFO.
2
NOTE: RTMD[1:0] should remain stable during cascade
mode operation (i.e., remain low).
(ENI = HIGH) then the input data D is also written to
1,2
the FIFO memory array on the rising edge of CKI. If the
Output is enabled, (ENO = HIGH) then the input data
1,2
D is transferred to the output buffer, and the Read Pointer
is incremented by CKO. The control signal OE is function-
ing when BYE is asserted.
2-430
1024 × 36 Synchronous FIFO
LH543620
CKI
ENI
CKI
CKO
ENO1
EF
CKO
ENO
ENI1
ENI2
FF
ENO2
Q[35:0]
DI[71:36]
D[35:0]
DO[71:36]
CKI
CKO
ENO1
EF
ENI1
ENI2
FF
EF
FF
ENO2
Q[35:0]
DI[35:0]
DO[35:0]
D[35:0]
A. INTERLOCKED WIDTH EXPANSION
COMMON
CLOCK
CKI
ENI1
CKI
CKO
ENO1
AE
CKI
CKO
ENO1
EF
CKO
VCC
ENI1
ENI2
FF
ENI1
ENI2
FF
ENO1
EF
ENI2
FF
ENO2
Q[35:0]
ENO2
Q[35:0]
ENO2
DO[35:0]
DI[35:0]
D[35:0]
D[35:0]
RTMD[1:0]
L L
RTMD[1:0]
H H
B. PIPELINED CASCADING MODE
COMMON
CLOCK
CKO
ENO
CKI
ENI
CKI
CKO
ENO1
AE
CKI
CKO
ENO1
EF
VCC
ENI1
ENI2
FF
ENI1
ENI2
FF
ENO2
Q[35:0]
ENO2
Q[35:0]
DO[71:36]
D[35:0]
D[35:0]
DI[71:36]
RTMD[1:0]
H H
RTMD[1:0]
L L
CKI
ENI1
ENI2
FF
CKO
ENO1
AE
CKI
ENI1
ENI2
FF
CKO
ENO1
EF
VCC
EF
FF
ENO2
ENO2
Q[35:0]
DO[35:0]
DI[35:0]
D[35:0]
D[35:0]
RTMD[1:0]
L L
Q[35:0]
RTMD[1:0]
H H
C. 'TWO-DIMENSION' PIPELINED CASCADING MODE
NOTES:
DI = System data input width.
DO = System data output width.
543620-7
Figure 9. LH543620 Width and Depth Expansion Scheme
2-431
LH543620
1024 × 36 Synchronous FIFO
TIMING DIAGRAMS
tRS
RS
tRF
EF, AE
tRF
FF, HF,
AF, PF
tRO
OE = HIGH1
OE = LOW
Q[35:0]
tRSR
ENI1, ENI2,
ENO1, ENO2
ADI[2:0]3
ADO[2:0]
NOTES:
1. After reset, the outputs will be LOW if OE = LOW, and in a high-impedance
state if OE = HIGH.
2. The clocks (CKI, CKO) may be free-running during a reset operation.
3. If CAPR = L, then ADO = XXX and ADI must be = H,H,H for proper reset.
If CAPR = H, then ADI = XXX and ADO must be = H,H,H for proper reset.
543620-15
Figure 10. Reset Timing
2-432
1024 × 36 Synchronous FIFO
LH543620
tC
tCH
tCL
CKI
tEH
tEH
tES
tES
ENI1, ENI2
D[35:0]
tDS
tDH
tDS
tDH
tC
CKO
tEH
tES
tEH
tES
tCL
tCH
ENO1, ENO2
OE
tOZ
tOH
tOE
tOL
tA
tOH
tA
tOH
Q[35:0]
PREVIOUS DATA
NOTES:
1. Both ENI1 and ENI2 must be asserted (HIGH) to enable write operations.
2. Both ENO1 and ENO2 must be asserted (HIGH) to enable read operations.
543620-8
Figure 11. Write and Read Operation
2-433
LH543620
1024 × 36 Synchronous FIFO
CKI
tES
tEH
ENI1, ENI2
tDS
tDH
DATA VALID
tSKEW2
D[35:0]
CKO
EF
tEF
tEF
(NOTE)
tA
tOH
DATA-OUT VALID
Q[35:0]
ENO1, ENO2
OE
NOTE: If tSKEW2 < (minimum specification) then EF may change one CKO cycle later.
543620-9
Figure 12. Empty Flag Timing
2-434
1024 × 36 Synchronous FIFO
LH543620
WRITE
NO WRITE
CKI
tFF
tFF
FF
(NOTE)
tDS
tDH
D[35:0]
DATA WRITE
tES
ENI1, ENI2
tSKEW1
CKO
tES
tEH
ENO1, ENO2
tA
tOH
Q[35:0]
DATA READ
NOTE: If tSKEW1 < (minimum specification) then FF may change one CKI cycle later.
543620-10
Figure 13. Full Flag Timing
2-435
LH543620
1024 × 36 Synchronous FIFO
WORD (1024 - p-1) WRITE OCCURS
WORD (1024 - p-1) READ OCCURS
CKI
CKO
tSKEW1
ENI1, ENI2
ENO1, ENO2
tAF
tAF
SYNCHRONOUS MODE
AF
tAF
ASYNCHRONOUS MODE
tAF
AF
NOTES:
1. The synchronization mode of AF is set by programming bit 5 of control register.
2. When in synchronization mode and tSKEW1 < (min specification) then AF may change one CKI later.
543620-11
Figure 14. Almost-Full Flag -
Synchronous and Asynchronous Modes
WORD (q + 1) READ OCCURS
WORD (q + 1) WRITE OCCURS
CKI
CKO
ENO1, ENO2
ENI1, ENI2
tSKEW2
tAE
tAE
ASYNCHRONOUS MODE
AE
tAE
tAE
SYNCHRONOUS MODE
AE
NOTES:
1. The synchronization mode is set by programming bit 2 of control register.
2. When AE is in synchronous mode and tSKEW2 < (min specification) then AE may change one CKO cycle later.
543620-12
Figure 15. Almost-Empty Flag -
Synchronous and Asynchronous Modes
2-436
1024 × 36 Synchronous FIFO
LH543620
WORD 513 READ OCCURS
WORD 513 WRITE OCCURS
CKI
CKO
tSKEW2
tSKEW1
ENI1, ENI2
ENO1, ENO2
tHF
tHF
ASYNCHRONOUS MODE
HF
tHF
tHF
SYNCHRONOUS TO CKI
HF
HF
tHF
tHF
SYNCHRONOUS TO CKO
NOTE: The synchronization mode of HF is determined by the state of bits 3 and 4 of the Control Register.
543620-28
Figure 16. Half-Full Flag -
Synchronous and Asynchronous Modes
2-437
LH543620
1024 × 36 Synchronous FIFO
CKI
tDS
tDH
D[35:0]
N1
N2
N3
N4
N5
ENI1, ENI2
tSKEW2
CKO
tEF
EF
tA
tOH
Q[35:0]
N1
N2
N3
tEH
ENO1, ENO2
OE
NOTE: 1. If tSKEW2 < (minimum specification) then EF may change one CKO
later and the first word (N1) will appear on Q[35:0] one cycle later.
543620-13
Figure 17. First Word Latency
CKO
ENO1, ENO2
tPF
tPF
PF
tA
tOH
Q[35:0]
N3
N1
N2
N4
NOTE: Parity error at word N1.
543620-14
Figure 18. Parity Flag
2-438
1024 × 36 Synchronous FIFO
LH543620
BYE
D[35:0]
Q[35:0]
I1
I2
I3
tBA
tBD
(FIFO OUT)
I2
I3
(FIFO OUT)
NOTES:
1. If ENI is enabled during BYE = LOW, the bypass data
will be written into the FIFO.
2. If ENO is enabled the data at the Q Port is the bypass data.
The RP will be updated according to CKO.
543620-16
Figure 19. Bypass
CKO
tAS
tAH
ADO[2:0]
7
3
7
tA
tOH
Q[35:0]
N1
N2
tES
PARITY R.
tES
N3
N4
tEH
tEH
ENO1, ENO2
OE
→
→
→
FIFO (N2)
Q
FIFO (N3)
Q
PARITY R
Q
NOTE: N1, N2, N3, N4 are data from the FIFO and PARITY R. is
the Parity Register value.
543620-17
Figure 20. Read Resource Register
2-439
LH543620
1024 × 36 Synchronous FIFO
CKI
CAPR
tAS
tAH
ADI[2:0]
7
5
7
tDS
tDH
Q[35:0]
D1
C
D2
D3
D4
tEH
tES
tES
tEH
ENI1, ENI2
→
→
→
→
D3 FIFO
D1
FIFO
C
CONTROL REG.
D2
FIFO
543620-18
Figure 21. Write Resource Register From the Input Port
CKO
CAPR
tOES
tOEH
OE
tAS
tAH
ADO[2:0]
7
5
7
tDSO
tDHO
Q[35:0]
N1
C
N2
N3
tEH
tES
tES
tEH
ENO1, ENO2
→
→
→
→
FIFO (N3) Q
FIFO (N1)
Q
Q(C)
CONTROL
REG.
FIFO (N2)
Q
543620-19
Figure 22. Write Resource Register From Output Port
2-440
1024 × 36 Synchronous FIFO
LH543620
CKI
ENI1, ENI2
tWSS
WSI[1:0] WSI1
WSI2
DATA IS STORED
ACCORDING TO:
WSI1
WSI2
WSI2
WSI2
543620-20
Figure 23. WSI[1:0] Timing
CKO
ENO1, ENO2
tWSS
WSO[1:0] WSO1
WSO2
DATA IS READ
ACCORDING TO:
WSO1
WSO2
WSO2
WSO2
543620-21
Figure 24. WSO[1:0] Timing
2-441
LH543620
1024 × 36 Synchronous FIFO
CKO
tEH
tES
tES
tEH
ENO1, ENO2
ADO[2:0]
MEF
tAS
tAH
7
6
7
tMEF
tA
tOH
Q[35:0]
CKI
Q (FIFO)
MAILBOX
Q (FIFO)
MFF
tSKEWM
tMFF
NOTE: If tSKEWM < minimum specification MFF may be changed one CKI later.
543620-22
Figure 25. Mailbox Read
2-442
1024 × 36 Synchronous FIFO
LH543620
CKI
tEH
tES
tES
tEH
ENI1, ENI2
tAH
tAS
7
6
7
ADI[2:0]
MFF
tMFF
tDS
tDH
D[35:0]
CKO
I1
M
I2
I3
I4
MEF
tSKEWM
tMEF
NOTE: If tSKEWM < minimum specification MEF may be changed one CKO later.
543620-23
Figure 26. Mailbox Write
2-443
LH543620
1024 × 36 Synchronous FIFO
Figure 27. Retransmit Using Retransmit and Mark Mode
2-444
1024 × 36 Synchronous FIFO
LH543620
Figure 28. Retransmit Using Mark Mode and
Retransmit Mode
2-445
LH543620
1024 × 36 Synchronous FIFO
CKO
tOES
tOEH
OE
ENO1, ENO2
tA
tOZ
tOL
tOH
Q[35:0]
543620-26
Figure 29. OE When Bit 6 of the
Control Register is HIGH
2-446
1024 × 36 Synchronous FIFO
PACKAGE DIAGRAM
132PQFP (PQFP132-P-S950)
LH543620
0° - 8°
SECTION
0.15 [0.006]
0.25 [0.010] TYP.
0.51 [0.020] MIN.
45°
CHAMFER
0.10 [0.004]
0.635
[0.025] TYP
NON-ACCUM
28.02 [1.103]
27.86 [1.097]
27.69 [1.090]
27.18 [1.070]
TOP VIEW
24.21 [0.953]
24.05 [0.947]
24.21 [0.953]
24.05 [0.947]
0.51 [0.020]
MIN.
27.69 [1.090]
27.18 [1.070]
4.57 [0.180]
4.06 [0.160]
28.02 [1.103]
27.86 [1.097]
MAXIMUM LIMIT
MINIMUM LIMIT
DIMENSIONS IN MM [INCHES]
132 PQFP
132-pin PQFP
2-447
LH543620
1024 × 36 Synchronous FIFO
144TQFP (TQFP-144-P-2020)
0.20 [0.008]
0.09 [0.004]
0.27 [0.010]
0.17 [0.007]
0.50 [0.020]
TYP.
20.0
22.0
[0.787] [0.866]
BASIC BASIC
20.0 [0.787]
BASIC
22.0 [0.866]
BASIC
DETAIL
1.60 [0.063]
REF. MAX
1.45 [0.057]
1.35 [0.053]
0.15 [0.006]
0.05 [0.002]
0.75 [0.030]
0.47 [0.019]
1.00
[0.039]
REF.
MAXIMUM LIMIT
MINIMUM LIMIT
DIMENSIONS IN MM [INCHES]
144TQFP
2-448
1024 × 36 Synchronous FIFO
LH543620
ORDERING INFORMATION
LH543620
X
- ##
Device Type
Package
Speed
20
25
30
Cycle Times (ns)
P 132-Pin, Plastic Quad Flat Package (PQFP132-P-S950)
M 144-Pin, Thin Quad Flat Package
1024 x 36 Synchronous FIFO
Example: LH543620P-20 (1024 x 36 Synchronous FIFO, 20 ns, 132-Lead, Plastic Quad Flat Package)
543620-32
LIFE SUPPORT POLICY
SHARP components should not be used in medical devices with life support functions or in safety equipment (or similiar applications where
component failure would result in loss of life or physical harm) without the written approval of an officer of the SHARP Corporation.
LIMITED WARRANTY
SHARP warrants to its Customer that the Products will be free from defects in material and workmanship under normal use and service for a
period of one year from the date of invoice. Customer's exclusive remedy for breach of this warranty is that SHARP will either (i) repair or
replace, at its option, any Product which fails during the warranty period because of such defect (if Customer promptly reported the failure to
SHARP in writing) or, (ii) if SHARP is unable to repair or replace, refund the purchase price of the Product upon its return to SHARP. This
warranty does not apply to any Product which has been subjected to misuse, abnormal service or handling, or which has been altered or
modified in design or construction, or which has been serviced or repaired by anyone other than Sharp. The warranties set forth herein are in
lieu of, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE
WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY
EXCLUDED. In no event will Sharp be liable, or in any way responsible, for any incidental or consequential economic or property damage.
The above warranty is also extended to Customers of Sharp authorized distributors with the following exception: reports of failures of Products
during the warranty period and return of Products that were purchased from an authorized distributor must be made through the distributor.
In case Sharp is unable to repair or replace such Products, refunds will be issued to the distributor in the amount of distributor cost.
SHARP reserves the right to make changes in specifications at any time and without notice. SHARP does not assume any responsibility
for the use of any circuitry described; no circuit patent licenses are implied.
®
NORTH AMERICA
EUROPE
ASIA
SHARP Corporation
SHARP Electronics Corporation
Microelectronics Group
5700 NW Pacific Rim Blvd., M/S 20
Camas, WA 98607, U.S.A.
Phone: (360) 834-2500
Telex: 49608472 (SHARPCAM)
Facsimile: (360) 834-8903
http://www.sharpmeg.com
SHARP Electronics (Europe) GmbH
Microelectronics Division
Sonninstraße 3
20097 Hamburg, Germany
Phone: (49) 40 2376-2286
Telex: 2161867 (HEEG D)
Facsimile: (49) 40 2376-2232
Integrated Circuits Group
2613-1 Ichinomoto-Cho
Tenri-City, Nara, 632, Japan
Phone: (07436) 5-1321
Telex: LABOMETA-B J63428
Facsimile: (07436) 5-1532
©1991 by SHARP Corporation
Reference Code SMT91008
相关型号：
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