LH5496HD-35 [SHARP]
CMOS 512 X 9 FIFO; CMOS 512 ×9 FIFO
| 型号： | LH5496HD-35 |
| 厂家： | 
SHARP ELECTRIONIC COMPONENTS |
| 描述： | CMOS 512 X 9 FIFO |
| 文件： | 总16页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LH5496/96H
CMOS 512 × 9 FIFO
FEATURES
PIN CONNECTIONS
• Fast Access Times:
28-PIN PDIP
TOP VIEW
15 */20/25/35/50/65/80 ns
28
27
26
25
24
23
22
21
20
19
18
17
16
15
W
D8
D3
D2
D1
D0
XI
1
2
VCC
D4
• Full CMOS Dual Port Memory Array
• Fully Asynchronous Read and Write
• Expandable-in Width and Depth
• Full, Half-Full, and Empty Status Flags
• Read Retransmit Capability
3
D5
D6
4
D7
5
6
FL/RT
RS
7
8
EF
FF
Q0
Q1
9
XO/HF
Q7
• TTL Compatible I/O
10
11
12
13
14
Q6
Q5
Q4
R
• Packages:
Q2
Q3
28-Pin, 300-mil PDIP
28-Pin, 600-mil PDIP
32-Pin PLCC
Q8
VSS
5496-1D
• Pin and Functionally Compatible with IDT7201
Figure 1. Pin Connections for PDIP Packages
FUNCTIONAL DESCRIPTION
32-PIN PLCC
TOP VIEW
The LH5496/96H are dual port memories with internal
addressing to implement a First-In, First-Out algorithm.
Throughan advanced dual port architecture,theyprovide
fully asynchronous read/write operation.Empty, Full,and
Half-Full status flags are provided to prevent data over-
flow and underflow. In addition, internal logic provides for
unlimited expansion in both word size and depth.
1
30
4
3
2
32 31
D2
D1
D0
XI
5
6
7
8
9
D6
29
28
27
26
25
24
23
22
21
D7
NC
FL/RT
RS
Read and write operations automatically access se-
quential locations in memoryinthat dataisread outin the
same order that it was written, that is on a First-In,
First-Out basis. Since the address sequence is internally
predefined, no external address information is required
for theoperation ofthis device. Aninth databit isprovided
for parity or control information often needed in commu-
nication applications.
FF
Q0
Q1
NC
Q2
10
11
12
13
EF
XO/HF
Q7
Q6
14
19
20
15 16
17 18
Empty, Full, and Half-Full status flags monitor the
extent to which data has been written into the FIFO, and
prevent improper operations (i.e., Read if the FIFO is
empty, or Write if the FIFO is full). A retransmit feature
resets the Read address pointer to its initial position,
thereby allowing repetitive readout of the same data.
Expansion In and Expansion Out pins implement an
expansion scheme that allows individual FIFOs to be
cascaded to greater depth without incurring additional
latency (bubblethrough) delays.
5496-2D
Figure 2. Pin Connections for PLCC Package
* LH5496 only.
1
LH5496/96H
CMOS 512 × 9 FIFO
DATA INPUTS
D0 - D8
RESET
LOGIC
RS
OUTPUT
PORT
INPUT
PORT
R
W
CONTROL
CONTROL
DUAL-PORT
RAM
ARRAY
WRITE
POINTER
READ
POINTER
512 x 9
. . .
DATA OUTPUTS
Q0 - Q8
EF
FF
FLAG
LOGIC
EXPANSION
LOGIC
FL/RT
XI
XO/HF
5496-3
Figure 3. LH5496/96H Block Diagram
PIN DESCRIPTIONS
PIN
D0 – D8
Q0 – Q8
W
PIN TYPE *
DESCRIPTION
PIN
XO/HF
XI
PIN TYPE *
DESCRIPTION
Input Data Bus
Output Data Bus
Write Request
Read Request
Empty Flag
Expansion Out/Half-Full Flag
Expansion In
I
O/Z
I
O
I
FL/RT
RS
First Load/Retransmit
Reset
I
R
I
I
EF
VCC
Positive Power Supply
Ground
O
O
V
V
FF
Full Flag
VSS
* I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level
2
CMOS 512 × 9 FIFO
LH5496/96H
1
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
Supply Voltage to VSS Potential
Signal Pin Voltage to VSS Potential 3
DC Output Current 2
–0.5 V to 7 V
–0.5 V to VCC + 0.5 V (not to exceed 7 V)
±50 mA
Storage Temperature Range
Power Dissipation (Package Limit)
–65oC to 150oC
1.0 W
DC Voltage Applied To Outputs In High-Z State
–0.5 V to Vcc + 0.5 V (not to exceed 7 V)
NOTES:
1. Stresses greater than those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device.
This is a device stress rating for transient conditions only. Functional operation at these or any other conditions above
those indicated in the ‘Operating Range’ of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time.
3. Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle.
OPERATING RANGE
SYMBOL
PARAMETER
Temperature, Ambient, LH5496
Temperature, Ambient, LH5496H
Supply Voltage
MIN
0
MAX
70
UNIT
o
TA
C
o
TA
–40
4.5
0
85
C
VCC
VSS
VIL
5.5
0
V
V
V
V
Supply Voltage
Logic ‘0’ Input Voltage 1
–0.5
2.0
0.8
VIH
Logic ‘1’ Input Voltage
V
+ 0.5
CC
NOTE:
1. Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
SYMBOL
PARAMETER
TEST CONDITIONS
VCC = 5.5 V, VIN = 0 V to VCC
R ≥ VIH, 0 V ≤ VOUT ≤ VCC
IOH = –2.0 mA
MIN
–10
–10
2.4
MAX
10
UNIT
µA
µA
V
ILI
Input Leakage Current
Output Leakage Current
Output High Voltage
ILO
10
VOH
VOL
ICC
Output Low Voltage
IOL = 8.0 mA
0.4
100
15
V
Average Supply Current 1
Average Standby Current 1
Power Down Current 1
Measured at f = 40 MHz
All Inputs = VIH
mA
mA
mA
ICC2
ICC3
All Inputs = VCC – 0.2 V
5
NOTE:
1. ICC, ICC2, and ICC3 are dependent upon actual output loading and cycle rates. Specified values are with outputs open.
3
LH5496/96H
CMOS 512 × 9 FIFO
AC TEST CONDITIONS
PARAMETER
RATING
+5 V
Input Pulse Levels
V
SS
to 3 V
1.1 k Ω
Input Rise and Fall Times (10% to 90%)
Input Timing Reference Levels
Output Reference Levels
Output Load, Timing Tests
5 ns
DEVICE
UNDER
TEST
1.5 V
1.5 V
*
30 pF
680 Ω
Figure 4
1,2
CAPACITANCE
*
INCLUDES JIG & SCOPE CAPACITANCES
5496-4
PARAMETER
CIN (Input Capacitance)
COUT (Output Capacitance)
RATING
5 pF
Figure 4. Output Load Circuit
7 pF
NOTES:
1. Sample tested only.
2. Capacitances are maximum values at 25oC measured at 1.0 MHz
with VIN = 0 V.
4
CMOS 512 × 9 FIFO
LH5496/96H
1
AC ELECTRICAL CHARACTERISTICS (Over Operating Range)
tA = 15 ns 2 tA = 20 ns tA = 25 ns tA = 35 ns tA = 50 ns tA = 65 ns tA = 80 ns
SYMBOL
PARAMETER
UNIT
MAX
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN
MIN MAX
READ CYCLE TIMING
tRC
tA
Read Cycle Time
25
–
–
15
–
30
–
–
20
–
35
–
–
25
–
45
–
–
35
–
65
–
–
50
–
80
–
–
65
–
100
–
–
80
–
ns
ns
ns
ns
ns
Access Time
tRR
tRPW
tRLZ
Read Recover Time
Read Pulse Width3
Data Bus Active from Read LOW 4
10
15
5
10
20
5
10
25
5
10
35
5
15
50
5
15
65
5
15
80
10
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Data Bus Active from Write
HIGH 4,5
tWLZ
tDV
10
5
–
–
10
5
–
10
5
–
–
10
5
–
–
10
5
–
10
5
–
–
20
5
–
–
ns
ns
ns
Data Valid from Read Pulse HIGH
–
–
Data Bus High-Z from Read
HIGH 4
tRHZ
–
15
–
15
–
15
–
15
–
20
–
30
–
30
WRITE CYCLE TIMING
tWC
tWPW
tWR
tDS
Write Cycle Time
Write Pulse Width 3
Write Recovery Time
Data Setup Time
Data Hold Time
25
15
10
10
0
–
–
–
–
–
30
20
10
10
0
–
–
–
–
–
35
25
10
10
0
–
–
–
–
–
45
35
10
15
0
–
–
–
–
–
65
50
15
20
0
–
–
–
–
–
80
65
15
20
5
–
–
–
–
–
100
80
15
20
5
–
–
–
–
–
ns
ns
ns
ns
ns
tDH
RESET TIMING
tRSC
tRS
Reset Cycle Time
25
15
10
15
15
–
–
–
–
–
30
20
10
20
20
–
–
–
–
–
35
25
10
25
25
–
–
–
–
–
45
35
10
35
35
–
–
–
–
–
65
50
15
50
50
–
–
–
–
–
80
65
15
65
65
–
–
–
–
–
100
80
–
–
–
–
–
ns
ns
ns
ns
ns
Reset Pulse Width 3
Reset Recovery Time
Read HIGH to RS HIGH
Write HIGH to RS HIGH
tRSR
tRRSS
tWRSS
15
80
80
RETRANSMIT TIMING
tRTC
tRT
Retransmit Cycle Time
Retransmit Pulse Width 3
Retransmit Recovery Time
25
15
10
–
–
–
30
20
10
–
–
–
35
25
10
–
–
–
45
35
10
–
–
–
65
50
15
–
–
–
80
65
15
–
–
–
100
80
–
–
–
ns
ns
ns
tRTR
15
FLAG TIMING
tEFL
Reset LOW to Empty Flag LOW
–
–
25
–
30
–
35
35
–
–
45
45
–
–
65
65
–
–
80
80
–
–
100 ns
100 ns
Reset LOW to Half-Full and Full
Flags HIGH
tHFH,FFH
25
–
30
–
tREF
tRFF
tWEF
tWFF
tWHF
tRHF
Read LOW to Empty Flag LOW
Read HIGH to Full Flag HIGH
Write HIGH to Empty Flag HIGH
Write LOW to Full Flag LOW
–
–
–
–
–
–
20
20
20
20
25
25
–
–
–
–
–
–
25
25
25
25
30
30
–
–
–
–
–
–
25
25
25
25
35
35
–
–
–
–
–
–
35
35
35
35
45
45
–
–
–
–
–
–
45
45
45
45
65
65
–
–
–
–
–
–
60
60
60
60
80
80
–
–
–
–
–
–
60
60
60
60
ns
ns
ns
ns
Write LOW to Half-Full Flag LOW
Read HIGH to Half-Full Flag HIGH
100 ns
100 ns
EXPANSION TIMING
tXOL
tXOH
tXI
Expansion Out LOW
–
–
18
18
–
–
20
20
–
–
–
25
25
–
–
35
35
–
–
50
50
–
–
65
65
–
–
80
80
–
ns
ns
ns
ns
ns
Expansion Out HIGH
–
–
–
–
–
Expansion In Pulse Width
Expansion In Recovery Time
Expansion in Setup Time
15
10
7
20
10
10
25
10
10
35
10
15
50
10
15
65
10
15
80
10
15
tXIR
–
–
–
–
–
–
–
tXIS
–
–
–
–
–
–
–
NOTES:
1. LH5496 only.
2. All timing measurements performed at ‘AC Test Condition’ levels.
5
LH5496/96H
CMOS 512 × 9 FIFO
The internal read andwriteaddress pointers are main-
tained by the device such that consecutive read opera-
tions will access data in the same order as it was written.
The Empty flag is asserted (EF = LOW) after the falling
edge of R which accesses the last available data in the
FIFO memory. EF is deasserted (EF = HIGH) after the
next rising edge of W loads another word of valid data.
OPERATIONAL DESCRIPTION
Reset
The device is reset whenever the Reset pin (RS) is
taken to a LOW state. The reset operation initializes both
the read and write address pointers to the first memory
location.The XI and FL pins are also sampled atthis time
to determine whether the device is in Single mode or
Depth Expansion mode. A reset pulse is required when
the device is first powered up. The Read (R) and Write
(W) pins may be in any state when reset is initiated, but
Data Flow-Through
Read flow-through mode occurs when the Read (R)
pin is brought LOW while the FIFO is empty, and held
LOWinanticipationof a write cycle. At the end ofthe next
write cycle, the Empty flag will be momentarily deas-
serted, and the data just written will become available on
must be brought to a HIGH state t
and t
before
RPW
WPW
the rising edge of RS. The reset operation forces the
Empty Flag EF to be asserted (EF = LOW), and the
Half-Full Flag HF and the Full FLag FF to be deasserted
the data out pins after a maximum time of t
+ t .
A
WEF
(HF = FF = HIGH);the Data Outpins (D – D ) are forced
into a high-impedance state.
Additional writesmay occurwhiletheR pinremainsLOW,
but only data from the first write flows through to the
outputs. Additional data, if any, can only be accessed by
toggling R.
0
8
Write
A write cycle is initiated on the falling edge of the Write
(W) pin. Data setup and hold times must be observed on
Write flow-through mode occurs when the Write (W)
pin is brought LOW while the FIFO is full, and held LOW
inanticipation ofaread cycle.Attheendofthe readcycle,
the Full flag will be momentarily deasserted, but then
immediately reassertedin responsetoW held LOW. Data
is written into the FIFOon the rising edge ofW which may
thedatain(D –D )pins.Awriteoperationisonlypossible
0
8
if the FIFO is not full, (i.e. the Full flag pin is HIGH). Writes
may occur independently of any ongoing read operta-
tions.
At the falling edge of the first write after the memory is
half filled, the Half-Full flag will be asserted (HF = LOW)
and will remain asserted until the difference between the
write pointerand read pointer indicates thattheremaining
data in the device is lessthan orequal to one halfthe total
capacity of the FIFO. The Half-Full flag is deasserted
(HF = HIGH) by the appropriate rising edge of R.
occur t
+ t
after the read.
RFF
WPW
Retransmit
The FIFO can be made to reread previously read data
through the retransmit function. Retransmit is initiated by
pulsing RT LOW. This resets the internal read address
pointer to the first physical location in the memory while
leaving the internal write address pointer unchanged.
Data between the read and write pointers may be reac-
cessed by subsequent reads. Both R and W must be
inactive (HIGH) during the retransmit pulse. Retransmit
is useful if no more than 512 writes are performed be-
tween resets. Retransmit may affect the status of EF, HF,
and FF flags, depending on the relocation of the read
pointer. This function is not available in depth expansion
mode.
The Full flag is asserted (FF = LOW) atthe falling edge
of the write operation which fills the last available location
in the FIFO memory array. The Full flag will inhibit further
writes until cleared by a valid read. The Full flag is
deasserted (FF = HIGH) after the next rising edge of R
releases another memory location.
Read
A read cycle is initiated on the falling edge ofthe Read
(R) pin.Readdata becomesvalid onthedata out(Q –Q )
0
8
pins aftera time t from the falling edgeof R. After R goes
A
HIGH, the dataout pins return to a high-impedance state.
Reads may occur independent of any ongoing write
operations. Aread isonlypossibleifthe FIFOisnotempty
(EF = HIGH).
6
CMOS 512 × 9 FIFO
LH5496/96H
TIMING DIAGRAMS
tRSC
tRS
RS
R,W
tRRSS
tWRSS
tEFL
tRSR
EF
tFFH tHFH
,
FF,HF
NOTES:
1. tRSC = tRS + tRSR
.
2. W and R ≥ VIH around the rising edge of RS.
3. The Data Out pins (D0 - D8) are forced into a
high-impedance state whenever EF = LOW.
5496-14
Figure 5. Reset Timing
tRPW
tRC
tRR
tA
tA
R
tRLZ
t RHZ
tDV
Q0 - Q8
VALID DATA OUT
tWC
VALID DATA OUT
tWPW
tWR
W
t DS
t DH
D0 - D8
VALID DATA IN
VALID DATA IN
5496-5
Figure 6. Asynchronous Write and Read Operation
7
LH5496/96H
CMOS 512 × 9 FIFO
TIMING DIAGRAMS (cont’d)
LAST WRITE
FIRST READ
R
W
tWFF
tRFF
FF
5496-6
Figure 7. Full Flag from Last Write to First Read
LAST READ
FIRST WRITE
W
R
tREF
tWEF
EF
NOTE: The Data Out pins (D0 - D8) are forced into a
high-impedance state whenever EF = LOW.
5496-7
Figure 8. Empty Flag from Last Read to First Write
8
CMOS 512 × 9 FIFO
LH5496/96H
TIMING DIAGRAMS (cont’d)
VALID DATA IN
D0 - D8
W
R
tRPE
EF
tREF
tWEF
tWLZ
tA
VALID DATA OUT
Q0 - Q8
NOTES:
1. tRPE = tRPW
2. tRPE: Effective Read Pulse Width after Empty Flag HIGH.
3. The Data Out pins (D0 - D8) are forced into a
high-impedance state whenever EF = LOW.
5496-8
Figure 9. Read Data Flow-Through
R
tWPF
W
tRFF
FF
t WFF
t DH
t DS
VALID DATA IN
D0 - D8
tA
Q0 - Q8
VALID DATA OUT
NOTES:
1. tWPF = tWPW
2. tWPF: Effective Write Pulse Width after Full Flag HIGH.
5496-9
Figure 10. Write Data Flow-Through
9
LH5496/96H
CMOS 512 × 9 FIFO
TIMING DIAGRAMS (cont’d)
W
EF
R
tWEF
tRPE
NOTES:
1. tRPE = tRPW
2. tRPE: Effective Read Pulse Width after Empty Flag HIGH.
3. The Data Out pins (D0 - D8) are forced into a
high-impedance state whenever EF = LOW.
5496-10
Figure 11. Empty Flag Timing
R
tRFF
FF
tWPF
W
NOTES:
1. tWPF = tWPW
2. tWPF: Effective Write Pulse Width after Full Flag HIGH.
5496-11
Figure 12. Full Flag Timing
HALF-FULL
OR LESS
MORE THAN
HALF-FULL
HALF-FULL
OR LESS
W
R
tWHF
tRHF
HF
5496-12
10
CMOS 512 × 9 FIFO
LH5496/96H
TIMING DIAGRAMS (cont’d)
tRT
RT
tRTR
R,W
NOTES:
1. tRTC = tRT + tRTR
2. EF, HF and FF may change state during retransmit, but flags will be valid at tRTC
.
5496-13
Figure 14. Retransmit Timing
WRITE TO LAST
AVAILABLE
LOCATION
W
R
READ FROM
LAST VALID
LOCATION
t XOL
tXOH
t XOL
tXOH
XO
5496-15
Figure 15. Expansion Out Timing
t XI
tXIR
XI
tXIS
WRITE TO FIRST
AVAILABLE
LOCATION
W
R
tXIS
READ FROM FIRST
VALID
LOCATION
5496-16
Figure 16. Expansion In Timing
11
LH5496/96H
CMOS 512 × 9 FIFO
Width Expansion
OPERATIONAL MODES
Word-width expansion is implemented by placing mul-
tiple LH5496/96H devices in parallel. Each LH5496/96H
should be configured for standalone mode. In this ar-
rangement, the behavior of the status flags is identical for
all devices; so, in principle, a representative value for
each of these flags could bederived from any one device.
In practice, it is better to derive ‘composite’ flag values
using external logic, since there may be minor speed
variations between different actual devices. (See Figures
17 and 18.)
Single Device Configuration
When depth expansion is not required for the given
application, the device is placed in Single mode by tying
the Expansion In pin (XI) to ground. This pin is internally
sampled during reset.
HF
R
W
WRITE
READ
9
9
EF
RT
DATA OUT
Q0 - Q8
DATA IN
D0 - D8
LH5496/96H
FF
FULL FLAG
RESET
EMPTY FLAG
RETRANSMIT
RS
XI
5496-17
Figure 17. Single FIFO (512 × 9)
18
DATA IN
HF
HF
9
9
W
FF
RS
W
WRITE
LH5496/96H
R
R
FULL FLAG
LH5496/96H
READ
EF
RT
9
RS
EMPTY FLAG
RETRANSMIT
RESET
RT
9
XI
XI
18
DATA OUT
5496-18
Figure 18. FIFO Width Expansion (512 × 18)
12
CMOS 512 × 9 FIFO
LH5496/96H
are shared by all devices, while internal logic controls the
steering of data. Only one FIFO will be enabled for any
given read cycle, so the common Data Out pins of all
devices are wire-ORed together. Likewise, the common
Data In pins of all devices are tied together.
OPERATIONAL MODES (cont’d)
Depth Expansion
Depth expansion is implemented by configuring the
required number of FIFOs in Expansion mode. In this
arrangement, the FIFOs are connected in a circular fash-
ion with the Expansion Out pin (XO) of each device tied
totheExpansion In pin (XI) of the nextdevice. One FIFO
in this group must be designated as the first load device.
This is accomplished by tying the First Load pin (FL) of
this device to ground. All other devices must have their
FL pin tied to a high level. In this mode, W and R signals
In Expansion mode, external logic is required to gen-
erate a composite Full or Empty flag. This is achieved by
ORing the FF pins of all devices and ORing the EF pins
of all devices respectively. The Half-Full flag and
Retransmit functions are not available in Depth Expan-
sion mode.
XO
R
W
9
9
9
DATA IN
D0 - D8
9
DATA OUT
Q0 - Q8
LH5496/96H
EF
FL
FF
RS
Vcc
XI
XO
9
9
LH5496/96H
FF
EF
FL
FULL
EMPTY
Vcc
RS
XI
XO
9
9
FF
EF
FL
LH5496/96H
RS
RS
XI
5496-19
Figure 19. FIFO Depth Expansion (1536 × 9)
13
LH5496/96H
CMOS 512 × 9 FIFO
LH5496/96H devices in parallel but opposite directions.
The Data In pins of a device may be tied to the corre-
spondingData Outpinsofanotherdevice operatingin the
opposite direction to form a single bidirectional bus inter-
face. Care must be taken to assure that the appropriate
read, write, and flag signals are routed to each system.
Both depth and width expansion may be used in this
configuration.
OPERATIONAL MODES (cont’d)
Compound Expansion
A combination of width and depth expansion can be
easily implemented by operating groups of depth
expanded FIFOs in parallel.
Bidirectional Operation
Applications which require bidirectional data buffering
between two systems can be realized by operating
Q0 - Q8
Q0 - Q17
Q0 - QN-10
Q0 - QN-1
DATA OUT
R
LH5496/96H
DEPTH EXPANSION
BLOCK
LH5496/96H
DEPTH EXPANSION
BLOCK
LH5496/96H
DEPTH EXPANSION
BLOCK
W
RS
DATA IN
D9 - DN-1
D18 - DN-1
DN-9 - DN-1
D0 - DN-1
5496-20
Figure 20. Compound FIFO Expansion
Wa
Rb
EFb
FFa
LH5496/96H
HFb
RTb
RS
Da0 - 8
Qb0 - 8
XI
SYSTEM A
SYSTEM B
Qa0 - 8
Db0 - 8
Ra
Wb
LH5496/96H
EFa
FFb
HFa
RTa
RS
XI
5496-21
Figure 21. Bidirectional FIFO Buffer
14
CMOS 512 × 9 FIFO
LH5496/96H
PACKAGE DIAGRAMS
28SK-DIP (DIP028-P-0300)
DETAIL
28
15
14
7.05 [0.278]
6.65 [0.262]
0° TO 15°
1
0.35 [0.014]
0.15 [0.006]
35.00 [1.378]
34.40 [1.354]
7.62 [0.300]
3.65 [0.144]
3.25 [0.128]
TYP.
4.40 [0.173]
4.00 [0.157]
3.40 [0.134]
3.00 [0.118]
0.51 [0.020] MIN.
2.54 [0.100]
TYP.
0.56 [0.022]
0.36 [0.014]
MAXIMUM LIMIT
MINIMUM LIMIT
DIMENSIONS IN MM [INCHES]
28DIP-1
28-pin, 300-mil PDIP
28DIP (DIP028-P-0600)
28
15
DETAIL
13.45 [0.530]
12.95 [0.510]
0° TO 15°
1
14
0.30 [0.012]
0.20 [0.008]
36.30 [1.429]
35.70 [1.406]
15.24 [0.600]
TYP.
4.50 [0.177]
4.00 [0.157]
5.20 [0.205]
5.00 [0.197]
3.50 [0.138]
3.00 [0.118]
0.51 [0.020] MIN.
2.54 [0.100]
TYP.
0.60 [0.024]
0.40 [0.016]
MAXIMUM LIMIT
MINIMUM LIMIT
DIMENSIONS IN MM [INCHES]
28DIP-2
28-pin, 600-mil PDIP
15
LH5496/96H
CMOS 512 × 9 FIFO
32PLCC (PLCC32-P-R450)
1.27 [0.050]
4 SIDES BSC
15.11 [0.595]
14.86 [0.585]
13.46 [0.530]
12.45 [0.490]
14.05 [0.553]
13.89 [0.547]
11.51 [0.453]
11.35 [0.447]
DETAIL
12.57 [0.495]
12.32 [0.485]
0.81 [0.032]
0.66 [0.026]
3.56 [0.140]
3.12 [0.123]
2.41 [0.095]
1.52 [0.060]
0.10 [0.004]
10.92 [0.430]
9.91 [0.390]
0.38 [0.015]
MIN
MAXIMUM LIMIT
MINIMUM LIMIT
0.53 [0.021]
0.33 [0.013]
DIMENSIONS IN MM (INCHES)
32PLCC
32-pin, 450-mil PLCC
ORDERING INFORMATION
15
20
25
35
50
65
80
*
LH5496/96H
X
X
- ##
Device Type Temperature Package Speed
Range
Access Time (ns)
Blank 28-pin, 600-mil Plastic DIP (DIP28-P-600)
D 28-pin, 300-mil Plastic DIP (DIP28-P-300)
U 32-pin Plastic Leaded Chip Carrier (PLCC32-P-R450)
Blank Commercial (0° C to 70° C)
H Industrial (-40° C to 85° C)
CMOS 1K x 9 FIFO
*
LH5496 only
Example: LH5496U-25 (CMOS 512 x 9 FIFO, 32-pin PLCC, 25 ns)
5496MD
16
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