LR38616 [SHARP]
Timing Generator IC for 2 140 k-pixel CCDs; 时序产生器IC为2 140 K-像素的CCD
| 型号： | LR38616 |
| 厂家： | 
SHARP ELECTRIONIC COMPONENTS |
| 描述： | Timing Generator IC for 2 140 k-pixel CCDs |
| 文件： | 总9页 (文件大小：66K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LR38616
Timing Generator IC for
2 140 k-pixel CCDs
LR38616
DESCRIPTION
PIN CONNECTIONS
The LR38616 is a CMOS timing generator IC
which generates timing pulses for driving 2 140 k-
pixel CCD area sensors and processing pulses.
48-PIN QFP
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
FEATURES
• Designed for 1/2-type 2 140 k-pixel CCD area
sensors
OFDC 1
V1x 2
VH1Ax 3
VH1Bx 4
V2x 5
VDD3 6
GND 7
V3x 8
36 ID
35 ED2
34 ED1
33 ED0
32 HD
• Frequency of driving horizontal CCD : 17.987 MHz
• Both double speed drive monitoring mode and
still mode are possible
31 GND
30 VDD3
29 VD
28 DCLK
27 CLK
26 CKO
25 CKI
• Two still mode types :
3 fields period and 4 fields period
• External shutter control function with serial data
input is possible
VH3Ax 9
VH3Bx 10
V4x 11
OFDX 12
• +3 V and +4.5 V power supplies
• Package :
13 14 15 16 17 18 19 20 21 22 23 24
48-pin QFP (QFP048-P-0707) 0.5 mm pin-pitch
(QFP048-P-0707)
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in
catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
1
LR38616
BLOCK DIAGRAM
36
35
34
33
32
31
30
29
28
27
26
25
OSC
GATE
TST1
37
VCON
GND
RS
24
23
22
21
20
19
18
17
16
15
14
13
DATA LATCH & SHUTTER CONTROL
TST2
TVMD
VDD4
FH1
38
39
40
41
42
43
44
45
46
47
48
ACLX
VDD3
1/2
1/8
RESET
1/2
GND
FH2
FS
H COUNTER
FCDS
GND
ADCK
CLPX
BCPX
PBLK
GATE
RESET
RESET
VDD4
TST3
FR
DECODER
V COUNTER
STMD
SHTR
LEVEL
SHIFTER
1
2
3
4
5
6
7
8
9
10
11
12
2
LR38616
PIN DESCRIPTION
PIN NO. SYMBOL
I/O
POLARITY
PIN NAME
Control pulse output
for OFD voltage
Vertical transfer
pulse output 1
DESCRIPTION
A pulse to control OFD voltage.
1
2
OFDC
V1X
O3
A vertical transfer pulse for CCD.
Connect to V1X pin of vertical driver IC.
O3
O3
A pulse that transfers the charge of the photo-diode to
the vertical shift register.
Connect to VH1AX pin of vertical driver IC.
A pulse that transfers the charge of the photo-diode to
the vertical shift register.
Connect to VH1BX pin of vertical driver IC.
A vertical transfer pulse for CCD.
Connect to V2X pin of vertical driver IC.
Supply of +3.3 V power.
Readout pulse
output 1A
3
VH1AX
Readout pulse
output 1B
4
5
VH1BX
V2X
O3
O3
Vertical transfer
pulse output 2
Power supply
Ground
6
7
VDD3
GND
–
–
–
–
A grounding pin.
Vertical transfer
pulse output 3
A vertical transfer pulse for CCD.
8
V3X
O3
Connect to V3X pin of vertical driver IC.
A pulse that transfers the charge of the photo-diode to
the vertical shift register.
Connect to VH3AX pin of vertical driver IC.
A pulse that transfers the charge of the photo-diode to
the vertical shift register.
Readout pulse
output 3A
9
VH3AX
O3
Readout pulse
output 3B
10 VH3BX
11 V4X
O3
O3
Connect to VH3BX pin of vertical driver IC.
A vertical transfer pulse for CCD.
Vertical transfer
pulse output 4
Connect to V4X pin of vertical driver IC.
A pulse that sweeps the charge of the photo-diode for
the electronic shutter. Connect to OFD pin of CCD
through the vertical driver IC and DC offset circuit.
Held at H level at normal mode.
A pulse that corresponds to the cease period of the
horizontal transfer pulse.
A pulse to clamp the optical black signal.
12 OFDX
13 PBLK
14 BCPX
15 CLPX
O3
O3
O3
O3
OFD pulse output
Pre-blanking pulse
output
Optical black clamp This pulse stays high during the absence of
pulse output
effective pixels within the vertical blanking or the period
of sweep-out signal.
A pulse to clamp the dummy outputs of CCD signal.
This pulse stays high during the sweep-out period.
An output pin for AD converter.
Clamp pulse output
16 ADCK
17 GND
O6MA3
–
AD clock output
Ground
The output phase of ADCK is selected by serial data
step by 90˚.
A grounding pin.
–
3
LR38616
PIN NO. SYMBOL
I/O
POLARITY
PIN NAME
DESCRIPTION
A pulse to clamp the feed-through level from CCD.
The output phase of FCDS is selected by serial data.
A pulse to sample-hold the signal from CCD.
The output phase of FS is selected by serial data.
Supply of +3.3 V power.
An input pin for resetting all internal circuits at power on.
Connect to VDD through the diode and GND through the
capacitor.
18 FCDS
O6MA3
CDS pulse output 1
19 FS
O6MA3
–
CDS pulse output 2
Power supply
20 VDD3
–
–
21 ACLX
ICU3
All clear input
A pulse to sample-hold the signal.
The output phase of RS is selected by serial data.
A grounding pin.
An input pin to control internal vertical clock for long
shutter speed.
22 RS
O6MA3
–
S/H pulse output
Ground
23 GND
–
–
H level or open
L level
: VD
24 VCON
ICU3
VD control input
: VD is masked by the pulse which
is latched at the rising edge of VD.
It's necessary to be set SMD = high and number of the
fields data n ≥ 2 in serial data control at VCON operation.
An input pin for reference clock oscillation.
The frequency is 35.874 MHz.
An output pin for reference clock oscillation.
The output is the inverse of CKI (pin 25).
An output pin to generate HD and VD pulses.
The frequency is 17.937 MHz.
25 CKI
26 CKO
27 CLK
OSCI3
OSCO3
O6MA3
–
–
Clock input
Clock output
Clock output
An output pin for DSP IC. The frequency is 17.937 MHz.
The output phase of DCLK is selected by serial data
step by 90˚.
An input pin for reference of vertical pulse.
The length of low level is 9H.
28 DCLK
29 VD
O6MA3
IC3
Clock output
Vertical reference
pulse input
The period is following :
Still mode
: 656H
Monitoring mode : 262.5H
30 VDD3
31 GND
–
–
–
–
Power supply
Ground
Supply of +3.3 V power.
A grounding pin.
Horizontal drive
pulse input
An input pin for reference of horizontal pulse.
Connect to HD pin of DSP IC.
32 HD
IC3
An input pin for the strobe pulse, to control the functions
of LR38616. For details, see "Serial Data Control".
An input pin for the clock of the shift register, to control
the functions of LR38616. For details, see "Serial Data
Control".
33 ED0
ICSU3
–
–
Strobe pulse input
Shift register clock
input
34 ED1
ICSU3
4
LR38616
PIN NO. SYMBOL
I/O
POLARITY
PIN NAME
DESCRIPTION
An input pin for the data of the shift register, to control
the functions of LR38616. For details, see "Serial Data
Control".
Shift register data
input
35 ED2
ICSU3
–
Line index pulse
output
Test pin 1
The pulse is used in color separator.
36 ID
O3
The signal switches between high and low at every line.
A test pin. Set open or to L level in the normal mode.
A test pin. Set open or to L level in the normal mode.
37 TST1
38 TST2
ICD4
ICD4
–
–
Test pin 2
TV mode selection
input
Power supply
Horizontal transfer
pulse output 1
Ground
Horizontal transfer
pulse output 2
Power supply
Test pin 3
39 TVMD
40 VDD4
41 FH1
42 GND
43 FH2
ICD4
–
–
–
An input pin for TV mode selection.
Supply of +4.5 V power.
A horizontal transfer pulse for CCD.
Connect to ØH1 pin of CCD.
A grounding pin.
A horizontal transfer pulse for CCD.
Connect to ØH2 pin of CCD.
O6MA43
–
–
O6MA43
44 VDD4
45 TST3
–
ICD4
–
–
Supply of +4.5 V power.
A test pin. Set open or to L level in the normal mode.
A pulse to reset the charge of output circuit.
The output phase of FR is selected by serial data.
An input pin for setting the repetition to take the still
46 FR
O6MA43
Reset pulse output
Drive mode selection picture.
47 STMD
48 SHTR
ICU4
O3
–
input
H level or open
L level
: 4 fields period
: 3 fields period
Trigger output
A trigger pulse for effective signal period.
IC3
: Input pin (CMOS level)
O3 : Output pin (output high level is VDD3.)
ICU3
ICSU3
ICU4
ICD4
: Input pin (CMOS level with pull-up resistor)
: Input pin (CMOS level with schmitt-trigger)
: Input pin (CMOS level with pull-up resistor)
: Input pin (CMOS level with pull-down resistor)
O6MA3 : Output pin (output high level is VDD3.)
O6MA43 : Output pin (output high level is VDD4.)
OSCI3 : Input pin for oscillation
OSCO3 : Output pin for oscillation
5
LR38616
Serial Data Control
SERIAL DATA INPUT TIMING
ED0
ED1
...
D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31
ED2
D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11
The data is shifted at the rising edge of ED1, and is
latched at the rising edge of ED0.
PWSA is effective at the rising edge of ED0, but
others are effective at the horizontal line in which
VH1AX to VH3BX are active.
As all internal data are set to low level by ACLX or
PWSA, ED0 to ED1 should be input for desirable
operations.
As all internal data except PWSA are set to low
level by PWSA, ED0 to ED1 should be input for
desirable operations.
ED0 should be low level during data inputs of ED1
and ED2.
6
LR38616
SERIAL DATA INPUTS
DATA
D00-D06
D07
D08
D09
D10
D11
D12
NAME
FUNCTION
DATA = L DATA = H AT ACLX = L
SD0-SD6 Step of high speed shutter
SD7
SD8
–
–
–
All L
Number of exposed fields
All L
SD9
SMD
INMD
PWSA
Electronic shutter mode control
Integration mode control
Power save control
L
L
L
Monitoring
Normal
Still
Power save
Polarity control of FCDS, FS and
RS pulses
D13
PLCH
Negative
Positive
L
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
DUMMY Dummy
BCPCNT BCP control
–
–
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Uncontinuously Continuously
ML1
ML2
MR1
MR2
MR3
MC1
MC2
–
–
–
–
MC3
Phase control
MS1
MS2
MS3
MF1
MF2
MF3
MA1
MA2
–
–
7
LR38616
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply voltage
SYMBOL
VDD3, VDD4
VI3
RATING
–0.3 to 6.0
UNIT
V
V
V
V
V
˚C
˚C
–0.3 to VDD3 + 0.3
–0.3 to VDD4 + 0.3
–0.3 to VDD3 + 0.3
–0.3 to VDD4 + 0.3
–20 to +70
Input voltage
VI4
VO3
VO4
Output voltage
Operating temperature
Storage temperature
TOPR
TSTG
–55 to +150
ELECTRICAL CHARACTERISTICS
DC Characteristics
PARAMETER
(VDD3 = 3.0 V to VDD4, VDD4 = 4.2 to 5.5 V, TOPR = –20 to +70 ˚C)
SYMBOL
VIL3-1
CONDITIONS
MIN. TYP. MAX. UNIT NOTE
Input "Low" voltage
Input "High" voltage
Input "Low" voltage
Input "High" voltage
Hysteresis voltage
Input "Low" voltage
Input "High" voltage
Input "Low" current
Input "High" current
Input "Low" current
Input "High" current
Input "Low" current
Input "High" current
Input "Low" current
Input "High" current
Output "Low" voltage
Output "High" voltage
Output "Low" voltage
Output "High" voltage
Output "Low" voltage
Output "High" voltage
0.2VDD3
V
V
V
V
V
1, 2
3
VIH3-1
VIL3-2
VIH3-2
0.8VDD3
0.2VDD3
Schmitt-buffer
0.75VDD3
0.2VDD4
VT+ – VT–
VIL4
0.08VDD3
0.8VDD4
V
V
4, 5
1
VIH4
|IIL3-1|
|IIH3-1|
|IIL3-2|
|IIH3-2|
|IIL4-1|
|IIH4-1|
|IIL4-2|
|IIH4-2|
VOL3-1
VOH3-1
VOL3-2
VOH3-2
VOL4
VI = 0 V
VI = VDD3
VI = 0 V
VI = VDD3
VI = 0 V
1.0
1.0
30
2.0
60
2.0
2.0
60
µA
µA
µA
µA
µA
µA
µA
µA
V
2.0
4.0
2, 3
4
VI = VDD4
VI = 0 V
5
VI = VDD4
IOL = 2 mA
IOH = –1 mA
IOL = 3 mA
IOH = –3 mA
IOL = 10 mA
IOH = –10 mA
4.0
0.4
6
V
V
V
DD3 – 0.5
DD3 – 0.5
DD4 – 0.5
V
0.4
0.4
V
V
V
7
8
VOH4
V
NOTES :
1. Applied to inputs (IC3, OSCI3).
2. Applied to input (ICU3).
3. Applied to input (ICSU3).
4. Applied to input (ICU4).
5. Applied to input (ICD4).
6. Applied to output (O3).
7. Applied to outputs (OSCO3, O6MA3). (Output (OSCO3)
measures on condition that input (OSCI3) level is 0 V or
VDD3.)
8. Applied to output (O6MA43).
8
PACKAGES FOR CCD AND CMOS DEVICES
PACKAGE
(Unit : mm)
48 QFP (QFP048-P-0707)
±0.05
0.15
TYP.
±0.08
25
0.5
0.2
36
37
24
13
48
1
(1.0)
12
(1.0)
±0.2
±0.3
±0.2
7.0
9.0
0.65
1.45
±0.2
±0.1
0.1
9
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