S-34C02A01-T8T1G [SII]
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT; CMOS 2线串行E2PROM用于DIMM串行存在检测
| 型号： | S-34C02A01-T8T1G |
| 厂家： | 
SEIKO INSTRUMENTS INC |
| 描述： | 2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT |
| 文件： | 总34页 (文件大小：339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev.1.2_00
2-WIRE CMOS SERIAL E2PROM
FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
S-34C02A is a 2-wired serial E2PROM for DIMM Serial
Presence Detect which operates with low current
consumption and the wide range operation. The S-34C02A
has the capacity of 2K-bit and the organization of 256
words × 8-bit, is able to Page Write and Sequential Read.
S-34C02A has Hardware Protect and Software Protect.
Hardware Protect inhibits Write to all memory area by
connecting the WP pin to VCC. Software Protect inhibits
Write in 50% of the lower address (the address 00h to 7Fh)
in all memory area by inputting command when the WP pin
is connected to GND or left open.
Features
• Operating voltage range
Read:
Write:
1.6 to 5.5 V
1.7 to 5.5 V
• Page write:
16 bytes / page
• Sequential read
• Operation frequency:
• Noise filtering
400 kHz (VCC = 2.5 to 5.5 V)
Schmitt trigger and noise filter on bus input pins (SCL, SDA)
• Write protect function during low power supply
• Endurance:
106 cycles / word*1 (at +25°C)
*1. For each address (Word: 8 bits)
100 years (at +25°C)
• Data retention:
• Memory size
• Write Protect:
2K-bit
Hardware Protect 100% (addresses 00h to FFh)
Software Protect for the lower address of 50% (addresses 00h to 7Fh)
• Lead-free product
Package
Drawing code
Tape
FT008-E
Package name
8-Pin TSSOP
Package
FT008-A
Reel
FT008-E
Caution This product is intended to use in general electronic devices such as consumer electronics, office
equipment, and communications devices. Before using the product in medical equipment or
automobile equipment including car audio, keyless entry and engine control unit, contact to SII is
indispensable.
Seiko Instruments Inc.
1
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
Pin Configuration
8-Pin TSSOP
Top view
Table 1
Pin No.
Symbol
A0
A1
Description
1
2
3
4
5
6
Address input
VCC
WP
SCL
SDA
A0
A1
1
2
3
4
8
7
6
5
Address input
Address input
Ground
A2
A2
GND
GND
SDA
SCL
Serial data input / output
Serial clock input
Figure 1
Write protection input
7
WP
Connected to VCC
:
Protection valid
S-34C02A0I-T8T1G
Connected to GND: Protection invalid
Power supply
8
VCC
Remark See Dimensions for details of the package drawings.
2
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
Block Diagram
VCC
GND
WP
SCL
SDA
Start / Stop
Detector
Voltage Detector
High-Voltage Generator
Serial Clock
Controller
LOAD
Device Address
Comparator
COMP
LOAD INC
Data Register
Memory
Cell
Array
A2
A1
A0
R/W
Address
Counter
X Decoder
Y Decoder
Selector
Data Output
ACK Output
Controller
DIN
DOUT
Figure 2
Seiko Instruments Inc.
3
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
Absolute Maximum Ratings
Table 2
Item
Power supply voltage
Input voltage
Symbol
VCC
VIN
Absolute Maximum Rating
Unit
V
V
−0.3 to +7.0
−0.3 to +7.0
A0 High level Input voltage
Output voltage
Operation ambient temperature
Storage temperature
VHV
VOUT
Topr
−0.3 to +10.0
−0.3 to VCC+0.3
−40 to +85
V
V
°C
°C
Tstg
−65 to +150
Caution The absolute maximum ratings are rated values exceeding which the product could suffer
physical damage. These values must therefore not be exceeded under any conditions.
Recommended Operating Conditions
Table 3
Item
Symbol
VCC
Condition
Read Operation
Write Operation
VCC = 1.6 to 5.5 V
VCC = 1.6 to 5.5 V
Min.
1.6
1.7
Max.
5.5
5.5
VCC
0.3 × VCC
10.0
Unit
V
V
V
V
Power supply voltage
VIH
VIL
VHV
High level input voltage
Low level input voltage
A0 High level input voltage
0.7 × VCC
0.0
V
HV − VCC > 4.8 V
7.0
V
Pin Capacitance
Table 4
(Ta = 25°C, f = 1.0 MHz, VCC = 5 V)
Item
Symbol
CIN
CI / O
Condition
VIN = 0 V (SCL, A0, A1, A2, WP)
VI / O = 0 V (SDA)
Min.
−
−
Max.
10
10
Unit
pF
pF
Input capacitance
Input / output capacitance
Endurance
Table 5
Operation Ambient Temperature
+25°C
Item
Endurance
Symbol
NW
Min.
106
Max.
−
Unit
cycles / word*1
*1. For each address (Word: 8 bits)
Data Retention
Table 6
Operation Ambient Temperature
+25°C
Item
Data retention
Symbol
Min.
100
Max.
−
Unit
year
−
4
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
DC Electrical Characteristics
Table 7
VCC = 2.5 to 5.5 V VCC = 1.6 to 2.5 V VCC = 1.7 to 2.5 V
Item
Symbol Condition
Unit
f = 400 kHz
Min. Max.
0.8
4.0
f = 100 kHz
Min. Max.
0.2
f = 100 kHz
Min. Max.
0.2
1.5
Current consumption (READ)
Current consumption (WRITE)
ICC1
ICC2
−
−
−
−
−
−
−
mA
mA
−
−
Table 8
VCC = 2.5 to 5.5 V
VCC = 1.6 to 2.5 V
Item
Symbol
Condition
Unit
Min.
−
Max.
1.5
Min.
−
Max.
1.5
Standby current consumption
Input leakage current
ISB
ILI
VIN = VCC or GND
SCL, SDA
VIN = GND to VCC
SDA
VOUT = GND to VCC
A0, A1, A2, WP
VIN < 0.3 × VCC
A0, A1, A2, WP
VIN > 0.7 × VCC
A0, A1, A2, WP
VIN = 0.3 × VCC
A0, A1, A2, WP
VIN = 0.7 × VCC
IOL = 3.2 mA
µA
µA
−
−
1.0
1.0
50.0
2.0
−
−
−
1.0
1.0
50.0
2.0
−
Output leakage current
Input current 1
ILO
IIL
µA
µA
µA
KΩ
KΩ
−
−
Input current 2
IIH
−
−
Input Impedance 1
Input Impedance 2
ZIL
ZIH
30
800
30
800
−
−
Low level output voltage
Current address hold voltage
VOL
VAH
−
1.5
0.4
5.5
−
1.5
0.4
2.5
V
V
−
Seiko Instruments Inc.
5
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
AC Electrical Characteristics
VCC
Table 9 Measurement Conditions
Input pulse voltage
0.1 × VCC to 0.9 × VCC
20 ns
0.5 × VCC
100 pF+Pull-up resistor 1.0 kΩ
Input pulse rising / falling time
Output determination voltage
Output load
R = 1.0 kΩ
SDA
C = 100 pF
Figure 3 Output Load Circuit
Table 10
VCC = 2.5 to 5.5 V
VCC = 1.6 to 2.5 V
Item
Symbol
Unit
Min.
0
Max.
400
−
−
0.9
−
−
−
−
−
Min.
0
Max.
100
−
−
3.5
−
−
−
−
−
SCL clock frequency
SCL clock time “L”
SCL clock time “H”
fSCL
kHz
µs
µs
µs
ns
µs
µs
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
ns
tLOW
tHIGH
tAA
1.3
0.6
0.1
50
0.6
0.6
100
0
0.6
−
−
0
0
4.7
4.0
0.1
100
4.7
4.0
200
0
4.0
−
−
0
0
SDA output delay time
SDA output hold time
Start condition setup time
Start condition hold time
Data input setup time
Data input hold time
Stop condition setup time
SCL y SDA rising time
SCL y SDA falling time
WP setup time
tDH
tSU.STA
tHD.STA
tSU.DAT
tHD.DAT
tSU.STO
tR
−
−
0.3
0.3
−
−
−
−
−
50
1.0
0.3
−
−
−
−
−
100
tF
tWS1
tWH1
tWS2
tWH2
tBUF
WP hold time
WP release setup time
WP release hold time
Bus release time
0
0
1.3
−
0
0
4.7
−
Noise suppression time
tI
tHIGH
tLOW
tR
tF
SCL
tHD.DAT
tSU.DAT
tSU.STA
tHD.STA
tSU.STO
SDA
(in)
tAA
tDH
tBUF
SDA
(out)
Figure 4 Bus Timing
6
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
Table 11
VCC = 1.7 to 5.5 V
Item
Write time
Symbol
tWR
Unit
ms
Min.
−
Max.
4.0
Acknowledment
Signal
Stop Condition
Start Condition
Start Condition
Write Data
tWR
SCL
SDA
D0
tWS1
tWH1
WP (valid)
WP (invalid)
tWH2
tWS2
Figure 5 Write Cycle Timing
Seiko Instruments Inc.
7
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
Pin Functions
1. A0, A1 and A2 (Address Input) Pins
In the S-34C02A, to set the slave address, connect each pin of A0, A1, A2 to GND or VCC. Therefore the users can set
8 types of slave address by a combination of A0, A1, A2 pins.
Comparing the slave address transmitted from the master device and one that you set, makes possible to select the S-
34C02A from other devices connected onto the bus.
Be sure to connect to fix the address input pin to GND or VCC
.
2. SDA (Serial Data Input / Output) Pin
The SDA pin is used for the bi-directional transmision of serial data. It consists of a signal input pin and an Nch open
drain output pin.
In use, generally, connect the SDA line to any other device which has the open-drain or open-collector output with
Wired-OR connection by pulling up to VCC by a resistor.
3. SCL (Serial Clock Input) Pin
The SCL pin is used for the serial clock input. Since the signals are processed at a rising or falling edge of the SCL
clock, pay the attention to the rising and falling time and comply with the specification.
4. WP (Write Protect) Pin
The Write protect function is to inhibit Write in all memory area or in the protect register while this pin is being
connected to VCC. While the WP pin is being connected to GND or left open, this pin inhibits Write in the first half of
memory (addresses 00h to 7Fh) according to the status of the protect register.
8
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
Operation
1. Start Condition
A start condition starts by changing the SDA line from “H” to “L” while the SCL line is “H”.
All operations start with a start condition.
2. Stop Condition
A stop condition starts by changing the SDA line from “L” to “H” while the SCL line is “H”.
During Read sequence if the S-34C02A receives a stop condition, its Read operation is interrupted so that the S-
34C02A goes in the standby mode.
During Write sequence if the S-34C02A receives a stop condition, the S-34C02A finishes installing Write data so that
the Write operation starts.
tSU.STA tHD.STA
tSU.STO
SCL
SDA
(in)
Start Condition
Figure 6 Start / Stop Conditions
Stop Condition
Seiko Instruments Inc.
9
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
3. Data Transmission
Data is transmitted by changing the SDA line while the SCL line is “L”.
If the SDA line changes while the SCL line is “H”, the S-34C02A goes in the start or stop condition status.
tSU.DAT
tHD.DAT
SCL
SDA
(in)
Figure 7 Data Transmission Timing
4. Acknowledgment
Data is transmitted sequentially in 8-bit. Changing the SDA line to “L” indicates that the devices on the system bus
have received data, thus the devices send an acknowledgment signal back during the 9th clock of cycle.
The S-34C02A does not send an acknowledgment signal back during the Write operation.
SCL
1
8
9
SDA
(in)
Acknowledgement
Output
SDA
(out)
Start Condition
tAA
tDH
Figure 8 Acknowledgment Output Timing
10
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
5. Device Addressing
To start the transmission, the master device on the system generates a start condition for the slave address. After that,
the master device transmits the 7-bit device address and the 1-bit Read/Write instruction code to the SDA bus.
In the S-34C02A, the higher 4 bits of the device address are device cord, and are fixed at “1010”.
The next 3 bits of the device address are slave address. This address is used to select the devices on the system bus,
and is compared with the address value which is set beforehand by the address input pins (A0, A1, A2). If the
comparison result matches, the slave address sends an acknowledgment signal back at the 9th clock of cycle.
Device Code
Slave Address
A1
1
0
1
0
A2
A0
R / W
LSB
MSB
Figure 9 Device Address
Seiko Instruments Inc.
11
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
6. Write Operation
6. 1 Byte Write
When the S-34C02A receives the 7-bit device address and the Read/Write instruction cord “0” after receiving a start
condition, it generates an acknowledgment signal.
Next, it receives the 8-bit word address, and generates an acknowledgment signal. After that, it receives 8-bit Write
data and generates an acknowledgment signal, it receives a stop condition so that the Write operation to the
specified memory address starts.
During the Write operation to the S-34C02A, all operations are inhibited to be performed and S-34C02A does not
send back an acknowledgment signal.
W
R
I
S
T
A
R
T
S
T
T
E
O
P
DEVICE
ADDRESS
DATA
WORD ADDRESS
1
0 1 0
A2 A1 A0
0
SDA LINE
W7 W6 W5 W4 W3 W2 W1 W0
D7 D6 D5 D4 D3 D2 D1 D0
M
S
B
L R
A
C
K
A
C
A
C
K
S
B
/
W
K
ADR INC
(ADDRESS INCREMENT)
Figure 10 Byte Write
12
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
6. 2 Page Write
The S-34C02A is able to Page Write of 16-bit.
Its basic process to transmit data is as same as Byte Write, but it operates Page Write by sequentially receiving 8-
bit Write data as much data as the page size has.
When the S-34C02A receives the 7-bit device address and Read/Write instruction code “0” after receiving a start
condition, it generates an acknowledgment signal. Next, by receiving the 8-bit word address, it generates an
acknowledgment signal. After the S-34C02A generated an acknowledgment signal by receiving 8-bit Write data, the
S-34C02A receives 8-bit Write data equivalent to the next word address so that it generates an acknowledgment
signal. Receiving 8-bit Write data and generating an acknowledgment signal are sequentially repeated, so that S-
34C02A can receive Write data which has the largest page size.
By receiving a stop condition, the Write operation in an address area equivalent to the received page size starts.
S
T
A
R
T
W
S
T
R
I
O
P
T
E
DEVICE
DATA (n+1)
DATA (n+x)
DATA (n)
WORD ADDRESS (n)
ADDRESS
SDA
LINE
D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
0
W7W6W5W4W3W2W1W0
D7
D0
D7
D0
A2 A1 A0
0
M
S
B
R A
/ C
L
S
B
A
C
K
A
C
K
A
C
K
A
C
K
K
W
ADR INC
Figure 11 Page Write
ADR INC
ADR INC
In the S-34C02A, the lower 4 bits of the word address are automatically incremented every time when the S-
34C02A receives 8-bit write data. If the size of Write data exceeds 16-byte, the higher 4-bit of the word address
remain unchanged, and the lower 4 bits are rolled over and previously received data will be overwritten.
Seiko Instruments Inc.
13
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
6. 3 Hardware Write Protect
Write protect is available in the S-34C02A.
When the WP pin is connected to VCC, the Write operation in all memory area is inhibited.
Fix the WP pin during the period from the start condition to the stop condition in the Write operation (Byte Write and
Page Write). Written data in the address is not assurable if the condition of the WP pin is changed during this
period. Refer to Figure 5 regarding the timing of Hardware Write Protect.
Be sure to connect the WP pin to GND when you don’t use Hardware Write Protect. Hardware Write Protect is valid
in the range of power supply voltage. If setting Hardware Write Protect valid, the S-34C02A does not generate an
acknowledgment signal.
In this case, the users cannot perform the SWP (Set RSWP), CWP (Clear RSWP), PSWP (Set PSWP) instructions.
6. 4 Software Write Protect
The S-34C02A has Permanent Software Write Protect (PSWP) and Reversible Software Write Protect (RSWP).
(1) PSWP
If the software protect has been set with the PSWP instruction, 50% of the lower address (addresses 00h to 7Fh)
in all memory is permanently Write-protected. This Write protect cannot be cleared by any instruction, or by
power-cycling the device, and regardless the state of WP pin. Also, once the PSWP instruction has been
successfully excuted, the S-34C02A no longer acknowledges any instruction (device code of “0110”) to access
the Write protect setting.
(2) RSWP
If the software protect has been set with the SWP (Set RSWP) instruction, 50% of the lower address (addresses
00h to 7Fh) in all memory is Write-protected. This write protect can be cleared with the CWP (Clear RSWP)
instruction.
These two instructions have the same format as a Byte Write instruction, but have a different device code. Like
the Byte Write instruction, it is followed by an address byte and a data byte, but in this case the contents can be
set in all “Don’t Care”. In the instructions of SWP and CWP, be sure to apply the high voltage of VHV to the A0
pin, and input “H” or “L” to the A1 and A2 pins.
W
R
I
S
T
A
R
T
S
T
T
E
O
P
DEVICE
ADDRESS
DATA
WORD ADDRESS
0
1
1 0
A2 A1 A0
0
SDA LINE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
M
S
B
L
S
B
R
/
W
A
C
K
A
C
K
A
C
K
X : Don't care
Figure 12 Software Write Protect
Table 12 Device Select Code
Device code
Slave address
Pin condition
R / W
B0
Instruction
B7
B6
B5
B4
B3
A2
0
B2
A1
0
B1
A0
1
1
A2
A1
A0
Memory Area Select *1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
A2
VSS
VSS
A2
VSS
VSS
A2
A1
VSS
VCC
A1
VSS
VCC
A1
A0
VHV
VHV
A0
VHV
VHV
A0
R / W
Set RSWP（SWP)
Clear RSWP（CWP)
Set PSWP（PSWP)*1
Read SWP
0
0
0
1
1
1
0
1
A2
0
0
A1
0
1
A0
1
1
Read CWP
Read PSWP*1
A2
A1
A0
*1. Slave addresses A2, A1, A0 are compared by the address input pins (A0, A1, A2) of a memory device with the address
value which is set beforehand.
14
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
Table 13 Acknowledgment for WRITE Instruction(R / W bit = 0)
ACK
Word
ACK
ACK
Status
WP
Instruction
DATA
Don’t care
DATA
Write
No
output
Address
output
output
Permanent
SWP, CWP or PSWP
Page or Byte Write in
Lower 128 bytes
SWP
CWP
PSWP
Page or Byte Write in
Lower 128 bytes
SWP
No
Don’t care
No
No
X
Software Write
Protect (PSWP)
Yes
Address
Yes
No
No
No
Yes
Yes
Don’t care
Don’t care
Don’t care
No
Yes
Yes
Don’t care
Don’t care
Don’t care
No
Yes
Yes
No
Yes
Yes
0
1
Reversible
Software Write
Protect (RSWP)
Yes
Address
Yes
DATA
No
No
No
Don’t care
Don’t care
Don’t care
Address
No
Don’t care
Don’t care
Don’t care
DATA
No
No
No
No
No
CWP
PSWP
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Page or Byte Write
SWP, CWP or PSWP
Page or Byte Write
SWP, CWP or PSWP
Page or Byte Write
No
Don’t care
Address
Don’t care
Address
Don’t care
DATA
Don’t care
DATA
Yes
Yes
No
Yes
Yes
No
0
1
No software protect
No
No
Table 14 Acknowledgment for READ Instruction(R / W bit = 1)
ACK
Word
Address
ACK
output
ACK
output
Status
Instruction
DATA
output
Permanent Software Write
Protect (PSWP)
SWP, CWP or PSWP
No
Don’t care
No
Don’t care
No
SWP
CWP
PSWP
No
Don’t care
Don’t care
Don’t care
Don’t care
No
No
No
No
Don’t care
Don’t care
Don’t care
Don’t care
No
No
No
No
Reversible Software Write
Protect (RSWP)
Yes
Yes
Yes
No software protect
SWP, CWP or PSWP
Seiko Instruments Inc.
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2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
6. 5 Acknowledge Polling
Acknowledge polling is used to find when the Write operation has completed. After receiving a stop condition the
Write operation has once started, all operations are inhibited to be performed so that the S-34C02A cannot respond
to the signals transmitted from the master device. The master device sends a start condition, the device address
and Read/Write instruction code to the S-34C02A (slave address), and detects the response from the slave
address. It is possible to find when the Write operation has completed. Thus if the slave device does not send an
acknowledgment signal back, the Write operation is in progress. If it sends an acknowledgment signal back, the
Write operation has completed. Fix the WP pin until an acknowledgment is confirmed. It is recommended to use the
Read instruction “1” for the Read/Write instruction code transmitted by the master device during acknowledgment
polling.
16
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
7. Read
7. 1 Current Address Read
Both in the Write and Read operation, the S-34C02A maintains the memory address that is one the S-34C02A
received when it has accessed last time. The memory address is maintained unless the power supply voltage is
equal to the current address hold voltage VAH or less. Therefore as long as the master device acknowledges the
position where the address pointer is, data can be read by the memory address of an address pointer without
specifying the word address. This is the current address Read.
The following is about the case that an address counter in the S-34C02A is in “n”.
When the S-34C02A receives the 7-bit device address and the Read/Write instruction code “1” after receiving a
start condition, it generates an acknowledgment signal.
Next, 8-bit data at address n is input from the S-34C02A synchronizing with a SCL clock. At the same time an
address counter is incremented at a falling edge of SCL clock right after the output of 8th bit data, so that address
n+1 is contained in an address counter. The Read operation ends when the master device outputs a stop condition,
not an acknowledgment signal.
NO ACK from
Master Device
S
T
A
R
T
R
E
A
D
S
T
O
P
DEVICE
ADDRESS
DATA
SDA LINE
1
0
1
0
A2 A1 A0
1
D7 D6 D5 D4 D3 D2 D1 D0
M
S
B
L
S
B
R
/
W
A
C
K
ADR INC
Figure 13 Current Address Read
Regarding the recognition of address pointer, pay the attention to the following;
In the Read operation, a memory address counter in the S-34C02A is automatically incremented every time at a
falling edge of the SCL clock right after the output of 8th bit data. However, in the Write operation, a memory
address counter is not be incremented because the higher 4 bits of the memory address (the higher 4 bits of the
word address) are fixed every time at a falling edge of the SCL clock right after the receipt of 8th bit data.
Seiko Instruments Inc.
17
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
7. 2 Random Read
Random Read is used to read data at an arbitrary memory address.
To load the memory address into an address counter in the S-34C02A, perform Dummy Write with the process
below.
When the S-34C02A receives the 7-bit device address and the Read/Write instruction code “0” after receiving a
start condition, it generates an acknowledgment signal. After that, it generates an acknowledgment signal by
receiving the 8-bit word address. By these operations, the memory address is loaded into the address counter in the
S-34C02A.
After this, in Byte Write and Page Write, the S-34C02A receives Write data, but in Dummy Write, the S-34C02A
does not receive data.
Since the memory address has been loaded into the memory address counter by Dummy Write, the master device
sends a start condition newly and performs the same operation as current Read. The users can read data which
starts from the arbitrary memory address.
Thus, the S-34C02A receives the 7-bit device address and the Read/Write instruction cord “1” after receiving a start
condition, it generates an acknowledgment signal.
And 8-bit data is output from the S-34C02A synchronizing with the SCL clock. After that, the Read operation ends
when the master device transmits a stop condition, not an acknowledgment signal.
W
R
I
S
T
A
R
T
S
T
A
R
T
NO ACK from
Master Device
S
T
R
E
A
D
T
E
O
P
DEVICE
DEVICE
ADDRESS
WORD ADDRESS (n)
ADDRESS
DATA
SDA
LINE
1
0
1
0 A2 A1 A0
0
1
0
1
0
A2 A1 A0
1
W7 W6 W5 W4 W3 W2 W1 W0
D7 D6 D5 D4 D3 D2 D1 D0
M
S
B
L R A
M
S
B
L R A
A
C
K
S /
B
C
K
S /
B
C
K
W
W
ADR INC
DUMMY WRITE
Figure 14 Random Read
18
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
7. 3 Sequential Read
Both in current Read and random Read, when the S-34C02A receives the 7-bit device address and Read/Write
instruction code “1” after receiving a start condition, it generates an acknowledgment signal.
When 8-bit data is output from the S-34C02A synchronizing with the SCL clock, an memory address counter in the
S-34C02A is automatically incremented at a falling edge of SCL clock right after the output of 8th bit data.
After that, the master device transmits an acknowledgment signal, the next data in the memory data address is
output. A memory address counter in the S-34C02A is incremented because the master device transmits an
acknowledge signal, so that S-34C02A keeps reading data sequentially. This is sequential read.
The Write operation ends when the master device transmits a stop condition, not an acknowledgment signal.
Although S-34C02A can read data sequentially in this sequential read, if a memory address counter reaches the
last word address, it rolls over to the first memory address.
NO ACK from
Master Device
S
T
R
E
A
D
A
C
K
A
C
K
A
C
K
O
P
DEVICE
ADDRESS
SDA
LINE
D7
D0
D7
D0
D7
D0
1
D7
D0
R A
/ C
DATA (n+1)
DATA (n+2)
DATA (n+x)
DATA (n)
K
W
ADR INC
ADR INC
ADR INC
ADR INC
Figure 15 Sequential Read
Seiko Instruments Inc.
19
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
8. Address Increment Timing
In the Read operation, the timing when a memory address counter is automatically incremented is at a falling edge of
the SCL clock right after the output of 8th bit.
In the Write operation, that timing is at a falling edge of the SCL clock when installing the 8th bit data.
SCL
8
9
1
8
9
SDA
ACK Output
R / W = 1
D7 Output
D0 Output
Address Increment
Figure 16 Address Increment Timing in Reading
SCL
SDA
8
9
1
8
9
R / W = 0
ACK Output
D7 Inpit
D0 Inpit
ACK Output
Address Increment
Figure 17 Address Increment Timing in Writing
Write Inhibition Function at Low Power Voltage
The S-34C02A has a built-in detection circuit which operates with the low power supply voltage, cancels Write when
the power supply voltage drops and power-on. Its detection and release voltages are 1.20 V typ. (Refer to Figure 18).
The S-34C02A cancels Write by detecting a low power supply voltage when it receives a stop condition.
In the data trasmission and the Write operation, data in the address written during the low power supply voltage is not
assurable.
Power Supply Voltage
Detection Voltage (−VDET
1.20 V Typ.
)
Release Voltage (+VDET
1.20 V Typ.
)
Write Instruction cancel
Figure 18 Operation at Low Power Voltage
20
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
Using S-34C02A
1. SDA I/O pin and SCL input pin
In consideration of I2C-bus protocol function, the SDA I/O and SCL input pins*1 should be connected with a pull-up
resister of 1 to 5 kΩ.
The S-34C02A cannot transmit normally without using a pull-up resistor.
*1. In the case that the SCL input pin of the S-34C02A is connected to the tri-state output pin in the master device,
connect the SCL pin with a pull-up resistor as well in order not to set the SCL input pin in high impedance. This
prevents the S-34C02A from error caused by an uncertain output (high impedance) from the tri-state pin when
resetting the master device during the voltage drop.
2. Equivalent circuit of I/O pin
Each input pin (A0, A1, A2, WP) of the S-34C02A has a built-in pull-down register. The SDA line has an open-drain
output. The followings are equivalent circuits of the pins.
SCL
Figure 19 SCL Pin
SDA
Figure 20 SDA Pin
Seiko Instruments Inc.
21
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
WP
Figure 21 WP Pin
A0, A1, A2
Figure 22 A0, A1, A2 Pin
22
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
3. Phase adjustment during S-34C02A access
The S-34C02A does not have a pin to reset (the internal circuit). The users cannot forcibly reset it externally. If the
communication to the S-34C02A interrupted, the users need to handle it as you do for software.
Although the reset signal is input to the master device, the S-34C02A’s internal circuit does not go in reset, but it does
by inputting a stop condition to the S-34C02A. The S-34C02A keeps the same status thus cannot do the next
operation. Especially, this case is correspond to that only the master device is reset when the power supply voltage
drops.
If the power supply voltage restored in this status, input the instruction after resetting (adjusting the phase with the
master device) the S-34C02A. How to reset is shown below.
[How to reset S-34C02A]
The S-34C02A is able to be reset by a start and stop instructions. When the S-34C02A is reading data “0” or is
outputting the acknowledgment signal, outputs “0” to the SDA line. In this status, the master device cannot output
an instruction to the SDA line. In this case, terminate the acknowledgment output operation or the Read operation,
and then input a start instruction. Figure 23 shows this procedure.
First, input a start condition. Then transmit 9 clocks (dummy clock) of SCL. During this time, the master device sets
the SDA line to “H”. By this operation, the S-34C02A interrupts the acknowledgment output operation or data
output, so input a start condition*1. When a start condition is input, the S-34C02A is reset. To make doubly sure,
input the stop condition to the S-34C02A. The normal operation is then possible.
Start
Condition
Start
Condition
Stop
Condition
Dummy Clock
1
2
8
9
SCL
SDA
Figure 23 Resetting S-34C02A
*1. After 9 clocks (dummy clock), if the SCL clock contuniues to being output without inputting a start condition, S-
34C02A may go in the Write operation when it receives a stop condition. To prevent this, input a start condition
after 9 clock (dummy clock).
Remark Regarding this reset procedure with dummy clock, it is recommended to perform at the system
initialization after applying the power supply voltage.
Seiko Instruments Inc.
23
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
4. Acknowledge check
The I2C-bus protocol includes an acknowledge check function as a handshake function to prevent a communication
error. This function allows detection of a communication failure during data communication between the master device
and S-34C02A. This function is effective to prevent malfunction, so it is recommended to perform an acknowledge
check with the master device.
5. Built-in power-on-clear circuit
The S-34C02A has a built-in power-on-clear circuit that initializes itself at the same time during power-on.
Unsuccessful initialization may cause a malfunction. To operate the power-on-clear circuit normally, the following
conditions must be satisfied to raise the power supply voltage.
5. 1 Raising power supply voltage
Shown in Figure 24, raise the power supply voltage from 0.2 V max., within the time defined as tRISE which is the
time required to reach the power supply voltage to be set.
For example, if the power supply voltage is 5.0 V, tRISE = 200 ms seen in Figure 25. The power supply voltage must
be raised within 200 ms.
tRISE (Max.)
Power Supply Voltage (VCC
)
VINIT (Max.)
0.2 V
0 V*1
tINIT*2 (Max.)
*1. 0 V means there is no difference in potential between the VCC pin and the GND pin of the S-34C02A.
*2. tINIT is the time required to initialize the S-34C02A. No instructions are accepted during this time.
Figure 24 Raising Power Supply Voltage
24
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
5.0
4.0
Power Supply Voltage (VCC
[V]
)
3.0
2.0
50
100 150
200
Rise Time (tRISE) Max.
[ms]
For example: If the supply voltage = 5.0 V, raise the power supply voltage to 5.0 V within 200 ms.
Figure 25 Rise Time of Power Supply Voltage
When initialization is successfully completed by the power-on-clear circuit, the S-34C02A enters the standby status.
If the power-on-clear circuit does not operate, the followings are the possible causes.
(1) Because the S-34C02A has not completed initialization, an instruction previously input is still valid or an instruction
may be inappropriately recognized. In this case, S-34C02A may perform the Write operation.
(2) The voltage drops due to power off while the S-34C02A is being accessed. Even if the master device is reset due
to the low power voltage, the S-34C02A may malfunction unless the power-on-clear operation conditions of S-
34C02A are satisfied. For the power-on-clear operation conditions of the S-34C02A, refer to 5.1 Raising power
supply voltage.
If the power-on-clear circuit does not operate, match the phase (reset) so that the S-34C02A’s internal circuit is normally
reset. The statuses of the S-34C02A immediately after the power-on-clear circuit operation and when phase is matched
(reset) are the same.
Seiko Instruments Inc.
25
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
5. 2 Initialization time
The S-34C02A initializes at the same time when the power supply voltage is raised. Input instructions to the S-
34C02A after initialization. S-34C02A does not accept any instruction during initialization.
Figure 26 shows the initialization time of the S-34C02A.
100 m
10 m
S-34C02A
1.0 m
Initialization Time
(tINIT) Max.
[s]
100 µ
10 µ
1.0 µ
1.0 µ 10 µ 100 µ 1.0 m 10 m 100 m
Rise Time (tRISE
[s]
)
Figure 26 Initialization Time of S-34C02A
26
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
6. Data hold time (tHD.DAT = 0 ns)
If SCL and SDA of the S-34C02A are changed at the same time, it is necessary to prevent a start/stop condition from
being mistakenly recognized due to the effect of noise. If a start/stop condition is mistakenly recognized during
communication, the S-34C02A enters the standby status.
In the S-34C02A, it is recommended to set the delay time of 0.3 µs minimum from a falling edge of SCL for the SDA.
This is to prevent S-34C02A from going in a stop/start condition due to the time lag caused by the load of the bus line.
tHD.DAT = 0.3 µs Min.
SCL
SDA
Figure 27 S-34C02A Data Hold Time
7. SDA pin and SCL pin noise suppression time
The S-34C02A includes a built-in low-pass filter at the SDA and SCL pins to suppress noise. This means that if the
power supply voltage is 5.0 V, noise with a pulse width of 160 ns or less can be suppressed.
For details of the assurable value, refer to noise suppression time (tl) in Table 10.
300
Noise Suppression Time (tI) Max.
[ns]
200
100
2
3
4
5
Power Supply Voltage (VCC
[V]
)
Figure 28 Noise Suppression Time for SDA and SCL Pins
Seiko Instruments Inc.
27
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
8. S-34C02A Operation when inputting a stop condition with the clock less than the defined data
length (less than 8-bit) to the SCL pin inputting Write data
If S-34C02A forcibly recieves a stop condition while it is receiving Write data of 1-byte, it does not perform the Write
operation.
To operate Page Write, if S-34C02A recieves a stop condition after receiving data of 1-byte or more, S-34C02A
operates Write only in the address equivalent to the byte of which S-34C02A normally received 8-bit data before a
stop condition.
9. S-34C02A Operation and data if inputting Write data more than the defined Page Size during Page
Write
The S-34C02A is able to Page Write of 16-byte, but in case if it receives data of 17-byte, 8-bit data of the 17th byte is
overwritten in the first byte in the same page because the S-34C02A cannot Write data across the page address.
10. Precaution for use
Absolute maximum ratings: Do not operate these ICs in excess of the absolute maximum ratings (as listed on the
data sheet). Exceeding the supply voltage rating can cause latch-up.
Operations with moisture on the E2PROM pins may occur malfunction by short-circuit between pins. Especially, in
occasions like picking the E2PROM up from low temperature tank during the evaluation. Be sure that not remain frost
on the E2PROM pin to prevent malfunction by short-circuit.
Also attention should be paid in using on environment, which is easy to dew for the same reason.
28
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
Precautions
● Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
● SII claims no responsibility for any and all disputes arising out of or in connection with any infringement of the
products including this IC upon patents owned by a third party.
Seiko Instruments Inc.
29
2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
Product Name Structure
1. 8-Pin TSSOP Package
S-34C02A
0
I
-
xxxx
G
Package name (abbreviation) and IC packing specifications
T8T1 : 8-Pin TSSOP, Tape
Operating temperature
I : +85 °C
Fixed
Product name
S-34C02A : 2K-bit
30
Seiko Instruments Inc.
+0.3
-0.2
3.00
5
8
1
4
0.17±0.05
0.2±0.1
0.65
No. FT008-A-P-SD-1.1
TSSOP8-E-PKG Dimensions
FT008-A-P-SD-1.1
TITLE
No.
SCALE
UNIT
mm
Seiko Instruments Inc.
4.0±0.1
2.0±0.05
ø1.55±0.05
0.3±0.05
+0.1
-0.05
8.0±0.1
ø1.55
(4.4)
+0.4
-0.2
6.6
8
1
4
5
Feed direction
No. FT008-E-C-SD-1.0
TITLE
TSSOP8-E-Carrier Tape
FT008-E-C-SD-1.0
No.
SCALE
UNIT
mm
Seiko Instruments Inc.
13.4±1.0
17.5±1.0
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.5
No. FT008-E-R-SD-1.0
TSSOP8-E-Reel
FT008-E-R-SD-1.0
TITLE
No.
SCALE
UNIT
QTY.
3,000
mm
Seiko Instruments Inc.
·
·
The information described herein is subject to change without notice.
Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein
whose related industrial properties, patents, or other rights belong to third parties. The application circuit
examples explain typical applications of the products, and do not guarantee the success of any specific
mass-production design.
·
·
·
When the products described herein are regulated products subject to the Wassenaar Arrangement or other
agreements, they may not be exported without authorization from the appropriate governmental authority.
Use of the information described herein for other purposes and/or reproduction or copying without the
express permission of Seiko Instruments Inc. is strictly prohibited.
The products described herein cannot be used as part of any device or equipment affecting the human
body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus
installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc.
Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the
failure or malfunction of semiconductor products may occur. The user of these products should therefore
give thorough consideration to safety design, including redundancy, fire-prevention measures, and
malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.
·
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