S-93C46CD0I-T8T1U3 [SII]
3-WIRE SERIAL E2PROM;
| 型号： | S-93C46CD0I-T8T1U3 |
| 厂家： | 
SEIKO INSTRUMENTS INC |
| 描述： | 3-WIRE SERIAL E2PROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总39页 (文件大小：2058K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S-93C46C/56C/66C/76C/86C
3-WIRE SERIAL E2PROM
www.sii-ic.com
© SII Semiconductor Corporation, 2016
Rev.1.1_00
This IC is a high speed, low current consumption, 3-wire serial E2PROM with a wide operating voltage range. This IC has the
capacity of 1 K-bit, 2 K-bit, 4 K-bit, 8 K-bit and 16 K-bit, and the organization is 64 words × 16-bit, 128 words × 16-bit,
256 words × 16-bit, 512 words × 16-bit and 1024 words × 16-bit, respectively. Sequential read is available, at which time
addresses are automatically incremented in 16-bit blocks. The communication method is by the Microwire bus.
Caution This product is intended to use in general electronic devices such as consumer electronics, office
equipment, and communications devices. Before using the product in medical equipment or automobile
equipment including car audio, keyless entry and engine control unit, contact to SII Semiconductor
Corporation is indispensable.
Features
Packages
•
8-Pin SOP (JEDEC)
• Memory capacity
S-93C46C:
1 K-bit (64-word × 16-bit)
2 K-bit (128-word × 16-bit)
4 K-bit (256-word × 16-bit)
8 K-bit (512-word × 16-bit)
16 K-bit (1024-word × 16-bit)
5
S-93C56C:
S-93C66C:
8
4
S-93C76C:
S-93C86C:
1
• Operation voltage range
Read:
1.6 V to 5.5 V
1.8 V to 5.5 V
2.0 MHz max.
4.0 ms max.
(5.0 × 6.0 × t1.75 mm)
Write:
• Operation frequency:
• Write time:
• Sequential read
• Write protect function during the low power supply voltage
• Function to protect against write due to erroneous instruction recognition
•
8-Pin TSSOP
5
8
4
106 cycle / word*1 (Ta = +85°C)
100 years (Ta = +25°C)
50 years (Ta = +85°C)
FFFFh
1
• Endurance:
• Data retention:
(3.0 × 6.4 × t1.1 mm)
• Initial delivery state:
• Operation temperature range: Ta = −40°C to +85°C
• Lead-free (Sn 100%), halogen-free
•
TMSOP-8
5
8
4
*1. For each address (Word: 16-bit)
1
(2.9 × 4.0 × t0.8 mm)
•
SNT-8A
5
4
1
8
(2.5 × 2.0 × t0.5 mm)
1
3-WIRE SERIAL E2PROM
S-93C46C/56C/66C/76C/86C
Rev.1.1_00
Block Diagram
VCC
GND
Address
decoder
Memory array
DO
Data register
Output buffer
DI
Mode decode logic
CS
Clock pulse
monitoring circuit
Voltage detector
SK
Clock generator
2
3-WIRE SERIAL E2PROM
Rev.1.1_00
S-93C46C/56C/66C/76C/86C
Product Name Structure
1. Product name
S-93CxxC
x
0
I
-
xxxx
U
3
Environmental code
U: Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specification*1
J8T1: 8-Pin SOP (JEDEC), Tape
T8T1: 8-Pin TSSOP, Tape
K8T3: TMSOP-8, Tape
I8T1:
SNT-8A, Tape
Operation temperature
I: Ta = −40°C to +85°C
Fixed
Pin assignment
D:
8-Pin SOP (JEDEC)
8-Pin TSSOP
TMSOP-8
SNT-8A
R:
8-Pin SOP (JEDEC) (Rotated)*2
Product name
S-93C46C:
S-93C56C:
S-93C66C:
S-93C76C:
S-93C86C:
1 K-bit
2 K-bit
4 K-bit
8 K-bit
16 K-bit
*1. Refer to the tape drawing
*2. S-93C46C/56C/66C only
2. Packages
Package Name
Dimension
Tape
Reel
Land
8-Pin SOP (JEDEC)
8-Pin TSSOP
TMSOP-8
FJ008-Z-P-SD
FT008-Z-P-SD
FM008-A-P-SD
PH008-A-P-SD
FJ008-Z-C-SD
FT008-Z-C-SD
FM008-A-C-SD
PH008-A-C-SD
FJ008-Z-R-SD
FT008-Z-R-SD
FM008-A-R-SD
PH008-A-R-SD
−
−
−
SNT-8A
PH008-A-L-SD
3
3-WIRE SERIAL E2PROM
S-93C46C/56C/66C/76C/86C
Rev.1.1_00
3. Product name list
Product Name
S-93C46CD0I-J8T1U3
S-93C46CR0I-J8T1U3
S-93C46CD0I-T8T1U3
S-93C46CD0I-K8T3U3
S-93C46CD0I-I8T1U3
S-93C56CD0I-J8T1U3
S-93C56CR0I-J8T1U3
S-93C56CD0I-T8T1U3
S-93C56CD0I-K8T3U3
S-93C56CD0I-I8T1U3
S-93C66CD0I-J8T1U3
S-93C66CR0I-J8T1U3
S-93C66CD0I-T8T1U3
S-93C66CD0I-K8T3U3
S-93C66CD0I-I8T1U3
S-93C76CD0I-J8T1U3
S-93C76CD0I-T8T1U3
S-93C76CD0I-K8T3U3
S-93C76CD0I-I8T1U3
S-93C86CD0I-J8T1U3
S-93C86CD0I-T8T1U3
S-93C86CD0I-K8T3U3
S-93C86CD0I-I8T1U3
Capacity
1 K-bit
1 K-bit
1 K-bit
1 K-bit
1 K-bit
2 K-bit
2 K-bit
2 K-bit
2 K-bit
2 K-bit
4 K-bit
4 K-bit
4 K-bit
4 K-bit
4 K-bit
8 K-bit
8 K-bit
8 K-bit
8 K-bit
16 K-bit
16 K-bit
16 K-bit
16 K-bit
Package Name
8-Pin SOP (JEDEC)
8-Pin SOP (JEDEC) (Rotated)
8-Pin TSSOP
TMSOP-8
SNT-8A
8-Pin SOP (JEDEC)
8-Pin SOP (JEDEC) (Rotated)
8-Pin TSSOP
TMSOP-8
SNT-8A
8-Pin SOP (JEDEC)
8-Pin SOP (JEDEC) (Rotated)
8-Pin TSSOP
TMSOP-8
SNT-8A
8-Pin SOP (JEDEC)
8-Pin TSSOP
TMSOP-8
SNT-8A
8-Pin SOP (JEDEC)
8-Pin TSSOP
TMSOP-8
SNT-8A
4
3-WIRE SERIAL E2PROM
Rev.1.1_00
S-93C46C/56C/66C/76C/86C
Pin Configuration
1. 8-Pin SOP (JEDEC)
Top view
Pin No.
Symbol
Description
Chip select input
Serial clock input
Serial data input
Serial data output
Ground
1
2
3
4
5
6
7
8
CS
SK
DI
1
2
3
4
8
7
6
5
DO
GND
TEST*1
NC
Test
No connection
Power supply
VCC
2. 8-Pin SOP (JEDEC) (Rotated)
Top view
Pin No.
Symbol
Description
No connection
Power supply
Chip select input
Serial clock input
Serial data input
Serial data output
Ground
1
2
3
4
5
6
7
8
NC
1
2
3
4
8
7
6
5
VCC
CS
SK
DI
DO
GND
TEST*1
Test
3. 8-Pin TSSOP
Top view
Pin No.
Symbol
Description
Chip select input
Serial clock input
Serial data input
Serial data output
Ground
1
2
3
4
5
6
7
8
CS
1
2
3
4
8
7
6
5
SK
DI
DO
GND
TEST*1
NC
Test
No connection
Power supply
VCC
*1. Connect to GND or the VCC pin, or set to open. Even if this pin is not connected, performance is not affected so
long as the absolute maximum rating is not exceeded.
5
3-WIRE SERIAL E2PROM
S-93C46C/56C/66C/76C/86C
Rev.1.1_00
4. TMSOP-8
Top view
Pin No.
Symbol
Description
Chip select input
1
2
3
4
5
6
7
8
CS
SK
DI
1
2
3
4
8
7
6
5
Serial clock input
Serial data input
Serial data output
Ground
DO
GND
TEST*1
NC
Test
No connection
Power supply
VCC
5. SNT-8A
Top view
Pin No.
Symbol
Description
1
2
3
4
5
6
7
8
CS
Chip select input
Serial clock input
Serial data input
Serial data output
Ground
1
8
7
6
5
2
3
4
SK
DI
DO
GND
TEST*1
NC
Test
No connection
Power supply
VCC
*1. Connect to GND or the VCC pin, or set to open. Even if this pin is not connected, performance is not affected so
long as the absolute maximum rating is not exceeded.
6
3-WIRE SERIAL E2PROM
Rev.1.1_00
S-93C46C/56C/66C/76C/86C
Absolute Maximum Ratings
Table 1
Item
Power supply voltage
Input voltage
Symbol
Absolute Maximum Rating
Unit
V
V
VCC
VIN
−0.3 to +6.5
−0.3 to +6.5
Output voltage
Operation ambient temperature Topr
Storage temperature Tstg
VOUT
−0.3 to VCC + 0.3
−40 to +85
−65 to +150
V
°C
°C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
Recommended Operating Conditions
Table 2
Ta = −40°C to +85°C
Item
Symbol
VCC
Condition
READ, EWDS
Unit
Min.
Max.
1.6
5.5
V
V
V
V
V
V
V
V
V
Power supply voltage
WRITE, ERASE,EWEN
WRAL, ERAL
1.8
5.5
2.5
5.5
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 4.5 V
VCC = 1.6 V to 2.7 V
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 4.5 V
VCC = 1.6 V to 2.7 V
2.0
VCC
High level input voltage VIH
Low level input voltage VIL
0.8 × VCC
0.8 × VCC
0.0
VCC
VCC
0.8
0.0
0.2 × VCC
0.15 × VCC
0.0
Pin Capacitance
Table 3
(Ta = +25°C, f = 1.0 MHz, VCC = 5.0 V)
Item
Symbol
Condition
Min.
Max.
Unit
Input capacitance
Output capacitance
CIN
COUT
VIN = 0 V
VOUT = 0 V
8
10
pF
pF
−
−
Endurance
Table 4
Item
Symbol Operation Ambient Temperature
Min.
106
Max.
Unit
cycle / word*1
Endurance
NW Ta = −40°C to +85°C
−
*1. For each address (Word: 16-bit)
Data Retention
Table 5
Operation Ambient Temperature
Ta = +25°C
Ta = −40°C to +85°C
Item
Symbol
Min.
Max.
Unit
year
year
100
50
−
−
Data retention
−
7
3-WIRE SERIAL E2PROM
S-93C46C/56C/66C/76C/86C
Rev.1.1_00
DC Electrical Characteristics
Table 6
Ta = −40°C to +85°C
VCC = 1.6 V to 1.8 V, VCC = 1.8 V to 2.5 V, VCC = 2.5 V to 4.5 V, VCC = 4.5 V to 5.5 V,
Item
Symbol Condition
No load at
Unit
mA
fSK = 0.5 MHz
fSK = 1.0 MHz
fSK = 2.0 MHz
fSK = 2.0 MHz
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Current
consumption ICC1
(read)
−
0.4
−
0.4
−
0.5
−
0.8
DO pin
Table 7
Ta = −40°C to +85°C
Item
Symbol
Condition
VCC = 1.8 V to 4.5 V
VCC = 4.5 V to 5.5 V
Unit
mA
Min.
Max.
2.0
Min.
Max.
2.0
Current consumption (write) ICC2
No load at DO pin
−
−
Table 8
Ta = −40°C to +85°C
VCC = 1.6 V to 2.5 V VCC = 2.5 V to 4.5 V VCC = 4.5 V to 5.5 V Unit
Item
Symbol
ISB
Condition
CS = GND,
DO = Open,
Other input pins are
Min.
Max.
Min.
Max.
Min.
Max.
Standby current
consumption
−
2.0
−
2.0
−
2.0
μA
V
CC or GND
CS, SK, DI,
IN = GND to VCC
DO,
Input leakage current ILI
Output leakage
−
−
−
1.0
1.0
1.2
−
−
−
1.0
1.0
1.2
−
−
−
1.0
1.0
1.2
μA
μA
μA
V
ILO
current
V
OUT = GND to VCC
TEST,
Pull-down current
IPD
VIN = GND ~ VCC
IOL = 2.1 mA
−
−
−
−
−
0.1
−
−
−
−
−
−
−
−
−
0.1
−
−
−
−
−
2.4
0.4
0.1
−
−
−
V
V
V
V
V
Low level
output voltage
VOL
IOL = 100 μA
I
OH = −400 μA
High level
output voltage
VOH
IOH = −100 μA
IOH = −10 μA
Only program disable
mode
VCC
VCC
0.3
0.2
VCC
VCC
−
−
0.3
0.2
VCC
−
0.2
Data hold voltage
of write enable latch
VDH
1.5
−
1.5
−
1.5
−
V
8
3-WIRE SERIAL E2PROM
Rev.1.1_00
S-93C46C/56C/66C/76C/86C
AC Electrical Characteristics
Table 9 Measurement Conditions
Input pulse voltage
Output reference voltage
Output load
0.1 × VCC to 0.9 × VCC
0.5 × VCC
100 pF
Table 10
Ta = −40°C to +85°C
VCC = 1.8 V to 2.5 V VCC = 2.5 V to 4.5 V VCC = 4.5 V to 5.5 V Unit
Item
Symbol
VCC = 1.6 V to 1.8 V
Min.
Max.
Min.
0.2
0
Max.
Min.
0.15
0
Max.
Min.
0.15
0
Max.
CS pin setup time
CS pin hold time
tCSS
tCSH
0.4
0
−
−
−
−
−
−
−
−
μs
μs
CS pin deselect time tCDS
0.4
0.2
0.2
−
−
−
−
0.8
0.5
−
0.2
0.1
0.1
−
−
−
−
0.6
1.0
−
0.2
0.1
0.1
−
−
−
−
0.25
2.0
−
0.2
0.1
0.1
−
−
−
−
0.25
2.0
−
μs
μs
μs
μs
Data setup time
Data hold time
tDS
tDH
tPD
Output delay time
Clock frequency*1
SK clock time "L"*1
SK clock time "H"*1
fSK
0
0
0
0
MHz
tSKL
tSKH
0.5
0.5
0
0.2
0.2
0
0.2
0.2
0
0.1
0.1
0
μs
μs
μs
μs
−
−
−
−
Output disable time tHZ1, tHZ2
0.5
0.5
4.0
0.2
0.2
4.0
0.2
0.2
4.0
0.15
0.15
4.0
Output enable time
Write time
tSV
tPR
0
0
0
0
−
−
−
−
ms
*1. The clock cycle of the SK clock (frequency fSK) is 1/fSK μs. This clock cycle is determined by a combination of
several AC characteristics. Note that the clock cycle cannot be set as (1/fSK) = tSKL (min.) + tSKH (min.) by minimizing
the SK clock cycle time.
*2
tCSS
1/fSK
tCDS
CS
SK
tSKH
tSKL
tCSH
tDS
tDS tDH
tDH
Valid data
Valid data
DI
tPD
tPD
High-Z*1
High-Z
High-Z
High-Z
DO
tSV
(READ)
tHZ1
tHZ2
DO
(VERIFY)
*1.
*2.
Indicates high impedance.
1/fSK is the SK clock cycle. This clock cycle is determined by a combination of several AC characteristics.
Note that the clock cycle cannot be set as (1/fSK) = tSKL (min.) + tSKH (min.) by minimizing the SK clock cycle
time.
Figure 1 Timing Chart
9
3-WIRE SERIAL E2PROM
S-93C46C/56C/66C/76C/86C
Rev.1.1_00
Pin Functions
1. CS (chip select input) pin
This is an input pin to set a chip in the select status. In the "L" input level, this IC is in the non-select status and its
output is "High-Z". This IC is in standby as long as it is not in write inside. This IC goes in active by setting the chip
select to "H". Input any instruction code after power-on and a rising of chip select.
2. SK (serial clock input) pin
This is a clock input pin to set the timing of serial data. A start bit, an operation code, an address and a write data are
received at a rising edge of clock. Data is output during rising edge of clock.
3. DI (serial data input) pin
This pin is to input serial data. This pin receives a start bit, an operation code, an address and a write data. This pin
latches data at rising edge of serial clock.
4. SO (serial data output) pin
This pin is to output serial data. The data output changes at rising edge of serial clock.
5. TEST (test input) pin
This is an input pin in test mode. Connect to GND or the VCC pin, or set to open. Because this pin has a built-in
pull-down element, pull-down current flows when it connected to VCC pin.
Initial Delivery State
Initial delivery state of all addresses is "FFFFh".
10
3-WIRE SERIAL E2PROM
Rev.1.1_00
S-93C46C/56C/66C/76C/86C
Instruction Sets
1. S-93C46C
Table 11
Operation
Code
Instruction
Start Bit
Address
Data
SK input clock
READ (Data read)
WRITE (Data write)
ERASE (Data erase)
WRAL (Chip write)
ERAL (Chip erase)
EWEN (Write enable)
EWDS (Write disable)
1
1
1
1
1
1
1
1
2
1
0
1
0
0
0
0
3
0
1
1
0
0
0
0
4
A5
A5
A5
0
1
1
0
5
A4
A4
A4
1
0
1
0
6
A3
A3
A3
x
x
x
x
7
A2
A2
A2
x
x
x
x
8
A1
A1
A1
x
x
x
x
9
A0
A0
A0
x
x
x
x
10 to 25
D15 to D0 output*1
D15 to D0 input
−
D15 to D0 input
−
−
−
*1. When the 16-bit data in the specified address has been output, the data in the next address is output.
Remark x = Don't care.
2. S-93C56C
Table 12
Operation
Code
Instruction
Start Bit
Address
Data
SK input clock
READ (Data read)
WRITE (Data write)
ERASE (Data erase)
WRAL (Chip write)
ERAL (Chip erase)
EWEN (Write enable)
EWDS (Write disable)
1
1
1
1
1
1
1
1
2
1
0
1
0
0
0
0
3
0
1
1
0
0
0
0
4
x
x
x
0
1
1
0
5
6
7
8
9
10 11
12 to 27
D15 to D0 output*1
A6 A5 A4 A3 A2 A1 A0
A6 A5 A4 A3 A2 A1 A0
A6 A5 A4 A3 A2 A1 A0
1
0
1
0
D15 to D0 input
−
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D15 to D0 input
−
−
−
*1. When the 16-bit data in the specified address has been output, the data in the next address is output.
Remark x = Don't care.
3. S-93C66C
Table 13
Operation
Code
Instruction
Start Bit
Address
Data
SK input clock
READ (Data read)
WRITE (Data write)
ERASE (Data erase)
WRAL (Chip write)
ERAL (Chip erase)
EWEN (Write enable)
EWDS (Write disable)
1
1
1
1
1
1
1
1
2
1
0
1
0
0
0
0
3
0
1
1
0
0
0
0
4
5
6
7
8
9
10 11
12 to 27
D15 to D0 output*1
A7 A6 A5 A4 A3 A2 A1 A0
A7 A6 A5 A4 A3 A2 A1 A0
A7 A6 A5 A4 A3 A2 A1 A0
0
1
1
0
D15 to D0 input
−
1
0
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D15 to D0 input
−
−
−
*1. When the 16-bit data in the specified address has been output, the data in the next address is output.
Remark x = Don't care.
11
3-WIRE SERIAL E2PROM
S-93C46C/56C/66C/76C/86C
Rev.1.1_00
4. S-93C76C
Table 14
Operation
Code
Instruction
Start Bit
Address
Data
SK input clock
READ (Data read)
WRITE (Data write)
ERASE (Data erase)
WRAL (Chip write)
ERAL (Chip erase)
EWEN (Write enable)
EWDS (Write disable)
1
1
1
1
1
1
1
1
2
1
0
1
0
0
0
0
3
0
1
1
0
0
0
0
4
x
x
x
0
1
1
0
5
6
7
8
9
10 11 12 13
14 to 29
D15 to D0 output*1
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
D15 to D0 input
−
1
0
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D15 to D0 input
−
−
−
*1. When the 16-bit data in the specified address has been output, the data in the next address is output.
Remark x = Don't care.
5. S-93C86C
Table 15
Operation
Code
Instruction
Start Bit
Address
Data
SK input clock
READ (Data read)
WRITE (Data write)
ERASE (Data erase)
WRAL (Chip write)
ERAL (Chip erase)
EWEN (Write enable)
EWDS (Write disable)
1
1
1
1
1
1
1
1
2
3
0
1
1
0
0
0
0
4
5
6
7
8
9
10 11 12 13
14 to 29
D15 to D0 output*1
1
0
1
0
0
0
0
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
D15 to D0 input
−
0
1
1
0
1
0
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D15 to D0 input
−
−
−
*1. When the 16-bit data in the specified address has been output, the data in the next address is output.
Remark x = Don't care.
12
3-WIRE SERIAL E2PROM
Rev.1.1_00
S-93C46C/56C/66C/76C/86C
Operation
All instructions are executed by inputting the DI pin in synchronization with the rising of the SK pulse after the CS pin
goes to "H". An instruction set is input in the order of start bit, instruction, address, and data.
Instruction input finishes when the CS pin goes to "L". "L" must be input to the CS pin between commands during tCDS
.
While "L" is being input to the CS pin, this IC is in standby mode, so the SK pin and the DI pin inputs are invalid and no
instructions are allowed.
1. Start Bit
A start bit is recognized when the DI pin goes to "H" at the rising of the SK pulse after the CS pin goes to "H". After the
CS pin goes to "H", a start bit is not recognized even if the SK pulse is input as long as the DI pin is "L".
1. 1 Dummy clock
The SK clocks input while the DI pin is "L" before a start bit is input are called dummy clocks. Dummy clocks are
effective when aligning the number of instruction sets (clocks) sent by the CPU with those required for serial
memory operation. For example, when the CPU instruction set is 16 bits, the number of instruction set clocks can
be adjusted by inserting the 7-bit dummy clock in S-93C46C, the 5-bit dummy clock in S-93C56C/66C and the
3-bit dummy clock in S-93C76C/86C.
1. 2 Start bit input failure
(1) When the output of the DO pin is "H" during the verify period after a write operation, if "H" is input to the DI pin
at the rising of the SK pulse, this IC recognizes that a start bit has been input. To prevent this failure, input "L"
to the DI pin during the verify operation period (refer to "3. 1 Verify operation").
(2) When a 3-wire interface is configured by connecting the DI input pin and the DO output pin, a period in which
the data output from the CPU and the serial memory collide may be generated, preventing successful input of
the start bit. Take the measures described in " 3-Wire Interface (Direct Connection between DI Pin and
DO Pin)".
2. Reading (READ)
The READ instruction reads data from a specified address.
After the CS pin goes to "H", input an instruction in the order of the start bit, read instruction, and address. Since the
last input address (A0) has been latched, the output status of the DO pin changes from "High-Z" to "L", which is held
until the next rising of the SK pulse. 16-bit data starts to be output in synchronization with the next rising of the SK
pulse.
2. 1 Sequential read
After the 16-bit data at the specified address has been output, inputting the SK pulse while the CS pin is "H"
automatically increments the address, and causes the 16-bit data at the next address to be output sequentially.
The above method makes it possible to read the data in the whole memory space. The last address (An A1
A0 = 1 1 1) rolls over to the top address (An A1 A0 = 0 0 0).
13
3-WIRE SERIAL E2PROM
S-93C46C/56C/66C/76C/86C
Rev.1.1_00
CS
1
2
3
4
5
6
7
8
9
10 11 12
27
38 39 40 41 42
SK
DI
22 23 24 25 26
43
1
0
<1>
A5 A4 A3 A2 A1 A0
High-Z
High-Z
D15 D14 D13
D2 D1 D0 D15 D14 D13
D2 D1 D0 D15 D14 D13
0
DO
ADRINC
ADRINC
Figure 2 Read Timing (S-93C46C)
CS
SK
1
2
3
0
4
5
6
7
8
9
10 11 12 13 14
29
40 41 42 43 44
45
24 25 26 27 28
1
<1>
A6
A5 A4 A3 A2 A1 A0
DI
x: S-93C56C
A7: S-93C66C
High-Z
High-Z
D15 D14 D13
D2 D1 D0 D15 D14 D13
D2 D1 D0 D15 D14 D13
0
DO
ADRINC
ADRINC
Figure 3 Read Timing (S-93C56C/66C)
CS
SK
1
2
3
4
5
6
7
8
9
10 11 12
31
13 14 15 16
26 27 28 29 30
42 43 44 45 46 47
<1>
1
0
A8
A7 A6 A5 A4 A3 A2
A1 A0
DI
x: S-93C76C
A9: S-93C86C
High-Z
High-Z
D15 D14 D13
D2 D1 D0 D15 D14 D13
D2 D1 D0 D15 D14 D13
0
DO
ADRINC
ADRINC
Figure 4 Read Timing (S-93C76C/86C)
14
3-WIRE SERIAL E2PROM
Rev.1.1_00
S-93C46C/56C/66C/76C/86C
3. Writing (WRITE, ERASE, WRAL, ERAL)
A write operation includes four write instructions: data write (WRITE), data erase (ERASE), chip write (WRAL), and
chip erase (ERAL).
A write instruction (WRITE, ERASE, WRAL, ERAL) starts a write operation to the memory cell when "L" is input to the
CS pin after a specified number of clocks have been input. The SK pin and the DI pin inputs are invalid during the
write period, so do not input an instruction.
Input an instruction while the output status of the DO pin is "H" or "High-Z".
A write operation is valid only in program enable mode (refer to "4. Write enable (EWEN) / write disable (EWDS)").
3. 1 Verify operation
A write operation executed by any instruction is completed within 4 ms (write time tPR), so if the completion of the
write operation is recognized, the write cycle can be minimized. A sequential operation to confirm the status of a
write operation is called a verify operation.
3. 1. 1 Operation method
After the write operation has started (CS pin = "L"), the status of the write operation can be verified by
confirming the output status of the DO pin by inputting "H" to the CS pin again. This sequence is called a verify
operation, and the period that "H" is input to the CS pin after the write operation has started is called the verify
operation period.
The relationship between the output status of the DO pin and the write operation during the verify operation
period is as follows.
(1) DO pin = "L": Writing in progress (busy)
(2) DO pin = "H":Writing completed (ready)
3. 1. 2 Operation example
There are two methods to perform a verify operation: Waiting for a change in the output of the DO pin while
keeping the CS pin "H", or suspending the verify operation (CS pin = "L") once and then performing it again to
verify the output of the DO pin. The latter method allows the CPU to perform other processing during the wait
period, allowing an efficient system to be designed.
Caution 1. Input "L" to the DI pin during a verify operation.
2. If "H" is input to the DI pin at the rising of the SK pulse when the output status of the DO pin is
"H", this IC latches the instruction assuming that a start bit has been input. In this case, note
that the DO pin immediately enters "High-Z".
15
3-WIRE SERIAL E2PROM
S-93C46C/56C/66C/76C/86C
Rev.1.1_00
3. 2 Writing data (WRITE)
To write 16-bit data to a specified address, change the CS pin to "H" and then input the WRITE instruction,
address, and 16-bit data following the start bit. The write operation starts when the CS pin goes to "L". There is no
need to set the data to "1" before writing. When the clocks more than the specified number have been input, the
clock pulse monitoring circuit cancels the WRITE instruction. For details of the clock pulse monitoring circuit, refer
to " Function to Protect Against Write due to Erroneous Instruction Recognition".
tCDS
Standby
CS
SK
Verify
1
2
3
4
5
6
7
8
9
10
25
DI
<1>
0
1
A4
A1 A0
A3
A5
D15
D0
A2
tSV
tHZ1
High-Z
busy
ready
DO
High-Z
tPR
Figure 5 Data Write Timing (S-93C46C)
tCDS
Standby
CS
Verify
SK
DI
11 12
A2 A1 A0
27
1
2
3
4
5
6
7
8
9
10
1
0
A5
x: S-93C56C
A3
A6
A4
<1>
D15
D0
tSV
tHZ1
High-Z
A7: S-93C66C
busy
ready
DO
High-Z
tPR
Figure 6 Data Write Timing (S-93C56C/66C)
tCDS
Standby
CS
SK
Verify
13 14
29
D0
1
2
0
3
4
5
6
7
8
9
10
11 12
A2 A1
DI
<1>
1
A4 A3
A0
A7
A5
A8
A6
D15
tSV
tHZ1
x: S-93C76C
High-Z
A9: S-93C86C
busy
ready
DO
High-Z
tPR
Figure 7 Data Write Timing (S-93C76C/86C)
16
3-WIRE SERIAL E2PROM
Rev.1.1_00
S-93C46C/56C/66C/76C/86C
3. 3 Erasing data (ERASE)
To erase 16-bit data at a specified address, set all 16 bits of the data to "1", change the CS pin to "H", and then
input the ERASE instruction and address following the start bit. There is no need to input data. The data erase
operation starts when the CS pin goes to "L". When the clocks more than the specified number have been input,
the clock pulse monitoring circuit cancels the ERASE instruction. For details of the clock pulse monitoring circuit,
refer to " Function to Protect Against Write due to Erroneous Instruction Recognition".
tCDS
Standby
CS
SK
Verify
1
2
3
4
5
6
7
8
9
<1>
A5 A4 A3 A2 A1
High-Z
A0
1
1
DI
tSV
tHZ1
busy
ready
DO
High-Z
tPR
Figure 8 Data Erase Timing (S-93C46C)
tCDS
Standby
CS
SK
Verify
1
2
1
3
4
5
6
7
8
9
10 11
<1>
1
A6 A5 A4 A3 A2 A1
A0
DI
tSV
x: S-93C56C
A7: S-93C66C
tHZ1
High-Z
busy
ready
DO
High-Z
tPR
Figure 9 Data Erase Timing (S-93C56C/66C)
tCDS
Standby
CS
SK
Verify
1
2
1
3
1
4
5
6
7
8
9
10
11
13
12
A1
A8 A7 A6 A5 A4 A3 A2
A0
<1>
DI
tSV
x: S-93C76C
tHZ1
A9: S-93C86C
High-Z
busy
ready
DO
High-Z
tPR
Figure 10 Data Erase Timing (S-93C76C/86C)
17
3-WIRE SERIAL E2PROM
S-93C46C/56C/66C/76C/86C
Rev.1.1_00
3. 4 Writing to chip (WRAL)
To write the same 16-bit data to the entire memory address space, change the CS pin to "H", and then input the
WRAL instruction, an address, and 16-bit data following the start bit. Any address can be input. The write
operation starts when the CS pin goes to "L". There is no need to set the data to "1" before writing. When the
clocks more than the specified number have been input, the clock pulse monitoring circuit cancels the WRAL
instruction. For details of the clock pulse monitoring circuit, refer to " Function to Protect Against Write due to
Erroneous Instruction Recognition".
tCDS
Standby
CS
SK
Verify
1
2
0
3
4
5
6
7
8
9
10
25
DI
0
0
<1>
1
D15
D0
tSV
tHZ1
4xs
High-Z
busy
ready
DO
High-Z
tPR
Figure 11 Chip Write Timing (S-93C46C)
tCDS
Standby
CS
SK
Verify
11 12
D15
27
1
2
0
3
4
5
1
6
7
8
9
10
DI
0
0
<1>
D0
tSV
tHZ1
6xs
High-Z
busy
ready
DO
High-Z
tPR
Figure 12 Chip Write Timing (S-93C56C/66C)
tCDS
Standby
CS
SK
Verify
13
14
29
1
2
0
3
4
5
6
7
8
9
10
11
12
DI
0
0
D15
D0
<1>
1
tSV
tHZ1
8xs
High-Z
busy
ready
DO
High-Z
tPR
Figure 13 Chip Write Timing (S-93C76C/86C)
18
3-WIRE SERIAL E2PROM
Rev.1.1_00
S-93C46C/56C/66C/76C/86C
3. 5 Erasing chip (ERAL)
To erase the data of the entire memory address space, set all the data to "1", change the CS pin to "H", and then
input the ERAL instruction and an address following the start bit. Any address can be input. There is no need to
input data. The chip erase operation starts when the CS pin goes to "L". When the clocks more than the specified
number have been input, the clock pulse monitoring circuit cancels the ERAL instruction. For details of the clock
pulse monitoring circuit, refer to " Function to Protect Against Write due to Erroneous Instruction
Recognition".
Standby
CS
Verify
tCDS
SK
1
2
0
3
4
1
5
6
7
8
9
DI
<1>
0
0
tHZ1
tSV
4xs
High-Z
Busy
DO
Ready
High-Z
tPR
Figure 14 Chip Erase Timing (S-93C46C)
Standby
CS
SK
Verify
tCDS
1
2
3
4
1
5
6
7
8
9
10
11
DI
<1>
0
0
0
tHZ1
tSV
6xs
High-Z
Busy
DO
Ready
High-Z
tPR
Figure 15 Chip Erase Timing (S-93C56C/66C)
Standby
CS
SK
Verify
tCDS
1
2
0
3
4
5
6
7
8
9
10 11
12
13
<1>
DI
0
1
0
tSV
8xs
tHZ1
High-Z
busy
DO
ready
High-Z
tPR
Figure 16 Chip Erase Timing (S-93C76C/86C)
19
3-WIRE SERIAL E2PROM
S-93C46C/56C/66C/76C/86C
Rev.1.1_00
4. Write enable (EWEN) / write disable (EWDS)
The EWEN instruction is an instruction that enables a write operation. The status in which a write operation is enabled
is called the program enable mode.
The EWDS instruction is an instruction that disables a write operation. The status in which a write operation is
disabled is called the program disable mode.
After the CS pin goes to "H", input an instruction in the order of the start bit, EWEN or EWDS instruction, and address
(optional). Each mode becomes valid by inputting "L" to the CS pin after the last address (optional) has been input.
Standby
CS
SK
1
2
3
4
5
6
7
8
9
DI
0
0
<1>
4xs
11 = EWEN
00 = EWDS
Figure 17 Write Enable / Disable Timing (S-93C46C)
Standby
CS
SK
1
2
3
4
5
6
7
8
9
10
11
DI
0
0
<1>
6xs
11 = EWEN
00 = EWDS
Figure 18 Write Enable / Disable Timing (S-93C56C/66C)
CS
SK
Standby
12
13
1
2
0
3
4
5
6
7
8
9
10
11
DI
<1>
0
8xs
11 = EWEN
00 = EWDS
Figure 19 Write Enable / Disable Timing (S-93C76C/86C)
Remark It is recommended to execute an EWDS instruction for preventing an incorrect write operation if a write
instruction is erroneously recognized when executing instructions other than write instruction, and
immediately after power-on and before power-off.
20
3-WIRE SERIAL E2PROM
Rev.1.1_00
S-93C46C/56C/66C/76C/86C
Write Protect Function during the Low Power Supply Voltage
This IC provides a built-in detection circuit to detect a low power supply voltage. When the power supply voltage is low or
at power-on, the write instructions (WRITE, ERASE, WRAL, and ERAL) are cancelled, and the write disable (EWDS)
status is automatically set. The detection voltage and the release voltage are 1.2 V typ. (refer to Figure 20).
Therefore, when a write operation is performed after the power supply voltage has dropped and then risen again up to
the level at which writing is possible, a write enable instruction (EWEN) must be sent before a write instruction (WRITE,
ERASE, WRAL, or ERAL) is executed.
When the power supply voltage drops during a write operation, the data being written to an address at that time is not
guaranteed.
Power supply voltage
Release voltage (+VDET
1.2 V typ.
)
Detection voltage (−VDET
1.2 V typ.
)
Write instructions are cancelled
Write disable status (EWDS) is automatically set
Figure 20 Operation during the Low Power Supply Voltage
21
3-WIRE SERIAL E2PROM
S-93C46C/56C/66C/76C/86C
Rev.1.1_00
Function to Protect Against Write due to Erroneous Instruction Recognition
This IC provides a built-in clock pulse monitoring circuit which is used to prevent an erroneous write operation by
canceling write instructions (WRITE, ERASE, WRAL, and ERAL) recognized erroneously due to an erroneous clock
count caused by the application of noise pulses or double counting of clocks. Instructions are cancelled if a clock pulse
whose count other than the one specified for each write instruction (WRITE, ERASE, WRAL, or ERAL) is detected.
Example: Erroneous Recognition of EWDS as ERASE
Example of S-93C76C/86C
Noise pulse
CS
1
2
3
4
5
6
7
8
9
10 11 12 13
SK
DI
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Input EWDS instruction
Erroneous recognition as ERASE
instruction due to noise pulse
1 1 10
0
0
0 0
0
0
0
0
In products that do not incorporate a clock pulse monitoring circuit, "FFFFh" is mistakenly written to address
00h. However the S-93C76C/86C detects the overcount and cancels the instruction without performing a write
operation.
Figure 21 Example of Clock Pulse Monitoring Circuit Operation
22
3-WIRE SERIAL E2PROM
Rev.1.1_00
S-93C46C/56C/66C/76C/86C
3-Wire Interface (Direct Connection between DI Pin and DO Pin)
There are two types of serial interface configurations: a 4-wire interface configured using the CS pin, the SK pin, the DI
pin and the DO pin and a 3-wire interface that connects the DI pin and the DO pin.
When the 3-wire interface is employed, a period in which the data output from the CPU and the data output from the
serial memory collide may occur, causing a malfunction. To prevent such a malfunction, connect the DI pin and the DO
pin of this IC via a resistor (10 kΩ to 100 kΩ) so that the data output from the CPU takes precedence in being input to
the DI pin (refer to Figure 22).
CPU
S-93C46C/56C/66C/76C/86C
SIO
DI
DO
R: 10 kΩ to 100 kΩ
Figure 22 Connection of 3-Wire Interface
Input Pin and Output Pin
1. Connection of input pin
All input pins in this IC have the CMOS structure. Do not set these pins in "High-Z" during operation when you design.
Especially, set the CS pin to "L" at power-on, power-off, and during standby. The error write does not occur as long as
the CS pin is "L". Set the CS pin to GND via a resistor (the pull-down resistor of 10 kΩ to 100 kΩ).
To prevent the error for sure, it is recommended to use equivalent pull-down resistors for input pins other than the CS
pin.
2. Equivalent circuit of input pin and output pin
Figure 23, Figure 24 and Figure 25 show the equivalent circuits of input pins in this IC. In Figure 23 and Figure 24,
none of the input pins incorporate pull-up and pull-down elements, so special care must be taken when designing to
prevent a floating status.
In Figure 25, the TEST pin has a built-in pull-down element.
Figure 26 shows the equivalent circuit of the output pin. This pin has the tri-state output of "H" / "L" / "High-Z".
23
3-WIRE SERIAL E2PROM
S-93C46C/56C/66C/76C/86C
Rev.1.1_00
2. 1 Input pin
CS
Figure 23 CS Pin
SK, DI
Figure 24 SK, DI Pin
TEST
Figure 25 TEST Pin
24
3-WIRE SERIAL E2PROM
Rev.1.1_00
S-93C46C/56C/66C/76C/86C
2. 2 Output pin
VCC
DO
Figure 26 DO Pin
3. Input pin noise suppression time
This IC has a built-in low-pass filter at the SK pin, the DI pin and the CS pin to suppress noise. If the supply voltage is
5.0 V, noise with a pulse width of 20 ns or less at room temperature can be suppressed by the low-pass filter.
Note that noise with a pulse width of more than 20 ns is recognized as a pulse since the noise can not be suppressed
if the voltage exceeds VIH / VIL.
Precautions
• Do not operate these ICs in excess of the absolute maximum ratings. Attention should be paid to the power supply
voltage, especially. The surge voltage which exceeds the absolute maximum ratings can cause latch-up and
malfunction. Perform operations after confirming the detailed operation condition in the data sheet.
• Operations with moisture on this IC's pins may occur malfunction by short-circuit between pins. Especially, in
occasions like picking this IC up from low temperature tank during the evaluation. Be sure that not remain frost on this
IC's pin to prevent malfunction by short-circuit.
Also attention should be paid in using on environment, which is easy to dew for the same reason.
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
• SII Semiconductor Corporation claims no responsibility for any and all disputes arising out of or in connection with any
infringement of the products including this IC upon patents owned by a third party.
25
+0.20
-0.35
5.02
8
5
1
4
0.20±0.05
+0.11
-0.07
0.4
1.27
No. FJ008-Z-P-SD-2.1
TITLE
SOP8J-Z-PKG Dimensions
FJ008-Z-P-SD-2.1
No.
ANGLE
UNIT
mm
SII Semiconductor Corporation
4.0±0.1(10 pitches:40.0±0.2)
2.0±0.05
ø1.55±0.05
0.3±0.05
8.0±0.1
ø1.5 min.
2.1±0.1
+0.30
-0.25
6.5
8
5
1
4
Feed direction
No. FJ008-Z-C-SD-1.0
TITLE
SOP8J-Z-Carrier Tape
FJ008-Z-C-SD-1.0
No.
ANGLE
UNIT
mm
SII Semiconductor Corporation
17.5±1.5
13.4±1.0
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.2
No. FJ008-Z-R-SD-1.0
SOP8J-Z-Reel
TITLE
No.
FJ008-Z-R-SD-1.0
ANGLE
UNIT
QTY.
4,000
mm
SII Semiconductor Corporation
+0.3
-0.2
3.00
5
8
1
4
0.15±0.07
0.2±0.1
0.65
No. FT008-Z-P-SD-1.2
TITLE
TSSOP8-Z-PKG Dimensions
FT008-Z-P-SD-1.2
No.
ANGLE
UNIT
mm
SII Semiconductor Corporation
4.0±0.1
2.0±0.05
0.3±0.05
ø1.55±0.05
+0.2
-0.05
8.0±0.1
ø1.55
+0.4
-0.2
6.6
8
5
1
4
Feed direction
No. FT008-Z-C-SD-1.0
TITLE
TSSOP8-Z-Carrier Tape
FT008-Z-C-SD-1.0
No.
ANGLE
UNIT
mm
SII Semiconductor Corporation
13.4±1.0
17.5±1.0
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.2
No. FT008-Z-R-SD-1.0
TSSOP8-Z-Reel
FT008-Z-R-SD-1.0
TITLE
No.
ANGLE
UNIT
QTY.
4,000
mm
SII Semiconductor Corporation
2.90±0.2
8
5
1
4
0.13±0.1
0.2±0.1
0.65±0.1
No. FM008-A-P-SD-1.2
TMSOP8-A-PKG Dimensions
FM008-A-P-SD-1.2
TITLE
No.
ANGLE
UNIT
mm
SII Semiconductor Corporation
2.00±0.05
4.00±0.1
1.00±0.1
4.00±0.1
+0.1
-0
1.5
1.05±0.05
0.30±0.05
3.25±0.05
1
8
4
5
Feed direction
No. FM008-A-C-SD-2.0
TMSOP8-A-Carrier Tape
FM008-A-C-SD-2.0
TITLE
No.
ANGLE
UNIT
mm
SII Semiconductor Corporation
16.5max.
13.0±0.3
Enlarged drawing in the central part
13±0.2
(60°)
(60°)
No. FM008-A-R-SD-1.0
TMSOP8-A-Reel
FM008-A-R-SD-1.0
TITLE
No.
ANGLE
UNIT
QTY.
4,000
mm
SII Semiconductor Corporation
1.97±0.03
6
5
8
7
+0.05
-0.02
0.08
1
2
3
4
0.5
0.48±0.02
0.2±0.05
No. PH008-A-P-SD-2.1
TITLE
SNT-8A-A-PKG Dimensions
PH008-A-P-SD-2.1
No.
ANGLE
UNIT
mm
SII Semiconductor Corporation
+0.1
-0
4.0±0.1
2.0±0.05
0.25±0.05
ø1.5
0.65±0.05
ø0.5±0.1
4.0±0.1
2.25±0.05
5°
4 3 2 1
5 6 7 8
Feed direction
No. PH008-A-C-SD-1.0
TITLE
SNT-8A-A-Carrier Tape
PH008-A-C-SD-1.0
No.
ANGLE
UNIT
mm
SII Semiconductor Corporation
12.5max.
9.0±0.3
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. PH008-A-R-SD-1.0
SNT-8A-A-Reel
TITLE
No.
PH008-A-R-SD-1.0
5,000
QTY.
ANGLE
UNIT
mm
SII Semiconductor Corporation
0.52
2
2.01
0.52
1
0.2
0.3
1.
2.
(0.25 mm min. / 0.30 mm typ.)
(1.96 mm ~ 2.06 mm)
1.
2.
0.03 mm
3.
4.
SNT
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package (1.96 mm to 2.06mm).
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
(0.25 mm min. / 0.30 mm typ.)
(1.96 mm ~ 2.06 mm)
1.
2.
SNT-8A-A
-Land Recommendation
TITLE
No.
No. PH008-A-L-SD-4.1
PH008-A-L-SD-4.1
ANGLE
UNIT
mm
SII Semiconductor Corporation
Disclaimers (Handling Precautions)
1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
SII Semiconductor Corporation is not responsible for damages caused by the reasons other than the products or
infringement of third-party intellectual property rights and any other rights due to the use of the information described
herein.
3. SII Semiconductor Corporation is not responsible for damages caused by the incorrect information described herein.
4. Take care to use the products described herein within their specified ranges. Pay special attention to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
SII Semiconductor Corporation is not responsible for damages caused by failures and/or accidents, etc. that occur
due to the use of products outside their specified ranges.
5. When using the products described herein, confirm their applications, and the laws and regulations of the region or
country where they are used and verify suitability, safety and other factors for the intended use.
6. When exporting the products described herein, comply with the Foreign Exchange and Foreign Trade Act and all
other export-related laws, and follow the required procedures.
7. The products described herein must not be used or provided (exported) for the purposes of the development of
weapons of mass destruction or military use. SII Semiconductor Corporation is not responsible for any provision
(export) to those whose purpose is to develop, manufacture, use or store nuclear, biological or chemical weapons,
missiles, or other military use.
8. The products described herein are not designed to be used as part of any device or equipment that may affect the
human body, human life, or assets (such as medical equipment, disaster prevention systems, security systems,
combustion control systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment,
aviation equipment, aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle
use or other uses. Do not use those products without the prior written permission of SII Semiconductor Corporation.
Especially, the products described herein cannot be used for life support devices, devices implanted in the human
body and devices that directly affect human life, etc.
Prior consultation with our sales office is required when considering the above uses.
SII Semiconductor Corporation is not responsible for damages caused by unauthorized or unspecified use of our
products.
9. Semiconductor products may fail or malfunction with some probability.
The user of these products should therefore take responsibility to give thorough consideration to safety design
including redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing
injury or death, fires and social damage, etc. that may ensue from the products' failure or malfunction.
The entire system must be sufficiently evaluated and applied on customer's own responsibility.
10. The products described herein are not designed to be radiation-proof. The necessary radiation measures should be
taken in the product design by the customer depending on the intended use.
11. The products described herein do not affect human health under normal use. However, they contain chemical
substances and heavy metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips
may be sharp. Take care when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products described herein, comply with the laws and ordinances of the country or region where
they are used.
13. The information described herein contains copyright information and know-how of SII Semiconductor Corporation.
The information described herein does not convey any license under any intellectual property rights or any other
rights belonging to SII Semiconductor Corporation or a third party. Reproduction or copying of the information
described herein for the purpose of disclosing it to a third-party without the express permission of SII Semiconductor
Corporation is strictly prohibited.
14. For more details on the information described herein, contact our sales office.
1.0-2016.01
www.sii-ic.com
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