C8051F020-GQR [SILICON]

Microcontroller, 8-Bit, FLASH, 25MHz, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100;
C8051F020-GQR
型号: C8051F020-GQR
厂家: SILICON    SILICON
描述:

Microcontroller, 8-Bit, FLASH, 25MHz, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100

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C8051F020  
25 MIPS, 64 kB Flash, 12-Bit ADC, 100-Pin Mixed-Signal MCU  
Analog Peripherals  
High-Speed 8051 µC Core  
12-Bit ADC  
-
Pipelined instruction architecture; executes 70% of instructions in 1 or 2  
system clocks  
-
-
-
-
-
-
±1 LSB INL; no missing codes  
-
Up to 25 MIPS throughput with 25 MHz system clock  
22 vectored interrupt sources  
Programmable throughput up to 100 ksps  
8 external inputs; programmable as single-ended or differential  
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5  
Data-dependent windowed interrupt generator  
Built-in temperature sensor (±3 °C)  
-
Memory  
-
-
4352 bytes data RAM  
64 kB Flash; in-system programmable in 512-byte sectors (512 bytes  
8-Bit ADC  
are reserved)  
-
External parallel data memory interface  
-
-
-
-
±1 LSB INL; no missing codes  
Programmable throughput up to 500 ksps  
8 external inputs  
Programmable amplifier gain: 4, 2, 1, 0.5  
Digital Peripherals  
-
-
64 port I/O; all are 5 V tolerant  
Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial  
Two 12-Bit DACs  
ports available concurrently  
-
Can synchronize outputs to timers for jitter-free waveform generation  
-
-
-
-
Programmable 16-bit counter/timer array with 5 capture/compare mod-  
ules  
Two Comparators  
5 general-purpose 16-bit counter/timers  
Dedicated watchdog timer; bidirectional reset  
Real-time clock mode using Timer 3 or PCA  
Internal Voltage Reference  
V
Monitor/Brown-out Detector  
DD  
On-Chip JTAG Debug & Boundary Scan  
Clock Sources  
-
-
-
-
On-chip debug circuitry facilitates full speed, non-intrusive in-system  
debug (no emulator required)  
-
-
-
Internal programmable oscillator: 2–16 MHz  
External oscillator: Crystal, RC, C, or Clock  
Can switch between clock sources on-the-fly  
Provides breakpoints, single stepping, watchpoints, stack monitor  
Inspect/modify memory and registers  
Superior performance to emulation systems using ICE-chips, target  
Supply Voltage: 2.7 to 3.6 V  
pods, and sockets  
-
Typical operating current: 10 mA at 25 MHz  
Multiple power saving sleep and shutdown modes  
-
IEEE1149.1 compliant boundary scan  
-
100-Pin TQFP  
Temperature Range: –40 to +85 °C  
VDD  
VDD  
VDD  
Digital Power  
DGND  
DGND  
UART0  
P0  
P0.0  
P0.7  
8
DGND  
Drv  
UART1  
SMBus  
SPI Bus  
PCA  
AV+  
AV+  
C
R
O
S
S
B
A
R
Analog Power  
0
5
1
AGND  
AGND  
P1.0/AIN1.0  
P1.7/AIN1.7  
P1  
Drv  
TCK  
TMS  
TDI  
Boundary Scan  
Debug HW  
JTAG  
Logic  
Timers 0,  
1, 2, 4  
TDO  
P2.0  
P2.7  
P2  
SFR Bus  
Drv  
Reset  
RST  
Timer 3/  
RTC  
VDD  
64 kB  
WDT  
MONEN  
P3.0  
P3.7  
P3  
Monitor  
P0, P1,  
P2, P3  
Latches  
C
o
r
FLASH  
Drv  
External  
Oscillator  
Circuit  
XTAL1  
XTAL2  
256 Byte  
RAM  
Crossbar  
Config.  
System  
Clock  
VREF1  
Internal  
A
M
U
X
4 kB  
ADC  
8:1  
Oscillator  
Prog  
Gain  
500 ksps  
(8-Bit)  
e
RAM  
VREF  
VREF  
VREFD  
External Data Memory Bus  
P4.0  
DAC1  
DAC1  
(12-Bit)  
C
T
L
P4 Latch  
Bus Control  
P4  
P4.4  
P4.5/ALE  
P4.6/RD  
P4.7/WR  
DRV  
DAC0  
DAC0  
(12-Bit)  
VREF0  
P5.0/A0  
P5 Latch  
P6 Latch  
P5  
AIN0.0  
AIN0.1  
AIN0.2  
AIN0.3  
AIN0.4  
AIN0.5  
AIN0.6  
AIN0.7  
A
d
d
r
DRV  
Address Bus  
Data Bus  
P5.7/A7  
P6.0/A8  
ADC  
A
M
U
X
P6  
Prog  
Gain  
100 ksps  
(12-Bit)  
DRV  
P6.7/A15  
D
a
t
P7.0/D0  
P7.7/D7  
P7 Latch  
TEMP  
SENSOR  
P7  
DRV  
CP0+  
CP0-  
CP1+  
CP1-  
CP0  
a
CP1  
Precision Mixed Signal  
Copyright © 2004 by Silicon Laboratories  
6.15.2004  
C8051F020  
25 MIPS, 64 kB Flash, 12-Bit ADC, 100-Pin Mixed-Signal MCU  
Selected Electrical Specifications  
(TA = –40 to +85 C°, VDD = 2.7 V unless otherwise specified)  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
GLOBAL CHARACTERISTICS  
Digital Supply Voltage  
2.7  
3.6  
V
Digital Supply Current  
with CPU active  
(VDD = 2.7 V)  
Clock = 25 MHz  
Clock = 1 MHz  
10  
0.4  
20  
10  
mA  
mA  
µA  
µA  
Clock = 32 kHz; VDD Monitor Disabled  
Oscillator not running; VDD Monitor  
Enabled  
Digital Supply Current  
(shutdown)  
Oscillator not running; VDD Monitor  
Disabled  
0.1  
µA  
CPU & DIGITAL I/O PORTS  
Clock Frequency Range  
Port Output High Voltage  
Port Output Low Voltage  
Input High Voltage  
Input Low Voltage  
A/D CONVERTER  
Resolution  
DC  
25  
0.6  
MHz  
V
IOH = –3 mA, Port I/O push-pull  
IOL = 8.5 mA  
VDD – 0.7  
V
0.7 x VDD  
V
0.3 x VDD  
V
12  
bits  
LSB  
LSB  
dB  
Integral Nonlinearity  
Differential Nonlinearity  
Signal-to-Noise Plus  
Distortion  
±1  
±1  
Guaranteed Monotonic  
66  
0
Throughput Rate  
100  
ksps  
V
Input Voltage Range  
D/A CONVERTERS  
Resolution  
VREF  
12  
10  
bits  
LSB  
µs  
Differential Nonlinearity  
Output Settling Time  
COMPARATORS  
Supply Current  
Guaranteed Monotonic  
±1  
(each Comparator, VDD = 2.7 V)  
| (CP+) – (CP-) | = 100 mV  
1.3  
4
µA  
µs  
V
Response Time  
Input Voltage Range  
Input Bias Current  
Input Offset Voltage  
–0.25  
–5  
VDD + 0.25  
+5  
0.001  
nA  
mV  
–10  
+10  
C8051F020DK Development Kit  
Package Information  
D
MIN NOM MAX  
(mm) (mm) (mm)  
D1  
A
-
-
-
1.20  
0.15  
A1 0.05  
A2 0.95 1.00 1.05  
b
D
0.17 0.22 0.27  
-
-
-
-
-
16.00  
14.00  
0.50  
-
-
-
-
-
D1  
e
E1  
E
E
16.00  
14.00  
E1  
100  
PIN 1  
DESIGNATOR  
1
e
A2  
A
b
A1  
Precision Mixed Signal  
Copyright © 2004 by Silicon Laboratories  
6.15.2004  
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.  
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders  

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